WO2019048065A1

WO2019048065A1 - Amplifier circuit

Info

Publication number: WO2019048065A1
Application number: PCT/EP2017/072732
Authority: WO
Inventors: Daniele Mastantuono; Mattias PALM; Roland Strandberg; Lars SUNDSTRÖM
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2017-09-11
Filing date: 2017-09-11
Publication date: 2019-03-14

Abstract

An amplifier circuit (70) that comprises a first and a second field-effect transistor (M1, M2) of the same type is disclosed. It further comprises an input terminal (in) connected to the gate of the second field-effect transistor (M2), an output terminal (out) connected to a node between the drain of the first field-effect transistor (M1) and the source of the second field-effect transistor (M2), and a set of supply terminals configured to receive an upper and a lower supply voltage (VDD, GND), said set comprising a first supply terminal (S1) and a second supply terminal (S2). Moreover, it comprises a first circuit path (P1) connecting the source of the first field-effect transistor (M1) to the first supply terminal (S1), a second circuit path (P2) connecting the drain of the second field-effect transistor (M2) to the second supply terminal, the second circuit path comprising an impedance circuit (Z1), a third circuit path (P3) connecting the gate of the first field-effect transistor (M1) to a circuit node (x) between the impedance circuit (Z1) and the drain of the second field-effect transistor (M2), and a bias circuit (80) configured to generate a bias voltage to the gate of the first field-effect transistor (M1). The bias circuit (80) is controllable to generate the bias voltage as a controllable voltage. The impedance circuit (Z1) is controllable to provide a controllable impedance.

Description

AMPLIFIER CIRCUIT Technical field

The present invention relates to an amplifier circuit. Background

Amplifier circuits are utilized in many different applications, for example when buffering of a signal is needed. One such example is an amplifier circuit used as an input buffer in an analog-to-digital converter (ADC. An ADC is an interface circuit between the analog domain and the digital domain which converts a signal from an analog representation to a digital representation. An ADC may, for instance, be used in a radio receiver to convert a received analog signal to a digital representation for further digital signal processing. An example of an ADC is provided in J. Wu et al., "27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS," 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 466-467.

In state-of-the art and future communications systems, high speed, low power, large bandwidth ADCs are becoming increasingly important for highly integrated systems.

Examples of such systems are MIMO (Multiple-Input Multiple-Output) and digital beamforming architectures, where the integration of ADCs with relatively high sampling frequency, relatively high ENOB (Effective Number Of Bits), and relatively low power consumption is important for implementing an advanced antenna systems (AAS) with potentially hundreds of receivers. Such receivers need to comply with relatively hard specifications that have been derived from typical radio environment scenarios. For example, it should be possible to receive a relatively weak wanted signal in presence of relatively strong interfering signals. Due to nonlinearities and other non-idealities these interfering signals may lead to co-channel interference that deteriorates the wanted signal. In such scenarios, a relatively high degree of linearity, e.g. determined in terms of the spurious-free dynamic range (SFDR), is desirable in ADCs in the receivers. Since the linearity of an input buffer amplifier circuit of an ADC is one of the factors that determines the overall linearity of the ADC, it is readily understood that there is a need for amplifier circuits with relatively high degree of linearity as well. There are other scenarios where amplifier circuits with relatively high degree of linearity are desirable as well. The communication scenario outlined above is used as an example throughout this disclosure. Summary

The inventors have developed an amplifier circuit topology that enables controlling, or tuning, the amplifier circuit to exhibit a relatively high degree of linearity over a relatively wide range of operating conditions.

According to a first aspect, there is provided an amplifier circuit that comprises a first and a second field-effect transistor of the same type. It further comprises an input terminal connected to the gate of the second field-effect transistor, an output terminal connected to a node between the drain of the first field-effect transistor and the source of the second field- effect transistor, and a set of supply terminals configured to receive an upper and a lower supply voltage, said set comprising a first supply terminal and a second supply terminal. Moreover, it comprises a first circuit path connecting the source of the first field-effect transistor to the first supply terminal, a second circuit path connecting the drain of the second field-effect transistor to the second supply terminal, the second circuit path comprising an impedance circuit, a third circuit path connecting the gate of the first field-effect transistor to a circuit node between the impedance circuit and the drain of the second field-effect transistor, and a bias circuit configured to generate a bias voltage to the gate of the first field- effect transistor. The bias circuit is controllable to generate the bias voltage as a controllable voltage. The impedance circuit is controllable to provide a controllable impedance.

In some embodiments, the first field-effect transistor and the second field-effect transistor are NMOS transistors, the first supply terminal is configured to receive the lower supply voltage, and the second supply terminal is configured to receive the upper supply voltage.

In some embodiments, the first field-effect transistor and the second field-effect transistor are PMOS transistors, the first supply terminal is configured to receive the upper supply voltage, and the second supply terminal is configured to receive the lower supply voltage. In some embodiments, the third circuit path provides an AC coupling.

According to a second aspect, there is provided an ADC. It comprises the amplifier circuit of the first aspect as an input buffer circuit. Furthermore, it comprises a control circuit configured to control the controllable impedance circuit and the controllable bias circuit of the amplifier circuit.

In some embodiments, the control circuit is configured to observe an output of the ADC and control the controllable impedance circuit and the controllable bias circuit in response thereto. In some embodiments, the control circuit is configured to observe a distortion product of the output of the ADC and control the controllable impedance circuit and the controllable bias circuit to reduce the distortion product.

According to a third aspect, there is provided an electronic apparatus comprising the amplifier circuit of the first aspect or the ADC of the second aspect.

In some embodiments, the electronic apparatus is a communication apparatus. The communication apparatus may e.g. be a wireless communication device for a cellular communications system or a base station for a cellular communications system.

According to a fourth aspect, there is provided a method of controlling the ADC of the second aspect. The method comprises observing, by the control circuit, a distortion product of an output of the ADC. Furthermore, the method comprises controlling, by the control circuit, the controllable impedance circuit and the controllable bias circuit to reduce the distortion product.

According to a fifth aspect, there is provided a computer program product comprising computer program code for performing the method of the fourth aspect when said computer program code is executed by a programmable control circuit of the ADC.

According to a sixth aspect, there is provided a computer readable medium storing a computer program product comprising computer program code for performing the method of claim 12 when said computer program code is executed by a programmable control circuit of the ADC.

It should be emphasized that the term "comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. Brief description of the drawings

Fig. 1 illustrates a communication environment.

Fig. 2 shows a block diagram.

Figs. 3-7 show circuit diagrams.

Fig. 8 shows a block diagram.

Fig. 9 shows a flowchart.

Fig. 10 illustrates a computer-readable medium and a programmable control circuit. Detailed description

Fig. 1 illustrates a communication environment wherein embodiments of the present invention may be employed. A wireless communication device 1 , or wireless device 1 for short, of a cellular communications system is in wireless communication with a radio base station 2 of the cellular communications system. The wireless device 1 may be what is generally referred to as a user equipment (UE). The wireless devices 1 is depicted in Fig. 1 as a mobile phone, but may be any kind of device with cellular communication capabilities, such as a tablet or laptop computer, machine -type communication (MTC) device, or similar.

Furthermore, a cellular communications system is used as an example throughout this disclosure. However, embodiments of the present invention may be applicable in other types of systems as well, such as but not limited to WiFi systems.

The radio base station 2 and wireless device 1 are examples of what in this disclosure is generically referred to as communication apparatuses. Embodiments are described below in the context of a communication apparatus in the form of the radio base station 2 or wireless device 1. However, other types of communication apparatuses can be considered as well, such as a WiFi access point or WiFi enabled device.

Fig. 2 shows a simplified block diagram of a communication apparatus, such as the wireless device 1 or base station 2, according to some embodiments. It comprises a transceiver circuit 10 and an antenna module 15. The antenna module comprises one or more antennas, or antenna elements, for transmitting and/or receiving radio signals. The transceiver circuit 10 comprises a radio-frequency (RF) frontend circuit 20 connected to the antenna module. The RF frontend circuit 20 may comprise circuit elements such as filters, low-noise amplifiers (LNAs), down-conversion mixers, etc in a receive path. Furthermore, the RF front- end circuit 20 may comprise circuit elements such as filters, up-conversion mixers, and power amplifiers (PAs), etc in a transmit path. The design of such RF front-end circuits in general is well known in the art and is not further described herein. In the block diagram in Fig. 2, the transceiver circuit 10 comprises a digital-to-analog converter (DAC) 25 and an ADC 30 as interface circuits between the RF frontend circuit 20, which operates in the analog domain, and a digital signal processing (DSP) circuit 35 comprised in the transceiver circuit 10. The DSP circuit 35 may e.g. be a baseband processor or the like.

Fig. 3 illustrates a schematic circuit diagram of an embodiment of an amplifier circuit 70. The amplifier circuit 70 may e.g. be used as an input buffer circuit in the ADC 70. The amplifier circuit 70 comprises a first and a second field-effect transistor (FET) Ml, M2 of the same type. There are many different types of field-effect transistors that may be used, for instance MOS (Metal-Oxide-Semiconductor) transistors (or MOSFETs), SOI (Silicon-on- Insulator) FETs (e.g. fully depleted SOI FETs), FinFETs, etc. In Fig. 3, Ml and M2 are both NMOS transistors, but in alternative embodiments, they may both be PMOS transistors.

An input terminal (labeled "in" in Fig. 3) is connected to the gate of the second FET M2. An output terminal (labeled "out" in Fig. 3) is connected to a node between the drain of the first FET Ml and the source of the second FET M2. The amplifier circuit 70 comprises a set of supply terminals configured to receive an upper and a lower supply voltage. In this context, the words "upper" and "lower" indicates that the upper supply voltage is higher than the lower supply voltages. It does not exclude the possibility that there are other supply voltages on the same integrated circuit that, for instance, could be even lower than the "lower supply voltage" or even higher than the "upper supply voltage". In Fig. 3 VDD is used as a label for the upper supply voltage and GND is used as a label for the lower supply voltage. GND, or "ground", is usually used to indicate what is considered as electrical potential 0 V in an electronic circuit, but does not imply that that node is physically connected to earth. The set of supply terminals comprises a first supply terminal SI and a second supply terminal S2. In Fig. 3, terminal SI is configured to receive the lower supply voltage (GND) and terminal S2 is configured to receive the upper supply voltage (VDD). In embodiments where the transistors Ml and M2 are PMOS transistors, terminal SI would instead be configured to receive the upper supply voltage and terminal S2 would instead be configured to receive the lower supply voltage. The amplifier circuit 70 comprises a first circuit path PI connecting the source of the first FET Ml to the first supply terminal SI . In Fig. 3, the first circuit path PI is shown as a direct connection. However, the first circuit path PI may, in some embodiments, comprise a circuit element, such as a resistor or an inductor, between the source of the first FET Ml and the first supply terminal.

The amplifier circuit 70 comprises a second circuit path P2 connecting the drain of the second FET M2 to the second supply terminal. The second circuit path P2 comprises an impedance circuit Zl . In some embodiments, the impedance circuit Zl is predominantly resistive in the operating frequency band of the amplifier circuit. Hence, in some

embodiments, the impedance circuit may be referred to as a resistor.

The amplifier circuit 70 comprises a third circuit path P3 connecting the gate of the first FET Ml to a circuit node x between the impedance circuit Zl and the drain of the second FET M2. In some embodiments, third circuit path P3 provides an AC coupling between the gate of the first FET Ml and the circuit node x. In Fig. 3, this is provided by a capacitor CI, which blocks DC signals (i.e. is seen as an open circuit at low frequencies) and passes AC signals (i.e. is seen more or less as a short circuit in the operating frequency band).

Furthermore, the amplifier circuit comprises a bias circuit 80 configured to generate a bias voltage to the gate of the first FET Ml .

According to embodiments, the bias circuit 80 is controllable to generate the bias voltage as a controllable voltage. Furthermore, the impedance circuit Zl is controllable to provide a controllable impedance. The inventors have realized that this circuit topology, where both the bias voltage generated by the bias circuit 80 and the impedance of the impedance circuit Zl are controllable, enables controlling, or tuning, the amplifier circuit to exhibit a relatively high degree of linearity over a relatively wide range of operating conditions. This, in turn, for instance enables the design of an ADC 70 with a relatively high degree of linearity, e.g. in terms of ENOB or SFDR, over a relatively wide range of sampling frequencies, input signal bandwidths, and/or input signal power.

Fig. 4 illustrates an embodiment of the controllable impedance circuit Zl . It comprises an impedance Zlo connected between the second supply terminal S2 and the node x.

Furthermore, it comprises a plurality of impedances Zl i and ΖΙκ that can be selectably connected between the second supply terminal S2 and the node x by means of switches swi- SWK. The switches swi-swjf, and thereby the impedance of the impedance circuit Zl , can be digitally controlled, as is readily understood by a skilled person.

Fig. 5 illustrates another embodiment of the controllable impedance circuit Zl . As in Fig. 3, it comprises an impedance Zlo connected between the second supply terminal S2 and the node x. Instead of the impedances Z - ΖΙκ (and corresponding switches swi-swjf), it comprises FETs ΜΖΙ ι-ΜΖΙ,κ connected between the second supply terminal S2 and the node x. The transistors MZ1 ι-ΜΖΙ,κ are individually biased with gate bias voltages Vbi-V s:. In some embodiments, these bias voltages are controlled to have one of two possible values, one value at which the corresponding transistor is switched off, presenting an ideally (but not in practice, due to parasitics) infinite impedance, and another value at which the corresponding transistor is switched on, presenting a finite non-zero impedance. The gate bias voltages Vbi- V s:, and thereby the impedance of the impedance circuit Zl , can be digitally controlled, as is readily understood by a skilled person.

Fig. 6 illustrates an embodiment of the controllable bias circuit 80 according to an embodiment. It comprises a diode-connected (i.e. with the drain connected to the gate) FET Mb of the same type as first FET Ml . The embodiment of the controllable bias circuit also comprises a variably controllable current source lb configured to supply a current to the drain of the transistor Mb. The gate bias voltage for the first FET Ml is generated at the gate of the transistor Mb. As will be recognized by a skilled person, the transistors Mb and Ml are connected in a current-mirror configuration. The current source lb may be implemented as a current-steering DAC. Thus, the gate bias voltage of the first FET can be digitally controlled. Hence, the controllable bias circuit may be digitally controllable. As indicated in Fig. 6, the gates of transistors Mb and Ml may be directly connected, or the controllable bias circuit 80 may optionally include a resistor Rb connected between the gate of transistor Mb and the gate of transistor Ml . Furthermore, the controllable bias circuit may comprise a capacitor Cb connected between the gate of transistor Mb and a supply voltage, such as GND or VDD, to stabilize the generated bias voltage.

Fig. 7 shows a schematic circuit diagram of a differential version of the amplifier circuit 70. It has a differential input port with input terminals in_p and in m. Furthermore, it has a differential output port with output terminals out_p and out m. It has dual versions of Ml, M2, Zl, and CI, making up two halves of the differential amplifier circuit 70. Furthermore, it has a controllable bias circuit 80 that is shared between said two halves. The controllable impedance circuits Zl are implemented as in Fig. 5, with K = 3. The indications m = 1, m = 2, and m = 3 in Fig. 7 indicates that the W/L (width/length) ratio of transistor MZ1₂ is twice the W/L ratio of MZ11, and that the W/L ratio of transistor MZ1₃ is four times the W/L ratio MZl i. The label rbias<2:0> indicates a bus for providing the Vbl-Vb3 (see Fig. 5). The label ibias<2:0> indicates a three-bit bus for providing control bits for controlling the current source lb. Fig. 7 indicates parameter values for circuit elements used in simulations. The ratio indicates that the transistor Ml has a width of 2240 μιη and a length of 0.15μιη. The ratio indicates that the transistor M2 has a width of 1250 μιη and a length of 0.15μιη. The ratio indicates that the transistor MZ11 has a width of 23 μιη and a length of 0.15μιη.

Transistors MZ1₂ and MZI3 also have the length 0.15 μιη, but their widths are 46 μιη and 92 μιη, respectively. As seen in the left of Fig. 7, a 100 Ω resistor has been placed between the input terminals in_p and in m.

Simulations have been performed using process parameters of a 28nm CMOS FD-SOI (Fully Depleted Silicon On Insulator) process. In the simulations, a sample-and-hold (S&H) circuit was used at the output of the amplifier circuit 70, and the simulations were performed at different operating conditions, namely different sampling rates of the S&H circuit, ranging from 1 Giga Samples Per Second (GSPS) to 4 GSPS, different temperatures, and for different manufacturing process parameters. A single-tone sinusoidal input at different signal frequencies and different amplitudes was used as input.

It could be concluded from the simulations that the optimum SFDR was relative insensitive to different temperature and process parameter and the same combinations of settings of the controllable bias circuit 80 and the controllable impedance circuit Zl (which in these simulations was predominantly resistive for the signal frequencies considered) could be used. It was also noted that the optimum combination of settings for a given sampling rate was relatively insensitive to variations of signal frequency and amplitude level. On the other hand, different settings were needed in case the sampling rate of the S&H used at the output was changing. If (under fixed operating conditions) the optimum combination of settings was found for a certain signal frequency and amplitude level, that same combination also gave a good (or near optimal) SFDR over a relatively wide range of signal frequencies and amplitude levels. In summary, as indicated above, the controllability of both the impedance circuit Zl and the bias circuit 80 enables obtaining a relatively high degree of linearity over a relatively wide range of operating conditions. Furthermore, this can be obtained in a manner that is insensitive towards variations in signal frequency and amplitude level.

Fig. 8 is a block diagram of an ADC, such as the ADC 30, according to some

embodiments, having an input "in" and an output "out". It includes an embodiment of the amplifier circuit 70 as an input buffer circuit. Furthermore, it includes a control circuit 120 configured to control the controllable impedance circuit Zl and the controllable bias circuit 80 of the amplifier circuit 70. For example, the control circuit 120 may be configured to provide different combinations of settings for the controllable impedance circuit Zl and the controllable bias circuit for different sampling rates of the ADC 30. Different ways of converting the output of the amplifier circuit 70 into a digital signal to be output at the output "out" are known, and are not discussed herein in any greater detail. These includes, for example, time-interleaved analog-to-digital (A/D) conversion, successive-approximation A/D conversion, ΣΔ A/D conversion, etc. As indicated in Fig. 8, the ADC 30 may comprise an S&H circuit 100 configured to sample the output from the amplifier circuit 70 at a sampling rate of the ADC 30, followed by a quantizer 110 configured to quantize the output of the S&H circuit.

As indicated in Fig. 8, the control circuit 120 may be configured to observe an output of the ADC 30 and control the controllable impedance circuit Zl and the controllable bias circuit 80 in response thereto. For example, this may be done using one or more known test signals, such as sinusoidal test signals, applied to the input "in" of the ADC 30. For example, the control circuit 120 may be configured to observe a distortion product of the output of the ADC 30 and control the controllable impedance circuit Zl and the controllable bias circuit 80 to reduce the distortion product. An example of such a distortion product, which can relatively often be the dominant distortion product, is the third-order distortion product. Mathematically, the third-order distortion products can be seen as a surface function of the parameter settings of the controllable bias circuit 80 and the controllable impedance circuit Zl . In order to search for the minimum third-order distortion, the control unit 120 may employ known optimization methods, e.g. based on gradient estimation (e.g. secant method) or assumed shape of surface (e.g. successive parabolic interpolation). Alternatively, the control circuit may be configured to explore the entire search space of combinations of settings of the controllable bias circuit 80 and the controllable impedance circuit Zl . For example, if there are multiple third-order distortion level requirements, each associated with a different input signal level and/or frequency, such an exhaustive search may be useful to find combinations of settings complying with the multiple third-order distortion level requirements.

The determination of settings for the controllable bias circuit 80 and the controllable impedance circuit Zl may be performed by the control circuit 120 during dedicated calibration periods, e.g. at power up of the ADC 30 and/or at regular intervals when no received signals are to be processed by the ADC 30. When the ADC 30 is reconfigured with respect to sampling rate, this will effectively change the impedance of the S&H circuit as seen from the output of the amplifier circuit 70. This in turn can influence the linearity of the amplifier circuit 70. Consequently, in some embodiments, a change of sampling rate of the ADC 30 triggers a new determination of settings (or "new calibration period") of the controllable bias circuit 80 and the controllable impedance circuit Zl . In some embodiments, settings may be stored in a table for different sampling rates, either to be used directly upon change of sampling rate or as starting point for a new search for settings to be applied.

According to some embodiments, there is provided a method of controlling the ADC 30. An embodiment of the method is illustrated in Fig. 9 with a flowchart. Operation of the method is started in step 200. The method includes, in step 210, observing, by the control circuit 120, a distortion product of an output of the ADC 30. Furthermore, the method includes, in step 220, controlling, by the control circuit 120, the controllable impedance circuit Zl and the controllable bias circuit 80 to reduce the distortion product. The method is ended in step 230. The method may e.g. be performed during dedicated calibration periods, as discussed above. In line with what is described above, the method may include using one or more known test signals, such as sinusoidal test signals, applied to the input "in" of the ADC 30. For simplicity, the flowchart in Fig. 9 shows steps 210 and 220 as being performed in a single sequence. However, as would be readily understood by a skilled person, multiple iterations may be required in the search for the settings to be applied to the controllable impedance circuit Zl and the controllable bias circuit 80.

In some embodiments, the control circuit 120 may be implemented as a dedicated application-specific hardware unit. Alternatively, said control circuit 120, or parts thereof, may be implemented with programmable and/or configurable hardware units, such as but not limited to one or more field-programmable gate arrays (FPGAs), processors, or

microcontrollers. Thus, the control circuit 120 may be a programmable control circuit 120. Hence, embodiments of the present invention may be embedded in a computer program product, which enables implementation of the method and functions described herein, e.g. the embodiments of the method described with reference to Fig. 9. Therefore, according to embodiments, there is provided a computer program product comprising computer program code for performing any of the functions or method embodiments herein when said computer program code is executed by the programmable control circuit 120. The computer program product may comprise program code which is stored on a computer readable medium 500, as illustrated in Fig. 10, which can be loaded and executed by said programmable control circuit 120.

The disclosure above refers to specific embodiments. However, other embodiments than the above described are possible within the scope of the invention. For example, the ADC 30 and/or the amplifier circuit 70 may be used in other types of electronic apparatuses than communication apparatuses. The different features and steps of the embodiments may be combined in other combinations than those described.

Claims

1. An amplifier circuit (70), comprising

a first and a second field-effect transistor (Ml, M2) of the same type;

an input terminal (in) connected to the gate of the second field-effect transistor (M2); an output terminal (out) connected to a node between the drain of the first field-effect transistor (Ml) and the source of the second field-effect transistor (M2);

a set of supply terminals configured to receive an upper and a lower supply voltage (VDD, GND), said set comprising a first supply terminal (SI) and a second supply terminal (S2); a first circuit path (PI) connecting the source of the first field-effect transistor (Ml) to the first supply terminal (SI);

a second circuit path (P2) connecting the drain of the second field-effect transistor (M2) to the second supply terminal, the second circuit path comprising an impedance circuit (Zl); a third circuit path (P3) connecting the gate of the first field-effect transistor (Ml) to a circuit node (x) between the impedance circuit (Zl) and the drain of the second field-effect transistor (M2); and

a bias circuit (80) configured to generate a bias voltage to the gate of the first field-effect transistor (Ml); wherein

the bias circuit (80) is controllable to generate the bias voltage as a controllable voltage; and

the impedance circuit (Zl) is controllable to provide a controllable impedance.

2. The amplifier circuit (70) of claim 1, wherein the first field-effect transistor (Ml) and the second field-effect transistor (M2) are NMOS transistors, the first supply terminal is configured to receive the lower supply voltage (GND), and the second supply terminal (S2) is configured to receive the upper supply voltage (VDD).

3. The amplifier circuit (70) of claim 1, wherein the first field-effect transistor and the second field-effect transistor are PMOS transistors, the first supply terminal is configured to receive the upper supply voltage, and the second supply terminal is configured to receive the lower supply voltage.

4. The amplifier circuit (70) of any preceding claim, wherein the third circuit path (P3) provides an AC coupling.

5. An analog-to-digital converter, ADC, (30) comprising:

the amplifier circuit (70) of any preceding claim as an input buffer circuit; and

a control circuit (120) configured to control the controllable impedance circuit (Zl) and the controllable bias circuit (80) of the amplifier circuit (70).

6. The ADC (30) of claim 5, wherein the control circuit (120) is configured to observe an output of the ADC (30) and control the controllable impedance circuit (Zl) and the controllable bias circuit (80) in response thereto.

7. The ADC (30) of claim 6, wherein the control circuit (120) is configured to observe a distortion product of the output of the ADC (30) and control the controllable impedance circuit (Zl) and the controllable bias circuit (80) to reduce the distortion product.

8. An electronic apparatus (1, 2) comprising the amplifier circuit (70) of any one of claims 1 - 4 or the ADC (30) of any one of claims 5 - 7.

9. The electronic apparatus (1, 2) of claim 8, wherein the electronic apparatus (1, 2) is a communication apparatus.

10. The electronic apparatus (1) of claim 9, wherein the communication apparatus is a wireless communication device for a cellular communications system.

11. The electronic apparatus (2) of claim 9, wherein the communication apparatus is a base station for a cellular communications system.

12. A method of controlling the ADC (30) of claim 5, comprising

observing (210), by the control circuit (120), a distortion product of an output of the ADC (30); and

controlling (220), by the control circuit (120), the controllable impedance circuit (Zl) and the controllable bias circuit (80) to reduce the distortion product.

13. A computer program product comprising computer program code for performing the method of claim 12 when said computer program code is executed by a programmable control circuit (120) of the ADC (30).

14. A computer readable medium (500) storing a computer program product comprising computer program code for performing the method of claim 12 when said computer program code is executed by a programmable control circuit (120) of the ADC (30).