WO2019040199A1

WO2019040199A1 - TIME-TO-DIGITAL CONVERTER (TDC) BIASING FOR IMPROVED PHASE NOISE IN ALL-DIGITAL PHASE-LOCKED LOOPS (ADPLLs)

Info

Publication number: WO2019040199A1
Application number: PCT/US2018/042085
Authority: WO
Inventors: Charles Chang-I Wang; Emanuele Lopelli; Magnus Olov Wiklund; Bharani RAJENDIRAN
Original assignee: Qualcomm Incorporated
Priority date: 2017-08-25
Filing date: 2018-07-13
Publication date: 2019-02-28
Also published as: TW201914225A

Abstract

An all-digital phase locked loop (ADPLL) includes a digital controlled oscillator (DCO) to generate an output signal of the ADPLL and a time-to-digital converter (TDC) to detect a fractional phase of the DCO. A sampling circuit samples a fractional portion of a locking phase of the ADPLL, wherein the locking phase is a phase offset between an output signal of the ADPLL and an input signal of the ADPLL when the ADPLL enters a phase-locked loop. The fractional portion of the locking phase is replaced with a desired fractional phase, wherein the desired fractional phase is one of one or more fractional phases of the input signal, wherein a phase of the TDC is biased to the desired fractional phase to minimize the phase noise of the ADPLL.

Description

TIME-TO-DIGITAL CONVERTER (TDC) BIASING FOR IMPROVED PHASE NOISE IN ALL-DIGITAL PHASE-LOCKED LOOPS (ADPLLs)

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present Application for Patent claims the benefit of Provisional Patent Application No. 62/549,985 entitled "TIME-TO-DIGITAL CONVERTER (TDC) BIASING FOR IMPROVED PHASE NOISE IN ALL-DIGITAL PHASE-LOCKED LOOPS (ADPLLs)" filed August 25, 2017, pending, and assigned to the assignee hereof and hereby expressly incorporated herein by reference in its entirety.

Field of Disclosure

[0002] Disclosed aspects relate to all-digital phase-locked loops (ADPLLs). More specifically, exemplary aspects are directed to biasing a time-to-digital converter (TDC) of an ADPLL to reduce integrated phase noise (IPN) in the ADPLL.

Background

[0003] A phase-locked loop (PLL) is an electronic circuit which is used in communication systems like frequency synthesizers, modulators, demodulators, clock recovery circuits, etc. In a conventional PLL, there is a feedback circuit which locks a phase of an output signal relative to the phase of an input signal (or reference signal), wherein the input signal may be a periodic waveform such as a clock or a sinusoidal wave. A PLL comprises a phase detector (PD) to detect the phase of the input signal, a loop filter (e.g., a low-pass filter to filter out high frequency components from the phase detector's output) and a voltage controlled oscillator (VCO) configured to adjust the frequency of the output signal to match a multiple of the frequency of the input signal. As an alternative to the conventional analog PLL, digital PLLs (DPLLs) or more specifically referred to as All-Digital PLLs (ADPLLs), are seen to display lower power consumption characteristics.

[0004] FIG. 1 shows a conventional all-digital PLL (ADPLL) 100, comprising a digital phase detector or PD 102, a digital loop filter or loop filter 104, and a digital controlled oscillator or DCO 106. As illustrated, ADPLL 100 receives a frequency reference (Fref) signal as an input signal and generates an output signal identified based on its frequency as "Fout" (according to conventional norms, the output signal may alternatively be referred to as "Vout" based on its voltage). The Fref input signal may be derived from a crystal oscillator (XO), which may alternatively be a temperature compensated XO (TCXO), or the like, identified by the reference numeral 120. A frequency control word (FCW) is the value of the ratio of Fout/Fref. PD 102 is configured to detect a phase error between the phase of DCO 106 and the phase of Fref input signal. The output of PD 102 is the detected phase error, which is passed through loop filter 104 (e.g., a low-pass filter) and provided to DCO 106.

[0005] The output of DCO 106, referred to as the phase of DCO 106 or the DCO phase comprises two components, a whole number and a fractional part. The whole number is counted by a phase incrementor or PI 108 and the fractional part is measured by a time- to-digital converter or TDC 110. The outputs of PI 108 and TDC 110 are added in adder 112 before being fed back to phase detector 102. In phase detector 102, the output of adder 112 is subtracted from the phase evolution of the Fref input signal as derived from the FCW, to generate a phase error. The phase error is passed back through loop filter 104 and DCO 106. Ideally, the phase error is minimized over time and the output Fout of DCO 106 matches or is locked to the phase of the input signal Fref.

[0006] However, the conventional ADPLL implementations may be affected by phase noise which causes their behavior to deviate from the ideal situation described above, wherein the deviations may be much larger when the conventional ADPLLs are used for locking on to simple channels with at most a small number of fractional phases in the phase evolution of the Fref input signal. The deviations may lead to lower accuracies and higher power consumption. There is correspondingly a need to reduce phase noise for improving performance and power consumption of the ADPLLs.

SUMMARY

[0007] Exemplary embodiments of the invention are directed to an all-digital phase locked loop (ADPLL) with control circuitry configured to control fractional phase offset of the loop of the PLL based on controlling a phase offset between a DCO and the input signal when the phase is locked. By controlling the fractional phase offset, the phase noise is improved. Specifically, enhancements to a phase detector of an exemplary ADPLL for achieving the improvement in phase noise are disclosed, in both frequency-based and phase-based implementations of the phase detector. [0008] Accordingly, an exemplary aspect is directed to a method of controlling phase noise in an all-digital phase-locked loop (ADPLL), the method comprising sampling a fractional portion of a locking phase of the ADPLL, wherein the locking phase is a phase offset between an output signal of the ADPLL and an input signal of the ADPLL when the ADPLL enters a phase-locked loop, replacing the fractional portion of the locking phase with a desired fractional phase, wherein the desired fractional phase is one of one or more fractional phases of the input signal, and biasing a phase of a time-to-digital converter (TDC) of the ADPLL to the desired fractional phase, wherein the TDC is configured to detect a fractional phase of a digital controlled oscillator (DCO) for generating the output signal of the ADPLL, and wherein the phase noise of the ADPLL is minimized when the phase of the TDC is biased to the desired fractional phase.

[0009] Another exemplary aspect is directed to an apparatus comprising an all-digital phase- locked loop (ADPLL). The ADPLL comprises a digital controlled oscillator (DCO) configured to generate an output signal of the ADPLL, a time-to-digital converter (TDC) configured to detect a fractional phase of the DCO, a sampling circuit configured to sample a fractional portion of a locking phase of the ADPLL, wherein the locking phase is a phase offset between an output signal of the ADPLL and an input signal of the ADPLL when the ADPLL enters a phase-locked loop, and a circuit configured to replace the fractional portion of the locking phase with a desired fractional phase, wherein the desired fractional phase is one of one or more fractional phases of the input signal. A phase of the TDC of the ADPLL is biased to the desired fractional phase to minimize the phase noise of the ADPLL.

[0010] Another exemplary aspect is directed to an apparatus comprising an all-digital phase- locked loop (ADPLL). The ADPLL comprises means for sampling a fractional portion of a locking phase of the ADPLL, wherein the locking phase is a phase offset between an output signal of the ADPLL and an input signal of the ADPLL when the ADPLL enters a phase-locked loop, means for replacing the fractional portion of the locking phase with a desired fractional phase, wherein the desired fractional phase is one of one or more fractional phases of the input signal, and means for biasing a phase of a time-to- digital converter (TDC) of the ADPLL to the desired fractional phase, wherein the TDC comprises means for detecting a fractional phase of a digital controlled oscillator (DCO) for generating the output signal of the ADPLL, and wherein the phase noise of the ADPLL is minimized when the phase of the TDC is biased to the desired fractional phase.

[0011] Yet another exemplary aspect is directed to a non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for controlling phase noise in an all-digital phase-locked loop (ADPLL). The non-transitory computer-readable storage medium comprises code for sampling a fractional portion of a locking phase of the ADPLL, wherein the locking phase is a phase offset between an output signal of the ADPLL and an input signal of the ADPLL when the ADPLL enters a phase-locked loop, code for replacing the fractional portion of the locking phase with a desired fractional phase, wherein the desired fractional phase is one of one or more fractional phases of the input signal, and code for biasing a phase of a time-to-digital converter (TDC) of the ADPLL to the desired fractional phase, wherein the TDC is configured to detect a fractional phase of a digital controlled oscillator (DCO) for generating the output signal of the ADPLL, and wherein the phase noise of the ADPLL is minimized when the phase of the TDC is biased to the desired fractional phase.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are presented to aid in the description of embodiments of the invention and are provided solely for illustration of the embodiments and not limitation thereof.

[0013] FIG. 1 illustrates a conventional ADPLL implementation.

[0014] FIG. 2 illustrates a graph with phase noise shown as a function of phase offset.

[0015] FIG. 3A illustrates a conventional ADPLL design comprising a frequency-based phase detector.

[0016] FIG. 3B illustrates an exemplary ADPLL comprising a frequency-based phase detector, configured for reducing phase noise, according to exemplary aspects.

[0017] FIG. 4A illustrates a conventional ADPLL design comprising a phase-based phase detector.

[0018] FIG. 4B illustrates an exemplary ADPLL comprising a phase-based phase detector, configured for reducing phase noise, according to exemplary aspects.

[0019] FIG. 5 illustrates a graph for initial-phase sampling programmed to bias a TDC to a fractional phase. [0020] FIG. 6 illustrates a flow-chart of a method of controlling phase noise in an all-digital phase-locked loop (ADPLL) according to exemplary aspects.

[0021] FIG. 7 illustrates an example wireless communication system in which aspects of this disclosure may be advantageously employed.

DETAILED DESCRIPTION

[0022] Aspects of the invention are disclosed in the following description and related drawings directed to specific embodiments of the invention. Alternate embodiments may be devised without departing from the scope of the invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.

[0023] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments of the invention" does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and/or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0025] Further, many embodiments are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer-readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the invention may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, the corresponding form of any such embodiments may be described herein as, for example, "logic configured to" perform the described action.

[0026] Referring back to FIG. 1, the phase noise or integrated phase noise (IPN) of ADPLLs, such as ADPLL 100, is seen to be strongly affected by the fractional phase input to TDC 110, and more specifically, by the bias or DC value of the fractional phase input to TDC 110 (also referred to as the "TDC bias"). The effect of the TDC bias discussed above on IPN is seen to be the strongest on so-called "simple channels" of the input frequency.

[0027] To explain, simple channels refer to frequency channels of the input reference Fref which generate a small number of fractional phase values. As previously mentioned, the FCW is the ratio of Fout/Fref, which is a constant. The phase evolution of the reference Fref, which is the integral of the constant FCW, would exercise only a small number of fractional phase values in the case of simple channels. For example, if FCW=2.25, then the phase evolution of the reference Fref may be 0, 2.25, 4.5, 6.75, 9.0, 11.25, 13.5, and so on. From the above phase evolution of the reference input signal Fref, it is seen that the fractional part thereof exercises only a small number of phases, in this case, only 0, 0.25, 0.5, and 0.75. The effect of the TDC bias is seen to be stronger on these simple channels of the input frequency Fref, for which the fractional part of the FCW is 0 (i.e., only a single fractional phase is present), 0.5 (i.e., two fractional phases 0 and 0.5), or 0.25/0.75 (i.e., four fractional phases 0, 0.25, 0.5, and 0.75).

[0028] Referring to FIG. 2, for example, graph 200 is illustrated. Graph 200 contains an illustrative plot of the IPN on the y-axis for an example TDC characteristic, with the phase offset measured between the input signal Fref and the output signal Fref or output of DCO 106 (i.e., the fractional phase input to TDC 110) on the x-axis. It will be understood that for other TDC characteristics the low and high IPN regions may shift from the example illustration of graph 200, but the exemplary aspects of this disclosure are not limited to the specific example shown in graph 200 and as such, aspects of this disclosure are applicable for other TDC characteristics as well. The fractional phases in this illustrated example are for a single fractional phase of "0". Point 202 on graph 200 indicates a high IPN at a first fractional phase input to TDC 110 and point 204 indicates a low IPN at a second fractional phase input to TDC 110. As seen, the IPN at the second fractional phase is lower. As such, the second fractional phase at point 204, for example would be desirable for a low IPN and such a fractional phase is referred to as a desired fractional phase. Thus, in aspects of this disclosure, it is recognized that by controlling the fractional phase of the ADPLL, it is possible to bias the fractional phase input to TDC 110 to the desired fractional phase, which in turn can lead to lower and improved IPN.

[0029] Accordingly, in exemplary aspects of this disclosure, systems and methods for adjusting the phase offset, or more specifically, the fractional phase offset between the DCO and the input signal of an ADPLL are disclosed. In some aspects, exemplary phase detectors (both frequency-based and phase-based PDs) are disclosed, wherein the exemplary phase detectors are configured to adjust the phase offset between the DCO and the input reference signal when the ADPLL operates in a phase-locked mode. By adjusting this phase offset, the fractional phase input to the TDC is biased such that IPN is minimized.

[0030] In one exemplary ADPLL implementation, a frequency-based phase detector may be used, wherein the locking phase of the ADPLL is the same as the DCO phase when the phase-locked loop closes (i.e., when the ADPLL comes out of reset). Although the DCO phase is generally uncontrolled at loop closure, an initial-phase sampling technique, further explained below, may be utilized to sample the DCO phase at loop closure. The sampled DCO phase may then be subtracted from the known or desired fractional phase of the ADPLL to determine a phase offset error. This phase offset error may be added (or subtracted) to the phase which is input to the DCO such that the DCO phase, and correspondingly, the input phase to an exemplary TDC is biased to a value which minimizes the IPN.

[0031] In another exemplary ADPLL implementation, a phase-based phase detector may be employed, wherein the locking phase of the ADPLL is recognized as the initial phase of an FCW integrator employed in the phase-based phase detector. A phase offset is then added to the locking phase of the ADPLL to bias the TDC to a value which minimizes the IPN.

[0032] The above exemplary ADPLL implementations will now be discussed in greater detail with reference to FIGS. 3-4. [0033] With reference to FIG. 3A, a conventional ADPLL 300 is shown, comprising frequency-based phase detector (PD) 302 configured to receive input signal Fref (which may be generated from any type of a crystal oscillator as previously explained), from which the FCW is derived. ADPLL 300 is also shown to comprise a digital loop filter 304, a digital DCO 306, and a feedback path from output signal Fout to frequency -based PD 302. The feedback path is shown to comprise phase incrementor (PI) 308, TDC 310 and adder 312.

[0034] Further details of frequency-based PD 302 are illustrated in FIG. 3A, with integrator 320 configured to start in a reset mode. In the reset mode, the operation of ADPLL 300 commences when the loop closes based on the reset signal being de-asserted (e.g., when the reset signal goes low in an implementation wherein the reset signal is an active high signal, without loss of generality). Thus, the reset signal going low is considered to be a starting point of operation or an initial time instance t=0.

[0035] It will be recalled that the phase of DCO 306 is sampled at loop closure, using PI 308 (whole number count) and TDC 310 (fractional DCO phase) and added in adder 312 to generate the measured DCO phase ODCO upon loop closure. Block 324 is a differentiator configured to convert the DCO phase output from adder 312, representing the sum of PI 308 and TDC 310 into a frequency, which enables the frequency of DCO 306 (or the "DCO frequency) to be measured against the desired frequency of FCW, e.g., using adder 322 in frequency-based PD 302.

[0036] In frequency-based PD 302, the locking phase that the output signal Fout is locked on to with respect to the reference clock (of the input signal Fref ) is the phase of DCO 306 at loop closure (i.e., when the reset signal is released or de-asserted) or the "DCO phase". If the DCO phase of DCO 306 is left uncontrolled, then the bias point of TDC 310 may deviate from a value which would minimize the IPN.

[0037] Thus, in exemplary aspects, the phase of DCO 306 may be controlled by augmenting the conventional ADPLL 300 comprising frequency-based PD 302, in turn biasing TDC 310 to a value which minimizes the IPN.

[0038] With reference now to FIG. 3B, exemplary ADPLL 350 configured to control the DCO phase using an initial-phase sampling technique will be described. ADPLL 350 of FIG. 3B includes modifications and/or additions to ADPLL 300 of FIG. 3A, configured to control the fractional phase offset at loop closure, which is the TDC bias. Like reference numerals have been used to identify common or similar elements between ADPLL 300 and ADPLL 350, and the following discussion will focus predominantly on the differences between these circuits without repeating an exhaustive description of the like-numbered components.

[0039] As shown in FIG. 3B, there is an added connection or path 364 from the output of TDC 310 to a sampling circuit comprising multiplexor 360 and delay element 358. The sampling circuit is configured to hold the output of TDC 310 when reset is de-asserted, which is the fractional DCO phase offset when the phase-locked loop of ADPLL 350 closes (or simply stated, at the time of loop closure). In more detail, when reset is low the output from delay element 358 is selected by multiplexor 360 (instead of path 364) which means that the output of TDC 310 is held (Blocks 360 and 358 may be referred to as a digital sample-and-hold circuit).

[0040] In adder 356 (implemented as a subtractor), the sampled fractional DCO phase at loop closure is subtracted from the desired fractional phase. The difference between the sampled fractional DCO phase at loop closure and the desired fractional phase is used to effectively normalize or cancel out the sampled fractional DCO phase at the time of loop closure from the DCO phase. For this, multiplexor 354 outputs a value of "0" while reset remains asserted (thus preventing the initial phase sampling circuit's calculated phase from affecting the loop prior to loop closure) and once reset is de- asserted and the loop is closed, multiplexor 354 outputs the difference between the sampled fractional DCO phase at loop closure and the desired fractional phase calculated by adder 356.

[0041] This difference between the sampled fractional DCO phase at loop closure and the desired fractional phase is then provided from multiplexor 354 to exemplary frequency- based PD 352 or ADPLL 350. Frequency-based PD 352 includes an additional adder 353 which is configured to subtract from the conventionally calculated phase offset (using the previously described components 320, 322, 324 of frequency-based PD 302 of FIG. 3A), the difference between the sampled fractional DCO phase at loop closure, provided by multiplexor 354. Thus, adder 353 effectively cancels out the output of TDC 310 at loop closure which represents the initial DCO phase or the TDC bias once the phase-locked loop of ADPLL 350 closes. In this manner, the TDC bias of TDC 310 may be controlled (by eliminating the fractional DCO phase of DCO 306 at loop closure and imposing the desired fraction phase ()>desired), which correspondingly leads to eliminating phase noise or IPN in ADPLL 350. [0042] With reference now to FIG. 4A, conventional ADPLL 400 configured to receive input signal Fref (which may be generated from any type of a crystal oscillator as previously explained), from which the FCW is derived. ADPLL 400 is shown to include a phase- based phase detector (PD) 402, which will be explained further. ADPLL 400 is also shown to comprise digital loop filter 404, DCO 406 with output Fout, phase incrementor (PI) 408, TDC 410, and adder 412 configured similar to like components of ADPLLs 100 and 300 described previously.

[0043] Considering phase-based PD 402 in more detail, components FCW integrator 420 and adder 422 are shown. The reset signal being de-asserted presents the initial condition for phase-based PD 402, wherein FCW integrator 420 is configured to determine the initial or locking phase of ADPLL 400. In conventional implementations, flip-flops or registers store the initial locking phase, which is set in the flip-flops as a constant to prevent issues during timing closure of ADPLL 400. Thus, the initial phase offset when phase-based PD 402 comes out of reset may be a known constant, but this may not correspond to the DCO phase which would properly bias TDC 410 for minimizing the IPN. The initial locking phase of FCW integrator 420 is subtracted from the sum of PI 408 and TDC 410 in adder 422 to form the phase error, which after passing through loop filter 404 provides the DCO phase of DCO 406, and correspondingly, the fractional portion of the DCO phase forms the initial TDC bias of TDC 410 (which is uncontrolled in conventional implementations).

[0044] Accordingly, in exemplary aspects, circuit modifications and/or additions are devised to add a phase offset to the initial locking phase of phase-based PD 402 such that the sum of the added phase offset and the initial locking phase when FCW integrator 420 comes out of reset would effectively result in the fractional DCO phase of DCO 406 or the TDC bias of TDC 410 being set at the desired value to minimize IPN. In one implementation, if the initial locking phase of FCW integrator 420 is set to zero (e.g., the output of FCW integrator 420 is reset to zero when reset is de-asserted), then the added phase offset is the locking phase, based on which the TDC bias may be controlled.

[0045] With reference now to FIG. 4B, ADPLL 450 configured according to exemplary aspects will be described. ADPLL 450 of FIG. 4B includes modifications and/or additions to ADPLL 400 of FIG. 4A. Like reference numerals have been used to identify common or similar elements between ADPLL 400 and ADPLL 450, and the following discussion will focus predominantly on the differences between these circuits without repeating an exhaustive description of the like-numbered components.

[0046] Accordingly, as shown in FIG. 4B, multiplexor 454 is configured to select the desired fractional phase (e.g., 0/0.25/0.5/0.75, etc.) once ADPLL 450 comes out of reset (i.e., once reset signal is de-asserted). FCW integrator 420 may be configured to zero once reset is de-asserted (e.g., based on storing a zero value in flip-flops to be input as an initial condition for FCW integrator 420). Phase-based PD 452 is provided with an additional adder 453 as shown, which adds the desired fractional phase as the phase error upon loop closure. Since the phase output of FCW integrator 420 is zero, the desired fractional phase forms the initial locking phase of ADPLL 450. Thus, the desired fractional phase generated in the above manner effectively forms the fractional part of the DCO phase and likewise the TDC bias of TDC 410, setting the TDC bias to the value at which IPN is minimized or eliminated. Multiplexor 454 is also configured to prevent the locking phase from affecting the DCO while the reset signal is asserted or before the ADPLL 450 enters the phase-locked loop.

[0047] FIG. 5 illustrates graph 500 of simulation results of a system employing the mechanisms described herein for reducing IPN in an ADPLL by controlling the TDC bias. More specifically, graph 500 shows the fractional phase (y-axis) plotted as a function of time (x-axis), using an initial-phase sampling technique as described with reference to ADPLL 350 of FIG. 3B comprising frequency-based PD 352 configured according to exemplary aspects discussed herein. In FIG. 5, the fractional phase of ADPLL 350 at a TDC bias, set to correspond to a desired fractional phase of value 0.25, is illustrated. Accordingly, FIG. 5 shows that the locking phase of ADPLL 350 may be controlled to a desired value. From FIG. 2, it will be recalled that the IPN varies with the phase offset, with the IPN being the lowest at the TDC bias being equal to the desired fractional phase. Thus, by controlling the TDC bias to be substantially equal to the desired fractional phase, the phase noise may be substantially eliminated.

[0048] It is recognized that in exemplary ADPLL implementations, the phase difference between the output and the input signals (which is the locking phase) may be controlled, thus beneficially enabling the locking phase of the ADPLL to be set to a constant value every time a circuit implementing the exemplary ADPLL (e.g., a radio) is operated or turned on. [0049] Accordingly, it will be appreciated that aspects include various methods for performing the processes, functions and/or algorithms disclosed herein. For example, as illustrated in FIG. 6, an aspect can include method 600 of controlling phase noise in an all-digital phase-locked loop (ADPLL).

[0050] Block 602 comprises sampling a fractional portion of a locking phase of the ADPLL, wherein the locking phase is a phase offset between an output signal of the ADPLL and an input signal of the ADPLL when the ADPLL enters a phase-locked loop (e.g., in the case of ADPLL 350 comprising frequency-based PD 352, sampling the fractional phase of DCO 306 (or the fractional phase of adder when the ADPLL enters the phase-locked loop) to determine a sampled DCO fractional phase using the sampling circuit comprising multiplexor 360 and delay element 358 when reset is de-asserted; or in the case of ADPLL 450 comprising frequency-based PD 352, asserting the reset signal to reset FCW integrator 420 of frequency-based PD 352 to zero).

[0051] Block 604 comprises replacing the fractional portion of the locking phase with a desired fractional phase, wherein the desired fractional phase is one of one or more fractional phases of the input signal (e.g., in the case of ADPLL 350, using a circuit such as adder 356 for subtracting the sampled DCO fractional phase from the desired fractional phase to determine a phase difference; or in the case of ADPLL 450, a circuit such as adder 453 for adding the desired fractional phase to the output of FCW integrator 420, once the reset signal is de-asserted).

[0052] Block 604 comprises biasing a phase of a time-to-digital converter (TDC) of the ADPLL to the desired fractional phase (e.g., biasing TDC 310 of ADPLL 350 or TDC 410 of ADPLL 450), wherein the TDC is configured to detect a fractional phase of a digital controlled oscillator (DCO) (e.g., DCO 306 of ADPLL 350 or DCO 406 of ADPLL 450) for generating the output signal of the ADPLL, and wherein the phase noise of the ADPLL is minimized when the phase of the TDC is biased to the desired fractional phase (e.g., as shown in FIG. 5).

[0053] With reference now to FIG. 7, an example wireless communication system 700 in which aspects of this disclosure may be employed, is illustrated. As shown, wireless communication system 700 includes Access Point (AP) 710 in communication with Access Terminal (AT) 720. Unless otherwise noted, the terms "access terminal" and "access point" are not intended to be specific or limited to any particular Radio Access Technology (RAT). In general, access terminals may be any wireless communication device allowing a user to communicate over a communications network (e.g., a mobile phone, router, personal computer, server, entertainment device, Internet of Things (IoT) / Internet of Everything (IoE) capable device, in-vehicle communication device, etc.), and may be alternatively referred to in different RAT environments as a User Device (UD), a Mobile Station (MS), a Subscriber Station (STA), a User Equipment (UE), etc.

[0054] Similarly, an access point may operate according to one or several RATs in communicating with access terminals depending on the network in which the access point is deployed, and may be alternatively referred to as a Base Station (BS), a Network Node, a NodeB, an evolved NodeB (eNB), etc.

[0055] In the example of FIG. 7, AP 710 and the AT 720 each generally include a wireless communication device (represented by communication devices 772 and 722) for communicating with other network nodes via at least one designated RAT. Communication devices 772 and 722 may be variously configured for transmitting and encoding signals (e.g., messages, indications, information, and so on), and, conversely, for receiving and decoding signals (e.g., messages, indications, information, pilots, and so on) in accordance with the designated RAT. Communication device 772 of AP 710 includes RAT transceiver 740 configured to operate in accordance with a given RAT (e.g., Bluetooth®, Bluetooth® Low Energy, Wi-Fi, etc.). Similarly, communication device 722 of the AT 720 includes RAT transceiver 750 configured to operate in accordance with the RAT. As used herein, a "transceiver" may include a transmitter circuit, a receiver circuit, or a combination thereof, but need not provide both transmit and receive functionalities in all designs. For example, a low functionality receiver circuit may be employed in some designs to reduce costs when providing full communication is not necessary (e.g., a Wi-Fi chip or similar circuitry simply providing low-level sniffing). RAT transceivers 740 and 750 may include ADPLL 742 and ADPLL 752, respectively, which may be configured according to exemplary ADPLLs 350/450 described previously.

[0056] Further, AP 710 and AT 720 may also each generally include a communication controller (represented by communication controllers 714 and 724) for controlling operation of their respective communication devices 772 and 722 (e.g., directing, modifying, enabling, disabling, etc.). Communication controllers 714 and 724 may operate at the direction of, or otherwise in conjunction with, respective host system functionality (illustrated as processing systems 716 and 726 and memory components 718 and 728). In some designs, communication controllers 714 and 724 may be partly or wholly subsumed by the respective host system functionality.

[0057] Turning to the illustrated communication in more detail, AT 720 may transmit and receive messages via wireless link 730 with the AP 710, the messages including information related to various types of communication (e.g., voice, data, multimedia services, associated control signaling, etc.). Wireless link 730 may operate over a communication medium of interest, shown by way of example in FIG. 7 as medium 732, which may be shared with other communications as well as other RATs. A medium of this type may be composed of one or more frequency, time, and/or space communication resources (e.g., encompassing one or more channels across one or more carriers) associated with communications between one or more transmitter / receiver pairs, such as AP 710 and AT 720 for medium 732.

[0058] As a particular example, medium 732 may correspond to at least a portion of an unlicensed frequency band shared with other RATs. In general, AP 710 and AT 720 may operate via wireless link 730 according to one or more RATs depending on the network in which they are deployed. These networks may include, for example, different variants of Code Division Multiple Access (CDMA) networks, Time Division Multiple Access (TDMA) networks, Frequency Division Multiple Access (FDMA) networks, Orthogonal FDMA (OFDMA) networks, Single-Carrier FDMA (SC-FDMA) networks, and so on. Although different licensed frequency bands have been reserved for such communications (e.g., by a government entity such as the Federal Communications Commission (FCC) in the United States), certain communication networks, in particular those employing small cell access points, have extended operation into unlicensed frequency bands such as the Unlicensed National Information Infrastructure (U-NII) band used by Wireless Local Area Network (WLAN) technologies, most notably IEEE 802. l lx WLAN technologies generally referred to as "Wi-Fi."

[0059] Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. [0060] Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

[0061] The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

[0062] Accordingly, an embodiment of the invention can include a computer-readable media embodying a method for improving phase noise in ADPLLs. Accordingly, the invention is not limited to illustrated examples and any means for performing the functionality described herein are included in embodiments of the invention.

[0063] While the foregoing disclosure shows illustrative embodiments of the invention, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the embodiments of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Claims

CLAIMS WHAT TS CLAIMED TS:

1. A method of controlling phase noise in an all-digital phase-locked loop (ADPLL), the method comprising:

sampling a fractional portion of a locking phase of the ADPLL, wherein the locking phase is a phase offset between an output signal of the ADPLL and an input signal of the ADPLL when the ADPLL enters a phase-locked loop;

replacing the fractional portion of the locking phase with a desired fractional phase, wherein the desired fractional phase is one of one or more fractional phases of the input signal; and

biasing a phase of a time-to-digital converter (TDC) of the ADPLL to the desired fractional phase, wherein the TDC is configured to detect a fractional phase of a digital controlled oscillator (DCO) for generating the output signal of the ADPLL, and wherein the phase noise of the ADPLL is minimized when the phase of the TDC is biased to the desired fractional phase.

2. The method of claim 1, wherein the ADPLL comprises a frequency -based phase detector, and wherein sampling the fractional portion of the locking phase of the ADPLL comprises sampling the fractional phase of the DCO when the ADPLL enters the phase-locked loop, to determine a sampled DCO fractional phase.

3. The method of claim 2, wherein replacing the fractional portion of the locking phase with the desired fractional phase comprises subtracting the sampled DCO fractional phase from the desired fractional phase to determine a phase difference.

4. The method of claim 3, wherein biasing the phase of the TDC of the ADPLL to the desired fractional phase comprises adding the phase difference to the locking phase.

5. The method of claim 2, wherein the ADPLL enters the phase-locked loop when a reset signal is de-asserted.

6. The method of claim 5, further comprising preventing the locking phase from affecting the DCO while the reset signal is asserted.

7. The method of claim 1, wherein the ADPLL comprises a phase-based phase detector, and wherein sampling the fractional portion of the locking phase of the ADPLL comprises asserting a reset signal to reset a frequency control word (FCW) integrator of the phase-based phase detector to zero.

8. The method of claim 7, wherein replacing the fractional portion of the locking phase with the desired fractional phase comprises adding the desired fractional phase to an output of the FCW integrator once the reset signal is de-asserted.

9. The method of claim 7, wherein the ADPLL enters the phase-locked loop when the reset signal is de-asserted.

10. The method of claim 7, further comprising preventing the locking phase from affecting the DCO while the reset signal is asserted.

11. An apparatus comprising:

an all-digital phase-locked loop (ADPLL), wherein the ADPLL comprises: a digital controlled oscillator (DCO) configured to generate an output signal of the ADPLL;

a time-to-digital converter (TDC) configured to detect a fractional phase of the

DCO;

a sampling circuit configured to sample a fractional portion of a locking phase of the ADPLL, wherein the locking phase is a phase offset between the output signal of the ADPLL and an input signal of the ADPLL when the ADPLL enters a phase-locked loop; and

a circuit configured to replace the fractional portion of the locking phase with a desired fractional phase, wherein the desired fractional phase is one of one or more fractional phases of the input signal;

wherein a phase of the TDC is biased to the desired fractional phase to minimize phase noise of the ADPLL.

12. The apparatus of claim 11, wherein the ADPLL comprises a frequency -based phase detector, and wherein the sampling circuit is configured to sample the fractional phase of the DCO when the ADPLL enters the phase-locked loop, to determine a sampled DCO fractional phase.

13. The apparatus of claim 12, wherein the circuit is configured to subtract the sampled DCO fractional phase from the desired fractional phase to determine a phase difference.

14. The apparatus of claim 13, further comprising an adder configured to add the phase difference to the locking, to bias the phase of the TDC to the desired fractional phase.

15. The apparatus of claim 12, wherein the ADPLL is configured to enter the phase- locked loop when a reset signal is de-asserted.

16. The apparatus of claim 15, further comprising a multiplexor configured to prevent the locking phase from affecting the DCO while the reset signal is asserted.

17. The apparatus of claim 11, wherein the ADPLL comprises a phase-based phase detector, and wherein the sampling circuit is configured to assert a reset signal to reset a frequency control word (FCW) integrator of the phase-based phase detector to zero, to sample the fractional portion of the locking phase of the ADPLL.

18. The apparatus of claim 17, wherein the circuit is configured to add the desired fractional phase to an output of the FCW integrator once the reset signal is de-asserted, to replace the fractional portion of the locking phase with the desired fractional phase.

19. The apparatus of claim 17, wherein the ADPLL enters the phase-locked loop when the reset signal is de-asserted.

20. The apparatus of claim 17, further comprising a multiplexor configured to prevent the locking phase from affecting the DCO while the reset signal is asserted.

21. An apparatus comprising:

an all-digital phase-locked loop (ADPLL) comprising:

means for sampling a fractional portion of a locking phase of the ADPLL, wherein the locking phase is a phase offset between an output signal of the ADPLL and an input signal of the ADPLL when the ADPLL enters a phase-locked loop;

means for replacing the fractional portion of the locking phase with a desired fractional phase, wherein the desired fractional phase is one of one or more fractional phases of the input signal; and

means for biasing a phase of a time-to-digital converter (TDC) of the ADPLL to the desired fractional phase, wherein the TDC comprises means for detecting a fractional phase of a digital controlled oscillator (DCO) for generating the output signal of the ADPLL, and wherein phase noise of the ADPLL is minimized when the phase of the TDC is biased to the desired fractional phase.

22. The apparatus of claim 21, wherein the ADPLL comprises means for frequency- based phase detection, and wherein the means for sampling the fractional portion of the locking phase of the ADPLL comprises means for sampling the fractional phase of the DCO when the ADPLL enters the phase-locked loop, to determine a sampled DCO fractional phase.

23. The apparatus of claim 22, wherein the means for replacing the fractional portion of the locking phase with the desired fractional phase comprises means for subtracting the sampled DCO fractional phase from the desired fractional phase to determine a phase difference.

24. The apparatus of claim 23, wherein the means for biasing the phase of the TDC of the ADPLL to the desired fractional phase comprises means for adding the phase difference to the locking phase.

25. The apparatus of claim 22, wherein the ADPLL enters the phase-locked loop when a reset signal is de-asserted.

26. The apparatus of claim 25, further comprising means for preventing the locking phase from affecting the DCO while the reset signal is asserted.

27. The apparatus of claim 21, wherein the ADPLL comprises means for phase- based phase detection, and wherein sampling the fractional portion of the locking phase of the ADPLL comprises asserting a reset signal to reset a frequency control word (FCW) integrator of the means for phase-based phase detection to zero.

28. The apparatus of claim 27, wherein the means for replacing the fractional portion of the locking phase with the desired fractional phase comprises means for adding the desired fractional phase to an output of the FCW integrator once the reset signal is de-asserted.

29. The apparatus of claim 27, further comprising means for preventing the locking phase from affecting the DCO while the reset signal is asserted.

30. A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for controlling phase noise in an all-digital phase-locked loop (ADPLL), the non-transitory computer-readable storage medium comprising:

code for sampling a fractional portion of a locking phase of the ADPLL, wherein the locking phase is a phase offset between an output signal of the ADPLL and an input signal of the ADPLL when the ADPLL enters a phase-locked loop;

code for replacing the fractional portion of the locking phase with a desired fractional phase, wherein the desired fractional phase is one of one or more fractional phases of the input signal; and

code for biasing a phase of a time-to-digital converter (TDC) of the ADPLL to the desired fractional phase, wherein the TDC is configured to detect a fractional phase of a digital controlled oscillator (DCO) for generating the output signal of the ADPLL, and wherein the phase noise of the ADPLL is minimized when the phase of the TDC is biased to the desired fractional phase.