WO2019033825A1 - 驱动电路及其控制方法、显示面板和显示装置 - Google Patents

驱动电路及其控制方法、显示面板和显示装置 Download PDF

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Publication number
WO2019033825A1
WO2019033825A1 PCT/CN2018/089114 CN2018089114W WO2019033825A1 WO 2019033825 A1 WO2019033825 A1 WO 2019033825A1 CN 2018089114 W CN2018089114 W CN 2018089114W WO 2019033825 A1 WO2019033825 A1 WO 2019033825A1
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Prior art keywords
signal
circuit
sub
logic board
interface
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English (en)
French (fr)
Inventor
刘媛媛
刘晓石
袁先锋
王洪军
汪敏
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US16/332,935 priority Critical patent/US10726755B2/en
Publication of WO2019033825A1 publication Critical patent/WO2019033825A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a driving circuit and a control method thereof, a display panel, and a display device.
  • Existing liquid crystal display devices such as televisions, monitors, notebooks, etc., mainly include components such as a signal system, a logic board, a gate drive sub-circuit, an array substrate, and a color filter substrate.
  • the gate driving sub-circuit is used for controlling the gate voltage of the thin film transistor on the array substrate, thereby controlling the opening and closing of the thin film transistor;
  • the signal system is for providing a control signal to the liquid crystal display panel, specifically, the control signal sent by the signal system After being transmitted to the logic board, the logic board completes the processing of the control signal, and then transmits the processed control signal to the gate driving sub-circuit.
  • the control signals emitted by the signal system typically include power signals, image signals, and timing control signals.
  • the abnormal control signal is liable to damage the gate driving sub-circuit.
  • the liquid crystal display panel will enter the self-protection mode, the logic board does not receive the control signal sent by the signal system, and the logic board generates a corresponding control signal and sends it to the gate drive sub-circuit, such as a logic board.
  • a full black picture signal, a gray scale picture signal, and the like are generated, thereby preventing the image abnormality signal from adversely affecting the gate driving sub-circuit.
  • the logic board of the liquid crystal display panel When the timing control signal is abnormal, the logic board of the liquid crystal display panel generally does not process, or is the same as the above-described image signal abnormality.
  • the above two kinds of control signal abnormality processing methods all make the gate driving sub-circuit still work when the control signal is abnormal, but the gate driving sub-circuit is easily damaged in the abnormal working state for a long time, and the abnormal display of the liquid crystal display panel is caused.
  • An aspect of the present disclosure provides a driving circuit including a logic board, a gate driving sub-circuit, and an interface control sub-circuit.
  • the interface control sub-circuit is configured to detect a timing control signal outputted by the logic board to the gate driving sub-circuit via the signal transmission interface, and in response to detecting that the timing control signal does not satisfy the preset condition, the signal transmission interface of the control logic board stops to the gate
  • the pole drive subcircuit outputs a timing control signal.
  • the timing control signal is a clock signal
  • the interface control sub-circuit is configured to detect a clock signal output by the logic board to the gate driving sub-circuit via the signal transmission interface, and is not satisfied in response to detecting the clock signal
  • the interface control sub-circuit includes a detection circuit unit and a protection circuit unit.
  • the detection circuit unit is configured to detect a signal frequency of a clock signal output from the logic board to the gate drive sub-circuit via the signal transmission interface, and transmit the detected signal frequency to the protection circuit unit.
  • the protection circuit unit is configured to determine whether the signal frequency of the received clock signal satisfies a preset signal frequency range, and the signal transmission interface of the control logic board stops to the gate in response to the signal frequency of the clock signal not meeting the preset signal frequency range
  • the drive subcircuit outputs a clock signal.
  • the detection circuit unit includes a period detector and a frequency calculator.
  • the period detector is configured to detect a signal period of a row start signal output by the logic board to the gate drive sub-circuit via the signal transmission interface.
  • the frequency calculator is configured to calculate a signal frequency of the clock signal according to a signal period of the line start signal detected by the period detector, and send the calculated signal frequency to the circuit protection circuit unit.
  • the signal frequency of the clock signal is equal to the screen resolution of the display panel in which the drive circuit is used divided by the signal period of the line start signal detected by the period detector.
  • the preset signal frequency range is [25 MHz, 110 MHz].
  • Another aspect of the present disclosure provides a display panel including any of the above-described driving circuits.
  • Yet another aspect of the present disclosure provides a display device including any of the above display panels.
  • a further aspect of the present disclosure provides a control method of any of the above driving circuits, comprising: detecting, by an interface control sub-circuit, a timing control signal outputted by a logic board to a gate driving sub-circuit via a signal transmission interface; in response to detecting The timing control signal does not satisfy the preset condition, and the signal transmission interface of the logic board is controlled by the interface control sub-circuit to stop outputting the timing control signal to the gate driving sub-circuit.
  • detecting, by the interface control sub-circuit, a timing control signal outputted by the logic board to the gate driving sub-circuit via the signal transmission interface includes: detecting, by the interface control sub-circuit, signaling by the logic board The signal frequency of the clock signal output by the interface to the gate drive subcircuit.
  • detecting, by the interface control sub-circuit, a signal frequency of a clock signal output by the logic board to the gate driving sub-circuit via a signal transmission interface includes: determining, by the interface control sub-circuit Whether the detected signal frequency of the clock signal satisfies the preset signal frequency range.
  • controlling, by the interface control sub-circuit, a signal transmission interface of the logic board to stop outputting timing to the gate driving sub-circuit includes: in response to the detected signal frequency of the clock signal not satisfying the preset signal frequency range, controlling, by the interface control sub-circuit, the signal transmission interface of the logic board to stop to the gate
  • the pole drive subcircuit outputs a clock signal.
  • detecting, by the interface control sub-circuit, a signal frequency of a clock signal output by the logic board to the gate driving sub-circuit via a signal transmission interface includes: detecting, by the interface control sub-circuit a signal period of a row start signal outputted by the logic board to the gate driving subcircuit via a signal transmission interface; and calculating a signal frequency of the clock signal according to the detected signal period of the row start signal .
  • calculating the signal frequency of the clock signal according to the detected signal period of the row start signal includes: dividing a screen resolution of the display panel in which the driving circuit is used by detection The signal period of the line start signal is obtained, and the obtained value is taken as the signal frequency of the clock signal.
  • the preset signal frequency range is [25 MHz, 110 MHz].
  • FIG. 1 is a structural block diagram of a driving circuit according to an embodiment of the present disclosure
  • FIG. 2 is a structural block diagram of an interface control sub-circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 3 is a structural block diagram of a detecting circuit unit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 4 is a flowchart of a method for controlling a driving circuit according to an embodiment of the present disclosure
  • FIG. 5 is a control flow of a driving circuit provided by an embodiment of the present disclosure.
  • connection In the description of the present disclosure, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; can be mechanical or electrical; can be directly connected or indirectly connected through an intermediate medium. The specific meanings of the above terms in the present disclosure can be understood in the specific circumstances by those skilled in the art.
  • FIG. 1 is a block diagram of a driving circuit provided by an embodiment of the present disclosure.
  • the driving circuit shown in FIG. 1 includes a logic board 1, a gate driving sub-circuit 2, and an interface control sub-circuit 3.
  • the logic board 1 is also referred to as a screen driver board and a TCON board, and is configured to convert the received Low-Voltage Differential Signaling (LVDS) image data input signal into a timing control signal capable of driving the display screen, and then The processed timing control signal is transmitted to the LVDS receiving chip of the display.
  • the logic board 1 is provided with a signal transmission interface (I/O interface) to transmit or receive signals or data through a signal transmission interface.
  • the I/O interface is internally provided with a plurality of special registers and corresponding control logic circuits, and the interface control sub-circuit 3 can send an instruction to the I/O interface of the logic board 1 to control the I/O interface of the logic board 1 to be turned on and off. In order to achieve control of the signal transmission of the logic board.
  • the gate driving sub-circuit 2 is configured to receive the timing control signal processed by the logic board 1, and control the operating state of the thin film transistor in the display screen according to the received timing control signal.
  • the interface control sub-circuit 3 is configured to detect a timing control signal outputted by the logic board 1 to the gate driving sub-circuit 2 via the signal transmission interface, and to control signal transmission of the logic board 1 in response to detecting that the timing control signal does not satisfy the preset condition
  • the interface stops outputting the timing control signal to the gate drive sub-circuit 2.
  • the interface control sub-circuit 3 can control the signal transmission interface of the logic board 1 to operate normally to output the timing control signal to the gate driving sub-circuit 2.
  • the interface control sub-circuit 3 can stop outputting the timing control signal to the gate driving sub-circuit 2 by controlling the signal transmission interface of the control logic board 1 to be turned off after determining that the timing control signal input from the logic board 1 to the gate driving sub-circuit 2 is abnormal. Therefore, the gate driving sub-circuit 2 does not work when the timing control signal is abnormal, thereby protecting the safety of the gate driving sub-circuit 2, realizing automatic protection of the display panel mounted with the driving circuit, and ensuring the driving circuit and the display panel And the life of the display device.
  • the interface control sub-circuit 3 can continue to detect and determine the next timing control signal, thereby implementing the transmission of the timing control signal. Control of the signal transmission interface of the logic board 1, and thus control of the gate drive sub-circuit 2.
  • the signal transmission interface of the control logic board 1 is turned off, so that the gate driving sub-circuit 2 stops operating, and then if it is detected that the timing control signal becomes normal, the signal transmission interface of the logic board 1 can be controlled. Turn on, causing the gate drive sub-circuit 2 to resume operation.
  • the interface control sub-circuit 3 may be separately integrated on a chip, or integrated on the logic board 1, or integrated on other chips in the drive circuit. In fact, the integrated position of the control interface sub-circuit 3 can be set as it is.
  • the timing control signals input from the logic board 1 to the gate driving sub-circuit 2 may include various types, and different kinds of timing control signals may correspond to different preset conditions.
  • the timing control signal can be a clock signal.
  • the signal frequency of the clock signal input from the logic board 1 to the gate driving sub-circuit 2 is too large, the screen display content is refreshed too fast, causing damage to the gate driving sub-circuit 2 and other devices;
  • the signal frequency of the clock signal input from the board 1 to the gate driving sub-circuit 2 is too small, the screen display content is refreshed too slowly, affecting the display of the screen content, and also causing damage to the liquid crystal panel device. Therefore, when the timing control signal is a clock signal, the preset condition may be a signal frequency range of the clock signal.
  • the interface control sub-circuit 3 may be specifically configured to detect a clock signal output from the logic board 1 to the gate drive sub-circuit 2 via the signal transmission interface, and in response to detecting that the clock signal does not satisfy the preset signal In the frequency range, the signal transmission interface of the control logic board 1 stops outputting the clock signal to the gate drive sub-circuit 2.
  • the interface control sub-circuit 3 may include a detection circuit unit 31 and a protection circuit unit 32.
  • the detection circuit unit 31 is configured to detect a signal frequency of a clock signal output from the logic board 1 to the gate drive sub-circuit 2 via the signal transmission interface, and transmit the detected signal frequency to the protection circuit unit 32.
  • the protection circuit unit 32 is configured to determine whether the signal frequency of the received clock signal satisfies a preset signal frequency range, and to control the signal transmission interface of the logic board 1 in response to the signal frequency of the received clock signal not satisfying the preset signal frequency range The output of the clock signal to the gate drive sub-circuit 2 is stopped.
  • the detecting circuit unit 31 may include a period detector 311 and a frequency calculator 312, wherein the period detector 311 is configured to detect that the logic board 1 drives the gate via the signal transmission interface The signal period of the STV signal output by the circuit 2, the frequency calculator 312 is configured to calculate the signal frequency of the clock signal based on the signal period of the STV signal detected by the period detector 311, and transmit the calculated signal frequency to the circuit protection circuit unit 32. .
  • the frequency calculator 312 calculates the signal frequency of the clock signal according to the signal period of the STV signal, specifically, the screen resolution of the display panel can be divided by the signal period of the STV signal detected by the period detector 311, and the obtained value is used as a clock.
  • the driving circuit provided by the embodiment of the present disclosure can turn off the signal transmission interface of the control logic board when the signal frequency of the clock signal is abnormal, thereby stopping outputting the clock signal to the gate driving sub-circuit, and thus The gate driving sub-circuit is stopped, thereby protecting the safety of the gate driving sub-circuit when the signal frequency of the clock signal is abnormal.
  • the embodiment of the present disclosure further provides a display panel including the driving circuit provided by the embodiment of the present disclosure. Since the display panel includes the driving circuit, it has the advantage of the driving circuit. For the advantages of the display panel, the embodiments of the present disclosure are not described herein again.
  • the embodiment of the present disclosure further provides a display device including the display panel provided by the embodiment of the present disclosure. Since the display device includes the display panel, it has the advantage of the display panel. For the advantages of the display device, the embodiments of the present disclosure are not described herein again.
  • FIG. 4 is a flowchart of a method for controlling a driving circuit according to an embodiment of the present disclosure.
  • the control method of the driving circuit includes: at step 101, detecting, by an interface control sub-circuit, a timing control signal outputted by a logic board to a gate driving sub-circuit via a signal transmission interface; and at step 102, responding After detecting that the timing control signal does not satisfy the preset condition, the signal transmission interface of the interface control sub-board control logic board stops outputting the timing control signal to the gate driving sub-circuit.
  • the signal transmission interface of the control circuit board is controlled to be closed by the interface control sub-circuit, so as to stop outputting the timing control signal to the gate driving sub-circuit, Therefore, the gate driving sub-circuit does not work when the timing control signal is abnormal, thereby protecting the safety of the gate driving sub-circuit and ensuring the service life of the driving circuit, thereby ensuring the service life of the display panel and the display device mounted with the driving circuit. .
  • the step of detecting, by the interface control sub-circuit, the timing control signal outputted by the logic board to the gate driving sub-circuit via the signal transmission interface may be Specifically, the signal frequency of the clock signal outputted by the logic board to the gate driving sub-circuit via the signal transmission interface is detected by the interface control sub-circuit.
  • the step of stopping the output of the timing control signal to the gate driving sub-circuit by the signal transmission interface of the interface control sub-board control logic board in response to detecting that the timing control signal does not satisfy the preset condition may include: In response to detecting that the signal frequency of the clock signal does not satisfy the preset signal frequency range, the signal transmission interface of the interface control sub-board control logic board stops outputting the clock signal to the gate drive sub-circuit.
  • the step of detecting, by the interface control sub-circuit, the signal frequency of the clock signal outputted by the logic board to the gate driving sub-circuit via the signal transmission interface may include: determining, by the interface control sub-circuit, whether the signal frequency of the detected clock signal is Meet the preset signal frequency range. Further, in response to detecting that the timing control signal does not satisfy the preset condition, the step of controlling the signal transmission interface of the logic board to stop outputting the timing control signal to the gate driving sub-circuit through the interface control sub-circuit Can include:
  • the signal transmission interface of the interface control sub-board control logic board stops outputting the clock signal to the gate drive sub-circuit.
  • the step of detecting, by the interface control sub-circuit, the signal frequency of the clock signal outputted by the logic board to the gate driving sub-circuit via the signal transmission interface may be The method includes: detecting, by the interface control sub-circuit, a signal period of the STV signal outputted by the logic board to the gate driving sub-circuit via the signal transmission interface; and calculating a signal frequency of the clock signal according to the signal period of the detected STV signal.
  • the step of calculating the signal frequency of the clock signal according to the signal period of the detected STV signal may include: dividing the screen resolution of the display panel by the signal period of the detected STV signal, and using the obtained value as a clock signal Signal frequency.
  • the signal transmission interface of the control logic board is turned off to stop outputting the clock signal to the gate driving sub-circuit, and thus the gate The driving sub-circuit stops working, thereby protecting the safety of the gate driving sub-circuit when the signal frequency of the clock signal is abnormal.
  • FIG. 5 is a flow of a control method of a driving circuit according to an embodiment of the present disclosure.
  • the signal period T of the STV signal input to the gate driving sub-circuit by the logic board is detected.
  • the signal period T of the STV signal is converted into the signal frequency f clk of the clock signal.
  • a preset signal frequency range for example, 25MHZ ⁇ f ⁇ 110MHZ
  • the pole drive sub-circuit outputs the STV signal; otherwise (N branch), the signal transmission interface (I/O interface) of the gate drive sub-circuit control logic board is turned off to stop outputting the STV signal to the gate drive sub-circuit, so that the gate The drive subcircuit stops working.
  • the signal period T of the next STV signal input from the logic board to the gate driving sub-circuit is continuously detected and judged, and the above multiple steps are repeatedly performed.

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Abstract

一种驱动电路及其控制方法、显示面板和显示装置。驱动电路包括逻辑板（1）、栅极驱动电路（2）和接口控制模块（3）。接口控制模块（3）配置成检测由逻辑板（1）经由信号传输接口向栅极驱动电路（2）输出的时序控制信号，并且响应于检测到时序控制信号不满足预置条件，控制逻辑板（1）的信号传输接口停止向栅极驱动电路（2）输出时序控制信号。

Description

驱动电路及其控制方法、显示面板和显示装置
相关申请
本申请要求享有2017年8月15日提交的中国专利申请No.201710697485.8的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，特别是涉及一种驱动电路及其控制方法、显示面板以及显示装置。
背景技术
现有的液晶显示装置，如电视、监视器、笔记本等，主要包括信号系统、逻辑板、栅极驱动子电路、阵列基板、彩膜基板等组件。栅极驱动子电路用于控制阵列基板上的薄膜晶体管的栅极电压，进而控制薄膜晶体管的开启和关闭；信号系统用于给液晶显示面板提供控制信号，具体地，由信号系统发出的控制信号被传输至逻辑板，逻辑板完成对控制信号的处理后，将处理后的控制信号传输至栅极驱动子电路。
由信号系统发出的控制信号通常包括电源信号、图像信号以及时序控制信号等。当图像信号异常或时序控制信号异常时，异常的控制信号易对栅极驱动子电路造成损害。常规地，当图像信号异常时，液晶显示面板将进入自保护模式，逻辑板不接收信号系统发出的控制信号，同时逻辑板会产生相应的控制信号并发送给栅极驱动子电路，如逻辑板产生全黑画面信号、某灰阶画面信号等，从而避免图像异常信号对栅极驱动子电路造成不良影响。当时序控制信号异常时，液晶显示面板的逻辑板一般不做处理，或者与上述的图像信号异常时的处理方式相同。上述两种控制信号异常处理方式均使栅极驱动子电路在控制信号异常时仍旧工作，但是栅极驱动子电路长期处于异常工作状态下易损坏，进而导致液晶显示面板出现异常显示。
发明内容
本公开的一方面提供了一种驱动电路，包括逻辑板、栅极驱动子 电路和接口控制子电路。接口控制子电路配置成检测由逻辑板经由信号传输接口向栅极驱动子电路输出的时序控制信号，并且响应于检测到时序控制信号不满足预置条件，控制逻辑板的信号传输接口停止向栅极驱动子电路输出时序控制信号。
根据本公开的一些实施例，时序控制信号为时钟信号，并且接口控制子电路配置成检测由逻辑板经由信号传输接口向栅极驱动子电路输出的时钟信号，并且响应于检测到时钟信号不满足预设的信号频率范围，控制逻辑板的信号传输接口停止向栅极驱动子电路输出时钟信号。
根据本公开的一些实施例，接口控制子电路包括检测电路单元和保护电路单元。检测电路单元配置成检测由逻辑板经由信号传输接口向栅极驱动子电路输出的时钟信号的信号频率，并将检测到的信号频率发送至保护电路单元。保护电路单元配置成判断接收的时钟信号的信号频率是否满足预设的信号频率范围，并且响应于时钟信号的信号频率不满足预设的信号频率范围，控制逻辑板的信号传输接口停止向栅极驱动子电路输出时钟信号。
根据本公开的一些实施例，检测电路单元包括周期检测器和频率计算器。周期检测器配置成检测由逻辑板经由信号传输接口向栅极驱动子电路输出的行起始信号的信号周期。频率计算器配置成根据周期检测器检测到的行起始信号的信号周期，计算时钟信号的信号频率，并将计算的信号频率发送至电路保护电路单元。
根据本公开的一些实施例，时钟信号的信号频率等于驱动电路使用在其中的显示面板的屏幕分辨率除以周期检测器检测到的行起始信号的信号周期。
根据本公开的一些实施例，预设的信号频率范围为[25MHz，110MHz]。
本公开的另一方面提供了一种显示面板，包括上述任一种驱动电路。
本公开的又一方面提供了一种显示装置，包括上述任一种显示面板。
本公开另外的方面提供了一种上述任一种驱动电路的控制方法，包括：通过接口控制子电路检测由逻辑板经由信号传输接口向栅极驱 动子电路输出的时序控制信号；响应于检测到所述时序控制信号不满足预置条件，通过所述接口控制子电路控制所述逻辑板的信号传输接口停止向所述栅极驱动子电路输出时序控制信号。
根据本公开的一些实施例，通过接口控制子电路检测由逻辑板经由信号传输接口向栅极驱动子电路输出的时序控制信号包括：通过所述接口控制子电路检测由所述逻辑板经由信号传输接口向所述栅极驱动子电路输出的时钟信号的信号频率。
根据本公开的一些实施例，通过所述接口控制子电路检测由所述逻辑板经由信号传输接口向所述栅极驱动子电路输出的时钟信号的信号频率包括：通过所述接口控制子电路判断检测到的所述时钟信号的信号频率是否满足预设的所述信号频率范围。
根据本公开的一些实施例，响应于检测到所述时序控制信号不满足预置条件，通过所述接口控制子电路控制所述逻辑板的信号传输接口停止向所述栅极驱动子电路输出时序控制信号包括：响应于检测到的所述时钟信号的信号频率不满足预设的所述信号频率范围，通过所述接口控制子电路控制所述逻辑板的所述信号传输接口停止向所述栅极驱动子电路输出时钟信号。
根据本公开的一些实施例，通过所述接口控制子电路检测由所述逻辑板经由信号传输接口向所述栅极驱动子电路输出的时钟信号的信号频率包括：通过所述接口控制子电路检测由所述逻辑板经由信号传输接口向所述栅极驱动子电路输出的行起始信号的信号周期；以及根据检测到的所述行起始信号的信号周期，计算所述时钟信号的信号频率。
根据本公开的一些实施例，根据检测到的所述行起始信号的信号周期，计算所述时钟信号的信号频率包括：将所述驱动电路使用在其中的显示面板的屏幕分辨率除以检测到的所述行起始信号的信号周期，将所得数值作为所述时钟信号的信号频率。
根据本公开的一些实施例，预设的信号频率范围为[25MHz，110MHz]。
附图说明
图1是本公开实施例提供的一种驱动电路的结构框图；
图2是本公开实施例提供的一种驱动电路中的接口控制子电路的结构框图；
图3是本公开实施例提供的一种驱动电路中的检测电路单元的结构框图；
图4是本公开实施例提供的驱动电路的控制方法的流程图；
图5是本公开实施例提供的驱动电路的控制流。
具体实施方式
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本公开作进一步详细的说明。
在本公开的描述中，除非另有说明，“多个”的含义是两个或两个以上；术语“上”、“下”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的机或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本公开的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
下面结合附图和实施例对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
图1是本公开实施例提供的一种驱动电路的框图。图1所示的驱动电路包括逻辑板1、栅极驱动子电路2和接口控制子电路3。
逻辑板1又称屏驱动板、TCON板，其配置成将所接收到的低电压差分信号(Low-Voltage Differential Signaling，LVDS)图像数据输入信号转换成能驱动显示屏的时序控制信号，再将处理后的时序控制信号传送至显示屏的LVDS接收芯片。逻辑板1设置有信号传输接口(I/O接口)，从而通过信号传输接口发送或接收信号或数据。I/O接口内部设置有若干个专用寄存器和相应的控制逻辑电路，接口控制子电路3可以通过向逻辑板1的I/O接口发送指令，以便控制逻辑板1的I/O接 口开启和关闭，从而实现对逻辑板的信号传输的控制。
栅极驱动子电路2配置成接收经逻辑板1处理后的时序控制信号，并且根据接收的时序控制信号，控制显示屏中薄膜晶体管的工作状态。
接口控制子电路3配置成检测由逻辑板1经由信号传输接口向栅极驱动子电路2输出的时序控制信号，并且响应于检测到时序控制信号不满足预置条件，控制逻辑板1的信号传输接口停止向栅极驱动子电路2输出时序控制信号。当时序控制信号满足预置条件时，接口控制子电路3可以控制逻辑板1的信号传输接口正常工作，以便向栅极驱动子电路2输出时序控制信号。
接口控制子电路3在判断由逻辑板1输入至栅极驱动子电路2的时序控制信号异常后，通过控制逻辑板1的信号传输接口关闭，可以停止向栅极驱动子电路2输出时序控制信号，使得栅极驱动子电路2在时序控制信号异常时不工作，从而保护了栅极驱动子电路2的安全，实现了安装有该驱动电路的显示面板的自动保护，保证了驱动电路、显示面板以及显示装置的使用寿命。
接口控制子电路3在完成对当前的时序控制信号的检测和判断，以及执行相应的控制操作后，可以继续对下一时序控制信号进行检测和判断，从而实现在时序控制信号的传输过程中，对逻辑板1的信号传输接口的控制，以及因而对栅极驱动子电路2的控制。当检测到时序控制信号异常时，控制逻辑板1的信号传输接口关闭，使得栅极驱动子电路2停止工作，之后如果检测到时序控制信号变为正常，则可以控制逻辑板1的信号传输接口开启，使栅极驱动子电路2重新开始工作。
在实际实现时，接口控制子电路3可以单独集成在一芯片上，也可以集成在逻辑板1上，或集成在驱动电路中的其他芯片上。实际上，控制接口子电路3的集成位置可以根据实际进行设置。
由逻辑板1输入至栅极驱动子电路2的时序控制信号可以包括多种，并且不同种类的时序控制信号可以对应不同的预置条件。
例如，时序控制信号可以为时钟信号。相应地，如果由逻辑板1输入至栅极驱动子电路2的时钟信号的信号频率过大，则屏幕显示内容刷新过快，会对栅极驱动子电路2及其他器件造成损坏；如果由逻辑板1输入至栅极驱动子电路2的时钟信号的信号频率过小，则屏幕 显示内容刷新过慢，影响屏幕内容的显示，也会对液晶屏的器件造成损坏。因此，当时序控制信号为时钟信号时，预置条件可以是时钟信号的信号频率范围。在这样的情况下，接口控制子电路3可以特别地配置成检测由逻辑板1经由信号传输接口向栅极驱动子电路2输出的时钟信号，并且响应于检测到时钟信号不满足预设的信号频率范围，控制逻辑板1的信号传输接口停止向栅极驱动子电路2输出时钟信号。
在示例实施例中，如图2所示，接口控制子电路3可以包括检测电路单元31和保护电路单元32。检测电路单元31配置成检测由逻辑板1经由信号传输接口向栅极驱动子电路2输出的时钟信号的信号频率，并将检测到的信号频率发送至保护电路单元32。保护电路单元32配置成判断接收的时钟信号的信号频率是否满足预设的信号频率范围，并且响应于接收的时钟信号的信号频率不满足预设的信号频率范围，控制逻辑板1的信号传输接口停止向栅极驱动子电路2输出时钟信号。
当由逻辑板1输入至栅极驱动子电路2的信号是STV信号，而并非是时钟信号时，所使用的时钟信号的信号频率是根据STV信号的信号周期换算得到的，其中STV信号为行起始信号。在这样的情况下，如图3所示，检测电路单元31可以包括周期检测器311和频率计算器312，其中，周期检测器311配置成检测由逻辑板1经由信号传输接口向栅极驱动子电路2输出的STV信号的信号周期，频率计算器312配置成根据周期检测器311检测到的STV信号的信号周期，计算时钟信号的信号频率，并将计算的信号频率发送至电路保护电路单元32。
频率计算器312在根据STV信号的信号周期计算时钟信号的信号频率时，具体地，可以将显示面板的屏幕分辨率除以周期检测器311检测到的STV信号的信号周期，将所得数值作为时钟信号的信号频率。假设STV周期检测电路单元31检测到的STV信号的信号周期为T，时钟信号的信号频率为f clk，显示面板的屏幕分辨率为SR(Screen Resolution)，则f clk＝SR/T。
通过上述的结构及功能分析可知，本公开实施例提供的驱动电路可以在时钟信号的信号频率异常时，控制逻辑板的信号传输接口关闭，从而停止向栅极驱动子电路输出时钟信号，并且因而使得栅极驱动子电路停止工作，从而保护栅极驱动子电路在时钟信号的信号频率异常时的安全。
本公开实施例还提供了一种显示面板，包括本公开实施例提供的驱动电路。由于显示面板包括该驱动电路，因此具有驱动电路的优点，对于显示面板的优点，本公开实施例在此不再赘述。
本公开实施例还提供了一种显示装置，包括本公开实施例提供的显示面板。由于显示装置包括该显示面板，因此具有显示面板的优点，对于显示装置的优点，本公开实施例在此不再赘述。
本公开实施例还提供了一种上述驱动电路的控制方法。图4是本公开实施例提供的驱动电路的控制方法的流程图。参照图4，所述驱动电路的控制方法包括：在步骤101处，通过接口控制子电路检测由逻辑板经由信号传输接口向栅极驱动子电路输出的时序控制信号；以及在步骤102处，响应于检测到时序控制信号不满足预置条件，通过接口控制子电路控制逻辑板的信号传输接口停止向栅极驱动子电路输出时序控制信号。
本公开实施例在判断由逻辑板输入至栅极驱动子电路的时序控制信号异常后，通过接口控制子电路控制逻辑板的信号传输接口关闭，以便停止向栅极驱动子电路输出时序控制信号，从而使得栅极驱动子电路在时序控制信号异常时不工作，因而保护栅极驱动子电路的安全，保证驱动电路的使用寿命，进而保证了安装有该驱动电路的显示面板、显示装置的使用寿命。
当由逻辑板传输至栅极驱动子电路的时序控制信号为时钟信号时，所述的通过接口控制子电路检测由逻辑板经由信号传输接口向栅极驱动子电路输出的时序控制信号的步骤可以具体地包括：通过接口控制子电路检测由逻辑板经由信号传输接口向栅极驱动子电路输出的时钟信号的信号频率。
在这样的情况下，所述的响应于检测到时序控制信号不满足预置条件，通过接口控制子电路控制逻辑板的信号传输接口停止向栅极驱动子电路输出时序控制信号的步骤可以包括：响应于检测到时钟信号的信号频率不满足预设的信号频率范围，通过接口控制子电路控制逻辑板的信号传输接口停止向栅极驱动子电路输出时钟信号。
进一步，所述通过接口控制子电路检测由逻辑板经由信号传输接口向栅极驱动子电路输出的时钟信号的信号频率的步骤可以包括：通过接口控制子电路判断检测到的时钟信号的信号频率是否满足预设的 信号频率范围。进一步，所述响应于检测到所述时序控制信号不满足预置条件，通过所述接口控制子电路控制所述逻辑板的信号传输接口停止向所述栅极驱动子电路输出时序控制信号的步骤可以包括：
响应于检测到的时钟信号的信号频率不满足预设的信号频率范围，通过接口控制子电路控制逻辑板的信号传输接口停止向栅极驱动子电路输出时钟信号。
当由逻辑板输入至栅极驱动子电路的信号为STV信号时，所述的通过接口控制子电路检测由逻辑板经由信号传输接口向栅极驱动子电路输出的时钟信号的信号频率的步骤可以包括：通过接口控制子电路检测由逻辑板经由信号传输接口向栅极驱动子电路输出的STV信号的信号周期；以及根据检测到的STV信号的信号周期，计算时钟信号的信号频率。
进一步，所述的根据检测到的STV信号的信号周期，计算时钟信号的信号频率的步骤可以包括：将显示面板的屏幕分辨率除以检测到的STV信号的信号周期，将所得数值作为时钟信号的信号频率。
通过使用本公开实施例提供的驱动电路的控制方法，可以在时钟信号的信号频率异常时，控制逻辑板的信号传输接口关闭，以便停止向栅极驱动子电路输出时钟信号，并且因而使得栅极驱动子电路停止工作，从而保护栅极驱动子电路在时钟信号的信号频率异常时的安全。
为使本领域技术人员更加清楚地理解本公开实施例提供的驱动电路的控制方法，现通过以下示例对本公开实施例提供的驱动电路的控制方法进行详细介绍。
图5是本公开实施例提供的驱动电路的控制方法流。如图5所示，首先，检测由逻辑板输入至栅极驱动子电路的STV信号的信号周期T。接着，将STV信号的信号周期T换算成时钟信号的信号频率f clk。然后，判断计算的信号频率f clk是否满足预设的信号频率范围(例如，25MHZ≤f≤110MHZ)，如果满足(Y分支)，则控制逻辑板的信号传输接口(I/O接口)向栅极驱动子电路输出STV信号；否则(N分支)，则栅极驱动子电路控制逻辑板的信号传输接口(I/O接口)关闭，以便停止向栅极驱动子电路输出STV信号，使得栅极驱动子电路停止工作。
在完成对当前的STV信号的信号周期T的检测和判断后，继续对由逻辑板输入至栅极驱动子电路的下一STV信号的信号周期T进行检 测和判断，并且重复执行上述多个步骤。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上对本公开所提供的驱动电路、显示面板、显示装置及其控制方法进行了详细介绍，本文中应用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的方法及其核心思想；同时，对于本领域的一般技术人员，依据本公开的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开的限制。

Claims (15)

  1. 一种驱动电路，包括逻辑板、栅极驱动子电路和接口控制子电路，其中
    所述接口控制子电路配置成检测由所述逻辑板经由信号传输接口向所述栅极驱动子电路输出的时序控制信号，并且响应于检测到所述时序控制信号不满足预置条件，控制所述逻辑板的信号传输接口停止向所述栅极驱动子电路输出时序控制信号。
  2. 根据权利要求1所述的驱动电路，其中，所述时序控制信号为时钟信号，并且
    所述接口控制子电路配置成检测由所述逻辑板经由信号传输接口向所述栅极驱动子电路输出的时钟信号，并且响应于检测到所述时钟信号不满足预设的信号频率范围，控制所述逻辑板的所述信号传输接口停止向所述栅极驱动子电路输出时钟信号。
  3. 根据权利要求2所述的驱动电路，其中，所述接口控制子电路包括检测电路单元和保护电路单元，
    所述检测电路单元配置成检测由所述逻辑板经由信号传输接口向所述栅极驱动子电路输出的时钟信号的信号频率，并将检测到的信号频率发送至所述保护电路单元，
    所述保护电路单元配置成判断接收的所述时钟信号的信号频率是否满足预设的所述信号频率范围，并且响应于所述时钟信号的信号频率不满足预设的所述信号频率范围，控制所述逻辑板的信号传输接口停止向所述栅极驱动子电路输出时钟信号。
  4. 根据权利要求3所述的驱动电路，其中，所述检测电路单元包括周期检测器和频率计算器，
    所述周期检测器配置成检测由所述逻辑板经由信号传输接口向所述栅极驱动子电路输出的行起始信号的信号周期，
    所述频率计算器配置成根据所述周期检测器检测到的所述行起始信号的信号周期，计算所述时钟信号的信号频率，并将计算的所述信号频率发送至所述电路保护电路单元。
  5. 根据权利要求4所述的驱动电路，其中，所述所述时钟信号的信号频率等于所述驱动电路使用在其中的显示面板的屏幕分辨率除以 所述周期检测器检测到的所述行起始信号的信号周期。
  6. 根据权利要求2所述的驱动电路，其中，所述预设的信号频率范围为[25MHz，110MHz]。
  7. 一种显示面板，包括权利要求1-6任一项所述的驱动电路。
  8. 一种显示装置，包括权利要求7所述的显示面板。
  9. 一种如权利要求1-6任一项所述的驱动电路的控制方法，包括：
    通过接口控制子电路检测由逻辑板经由信号传输接口向栅极驱动子电路输出的时序控制信号；
    响应于检测到所述时序控制信号不满足预置条件，通过所述接口控制子电路控制所述逻辑板的信号传输接口停止向所述栅极驱动子电路输出时序控制信号。
  10. 根据权利要求9所述的控制方法，其中，所述通过接口控制子电路检测由逻辑板经由信号传输接口向栅极驱动子电路输出的时序控制信号包括：
    通过所述接口控制子电路检测由所述逻辑板经由信号传输接口向所述栅极驱动子电路输出的时钟信号的信号频率。
  11. 根据权利要求10所述的控制方法，其中，所述通过所述接口控制子电路检测由所述逻辑板经由信号传输接口向所述栅极驱动子电路输出的时钟信号的信号频率包括：
    通过所述接口控制子电路判断检测到的所述时钟信号的信号频率是否满足预设的所述信号频率范围。
  12. 根据权利要求11所述的控制方法，其中，所述响应于检测到所述时序控制信号不满足预置条件，通过所述接口控制子电路控制所述逻辑板的信号传输接口停止向所述栅极驱动子电路输出时序控制信号包括：
    响应于检测到所述时钟信号的信号频率不满足预设的所述信号频率范围，通过所述接口控制子电路控制所述逻辑板的所述信号传输接口停止向所述栅极驱动子电路输出时钟信号。
  13. 根据权利要求10所述的控制方法，其中，所述通过所述接口控制子电路检测由所述逻辑板经由信号传输接口向所述栅极驱动子电路输出的时钟信号的信号频率包括：
    通过所述接口控制子电路检测由所述逻辑板经由信号传输接口向 所述栅极驱动子电路输出的行起始信号的信号周期；以及
    根据检测到的所述行起始信号的信号周期，计算所述时钟信号的信号频率。
  14. 根据权利要求13所述的控制方法，其中，所述根据检测到的所述行起始信号的信号周期，计算所述时钟信号的信号频率包括：
    将所述驱动电路使用在其中的显示面板的屏幕分辨率除以检测到的所述行起始信号的信号周期，将所得数值作为所述时钟信号的信号频率。
  15. 根据权利要求11所述的控制方法，其中，所述预设的信号频率范围为[25MHz，110MHz]。
PCT/CN2018/089114 2017-08-15 2018-05-31 驱动电路及其控制方法、显示面板和显示装置 Ceased WO2019033825A1 (zh)

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