WO2019031755A1 - Light emitting device having nitride-based thin film, manufacturing method therefor and template for manufacturing semiconductor device - Google Patents

Light emitting device having nitride-based thin film, manufacturing method therefor and template for manufacturing semiconductor device Download PDF

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Publication number
WO2019031755A1
WO2019031755A1 PCT/KR2018/008670 KR2018008670W WO2019031755A1 WO 2019031755 A1 WO2019031755 A1 WO 2019031755A1 KR 2018008670 W KR2018008670 W KR 2018008670W WO 2019031755 A1 WO2019031755 A1 WO 2019031755A1
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semiconductor layer
layer
conductive
substrate
nitride
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PCT/KR2018/008670
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French (fr)
Korean (ko)
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최유항
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주식회사 루미스타
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes

Definitions

  • the present invention relates to a light emitting device having a nitride-based thin film and a method of manufacturing the same, and more particularly, to a light emitting device having a nitride-based thin film and a method of manufacturing the same, Type nitride semiconductor layer and minimizes damage to the nitride-based semiconductor layer of the nitride semiconductor layer, as well as a specific pattern for maximizing the light extraction efficiency on the surface of the semiconductor layer without any additional process, a method for producing the same, and a template for semiconductor device fabrication.
  • nitrides of a Group III element such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct bandgap energy band structure.
  • GaN gallium nitride
  • AlN aluminum nitride
  • nitride materials for blue and ultraviolet light Has received a lot of attention.
  • blue and green light emitting devices using gallium nitride (GaN) have been used in various applications such as large-scale color flat panel displays, traffic lights, indoor lighting, high-density light sources, high resolution output systems and optical communication.
  • nitride semiconductor layer of such a group III element is difficult to fabricate a nitride semiconductor layer of such a group III element, particularly a substrate of the same type on which gallium nitride can be grown.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy MBE
  • a sapphire substrate having a hexagonal system structure is mainly used as a heterogeneous substrate.
  • sapphire is an electrically non-conductive material, the structure of the light emitting device is limited, and it is mechanically and chemically very stable, making it difficult to cut and shape the sapphire. Accordingly, in recent years, techniques for growing nitride semiconductor layers on different substrates such as sapphire and then separating the different substrates have been studied.
  • a laser lift-off method is used to separate a sapphire substrate having poor thermal conductivity from the light emitting structure in the fabrication of the nitride-based light emitting device.
  • Such a laser lift-off method leads to thermal and mechanical deformation of the light-emitting laminated structure including the active layer.
  • the laser beam as the strong energy source is irradiated to the rear surface of the transparent sapphire substrate, strong laser beam absorption occurs at the interface between the nitride semiconductor layer of the predetermined conductivity type and the sapphire substrate.
  • a temperature of 900 degrees or more occurs instantaneously, the nitride semiconductor at the interface is thermally decomposed, and the sialic substrate can be separated.
  • mechanical and thermal damage is caused by the pressure of nitrogen generated during thermochemical decomposition of the nitride semiconductor layer and the high power of the laser beam.
  • Damage to the thin film of the laminated light emitting structure causes not only a large leakage current but also a significant decrease in the chip yield of the light emitting device and a deterioration in the overall performance of the light emitting device.
  • the portion that can significantly improve the light output of the device is the n-type semiconductor layer. Since the refractive index of the semiconductor layer made of the flat plane of the n-type semiconductor layer is greatly different from the refractive index of the atmosphere, total reflection occurring at the interface between the atmosphere and the semiconductor layer occurs and a large part of the light generated in the active layer can not be leaked to the outside. As a result, a high light output can not be expected. Therefore, it is necessary to artificially deform the surface of the semiconductor layer to prevent the total reflection from occurring, and to allow the light to leak to the outside with a minimum loss.
  • a protruding structure is formed on a semiconductor layer by wet etching using a basic solution such as KOH or NaOH on the surface of a semiconductor layer of a predetermined conductivity type.
  • the present invention is directed to a light emitting device having a nitride-based thin film that minimizes damage to a nitride-based semiconductor layer caused by heat and gas pressure in a manufacturing process accompanied by a laser lift-off method, A method for manufacturing the same, and a template for manufacturing a semiconductor device.
  • Another aspect of the present invention is to provide a light emitting device, a method of manufacturing the same, and a template for manufacturing a semiconductor device, which realizes a specific pattern maximizing light extraction efficiency on the surface of a semiconductor layer without any additional process.
  • a light emitting device having a nitride-based thin film including: an isolation layer having an opening and remaining through a separation process by a laser lift-off method; A first conductive base semiconductor layer formed on the isolation layer, the first conductive base semiconductor layer being formed of a nitride-based semiconductor, the first conductive base semiconductor layer being exposed on the outer wall through the opening, A second conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer, a second conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer, The first conductivity type semiconductor layer, and the second conductivity type semiconductor layer, wherein when the laser lift-off method is performed, 1 conductivity type base semiconductor layer.
  • the nitride-based thin film having an acute angle with respect to the surface of the first conductive type additional semiconductor layer in which the inclination angle of the outer wall of the first conductive base semiconductor layer adjacent to the opening overlaps with the opening may be provided.
  • the isolation layer may be formed of a nitride semiconductor film that is undoped so that no impurities are implanted, a non-doped material film of the same component as the first conductive base semiconductor layer, a metal oxide film, and a metal nitride film Can be formed.
  • openings around the lamination patterns may be connected when viewed from above the separation layer, such that each of the lamination patterns composed of the separation layer and the first conductive base semiconductor layer are spaced apart from each other.
  • the isolation layer and the first conductive base semiconductor layer may be formed to a thickness of 1 ⁇ or more and 5 ⁇ or less, respectively.
  • the opening disposed near the upper side of the first conductive type base semiconductor layer adjacent to the first conductive type additional semiconductor layer may have a width of 0.5 ⁇ ⁇ or more and 5 ⁇ ⁇ or less.
  • the base substrate may be any one of a printed circuit board, a nonconductive resin substrate, a silicon substrate, and a ceramic substrate.
  • the semiconductor light emitting device further includes a plurality of layers stacked on the first conductivity type semiconductor layer and having different refractive indices, wherein the plurality of layers has a refractive index smaller from the first conductivity type semiconductor layer toward the opening Can be arranged in a losing order.
  • a method of manufacturing a light emitting device having a nitride-based thin film including: preparing a substrate for a template having transparency, a separating layer formed on the substrate for template, A first conductive base semiconductor layer formed of a nitride semiconductor and an opening penetrating the first conductive base semiconductor layer and the separation layer to expose the template substrate, Preparing a template for fabricating a semiconductor device having a separation degree higher than that of the first conductivity type base semiconductor layer by a separation step by a laser lift-off method for separating the first conductivity type base semiconductor layer Forming a first conductive type additional semiconductor layer on the first conductive type base semiconductor layer, forming a first conductive type additional semiconductor layer on the first conductive type base semiconductor layer, Forming an active layer and a second conductive type semiconductor layer sequentially on the body layer, forming electrodes which are connected to the first conductive type additional semiconductor layer and the second conductive type semiconductor layer and are spaced apart from each other,
  • the separation layer includes a first buffer layer provided on the template substrate and a second buffer layer provided on the first buffer layer, wherein the first and second buffer layers are formed to have a ratio
  • the first buffer layer is formed of an undoped nitride semiconductor film, a non-doped material film of the same component as the first conductive base semiconductor layer, a metal oxide film, and a metal nitride film
  • the first buffer layer is formed of a film having a density lower than that of the buffer layer, and in the step of separating the light emitting structure from the substrate for template, the second buffer layer may be cut in the first buffer layer to remain in the first conductive base semiconductor layer have.
  • the first buffer layer may be formed to a thickness of 10 nm or more and 1 ⁇ m or less
  • the second buffer layer and the first conductive base semiconductor layer may be formed to a thickness of 1 ⁇ m or more and 5 ⁇ m or less, respectively.
  • the separation layer adjacent to the template substrate may be formed to have a width of 3 m or less.
  • the method may further include forming conductive balls spaced apart from the electrodes before separating the light emitting structure from the substrate for the template, and forming a space between the conductive balls to expose the conductive balls to the outside And disposing a base substrate on the conductive balls, wherein the base substrate may be any one of a printed circuit board, a nonconductive resin substrate, a silicon substrate, a ceramic substrate, and a glass substrate.
  • the step of attaching the first transfer substrate through the tape onto the light emitting structure located on the opposite side of the template substrate A step of separating the first transfer substrate from the light emitting structure after the step of separating the light emitting structure from the substrate for template and transferring the second transfer substrate through the tape to the opposite side of the side to which the first transfer substrate is attached, And transferring the first transfer substrate having the light emitting structure attached thereon to a predetermined position to form conductive balls spaced apart from the electrodes and arranging the base substrate on the conductive balls Step < / RTI >
  • a template for fabricating a semiconductor device includes a template substrate, a separation layer formed on the template substrate, and a base semiconductor layer formed on the separation layer, and an opening penetrating the base semiconductor layer and the isolation layer to expose the template substrate, wherein the isolation layer includes a laser lift off region for separating the template substrate from the base semiconductor layer, Method, the selectivity of the separation process is higher than that of the base semiconductor layer.
  • FIGS. 1A and 1B are cross-sectional views of a template for manufacturing a semiconductor device used in a method of manufacturing a light emitting device having a nitride-based thin film according to an embodiment of the present invention.
  • Figs. 2A to 2C are plan views showing various types of openings of templates for fabricating semiconductor devices according to embodiments of the present invention. Fig.
  • FIG 3 is a cross-sectional view illustrating a process of manufacturing a template for fabricating a semiconductor device according to an embodiment of the present invention.
  • 4A to 4D are cross-sectional views illustrating a method of manufacturing a light emitting device having a nitride-based thin film according to an embodiment of the present invention.
  • 5A to 5C are cross-sectional views illustrating a method of manufacturing a light emitting device having a nitride-based thin film according to another embodiment of the present invention.
  • 6A and 6B are microscope images of the first and second conductivity type semiconductor layers on the manufacturing method according to another embodiment of the present invention.
  • 7A and 7B are SEM images of the first conductivity type semiconductor layer of the light emitting device according to the manufacturing method according to the embodiment of the present invention.
  • 8A to 8C are cross-sectional views showing a part of the structure of a light emitting device manufactured according to an embodiment of the present invention.
  • FIG. 9 is a graph showing the power profile of the light emitting devices shown in Figs. 8A to 8C.
  • 10A to 10C are graphs showing results of simulations assuming that a laser is irradiated according to a laser lift-off method in a combination of a template for fabricating a semiconductor device according to the present invention and a gallium nitride film covering a sapphire substrate according to the prior art, admit.
  • &Quot comprises " and / or “ comprising ", as used herein, unless the recited element, step, operation, and / Or additions.
  • each layer is exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not fully reflect the actual size.
  • FIGS. 1A and 1B are cross-sectional views of a template for manufacturing a semiconductor device used in a method of manufacturing a light emitting device having a nitride-based thin film according to an embodiment of the present invention.
  • FIGS. 2A to 2C are cross- Are plan views illustrating the shapes of the various openings of the templates.
  • Semiconductor devices may be light emitting devices, various amplifiers using conventional diodes and semiconductor layers, switching devices, and the like.
  • the semiconductor element is a light emitting element.
  • a template 100 for fabricating a semiconductor device includes a template substrate 110 having transparency, a separation layer 160 formed on the template substrate 110, The base semiconductor layer 140 and the separation layer 160 are formed to penetrate through the first conductive base semiconductor layer and the template substrate 110 to expose the first conductive base semiconductor layer and the template substrate 110, (Not shown).
  • the light emitting element includes an LED using a compound semiconductor layer of a plurality of compound semiconductor layers, for example, a group III-V element, and the LED may be a colored LED emitting light such as blue, green, or red, : UltraViolet) LED.
  • the emitted light of the light emitting device can be implemented using various semiconductors, but is not limited thereto.
  • the substrate 110 for a template is formed of a substrate having transparency so that a separation process can be performed by a laser lift-off method.
  • the substrate 110 may be a substrate such as sapphire (Aluminum oxide), GaN, GaAs, InP, .
  • Various electronic device structures and the like are formed on the template substrate 110 and the template substrate 110 is separated by the separation layer 160 so that various types of light emitting devices can be manufactured.
  • the separation layer 160 is a part to which the separation process of the laser lift-off method is applied in the manufacturing process of the light emitting device, and separates the light emitting structure formed on the isolation layer 160 from the substrate 110 for template by the above- .
  • the separation layer 160 may have a selectivity higher than that of the first conductive base semiconductor layer 140 when performing the separation process for separating the template substrate 110 and the first conductive base semiconductor layer 140. [ (Selective ratio).
  • the separation layer 160 may include a first buffer layer 120 and a second buffer layer 130 sequentially formed on the template substrate 110.
  • the first buffer layer 120 and the second buffer layer 130 may be formed of an undoped nitride semiconductor film to prevent impurities from being implanted, a non-doped material layer of the same composition as the first conductive base semiconductor layer 140,
  • the first buffer layer 120 may be formed of a film having a lower density than that of the second buffer layer 130.
  • the first conductive base semiconductor layer 140 is formed of a GaN-based film doped with an n-type impurity
  • the first and second buffer layers 120 and 130 are formed of a GaN film to which no n-type impurity is implanted.
  • the first buffer layer 120 and the second buffer layer 130 may be formed of a metal oxide film or a metal nitride film such as TiN, AlN, TaN, CrN, ZrN, NiO, MgO, CaO, TiO, NiO, Y 2 O 3 , and the like.
  • the separation process by the laser lift-off method for removing the template substrate 110 from the first conductive base semiconductor layer 140 can be easily performed And the first conductive base semiconductor layer 140 containing the same major component as the second buffer layer 130 having a high density can be well grown on the second buffer layer 130 without lattice mismatch .
  • the semiconductor film into which the n-type impurity is implanted is difficult or poorly cut due to a high lattice bonding force, even when output at a high power.
  • the first and second buffer layers 120 and 130 in which the impurities are implanted have a lower bonding strength between the lattice layers compared to the first conductive base semiconductor layer 140, -Type base semiconductor layer 140, as shown in FIG.
  • the first buffer layer 120 having a low density may be formed at a lower temperature than the second buffer layer 130 during the manufacturing process and may be formed into an agglomerate form of a plurality of particles. Since the second buffer layer 130 is formed as a dense film without voids and the first buffer layer is formed as an aggregate, the first buffer layer 120 has a higher selectivity than the second buffer layer 130 in the separation process. Accordingly, the separation process is preferably performed in the first buffer layer 120, and the second buffer layer 130 may remain in the first conductive base semiconductor layer 140. Although the first buffer layer 120 is described as a separation site, the first buffer layer 120 and the second buffer layer 130 adjacent to the first buffer layer 120 may be partially removed by a separation process. The second buffer layer 130 may be formed as a smooth surface by performing a planarization process on the top surface of the second buffer layer 130.
  • the second buffer layer 130 is formed at a temperature higher than that of the first buffer layer 120 so that dislocation, melt-back, crack, pit, surface morphology, ) Defects are caused in the second buffer layer 130 to a lesser degree. Accordingly, the first conductive base semiconductor layer 140 can be well grown in the second buffer layer 130 without crystal defects.
  • the first buffer layer 120 may be formed on the second buffer layer 130 to minimize damage to the first conductive base semiconductor layer 140 and the second buffer layer 130 during the separation process, Can be formed to have a smaller thickness.
  • the first buffer layer 120 may be formed to a thickness of 10 nm or more and 1 ⁇ m or less
  • the second buffer layer 130 may be formed to a thickness of 1 ⁇ m or more and 5 ⁇ m or less.
  • the first buffer layer 120 is formed to be less than 10 nm, it can not have an effective selectivity in the separation step. If the first buffer layer 120 is formed to be more than 1 ⁇ m, 110 are not easily separated from each other and cause damage to the second buffer layer 130 and the like.
  • the second buffer layer 130 and the first conductive base semiconductor layer 140 are affected by crystal defects of the first buffer layer 120 formed as an aggregate.
  • the second buffer layer 130 is formed to have a size of more than 5 ⁇
  • the template substrate 110 is warped due to mismatching between the template substrate 110 and the second buffer layer 130 and different thermal expansion coefficients,
  • the process yield for forming a mask pattern (refer to 170 in FIG. 3) arranged on the first conductive base semiconductor layer 140 is lowered to fabricate the first conductive semiconductor layer 150.
  • the separation layer 160 adjacent to the template substrate 110 may be formed to have a width of 3 ⁇ m or less.
  • the separation area for the template substrate 110 of the first buffer layer 120 is widened.
  • the first conductive base semiconductor layer 140 is formed of a nitride based compound semiconductor made of, for example, Group 3-Group 5 or the like as the nitride based semiconductor compound, and may be doped with the first conductive type impurity.
  • the first conductive base semiconductor layer 140 may be a semiconductor material having a composition formula of InxAlyGazN (0? X? 1, 0? Y? 1, 0? Z? 1), GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN compound semiconductors.
  • the first conductive type impurity may include n-type dopants such as Si, Ge, Sn, Se, and Te.
  • the first conductive base semiconductor layer 140 may be formed as a single layer or a multilayer, but is not limited thereto.
  • the inclined angle of the outer wall of the first conductive base semiconductor layer 140 adjacent to the opening 150 has an acute angle with respect to the surface of the template substrate 110 overlapping the opening portion .
  • the outer side walls of the acute angle can be realized by reverse arc etching and the outer side inclination angles d1 and d2 of the first conductive base semiconductor layer 140 that can be formed by the reverse arc etching method are 45 degrees or more and 75 degrees or less . Since the refractive indexes of the first conductive base semiconductor layer 140 and the opening portion 150 made of the GaN compound semiconductor are different from each other, the total reflection of the light emitted from the first conductive base semiconductor layer 140 is 23.5 . Thus, when the outer inclination angle is in the above-mentioned range, light is well emitted to the outside of the first conductive base semiconductor layer 140 without total reflection, and the light extraction efficiency is improved.
  • the first conductive base semiconductor layer 140 may have a thickness of 1 ⁇ or more and 5 ⁇ or less. When the first conductive base semiconductor layer 140 is formed to be less than 1 ⁇ , the first conductive type additional semiconductor layer 210 formed on the first conductive base semiconductor layer 140 is poorly grown. If the first conductive base semiconductor layer 140 is formed to have a thickness of more than 5 mu m, mismatching between the template substrate 110, the second buffer layer 130, and the first conductive base semiconductor layer, and different thermal expansion coefficients, The process yield for forming a mask pattern (170 in FIG. 3) arranged on the first conductive base semiconductor layer 140 to fabricate the opening 150 is lowered do.
  • the conductive base semiconductor layer 140 and the isolation layer 160 may have substantially right-angled or obtuse-angled outer walls.
  • the opening 150 is formed in the interface between the separation layer 160 and the template substrate 110 by absorbing heat and gas pressure accompanying separation of the template substrate 110 and the light emitting structure, Thereby relieving stress caused by separation.
  • the opening 150 is formed to have a gradually decreasing width toward the lower region toward the template substrate 110 And may be formed by etching. As shown in FIG. 1A, the opening 150 may be formed so that the outer walls connecting the isolation layer 160 and the first conductive base semiconductor layer 140 are formed at substantially the same inclination. As shown in FIG. 1B, The opening 150a may be formed so that the layer 160a and the first conductive base semiconductor layer 140a have different inclined outer walls.
  • the outer wall of the first buffer layer 120a is formed to have a small acute angle with respect to the surface of the template substrate 110 overlapping with the opening 150a, whereby the first buffer layer 120a is formed of a template And a contact area with the substrate 110 for the first substrate. Accordingly, the embodiment of FIG. 1B can realize excellent separation easiness and minimization of damage as compared with FIG. 1A.
  • the openings 150 and 150b may be formed of a circular or polygonal shape, such as a honeycomb, as shown in FIGS. 2A and 2B. However, the openings 150 and 150b may be formed in any shape as long as the shape achieves the above- . 2C, the openings 150c around the lamination patterns are formed on the template substrate 110 so that the patterns in which the isolation layer 160 and the first conductive base semiconductor layer 140c are vertically stacked are separated from each other, When viewed on the upper side of the display unit 110, as shown in FIG. Accordingly, the heat or gas involved in the separation process according to the laser lift-off method easily flows out to the outside of the light emitting structure, and the second buffer layer 130 and the first conductive base semiconductor layer 140 The damage can be further reduced.
  • the openings 150 may be formed to have a regular arrangement, they may be irregularly arranged.
  • the opening 150 disposed in the vicinity of the upper side of the first conductive base semiconductor layer 140 may have a width W of not less than 0.5 ⁇ m and not more than 5 ⁇ m.
  • the first conductive base semiconductor layer 140 is etched in a reverse arc etching method (etching the film to have an acute angle with respect to the surface of the template substrate 110) .
  • the opening 150 is formed to have a size of more than 5 ⁇ m, the spacing between the adjacent first conductive base semiconductor layers 140 is widened and the size of the first conductive type additional semiconductor layer 210 Defects occur in the lateral growth.
  • the first conductive type additional semiconductor layer 210 through the vertical growth of the surface of the template substrate 110 is laterally grown, As a result of the faster growth, the first conductivity type additional semiconductor layer 210 due to lateral growth is formed including many defects.
  • the opening 150 does not maintain a desired shape, and light emitted from the active layer 230 at a low incident angle is not totally reflected on the sidewalls of the first conductive base semiconductor layer 140,
  • the additional semiconductor layer 210 has low electrical characteristics such as leakage current due to defects such as dislocation, pits, and cracks.
  • the base semiconductor layer 140 includes n-type impurities.
  • the semiconductor element is a switching or amplifying element, depending on the design specifications of the semiconductor element, Or a doped state for isolation.
  • the first buffer layer 120 is denser than the second buffer layer 130 and the base semiconductor layer 140, the selectivity in the separation step according to the laser lift-off method is high. Accordingly, the first buffer layer 120 functions mainly as a separation site in the laser lift-off method.
  • FIG. 3 is a cross-sectional view illustrating a process of manufacturing a template for fabricating a semiconductor device according to an embodiment of the present invention.
  • a first buffer film 122 is formed on the transparent substrate 110 for a template.
  • the first buffer layer 122 is a material layer having a selectivity of a separation process that is higher than that of the first conductivity type semiconductor film 142.
  • the first buffer layer 122 may be formed of an undoped nitride semiconductor film, A non-doped material layer having the same composition as the semiconductor layer 142, a metal oxide layer, and a metal nitride layer.
  • the first buffer film 122 may be formed at a temperature of 200 degrees to 1000 degrees.
  • the first buffer film 122 is formed of a nitride semiconductor film or a material film of the same component, hydride vapor phase epitaxy (HVPE) or metal organic chemical vapor deposition (MOCVD) may be applied. If the buffer film 122 is formed of a metal oxide film or a metal nitride film, sputtering or E-beam deposition may be applied.
  • HVPE hydride vapor phase epitaxy
  • MOCVD metal organic chemical vapor deposition
  • the first buffer layer 122 When the first buffer layer 122 is formed at the above-described temperature, it may be formed into an agglomerate form of a plurality of grains and have a low density.
  • the first buffer layer 122 may have a thickness of 10 nm or more and 1 ⁇ m or less.
  • a second buffer layer 132 is formed on the first buffer layer 122.
  • the second buffer layer 132 is formed of any one of the films listed in the first buffer layer 122 and is formed through a film formation process having a temperature higher than that of the first buffer layer 122, . Accordingly, the second buffer film 132 can be formed with high density so as to have a higher separation selectivity than the first buffer film 122.
  • the second buffer layer 132 may be formed to have a thickness lower than that of the first buffer layer 122 through a film forming process, and may be formed to a thickness of, for example, 1 ⁇ m or more and 5 ⁇ m or less.
  • a first conductive base semiconductor film 142 is formed on the second buffer film 132.
  • the first conductive base semiconductor film 142 is formed of a nitride-based semiconductor compound.
  • the first conductive base semiconductor layer 140 may be formed of a compound semiconductor such as a Group III-V element.
  • the first conductive base semiconductor layer 142 may be formed by a method such as molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metal organic chemical vapor deposition (MOCVD), chemical vapor deposition , Chemical Vapor Deposition (PECVD), and Plasma Enhanced Chemical Vapor Deposition (PECVD), but the present invention is not limited thereto.
  • MBE molecular beam epitaxy
  • HVPE hydride vapor phase epitaxy
  • MOCVD metal organic chemical vapor deposition
  • PECVD chemical vapor deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • n-type impurities may be doped into the first conductive base semiconductor film 142 simultaneously with or at the same time as the process of the above method.
  • the first buffer layer 142 can be well grown on the second buffer layer 132 without lattice mismatch.
  • the first conductive base semiconductor film 142 may be formed to a thickness of, for example, 1 ⁇ ⁇ or more and 5 ⁇ ⁇ or less.
  • a mask pattern 170 having a predetermined opening pattern is arranged on the first conductive base semiconductor film 142.
  • the opening pattern has the width described above in order to form the width W of the opening 150 to 0.5 mu m or more and 5 mu m or less.
  • the first conductive base semiconductor film 142, the second buffer film 132, and the first buffer film 122, which are disposed under the mask pattern 170, are sequentially etched by the inverse warp etching method And a plurality of openings 150 are formed.
  • a plasma etching apparatus having an alternating magnetic pole disposed adjacent to the lower portion of the chuck can be applied.
  • the etching gas is Cl.
  • a mixed gas of BCl 3, Ar, H 2, Hbr, N 2, O 2, or the like can be used and etched so that the surface of the template substrate 110 is exposed. Further, a lot of etching proceeds in a portion adjacent to the template substrate 110, rather than a portion adjacent to the mask pattern 170. This is possible by advancing at a process pressure of 20 to 200 mT and a low bias of 50 to 400 W.
  • the first conductive base semiconductor film 142, the second buffer film 132, and the first buffer film 122 may be formed by sequentially performing dry etching and wet etching, And the difference in chemical etching rate between the electrodes.
  • the inclined angles of the outer walls connecting the first conductive base semiconductor layer 140 and the separation layer 160 are formed to have substantially the same acute angle as in the case of the first embodiment, Alternatively, as shown in FIG. 1B, the inclination angle of the outer wall may be formed to be different from the lower angle.
  • the outer wall of the first conductive base semiconductor layer 140 may be formed at 45 degrees to 75 degrees.
  • the first buffer layer 120 of the isolation layer 160 adjacent to the template substrate 110 is formed with a width of 3 ⁇ m or less by controlling the process conditions of the reverse oblique etching method.
  • the inclination angle of the outer wall is an acute angle.
  • the present invention is not limited to this, and if the separation easiness and the minimization of the damage of the first conductive base semiconductor layer 140 in the separation process can be achieved, -Type base semiconductor layer 140 and the isolation layer 160 may have an obtuse angle or a substantially perpendicular outer wall.
  • the opening 150 may be formed in a polygonal shape such as a circle and a honeycomb as shown in FIGS. 2A and 2B.
  • the isolation layer 160 and the first conductive base semiconductor layer 140 may be formed as shown in FIG. May be formed to have a structure in which each of the vertically stacked patterns is spaced apart from each other and viewed when viewed on top of the template substrate 110.
  • the present invention is not limited thereto and can be manufactured in any form.
  • the base semiconductor layer 140 includes n-type impurities.
  • the base semiconductor layer 140 may be formed in a non- Or in a doped state for isolation.
  • FIGS. 4A to 4D are cross-sectional views illustrating a method of manufacturing a light emitting device having a nitride-based thin film according to an embodiment of the present invention.
  • a first conductive type additional semiconductor layer 210 is formed on the template 100. Then, as shown in FIG.
  • the first conductive type additional semiconductor layer 210 may include an n-type impurity, and InxAlyGazN (0? X? 1, 0? Y? ? 1), GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN based compound semiconductor.
  • the first conductive type additional semiconductor layer 210 may be formed of the same compound semiconductor as the first conductive type base semiconductor layer 112.
  • the first conductive type additional semiconductor layer 210 may be formed in substantially the same manner as the first conductive base semiconductor film 142. When the n-type impurity is simultaneously or simultaneously with the first conductive type semiconductor layer 142, May be doped to the additional semiconductor layer 210.
  • the first conductive type additional semiconductor layer 210 may be formed laterally in a desired shape.
  • a first interlayer 220, an active layer 230, a second intermediate layer 240, a second conductive semiconductor layer 250 (not shown) are formed on the first conductive type additional semiconductor layer 210, And a reflective layer 260 are sequentially stacked.
  • the first intermediate layer 120 may be formed of a semiconductor having a band gap wider than the band gap of the barrier layer of the active layer 130, for example, as a conductive clad layer.
  • the first intermediate layer 120 may include GaN, AlGaN, InAlGaN or a superlattice structure, and may be doped with n-type.
  • the first intermediate layer 220 may be formed of a current diffusion layer and an electron injection layer.
  • the active layer 230 may include any one of a double heterostructure, a multi-well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure.
  • the well layer may be formed of a material having a band gap smaller than the band gap of the barrier layer.
  • the active layer 230 may be formed by a method such as MOCVD, CVD, PECVD, molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). And is not limited thereto.
  • a trimetalgallium gas (TMGa), an ammonia gas (NH3), a nitrogen gas (N2), and a trimethyl indium gas (TMIn) may be implanted to form a multiple quantum well structure.
  • the second intermediate layer 240 may be, for example, a conductive type cladding layer substantially the same as the first intermediate layer 120.
  • the second intermediate layer 240 may serve as electron blocking and cladding of the active layer (MQW cladding) to improve the light emitting efficiency.
  • the second intermediate layer 240 may be formed of an AlxInyGa (1-xy) N (0? X? 1, 0? Y? 1) semiconductor and may have energy higher than the energy band gap of the active layer 230 Band gap, and may be formed to a thickness of about 100 A to about 600 A, but the present invention is not limited thereto.
  • the second intermediate layer 240 may be formed of AlzGa (1-z) N / GaN (0? Z? 1) superlattice, but is not limited thereto.
  • the second intermediate layer 240 can effectively block the electrons that are ion-implanted into the P-type to overflow and increase the hole injection efficiency.
  • the second conductive semiconductor layer 250 disposed on the second intermediate layer 240 may be formed of a semiconductor compound.
  • the second conductive semiconductor layer 250 may be formed of a compound semiconductor such as Group 3-Group 5, Group 2 or Group 6, and may be doped with a second conductive impurity.
  • the second conductivity type impurity may be a P type dopant such as Mg, Zn, Ca, Sr, and Ba.
  • the second conductive semiconductor layer 250 may be formed as a single layer or a multilayer, but the present invention is not limited thereto.
  • the second conductive semiconductor layer 250 may be formed by a method such as molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), and plasma chemical vapor deposition Method, but the present invention is not limited thereto.
  • MBE molecular beam epitaxy
  • HVPE hydride vapor phase epitaxy
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • plasma chemical vapor deposition Method plasma chemical vapor deposition Method
  • a non-cetyl cyclopentadienyl magnesium (EtCp2Mg) ⁇ Mg (Mg) containing a P-type impurity such as trimethyl gallium gas (TMGa), ammonia gas (NH3), nitrogen gas (N2), and magnesium (C 2 H 5 C 5 H 4) 2 ⁇ is injected, a second conductive semiconductor layer 250 such as a P-type GaN layer can be formed.
  • a P-type impurity such as trimethyl gallium gas (TMGa), ammonia gas (NH3), nitrogen gas (N2), and magnesium (C 2 H 5 C 5 H 4) 2 ⁇
  • the reflective layer 260 disposed on the second conductive semiconductor layer 250 reflects light generated in the active layer 230 and may be formed of Ag, Ni, Al, Rh, Pd, Ir, Ru, Au, Hf, and a combination thereof.
  • a first electrode 280 is formed on the reflective layer 260 to fill the contact hole connected to the first conductive type additional semiconductor layer 210 and electrically connected to the second conductive type semiconductor layer 250. [ Thereby forming a second electrode 290 to be connected.
  • the first and second electrodes 280 and 290 are spaced apart.
  • the first and second electrodes 280 and 290 may be formed of a conductive material such as a metal. More specifically, the first and second electrodes 280 and 290 may be formed of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Hf, and an optional combination thereof, and may be formed as a single layer or a multilayer structure.
  • the contact hole includes a sidewall insulation layer 270 on the sidewall for isolation from the surroundings.
  • conductive balls 300 are formed on the first and second electrodes 280 and 290 by soldering or the like.
  • a base substrate 310 is formed on the conductive balls 300 and the space for exposing the conductive balls 300 to the outside.
  • the base substrate 310 may be formed of a printed circuit board, a non-conductive resin substrate, a silicon substrate, a ceramic substrate, or a glass substrate.
  • the base substrate 310 is formed of a printed circuit board, Not only does it serve to support the light emitting structure connected to the base substrate 310 in the separation process according to the present invention but also remains as a final structure of the light emitting device without being removed even after the separation process.
  • the space portion is a portion formed as an empty space without interposing any member between the conductive balls 310 separated during the separation process.
  • the separation step L removes the template layer 110 from the second buffer layer 130 with the first buffer layer 120 of the separation layer 160 as a boundary, .
  • the separation step (L) thermally decomposes the first buffer layer (120) by irradiating the separation layer (160) with a laser beam of a specific wavelength through the transparent template substrate (110).
  • the laser lift-off method can use a KrF laser (248 nm) and an ArF laser (194 nm). Heat and gas accompanying the laser lift-off method are supplied through the opening 150 of the template 100 for manufacturing a semiconductor device
  • the first conductive base semiconductor layer 140 can be protected from damage such as cracks and bow.
  • the first buffer layer 120 has a lower density than the second buffer layer 130 and the template substrate 110 can be separated by a laser with a lower output power, the first conductive base semiconductor layer 140, Can be further prevented.
  • the first conductive base semiconductor layer 140 is formed in a concavo-convex shape having an acute angle of inclination, so that the protruding first conductive base semiconductor layer 140 may be formed without additional processes such as etching. Further, according to the conventional etching, the protruding pattern is not uniform, but according to the present embodiment, the protruding pattern can be formed very uniformly over the entire surface.
  • the template substrate 110 partially contacts the first buffer layer 120 by the opening 150, when the base substrate 310 supports the light emitting structure during the separation process, There is no need to intervene. Particularly, the separating force acting between the template substrate 110 and the separation layer 160 can be reduced due to the partial contact. Therefore, even when the base substrate 310 and the support such as resin adhered to the light emitting structure are not provided in the space, The separation process can proceed smoothly even with the adhesion force between the base substrate 310 and the conductive balls 300. That is, the separation process can be simplified without adding a separate support.
  • the process is more efficient than using the temporary support substrate for the separation process.
  • the second buffer layer 130 remaining on the first conductive base semiconductor layer 140 is subjected to a polishing or etching process to planarize the upper surface of the second buffer layer 130, and HCl and ultrapure water
  • the foreign matter generated in the separation step is removed by a chemical treatment using a mixed solution of the organic solvent and the organic solvent.
  • the remaining second buffer layer 130, the first conductive base semiconductor layer 140, and the first conductive type additional semiconductor layer 210 are separated from the first conductive semiconductor layer 205, .
  • the first and second adjustment layers 322 and 324 having different refractive indexes are arranged on the first conductivity type semiconductor layer 205 Layer 320 is formed.
  • the first and second control layers 322 and 324 are arranged in order of decreasing refractive index from the first conductive base semiconductor layer 140 to the opening 150 and are formed by CVD, thermal evaporation, sputtering, .
  • the first and second control layers 312 and 314 may have a refractive index lower than that of the GaN first conductivity type semiconductor layer 205 and may be formed of SiN, SiO 2, TiO 2, TiN, ZnO, Al 2 O 3, or the like.
  • FIG. 4D a light emitting device having a nitride-based thin film according to an embodiment of the present invention will be described with reference to FIG. 4D.
  • the technical meaning of each of the above-described components is omitted, and each configuration is schematically referred to.
  • the light emitting device manufactured by the manufacturing method of FIGS. 4A to 4D includes an opening 150 and a second buffer layer 130 which is a separation layer remaining through a separation process by a laser lift-off method.
  • the light emitting device includes a first conductive type base semiconductor layer 140 formed by a nitride-based semiconductor at the lower portion of the second buffer layer 130 and an outer side wall exposed through the opening 150 by sharing the opening 150,
  • an additional semiconductor layer 220 includes a first conductive type semiconductor layer 205 which is sequentially stacked.
  • the second buffer layer 130 has a selectivity higher than that of the first conductive base semiconductor layer 140 when the laser lift-off method is performed.
  • the second buffer layer 130 may be formed of any one of a non-doped nitride semiconductor film, a non-doped material layer having the same composition as the first conductive base semiconductor layer 140, a metal oxide film, and a metal nitride film .
  • the first buffer layer (see 120 in FIG. 4B) functions mainly as a separation site, but the second buffer layer 130 is also partially removed due to heat accompanying the laser lift-off method.
  • the second buffer layer 130 can suppress the electrostatic discharge in the first conductive type semiconductor layer 205, although it remains in the manufacturing process. Since the first conductive semiconductor layer 205 is doped with a high concentration of N-type impurities, electrostatic discharge may be induced, but the second buffer layer 130 may minimize electrostatic discharge.
  • impurities of the first conductivity type semiconductor layer 205 are diffused by the heat accompanying the laser lift-off method, so that the doping concentration and conductivity in the first conductivity type semiconductor layer 205 are lowered, and the applied voltage is raised .
  • the impurity diffusion is prevented by the second buffer layer 130, so that the doping concentration and the conductivity can be prevented from lowering.
  • the second buffer layer 130 extends to the outer wall of the first conductive base semiconductor layer 140, the light extraction efficiency of the first conductive semiconductor layer 205 can be further improved.
  • the inclined angle of the outer side wall of the first conductive base semiconductor layer 140 adjacent to the opening 150 may have an acute angle with respect to the surface of the first conductive type additional semiconductor layer 220 which overlaps the opening 150.
  • the opening 150 may be formed in various shapes as well as the shapes shown in Figs. 2A and 2B. 2C, the openings 150c around the stacked patterns are formed in the second buffer layer 130 so that the stacked patterns composed of the second buffer layer 130 and the first conductive base semiconductor layer 140 are separated from each other. When viewed from above, can be connected.
  • the second buffer layer 130 and the first conductive base semiconductor layer 140 may be formed to have a thickness of 1 ⁇ m or more and 5 ⁇ m or less, respectively, and the first conductive type base semiconductor layer 140, The opening disposed near the bottom side of the layer 140 may have a width of 0.5 ⁇ ⁇ or more and 5 ⁇ ⁇ or less.
  • the light emitting device includes a first interlayer 220, an active layer 230, a second intermediate layer 240, a second conductive semiconductor layer 250, and a reflective layer 250, which are sequentially stacked under the first conductive semiconductor layer 205. (260).
  • the light emitting device includes first and second electrodes 280 and 290 connected to the first and second conductivity type semiconductor layers 205 and 250 and first and second electrodes 280 and 290 connected to the first and second electrodes 280 and 290, Conductive balls 300 disposed to be spaced apart from each other and a base substrate 310 attached to the conductive balls 300.
  • the base substrate 310 may be any one of a printed circuit board, a nonconductive resin substrate, a silicon substrate, a ceramic substrate, and a glass substrate.
  • the light emitting device may include first and second control layers 312 and 314 that are stacked on the first conductive type semiconductor layer 205 and have different refractive indices from each other and the first and second control layers 312 And 314 may be arranged in the order of decreasing refractive index from the first conductivity type semiconductor layer 205 to the opening 150.
  • 5A to 5C are cross-sectional views illustrating a method of manufacturing a light emitting device having a nitride-based thin film according to another embodiment of the present invention.
  • a first interlayer 220, an active layer 230, and a third interlayer are formed on the first conductive type additional semiconductor layer 210 by using the template 100 for fabricating a semiconductor device,
  • the second intermediate layer 240, the second conductive semiconductor layer 250 and the reflective layer 260 are sequentially stacked to form the first conductive type additional semiconductor layer 210 and the second conductive type semiconductor layer 250 electrically
  • the first and second electrodes 280 and 290 are formed.
  • the first transfer substrate 340 is then attached to the first and second electrodes 280 and 290 located on the opposite side of the template substrate 110 through the tape 330.
  • the first transfer substrate 340 may be formed of any one of silicon, glass, metal, and film. Although the first transfer substrate 340 is attached to one light emitting structure in the present embodiment, in the actual manufacturing process, the first transfer substrate 340 is attached to the plurality of light emitting structures, .
  • the light emitting structure is separated from the template substrate 110 by a laser lift-off method. Since the separation process has been described in detail with reference to FIG. 4C, a description thereof will be omitted.
  • the separating force is significantly reduced compared to the template without the opening. Accordingly, even if the light emitting structure is adhered to the first transfer substrate 340 with a weak adhesive force, the light emitting structure is stably fixed to the first transfer substrate 340 at the time of separation, and a plurality of light emitting structures Position.
  • the first and second control layers 322 and 324 (see FIG. 5C) having different refractive indexes are formed on the first conductive base semiconductor layer 140 in a state where the light emitting structure is attached to the first transfer substrate 340. (Not shown).
  • the first transfer substrate 340 is detached from the light emitting structure and a tape 350 is attached to the first and second electrodes 280 and 290 opposite to the side to which the first transfer substrate 340 is attached
  • the second transfer substrate 360 is attached.
  • the second transfer substrate 360 may be formed of the same material as the first transfer substrate 340, and may transfer a plurality of the light emitting structures simultaneously for a subsequent process.
  • the conductive balls are formed apart from the first and second electrodes 280 and 290 , And the base substrate is placed on the conductive balls.
  • the base substrate may be formed of the substrate described in Fig. 4B.
  • 6A and 6B are microscope images of the first and second conductivity type semiconductor layers on the manufacturing method according to another embodiment of the present invention.
  • the first transport substrate 340 stably adheres to the surface of the second conductive type semiconductor layer 360 while the laser lift-off method is in progress, And the tape 330 are not left at all.
  • 7A and 7B are SEM images of the first conductivity type semiconductor layer of the light emitting device according to the manufacturing method according to the embodiment of the present invention.
  • the light emitting device shown in FIGS. 7A and 7B was manufactured by separating the template substrate 110 from the second buffer layer 130 by a laser lift-off method.
  • the second buffer layer 130 or the first conductive base semiconductor layer 140 is formed by the heat and the gas which are released during the separation process through the opening 150 of the template 100 for fabricating a semiconductor device, Crystal defects such as cracks and pits do not occur on the surface of the substrate.
  • FIGS. 8A to 8C are cross-sectional views showing a part of the structure of the light emitting devices manufactured according to the conventional and the embodiments of the present invention
  • FIG. 9 is a graph showing the power profile of the light emitting devices shown in FIGS. 8A to 8C.
  • 8A is a conventional light emitting device 700a, which is a light emitting device 700a in which an encapsulation layer 720a for a package is stacked on a flat first conductivity type semiconductor layer 710a.
  • the 8B is a light emitting device 700b manufactured using a template for fabricating a semiconductor device according to an embodiment of the present invention.
  • the light emitting device 700b includes a first conductive type additional semiconductor layer 702, a first conductive type base semiconductor layer 704 having a protruding shape, And a second buffer layer 706 which is left in a dummy shape.
  • the light emitting device 700b is formed by laminating an encapsulation layer 720b on a first conductive type semiconductor layer 710b.
  • FIG. 8C shows a conventional light emitting device 700c in which a first conductivity type semiconductor layer 710c conformally formed on a protruding insulating substrate 730c and an encapsulation layer 720c Element 700c.
  • the x-axis is the distance in the light emitting element from “ 0 " corresponding to " 0 " shown in Figs. 6A to 6C and the y-axis is the light emitting power.
  • the power profile 820 of the light emitting device 700b according to FIG. 6b has a higher light output power than the power profile 810 of the light emitting device 700a according to FIG. 8a.
  • 8C has a structure in which the first conductivity type semiconductor layer 710c has a structure in which the light extraction efficiency is increased by the protruding pattern of the insulating substrate 730c.
  • the power profile 820 of the light emitting element 700b has a higher light output power than the power profile 830 of the light emitting element 700c of FIG. 8C.
  • 10A to 10C are graphs showing results of simulations assuming that a laser is irradiated according to a laser lift-off method in a combination of a template for fabricating a semiconductor device according to the present invention and a gallium nitride film covering a sapphire substrate according to the prior art, admit.
  • 10A to 10C are simulation results derived from a predetermined analytical modeling equation when a laser lift-off method is applied to a GaN film laminated on a template substrate formed of sapphire or the like.
  • FIGS. 10A and 10B are the results calculated by the modeling equation when the laser lift-off method in which the laser fluence is 0.3 J / cm 2 and the pulse width is 25 ns is applied.
  • Fig. 10A the x-axis is time and the y-axis is the temperature in the GaN film of the portion irradiated with the laser.
  • "910" is a simulation result at a portion irradiated with a laser when a laser lift-off method is performed on a template for fabricating a semiconductor device formed of a GaN film having an opening according to this embodiment.
  • &Quot; 920 " refers to a portion irradiated with a laser in a GaN film covering the entire surface of a sapphire substrate according to the prior art.
  • the temperature profile for the GaN film in this embodiment is lower over the entire time than in the prior art. This is because the thermal characteristics of the openings in the present embodiment are different from those in the prior art, and the heat generated in the separation process can be concentrated in the openings.
  • the x-axis is the distance on the GaN film from the irradiated portion of the laser set to " 0 ", and the y-axis is the temperature along the distance.
  • &Quot; 930 " is the simulation result when the laser lift-off method is performed in this embodiment.
  • &Quot; 940 " is a result of simulation according to the prior art.
  • the temperature profile of the GaN film in this embodiment is lower than that of the prior art over both sides based on the irradiated portion. This is also attributed to the above-mentioned reason.
  • 10C is a simulation result for calculating a threshold value of laser fluence according to the laser pulse width in the laser lift-off method.
  • the x-axis is the pulse width of the irradiated laser, and the y-axis is the threshold of laser fluence with respect to the pulse width.
  • &Quot 950 " is a simulation result when the laser lift-off method is performed in this embodiment.
  • 960 is the result of simulation according to the prior art.
  • the threshold value of laser fluence increases as the laser pulse width increases, it can be seen that the threshold value of laser fluence in the GaN film according to this embodiment is lower than that of the prior art over the entire pulse width. This is also attributed to the above-mentioned reason.

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Abstract

Provided are a light emitting device having a nitride-based thin film, a manufacturing method therefor and a template for manufacturing a semiconductor device. The light emitting device having a nitride-based thin film, according to an embodiment of the present invention, comprises: a separation layer, which comprises an aperture part and remains after a separation process using a laser lift-off method; a first conductive base semiconductor layer, which has the outer wall exposed to the aperture part and is formed of a nitride-based semiconductor on the separation layer; a first conductive semiconductor layer comprising a first conductive additional semiconductor layer; an active layer and a second conductive semiconductor layer sequentially arranged on the first conductive semiconductor layer; and electrodes connected to the first and second conductive semiconductor layers, and spaced from each other, wherein the separation layer has higher separation process selectivity than the first conductive base semiconductor layer when the laser lift-off method is carried out.

Description

질화물계 박막을 갖는 발광 소자, 이의 제조 방법 및 반도체 소자 제조용 템플릿LIGHT-EMITTING DEVICE HAVING NITRIDE-BASED FILM, TEMPERATURE MANUFACTURING METHOD, AND TEMPLATE
본 발명은 질화물계 박막을 갖는 발광 소자 및 이의 제조 방법에 관한 것으로서, 보다 상세하게는, 레이저 리프트 오프법(laser lift-off method)을 수반하는 제조 과정에서의 열과 가스 압력으로 인하여 유발되는 소정 도전형의 질화물계 반도체층의 손상을 최소화함과 아울러서, 반도체층의 표면에 광추출 효율을 극대화시키는 특정 패턴을 추가 공정없이 실현시키는 발광 소자, 이의 제조 방법 및 반도체 소자 제조용 템플릿에 관한 것이다. The present invention relates to a light emitting device having a nitride-based thin film and a method of manufacturing the same, and more particularly, to a light emitting device having a nitride-based thin film and a method of manufacturing the same, Type nitride semiconductor layer and minimizes damage to the nitride-based semiconductor layer of the nitride semiconductor layer, as well as a specific pattern for maximizing the light extraction efficiency on the surface of the semiconductor layer without any additional process, a method for producing the same, and a template for semiconductor device fabrication.
일반적으로 질화갈륨(GaN), 질화알루미늄(AlN) 등과 같은 Ⅲ족 원소의 질화물은 열적 안정성이 우수하고 직접 천이형의 에너지 밴드(band) 구조를 갖고 있어, 최근 청색 및 자외선 영역의 발광소자용 물질로 많은 각광을 받고 있다. 특히, 질화갈륨(GaN)을 이용한 청색 및 녹색 발광 소자는 대규모 천연색 평판 표시 장치, 신호등, 실내 조명, 고밀도광원, 고해상도 출력 시스템과 광통신 등 다양한 응용 분야에 활용되고 있다.In general, nitrides of a Group III element such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct bandgap energy band structure. Recently, nitride materials for blue and ultraviolet light Has received a lot of attention. In particular, blue and green light emitting devices using gallium nitride (GaN) have been used in various applications such as large-scale color flat panel displays, traffic lights, indoor lighting, high-density light sources, high resolution output systems and optical communication.
이러한 III족 원소의 질화물 반도체층, 특히 질화갈륨이 성장될 수 있는 동종의 기판을 제작하는 것이 어려워, 유사한 결정 구조를 갖는 이종 기판에서 금속유기화학기상증착법(MOCVD) 또는 분자선 증착법(molecular beam epitaxy; MBE) 등의 공정을 통해, 질화물 반도체층이 성장된다. 이종기판으로는 육방 정계의 구조를 갖는 사파이어(sapphire) 기판이 주로 사용된다. 그러나, 사파이어는 전기적으로 부도체이므로, 발광 소자의 구조를 제한하며, 기계적, 화학적으로 매우 안정하여 절단 및 형상화(shaping) 등의 가공이 어렵다. 이에 따라, 최근에는 사파이어와 같은 이종기판 상에 질화물 반도체층들을 성장시킨 후, 이종기판을 분리하여 발광 소자를 제조하는 기술이 연구되고 있다.It is difficult to fabricate a nitride semiconductor layer of such a group III element, particularly a substrate of the same type on which gallium nitride can be grown. In the case of a heterogeneous substrate having a similar crystal structure, metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy MBE), the nitride semiconductor layer is grown. A sapphire substrate having a hexagonal system structure is mainly used as a heterogeneous substrate. However, since sapphire is an electrically non-conductive material, the structure of the light emitting device is limited, and it is mechanically and chemically very stable, making it difficult to cut and shape the sapphire. Accordingly, in recent years, techniques for growing nitride semiconductor layers on different substrates such as sapphire and then separating the different substrates have been studied.
질화물계 발광 소자의 제작에 있어서 열전도율이 불량한 사파이어 기판을 발광 구조체로부터 분리하기 위해 레이저 리프트 오프법(laser lift-off method)을 사용한다. 이러한 레이저 리프트 오프법은 활성층을 포함하는 발광 적층 구조의 열적, 기계적 변형을 가져오게 된다. 강한 에너지원인 레이저 빔을 투명한 사파이어 기판의 후면에 조사하면, 소정 도전형의 질화물 반도체층과 사파이어 기판의 계면에서 레이저 빔 흡수가 강하게 발생한다. 이로 인하여, 900도 이상의 온도가 순간적으로 발생하게 되어 계면의 질화물 반도체가 열화학 분해되고, 사이어 기판을 분리시킬 수 있다. 그러나 질화물 반도체층의 열화학 분해시 발생하는 질소의 압력과 레이저 빔으로 높은 파워로 인하여 기계적, 열적인 손상이 유발된다.A laser lift-off method is used to separate a sapphire substrate having poor thermal conductivity from the light emitting structure in the fabrication of the nitride-based light emitting device. Such a laser lift-off method leads to thermal and mechanical deformation of the light-emitting laminated structure including the active layer. When the laser beam as the strong energy source is irradiated to the rear surface of the transparent sapphire substrate, strong laser beam absorption occurs at the interface between the nitride semiconductor layer of the predetermined conductivity type and the sapphire substrate. As a result, a temperature of 900 degrees or more occurs instantaneously, the nitride semiconductor at the interface is thermally decomposed, and the sialic substrate can be separated. However, mechanical and thermal damage is caused by the pressure of nitrogen generated during thermochemical decomposition of the nitride semiconductor layer and the high power of the laser beam.
적층 발광 구조의 박막이 손상되면, 많은 누설전류(leakage current)가 발생할 뿐만이 아니라, 발광 소자의 칩수율이 크게 저하되고, 발광소자의 전체적인 성능 저하를 유발하게 된다. Damage to the thin film of the laminated light emitting structure causes not only a large leakage current but also a significant decrease in the chip yield of the light emitting device and a deterioration in the overall performance of the light emitting device.
질화물계 발광 소자의 제조에 있어 소자의 광출력을 크게 향상시킬 수 있는 부분은 n형 반도체 층이다. n형 반도체층이 평탄한 평면으로 이루어진 반도체층의 굴절률과 대기의 굴절률에 큰 차이가 있기 때문에, 대기와 반도체층 계면에서 일어나는 전반사가 발생하여 활성층에서 발생된 광의 상당부분이 외부로 유출될 수 없다. 이로 인하여, 높은 광출력이 기대될 수 없다. 따라서 반도체층 표면을 인위적으로 변형함으로써 전반사가 일어나는 것을 방지하고 최소한의 손실로 광을 외부로 유출시키는 것이 필요하다.In the production of the nitride-based light-emitting device, the portion that can significantly improve the light output of the device is the n-type semiconductor layer. Since the refractive index of the semiconductor layer made of the flat plane of the n-type semiconductor layer is greatly different from the refractive index of the atmosphere, total reflection occurring at the interface between the atmosphere and the semiconductor layer occurs and a large part of the light generated in the active layer can not be leaked to the outside. As a result, a high light output can not be expected. Therefore, it is necessary to artificially deform the surface of the semiconductor layer to prevent the total reflection from occurring, and to allow the light to leak to the outside with a minimum loss.
이에 따라 종래에는 소정 도전형의 반도체층 표면을 KOH, NaOH와 같은 염기성 용액을 이용한 습식 식각에 의해 반도체층에 돌출 형태의 구조물을 형성하였다.Thus, conventionally, a protruding structure is formed on a semiconductor layer by wet etching using a basic solution such as KOH or NaOH on the surface of a semiconductor layer of a predetermined conductivity type.
그러나, 습식 식각을 이용하는 경우, 돌출 형태의 구조물이 전면적에 균일하게 형성되는데 곤란하며, 구조물의 사이즈 또한 공정상 제한되어 있어 광추출에 한계가 있다. However, in the case of using wet etching, it is difficult to uniformly form the protruding structure over the entire surface, and the size of the structure is also limited in the process, which limits the light extraction.
본 발명이 이루고자 하는 기술적 과제는 레이저 리프트 오프법(laser lift-off method)을 수반하는 제조 과정에서의 열과 가스 압력으로 인하여 유발되는 질화물계 반도체층의 손상을 최소화하는 질화물계 박막을 갖는 발광 소자, 이의 제조 방법 및 반도체 소자 제조용 템플릿을 제공하는데 있다. SUMMARY OF THE INVENTION The present invention is directed to a light emitting device having a nitride-based thin film that minimizes damage to a nitride-based semiconductor layer caused by heat and gas pressure in a manufacturing process accompanied by a laser lift-off method, A method for manufacturing the same, and a template for manufacturing a semiconductor device.
본 발명이 이루고자 하는 다른 기술적 과제는 반도체층의 표면에 광추출 효율을 극대화시키는 특정 패턴을 추가 공정없이 실현시키는 발광 소자, 이의 제조 방법 및 반도체 소자 제조용 템플릿을 제공하는데 있다. Another aspect of the present invention is to provide a light emitting device, a method of manufacturing the same, and a template for manufacturing a semiconductor device, which realizes a specific pattern maximizing light extraction efficiency on the surface of a semiconductor layer without any additional process.
본 발명의 목적은 이상에서 언급된 목적으로 제한되지 않으며, 언급되지 않은 다른 목적들은 아래의 기재로부터 당업자에게 명확하게 이해될 수 있을 것이다. The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.
상기 기술적 과제를 이루기 위한 본 발명의 일 양태에 따르면, 질화물계 박막을 갖는 발광 소자는 개구부를 구비하고, 레이저 리프트 오프법(laser lift-off method)에 의한 분리 공정을 통해 잔류되는 분리층과, 상기 개구부를 공유하여 상기 개구부를 통해 외측벽이 노출되며 상기 분리층 상에 질화물계 반도체로 형성되는 제 1 도전형 기저 반도체층(a first conductive base semiconductor layer)과, 상기 제 1 도전형 기저 반도체층 상에 형성되는 제 1 도전형 추가 반도체층을 포함하는 제 1 도전형 반도체층과, 상기 제 1 도전형 반도체층 상에 배치되는 활성층과, 상기 활성층 상에 위치되는 제 2 도전형 반도체층, 및 상기 제 1 도전형 반도체층 및 상기 제 2 도전형 반도체층에 연결되는 전극들을 포함하고, 상기 분리층은 상기 레이저 리프트 오프법을 수행할 때, 상기 제 1 도전형 기저 반도체층보다 높은 분리 공정의 선택도를 갖는다. According to an aspect of the present invention, there is provided a light emitting device having a nitride-based thin film, including: an isolation layer having an opening and remaining through a separation process by a laser lift-off method; A first conductive base semiconductor layer formed on the isolation layer, the first conductive base semiconductor layer being formed of a nitride-based semiconductor, the first conductive base semiconductor layer being exposed on the outer wall through the opening, A second conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer, a second conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer, The first conductivity type semiconductor layer, and the second conductivity type semiconductor layer, wherein when the laser lift-off method is performed, 1 conductivity type base semiconductor layer.
다른 실시예에서, 상기 개구부와 인접한 상기 제 1 도전형 기저 반도체층의 외측벽의 경사각이 상기 개구부와 중첩되는 상기 제 1 도전형 추가 반도체층의 표면에 대하여 예각을 갖는 질화물계 박막을 가질 수 있다. In another embodiment, the nitride-based thin film having an acute angle with respect to the surface of the first conductive type additional semiconductor layer in which the inclination angle of the outer wall of the first conductive base semiconductor layer adjacent to the opening overlaps with the opening may be provided.
또 다른 실시예에서, 상기 분리층은 불순물이 주입되지 않도록 비도핑된(undoped) 질화물 반도체막, 상기 제 1 도전형 기저 반도체층과 동일 성분의 비도핑된 물질막, 금속 산화막 및 금속 질화막 중에서 어느 하나로 형성될 수 있다. In still another embodiment, the isolation layer may be formed of a nitride semiconductor film that is undoped so that no impurities are implanted, a non-doped material film of the same component as the first conductive base semiconductor layer, a metal oxide film, and a metal nitride film Can be formed.
또 다른 실시예에서, 상기 분리층과 상기 제 1 도전형 기저 반도체층으로 구성된 적층 패턴들의 각각이 서로 이격되도록, 상기 적층 패턴들 주위의 개구부는 상기 분리층의 상부에서 볼 때, 연결될 수 있다. In another embodiment, openings around the lamination patterns may be connected when viewed from above the separation layer, such that each of the lamination patterns composed of the separation layer and the first conductive base semiconductor layer are spaced apart from each other.
또 다른 실시예에서, 상기 분리층 및 상기 제 1 도전형 기저 반도체층은 각각 1μm 이상, 5μm 이하의 두께로 형성될 수 있다. In still another embodiment, the isolation layer and the first conductive base semiconductor layer may be formed to a thickness of 1 탆 or more and 5 탆 or less, respectively.
또 다른 실시예에서, 상기 제 1 도전형 추가 반도체층과 인접한 상기 제 1 도전형 기저 반도체층의 상부측 근방에 배치된 개구부는 0.5μm 이상, 5μm 이하의 폭을 가질 수 있다. In another embodiment, the opening disposed near the upper side of the first conductive type base semiconductor layer adjacent to the first conductive type additional semiconductor layer may have a width of 0.5 占 퐉 or more and 5 占 퐉 or less.
또 다른 실시예에서, 상기 베이스 기판은 인쇄회로기판, 비전도성 수지 기판, 실리콘 기판 및 세라믹 기판 중 어느 하나일 수 있다. In another embodiment, the base substrate may be any one of a printed circuit board, a nonconductive resin substrate, a silicon substrate, and a ceramic substrate.
또 다른 실시예에서, 상기 제 1 도전형 반도체층 상에 적층되며, 굴절률이 서로 상이한 복수의 층을 더 포함하고, 상기 복수의 층은 상기 제 1 도전형 반도체층으로부터 상기 개구부로 갈수록 굴절률이 작아지는 순서로 배열될 수 있다. In another embodiment, the semiconductor light emitting device further includes a plurality of layers stacked on the first conductivity type semiconductor layer and having different refractive indices, wherein the plurality of layers has a refractive index smaller from the first conductivity type semiconductor layer toward the opening Can be arranged in a losing order.
상기 기술적 과제를 이루기 위한 본 발명의 다른 양태에 따르면, 질화물계 박막을 갖는 발광 소자의 제조 방법은 투명성을 갖는 템플릿용 기판과, 상기 템플릿용 기판 상에 형성되는 분리층과, 상기 분리층 상에 질화물계 반도체로 형성되는 제 1 도전형 기저 반도체층과, 상기 템플릿용 기판을 노출시키도록 상기 제 1 도전형 기저 반도체층과 상기 분리층을 관통하는 개구부를 포함하고, 상기 템플릿용 기판과 상기 제 1 도전형 기저 반도체층을 분리하는 레이저 리프트 오프법에 의한 분리 공정을 수행할 때, 상기 분리층이 상기 제 1 도전형 기저 반도체층보다 높은 분리 공정의 선택도를 갖는 반도체 소자 제조용 템플릿을 준비하는 단계와, 상기 제 1 도전형 기저 반도체층 상에 제 1 도전형 추가 반도체층을 형성하는 단계와, 상기 제 1 도전형 추가 반도체층 상에 활성층 및 제 2 도전형 반도체층을 순차적으로 형성하는 단계와, 상기 제 1 도전형 추가 반도체층 및 상기 제 2 도전형 반도체층에 연결되며 서로 이격되는 전극들을 형성하는 단계, 및 상기 분리층에 대한 레이저 리프트 오프법에 의해, 상기 분리층 상부에 형성된 발광 구조체를 상기 템플릿용 기판으로부터 분리하는 단계를 포함한다. According to another aspect of the present invention, there is provided a method of manufacturing a light emitting device having a nitride-based thin film, the method including: preparing a substrate for a template having transparency, a separating layer formed on the substrate for template, A first conductive base semiconductor layer formed of a nitride semiconductor and an opening penetrating the first conductive base semiconductor layer and the separation layer to expose the template substrate, Preparing a template for fabricating a semiconductor device having a separation degree higher than that of the first conductivity type base semiconductor layer by a separation step by a laser lift-off method for separating the first conductivity type base semiconductor layer Forming a first conductive type additional semiconductor layer on the first conductive type base semiconductor layer, forming a first conductive type additional semiconductor layer on the first conductive type base semiconductor layer, Forming an active layer and a second conductive type semiconductor layer sequentially on the body layer, forming electrodes which are connected to the first conductive type additional semiconductor layer and the second conductive type semiconductor layer and are spaced apart from each other, And separating the light emitting structure formed on the upper part of the separation layer from the substrate for template by a laser lift-off method for the layer.
다른 실시예에서, 상기 분리층은 상기 템플릿용 기판 상에 제공되는 제 1 버퍼층 및 상기 제 1 버퍼층 상에 제공되는 제 2 버퍼층을 포함하고, 상기 제 1 및 제 2 버퍼층은 불순물이 주입되지 않도록 비도핑된(undoped) 질화물 반도체막, 상기 제 1 도전형 기저 반도체층과 동일 성분의 비도핑된 물질막, 금속 산화막, 금속 질화막 중에서 동일하거나 서로 다른 막으로 형성되며, 상기 제 1 버퍼층은 상기 제 2 버퍼층보다 낮은 치밀도를 갖는 막으로 형성되고, 상기 발광 구조체를 상기 템플릿용 기판으로부터 분리하는 단계에서, 상기 제 1 버퍼층에서 절단되어 상기 제 2 버퍼층이 상기 제 1 도전형 기저 반도체층에 잔류될 수 있다. In another embodiment, the separation layer includes a first buffer layer provided on the template substrate and a second buffer layer provided on the first buffer layer, wherein the first and second buffer layers are formed to have a ratio Wherein the first buffer layer is formed of an undoped nitride semiconductor film, a non-doped material film of the same component as the first conductive base semiconductor layer, a metal oxide film, and a metal nitride film, Wherein the first buffer layer is formed of a film having a density lower than that of the buffer layer, and in the step of separating the light emitting structure from the substrate for template, the second buffer layer may be cut in the first buffer layer to remain in the first conductive base semiconductor layer have.
또 다른 실시예에서, 상기 제 1 버퍼층은 10nm 이상, 1μm 이하의 두께로 형성되고, 상기 제 2 버퍼층 및 상기 제 1 도전형 기저 반도체층은 각각 1μm 이상, 5μm 이하의 두께로 형성될 수 있다. In yet another embodiment, the first buffer layer may be formed to a thickness of 10 nm or more and 1 μm or less, and the second buffer layer and the first conductive base semiconductor layer may be formed to a thickness of 1 μm or more and 5 μm or less, respectively.
또 다른 실시예에서, 상기 템플릿용 기판에 인접한 상기 분리층은 3μm 이하의 폭을 갖도록 형성될 수 있다. In another embodiment, the separation layer adjacent to the template substrate may be formed to have a width of 3 m or less.
또 다른 실시예에서, 상기 발광 구조체를 상기 템플릿용 기판으로부터 분리하는 단계 전에, 상기 전극들에 이격되어 형성되는 도전성 볼들을 형성하는 단계, 및 상기 도전성 볼들 사이에 상기 도전성 볼들을 외부로 노출시키는 공간부와 상기 도전성 볼들 상에 베이스 기판을 배치하는 단계를 더 포함하고, 상기 베이스 기판은 인쇄회로기판, 비전도성 수지 기판, 실리콘 기판, 세라믹 기판 및 글래스 기판 중 어느 하나일 수 있다. In yet another embodiment, the method may further include forming conductive balls spaced apart from the electrodes before separating the light emitting structure from the substrate for the template, and forming a space between the conductive balls to expose the conductive balls to the outside And disposing a base substrate on the conductive balls, wherein the base substrate may be any one of a printed circuit board, a nonconductive resin substrate, a silicon substrate, a ceramic substrate, and a glass substrate.
또 다른 실시예에서, 상기 발광 구조체를 상기 템플릿용 기판으로부터 분리하는 단계 전에, 상기 템플릿용 기판과 반대측에 위치된 상기 발광 구조체 상에 테이프를 통해 제 1 이송용 기판을 부착하는 단계를 더 포함하고, 상기 발광 구조체를 상기 템플릿용 기판으로부터 분리하는 단계 후에, 상기 제 1 이송용 기판을 상기 발광 구조체로부터 이탈시키고, 상기 제 1 이송용 기판이 부착된 측의 반대측에 테이프를 통해 제 2 이송용 기판을 부착하는 단계, 및 상기 발광 구조체가 부착된 상기 제 1 이송용 기판을 소정 위치로 이송하여, 상기 전극들에 이격되게 배치되는 도전성 볼들을 형성함과 아울러서, 상기 도전성 볼들 상의 베이스 기판을 배치하는 단계를 더 포함할 수 있다.In another embodiment, before the step of separating the light emitting structure from the template substrate, the step of attaching the first transfer substrate through the tape onto the light emitting structure located on the opposite side of the template substrate A step of separating the first transfer substrate from the light emitting structure after the step of separating the light emitting structure from the substrate for template and transferring the second transfer substrate through the tape to the opposite side of the side to which the first transfer substrate is attached, And transferring the first transfer substrate having the light emitting structure attached thereon to a predetermined position to form conductive balls spaced apart from the electrodes and arranging the base substrate on the conductive balls Step < / RTI >
상기 기술적 과제를 이루기 위한 본 발명의 다른 양태에 따르면, 반도체 소자 제조용 템플릿은 템플릿용 기판과, 상기 템플릿용 기판 상에 형성되는 분리층과, 상기 분리층 상에 질화물계 반도체로 형성되는 기저 반도체층(base semiconductor layer), 및 상기 템플릿용 기판을 노출시키도록 상기 기저 반도체층과 상기 분리층을 관통하는 개구부를 포함하고, 상기 분리층은 상기 템플릿용 기판과 상기 기저 반도체층을 분리하는 레이저 리프트 오프법을 수행할 때, 상기 기저 반도체층보다 높은 분리 공정의 선택도를 갖는다. According to another aspect of the present invention, a template for fabricating a semiconductor device includes a template substrate, a separation layer formed on the template substrate, and a base semiconductor layer formed on the separation layer, and an opening penetrating the base semiconductor layer and the isolation layer to expose the template substrate, wherein the isolation layer includes a laser lift off region for separating the template substrate from the base semiconductor layer, Method, the selectivity of the separation process is higher than that of the base semiconductor layer.
기타 실시예들의 구체적인 사항들은 상세한 설명 및 도면들에 포함되어 있다. The details of other embodiments are included in the detailed description and drawings.
본 발명에 따르면, 레이저 리프트 오프법(laser lift-off method)을 수반하는 제조 과정에서의 열과 가스 압력으로 인하여 소정 도전형의 질화물계 반도체층에서 유발되는 크랙(crack) 등의 손상을 방지할 수 있다. According to the present invention, it is possible to prevent cracks and the like caused in the nitride-based semiconductor layer of a predetermined conductivity type due to heat and gas pressure in a manufacturing process accompanied by a laser lift-off method have.
이에 더하여, 반도체 소자 제조용 템플릿을 이용하여 발광 소자를 제작함으로써, 광추출 효율을 극대화하기 위한 돌출 형태의 반도체층의 특정 패턴은 추가 공정없이 형성될 수 있다. In addition, by manufacturing the light emitting device using the template for semiconductor device fabrication, a specific pattern of the protruding semiconductor layer for maximizing the light extraction efficiency can be formed without any additional process.
도 1a 및 1b는 본 발명의 일 실시예에 따른 질화물계 박막을 갖는 발광 소자의 제조 방법에 사용되는 반도체 소자 제조용 템플릿의 단면도들이다. 1A and 1B are cross-sectional views of a template for manufacturing a semiconductor device used in a method of manufacturing a light emitting device having a nitride-based thin film according to an embodiment of the present invention.
도 2a 내지 2c는 본 발명의 실시예들에 따른 반도체 소자 제조용 템플릿들의 다양한 개구부들의 형태를 나타내는 평면도들이다. Figs. 2A to 2C are plan views showing various types of openings of templates for fabricating semiconductor devices according to embodiments of the present invention. Fig.
도 3은 본 발명의 실시예에 따른 반도체 소자 제조용 템플릿을 제조 과정을 나타내는 단면도이다. 3 is a cross-sectional view illustrating a process of manufacturing a template for fabricating a semiconductor device according to an embodiment of the present invention.
도 4a 내지 4d는 본 발명의 일 실시예에 따른 질화물계 박막을 갖는 발광 소자의 제조 방법을 나타내는 단면도들이다. 4A to 4D are cross-sectional views illustrating a method of manufacturing a light emitting device having a nitride-based thin film according to an embodiment of the present invention.
도 5a 내지 5c는 본 발명의 다른 실시예에 따른 질화물계 박막을 갖는 발광 소자의 제조 방법을 나타내는 단면도들이다. 5A to 5C are cross-sectional views illustrating a method of manufacturing a light emitting device having a nitride-based thin film according to another embodiment of the present invention.
도 6a 및 6b는 본 발명의 다른 실시예에 따른 제조 방법에 제 1 및 제 2 도전형 반도체층 측의 현미경 이미지들이다.6A and 6B are microscope images of the first and second conductivity type semiconductor layers on the manufacturing method according to another embodiment of the present invention.
도 7a 및 7b는 본 발명의 실시예에 따른 제조 방법에 의한 발광 소자의 제 1 도전형 반도체층의 SEM 이미지들이다. 7A and 7B are SEM images of the first conductivity type semiconductor layer of the light emitting device according to the manufacturing method according to the embodiment of the present invention.
도 8a 내지 8c는 종래 및 본 발명의 실시예에 따라 제조된 발광 소자들의 일부 구성을 나타내는 단면도들이다. 8A to 8C are cross-sectional views showing a part of the structure of a light emitting device manufactured according to an embodiment of the present invention.
도 9은 도 8a 내지 8c에 도시된 발광 소자들의 파워 프로파일(power profile)을 나타내는 그래프이다. 9 is a graph showing the power profile of the light emitting devices shown in Figs. 8A to 8C.
도 10a 내지 10c는 본 발명에 따른 반도체 소자 제조용 템플릿 및 종래 기술에 따른 사파이어 기판과 그 전면을 덮은 질화갈륨막의 조합에 있어서, 레이저 리프트 오프법에 따라 레이저를 조사하는 경우를 상정한 시뮬레이션에 대한 결과들이다. 10A to 10C are graphs showing results of simulations assuming that a laser is irradiated according to a laser lift-off method in a combination of a template for fabricating a semiconductor device according to the present invention and a gallium nitride film covering a sapphire substrate according to the prior art, admit.
이하, 첨부한 도면들 및 후술되어 있는 내용을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명한다. 그러나, 본 발명은 여기서 설명되어지는 실시예들에 한정되지 않고 다른 형태로 구체화될 수도 있다. 오히려, 여기서 소개되는 실시예들은 개시된 내용이 철저하고 완전해질 수 있도록 그리고 당업자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위해 제공되어지는 것이다. 명세서 전체에 걸쳐서 동일한 참조번호들은 동일한 구성요소들을 나타낸다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings and the following description. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Like reference numerals designate like elements throughout the specification.
한편, 본 명세서에서 사용된 용어는 실시예들을 설명하기 위한 것이며 본 발명을 제한하고자 하는 것은 아니다. 본 명세서에서, 단수형은 문구에서 특별히 언급되지 않는 한 복수형도 포함된다. 또한, 명세서에서 사용되는 위치 관계의 표현, 예컨대 상부, 하부, 좌측, 우측 등은 설명의 편의를 위해 기재된 것이고, 본 명세서에 도시된 도면을 역으로 보는 경우에는, 명세서에 기재된 위치 관계는 반대로 해석될 수도 있다. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. In addition, the expression of the positional relationship used in the specification, for example, the upper, lower, left, and right sides is described for convenience of explanation, and when the drawings shown in this specification are reversed, the positional relationship described in the specification is reversed .
명세서에서 사용되는 "포함한다(comprises)" 및/또는 "포함하는(comprising)"은 언급된 구성요소, 단계, 동작 및/또는 소자가 하나 이상의 다른 구성요소, 단계, 동작 및/또는 소자의 존재 또는 추가를 배제하지 않는다. &Quot; comprises " and / or " comprising ", as used herein, unless the recited element, step, operation, and / Or additions.
또한, 도면에서 각 층의 두께나 크기는 설명의 편의 및 명확성을 위하여 과장되거나 생략되거나 또는 개략적으로 도시된다. 또한 각 구성요소의 크기는 실제 크기를 전적으로 반영하지 않는다. In the drawings, the thickness and size of each layer are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not fully reflect the actual size.
이하, 도 1 내지 도 2c를 참조하여, 본 발명의 실시예들에 따른 반도체 소자 제조용 템플릿들에 대하여 상세히 설명하기로 한다. 도 1a 및 1b는 본 발명의 일 실시예에 따른 질화물계 박막을 갖는 발광 소자의 제조 방법에 사용되는 반도체 소자 제조용 템플릿의 단면도들이고, 도 2a 내지 2c는 본 발명의 실시예들에 따른 반도체 소자 제조용 템플릿들의 다양한 개구부들의 형태를 나타내는 평면도들이다. Hereinafter, templates for fabricating semiconductor devices according to embodiments of the present invention will be described in detail with reference to FIGS. 1 to 2C. FIGS. 1A and 1B are cross-sectional views of a template for manufacturing a semiconductor device used in a method of manufacturing a light emitting device having a nitride-based thin film according to an embodiment of the present invention. FIGS. 2A to 2C are cross- Are plan views illustrating the shapes of the various openings of the templates.
반도체 소자는 발광 소자, 통상적인 다이오드 및 반도체층을 이용하는 다양한 증폭, 스위칭 소자 등일 수 있다. 이하에서는, 반도체 소자가 발광 소자인 경우를 위주로 설명하기로 한다. Semiconductor devices may be light emitting devices, various amplifiers using conventional diodes and semiconductor layers, switching devices, and the like. Hereinafter, the case where the semiconductor element is a light emitting element will be mainly described.
도 1을 참조하면, 본 발명의 일 실시예에 따른 반도체 소자 제조용 템플릿(100)은 투명성을 갖는 템플릿용 기판(110), 템플릿용 기판(110) 상에 형성되는 분리층(160), 분리층(160) 상에 질화물 반도체로 형성되는 제 1 도전형 기저 반도체층(a first conductive base semiconductor layer) 및 템플릿용 기판(110)을 노출시키도록 기저 반도체층(140)과 분리층(160)을 관통하는 복수의 개구부(150)를 포함한다. Referring to FIG. 1, a template 100 for fabricating a semiconductor device according to an embodiment of the present invention includes a template substrate 110 having transparency, a separation layer 160 formed on the template substrate 110, The base semiconductor layer 140 and the separation layer 160 are formed to penetrate through the first conductive base semiconductor layer and the template substrate 110 to expose the first conductive base semiconductor layer and the template substrate 110, (Not shown).
여기서, 발광 소자는 복수의 화합물 반도체층, 예컨대, 3족-5족 원소의 화합물 반도체층을 이용한 LED를 포함하며, LED는 청색, 녹색, 또는 적색 등과 같은 광을 방출하는 유색 LED이거나 자외선(UV:UltraViolet) LED일 수 있다. 발광 소자의 방출 광은 다양한 반도체를 이용하여 구현될 수 있으며, 이에 대해 한정하지는 않는다. Here, the light emitting element includes an LED using a compound semiconductor layer of a plurality of compound semiconductor layers, for example, a group III-V element, and the LED may be a colored LED emitting light such as blue, green, or red, : UltraViolet) LED. The emitted light of the light emitting device can be implemented using various semiconductors, but is not limited thereto.
템플릿용 기판(110)은 레이저 리프트 오프법에 의해 분리 공정을 수행할 수 있도록, 투명성을 갖는 기판으로 형성되며, 예컨대, 사파이어(sapphire; 산화알루미늄), GaN, GaAs, InP, 유리 등의 기판일 수 있다. 템플릿용 기판(110) 상에 다양한 전자 소자 구조 등이 형성된 후, 템플릿용 기판(110)이 분리층(160)에 의해 분리됨으로써, 다양한 형태의 발광 소자가 제작될 수 있다. The substrate 110 for a template is formed of a substrate having transparency so that a separation process can be performed by a laser lift-off method. For example, the substrate 110 may be a substrate such as sapphire (Aluminum oxide), GaN, GaAs, InP, . Various electronic device structures and the like are formed on the template substrate 110 and the template substrate 110 is separated by the separation layer 160 so that various types of light emitting devices can be manufactured.
분리층(160)은 발광 소자의 제조 과정에서 레이저 리프트 오프법의 분리 공정이 적용되는 부분이며, 전술한 공정으로 분리층(160)의 상부에 형성된 발광 구조체와 템플릿용 기판(110)을 분리시킨다. 분리층(160)은 템플릿용 기판(110)과 제 1 도전형 기저 반도체층(140)을 분리하는 분리 공정을 수행할 때, 제 1 도전형 기저 반도체층(140)보다 높은 분리 공정의 선택도(선택비)를 갖는 물질막으로 형성된다. The separation layer 160 is a part to which the separation process of the laser lift-off method is applied in the manufacturing process of the light emitting device, and separates the light emitting structure formed on the isolation layer 160 from the substrate 110 for template by the above- . The separation layer 160 may have a selectivity higher than that of the first conductive base semiconductor layer 140 when performing the separation process for separating the template substrate 110 and the first conductive base semiconductor layer 140. [ (Selective ratio).
구체적으로, 분리층(160)은 템플릿용 기판(110) 상에 순차적으로 형성되는 제 1 버퍼층(120) 및 제 2 버퍼층(130)을 포함할 수 있다. Specifically, the separation layer 160 may include a first buffer layer 120 and a second buffer layer 130 sequentially formed on the template substrate 110.
제 1 버퍼층(120) 및 제 2 버퍼층(130)은 불순물이 주입되지 않도록 비도핑된(undoped) 질화물 반도체막, 제 1 도전형 기저 반도체층(140)과 동일 성분의 비도핑된 물질막, 금속 산화막, 금속 질화막 중에서 동일하거나 서로 다른 막으로 형성될 수 있으며, 제 1 버퍼층(120)은 제 2 버퍼층(130)보다 낮은 치밀도를 갖는 막으로 형성될 수 있다. 제 1 도전형 기저 반도체층(140)과 동일 성분의 비도핑된 물질막은 제 1 도전형 기저 반도체층(140)에서 불순물, 예컨대 n형 불순물이 주입되지 않음과 동시에 단순히 제 1 도전형 기저 반도체층(140)과 동일한 주 성분을 포함한다. 제 1 도전형 기저 반도체층(140)이 n형 불순물이 주입된 GaN 계 막으로 형성되면, 제 1 및 제 2 버퍼층들(120,130)은 n형 불순물이 주입되지 않은 GaN막으로 형성된다. 제 1 또는 제 2 버퍼층(120, 130)이 금속 산화막 또는 금속 질화막으로 형성되는 경우, TiN, AlN, TaN, CrN, ZrN, NiO, MgO, CaO, TiO, NiO, CrO, MnO, SrO, BaO 및 Y2O3 중에서 선택된 1종 이상의 물질을 포함할 수 있다. The first buffer layer 120 and the second buffer layer 130 may be formed of an undoped nitride semiconductor film to prevent impurities from being implanted, a non-doped material layer of the same composition as the first conductive base semiconductor layer 140, The first buffer layer 120 may be formed of a film having a lower density than that of the second buffer layer 130. In this case, The undoped material layer having the same composition as that of the first conductive base semiconductor layer 140 is not doped with an impurity such as an n-type impurity in the first conductive base semiconductor layer 140, Lt; RTI ID = 0.0 > 140 < / RTI > When the first conductive base semiconductor layer 140 is formed of a GaN-based film doped with an n-type impurity, the first and second buffer layers 120 and 130 are formed of a GaN film to which no n-type impurity is implanted. When the first or second buffer layer 120 or 130 is formed of a metal oxide film or a metal nitride film, the first buffer layer 120 and the second buffer layer 130 may be formed of a metal oxide film or a metal nitride film such as TiN, AlN, TaN, CrN, ZrN, NiO, MgO, CaO, TiO, NiO, Y 2 O 3 , and the like.
이와 같이 제 1 및 제 2 버퍼층들(120,130)이 불순물을 함유하지 않으면, 템플릿용 기판(110)을 제 1 도전형 기저 반도체층(140)부터 제거하는 레이저 리프트 오프법에 의한 분리 공정이 용이하게 실시될 수 있으며, 치밀도가 높은 제 2 버퍼층(130)과 동일한 주 성분을 함유한 제 1 도전형 기저 반도체층(140)은 격자 부정합없이 제 2 버퍼층(130) 상에 양호하게 성장될 수 있다. If the first and second buffer layers 120 and 130 contain no impurities, the separation process by the laser lift-off method for removing the template substrate 110 from the first conductive base semiconductor layer 140 can be easily performed And the first conductive base semiconductor layer 140 containing the same major component as the second buffer layer 130 having a high density can be well grown on the second buffer layer 130 without lattice mismatch .
구체적으로, 레이저 리프트 오프법에 의하면, 고파워로 출력되더라도 n형 불순물이 주입된 반도체막은 높은 격자 결합력으로 인해 절단되는데 곤란하거나 불량하게 절단된다. 그러나, 불순물이 미주입된 제 1 및 제 2 버퍼층들(120,130)은 제 1 도전형 기저 반도체층(140)에 비해 격자 간의 낮은 결합력을 가져, 레이저 리프트 오프법의 출력 파워 범위내에서 제 1 도전형 기저 반도체층(140)에 비해 높은 선택도를 갖는다. Specifically, according to the laser lift-off method, the semiconductor film into which the n-type impurity is implanted is difficult or poorly cut due to a high lattice bonding force, even when output at a high power. However, the first and second buffer layers 120 and 130 in which the impurities are implanted have a lower bonding strength between the lattice layers compared to the first conductive base semiconductor layer 140, -Type base semiconductor layer 140, as shown in FIG.
치밀도가 낮은 제 1 버퍼층(120)은 제조 과정에서 제 2 버퍼층(130)보다 낮은 온도에서 형성되어, 복수의 알갱이의 응집체(agglomerate form)로 형성될 수 있다. 제 2 버퍼층(130)은 보이드없이 치밀한 막으로 형성되고, 제 1 버퍼층은 응집체로 형성되므로, 분리 공정에서 제 1 버퍼층(120)이 제 2 버퍼층(130)에 비해 더 높은 선택도를 갖는다. 이에 따라, 분리 공정은 가급적 제 1 버퍼층(120)에서 진행되고, 제 2 버퍼층(130)은 제 1 도전형 기저 반도체층(140)에 잔류될 수 있다. 여기서, 제 1 버퍼층(120)이 분리 사이트(site)인 것으로 설명하였으나, 제 1 버퍼층(120)과 인접한 제 2 버퍼층(130)이 분리 공정에 의해 일부 제거될 수 있으며, 이 경우에. 제 2 버퍼층(130)의 상면에 평탄화 공정을 수행하여 제 2 버퍼층(130)은 평활한 표면으로 형성될 수 있다.The first buffer layer 120 having a low density may be formed at a lower temperature than the second buffer layer 130 during the manufacturing process and may be formed into an agglomerate form of a plurality of particles. Since the second buffer layer 130 is formed as a dense film without voids and the first buffer layer is formed as an aggregate, the first buffer layer 120 has a higher selectivity than the second buffer layer 130 in the separation process. Accordingly, the separation process is preferably performed in the first buffer layer 120, and the second buffer layer 130 may remain in the first conductive base semiconductor layer 140. Although the first buffer layer 120 is described as a separation site, the first buffer layer 120 and the second buffer layer 130 adjacent to the first buffer layer 120 may be partially removed by a separation process. The second buffer layer 130 may be formed as a smooth surface by performing a planarization process on the top surface of the second buffer layer 130.
또한, 제 2 버퍼층(130)이 제 1 버퍼층(120)보다 높은 온도로 형성됨으로써, 전위(dislocation), 멜트 백(melt-back), 크랙(crack), 피트(pit), 표면 모폴로지(surface morphology) 불량 등의 결정 결함이 제 2 버퍼층(130)에 적게 유발된다. 이에 따라, 제 1 도전형 기저 반도체층(140)이 제 2 버퍼층(130)에 결정 결함없이 양호하게 성장될 수 있다. The second buffer layer 130 is formed at a temperature higher than that of the first buffer layer 120 so that dislocation, melt-back, crack, pit, surface morphology, ) Defects are caused in the second buffer layer 130 to a lesser degree. Accordingly, the first conductive base semiconductor layer 140 can be well grown in the second buffer layer 130 without crystal defects.
용이한 분리를 실현함과 동시에, 분리 과정에서 제 1 도전형 기저 반도체층(140) 및 제 2 버퍼층(130)에 대한 손상을 최소화하기 위해, 제 1 버퍼층(120)은 제 2 버퍼층(130)보다 작은 두께로 형성될 수 있다. 구체적으로, 제 1 버퍼층(120)은 10nm 이상, 1μm 이하의 두께로 형성될 수 있으며, 제 2 버퍼층(130)은 1μm 이상, 5μm 이하의 두께로 형성될 수 있다. The first buffer layer 120 may be formed on the second buffer layer 130 to minimize damage to the first conductive base semiconductor layer 140 and the second buffer layer 130 during the separation process, Can be formed to have a smaller thickness. Specifically, the first buffer layer 120 may be formed to a thickness of 10 nm or more and 1 μm or less, and the second buffer layer 130 may be formed to a thickness of 1 μm or more and 5 μm or less.
제 1 버퍼층(120)이 10nm 미만으로 형성되면, 분리 공정에서의 유효한 선택도를 가질 수 없으며, 1μm 초과로 형성되면, 분리 공정에서 제 2 버퍼층(130)을 포함하는 발광 구조체와 템플릿용 기판(110)과의 분리가 용이하지 않아, 제 2 버퍼층(130)등에 손상을 초래한다. If the first buffer layer 120 is formed to be less than 10 nm, it can not have an effective selectivity in the separation step. If the first buffer layer 120 is formed to be more than 1 μm, 110 are not easily separated from each other and cause damage to the second buffer layer 130 and the like.
제 2 버퍼층(130)이 1μm 미만으로 형성되면, 제 2 버퍼층(130)과 제 1 도전형 기저 반도체층(140)이 응집체로 형성된 제 1 버퍼층(120)의 결정 결함에 대한 영향을 받는다. 제 2 버퍼층(130)이 5μm 초과하여 형성되면, 템플릿용 기판(110)과 제 2 버퍼층(130) 사이의 부정합 및 상이한 열팽창 계수로 인하여, 템플릿용 기판(110)의 휨 현상이 발생되며, 개구부(150)를 제작하기 위해 제 1 도전형 기저 반도체층(140) 상에 배열되는 마스크 패턴(도 3의 170 참조)을 형성하기 위한 공정 수율이 저하된다. The second buffer layer 130 and the first conductive base semiconductor layer 140 are affected by crystal defects of the first buffer layer 120 formed as an aggregate. When the second buffer layer 130 is formed to have a size of more than 5 탆, the template substrate 110 is warped due to mismatching between the template substrate 110 and the second buffer layer 130 and different thermal expansion coefficients, The process yield for forming a mask pattern (refer to 170 in FIG. 3) arranged on the first conductive base semiconductor layer 140 is lowered to fabricate the first conductive semiconductor layer 150.
이에 더하여, 템플릿용 기판(110)에 인접한 분리층(160)은 3μm 이하의 폭을 갖도록 형성될 수 있다. 본 실시예와 달리, 분리층(160)의 제 1 버퍼층(120)이 전술한 폭보다 크게 형성되면, 제 1 버퍼층(120)의 템플릿용 기판(110)에 대한 분리 면적이 넓어져, 본원의 발명자는 레이저 리프트 오프법에 따른 분리 공정에 있어서 제 2 버퍼층(130) 및 제 1 도전형 기저 반도체층(140)에 손상이 발생됨을 지득하였다. In addition, the separation layer 160 adjacent to the template substrate 110 may be formed to have a width of 3 μm or less. When the first buffer layer 120 of the separation layer 160 is formed larger than the width described above, the separation area for the template substrate 110 of the first buffer layer 120 is widened, The inventors have found that damage occurs in the second buffer layer 130 and the first conductive base semiconductor layer 140 in the separation process according to the laser lift-off method.
제 1 도전형 기저 반도체층(140)은 질화물계 반도체 화합물로서 예컨대, 3족-5족 등으로 이루어진 질화물계 화합물 반도체로 형성되며, 제1 도전형 불순물로 도핑될 수 있다. 예를 들어, 제 1 도전형 기저 반도체층(140)은 InxAlyGazN (0≤x≤1, 0 ≤y≤1, 0≤z≤1)의 조성식을 갖는 반도체 물질, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN 계 화합물 반도체 중 어느 하나 이상으로 형성될 수 있다. 제 1 도전형 기저 반도체층(140)이 n형 반도체층인 경우, 제1 도전형 불순물은 Si, Ge, Sn, Se, Te 등과 같은 n형 도펀트를 포함할 수 있다. 제 1 도전형 기저 반도체층(140)은 단층 또는 다층으로 형성될 수 있으며, 이에 대해 한정하지는 않는다.The first conductive base semiconductor layer 140 is formed of a nitride based compound semiconductor made of, for example, Group 3-Group 5 or the like as the nitride based semiconductor compound, and may be doped with the first conductive type impurity. For example, the first conductive base semiconductor layer 140 may be a semiconductor material having a composition formula of InxAlyGazN (0? X? 1, 0? Y? 1, 0? Z? 1), GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN compound semiconductors. When the first conductive base semiconductor layer 140 is an n-type semiconductor layer, the first conductive type impurity may include n-type dopants such as Si, Ge, Sn, Se, and Te. The first conductive base semiconductor layer 140 may be formed as a single layer or a multilayer, but is not limited thereto.
또한, 개구부(150)와 인접한 제 1 도전형 기저 반도체층(140)의 외측벽의 경사각은 도 1a 및 1b에 도시된 바와 같이, 개구부와 중첩되는 템플릿용 기판(110)의 표면에 대하여 예각을 가질 수 있다. 예각의 외측벽은 역경사 식각법에 의해 실현될 수 있으며, 역경사 식각법에 의해 형성가능한 제 1 도전형 기저 반도체층(140)의 외측 경사각(d1, d2)은 45도 이상, 75도 이하로 형성될 수 있다. GaN계 화합물 반도체로 구성되는 제 1 도전형 기저 반도체층(140) 및 개구부(150)의 굴절율이 서로 상이하므로, 제 1 도전형 기저 반도체층(140)부터 방출되는 광의 전반사는 매우 낮은 임계각인 23.5도를 갖는다. 이에 따라, 외측 경사각이 전술한 범위에 있으면, 광은 전반사없이 제 1 도전형 기저 반도체층(140)의 외부로 양호하게 방출되어, 광추출 효율이 향상된다. 1A and 1B, the inclined angle of the outer wall of the first conductive base semiconductor layer 140 adjacent to the opening 150 has an acute angle with respect to the surface of the template substrate 110 overlapping the opening portion . The outer side walls of the acute angle can be realized by reverse arc etching and the outer side inclination angles d1 and d2 of the first conductive base semiconductor layer 140 that can be formed by the reverse arc etching method are 45 degrees or more and 75 degrees or less . Since the refractive indexes of the first conductive base semiconductor layer 140 and the opening portion 150 made of the GaN compound semiconductor are different from each other, the total reflection of the light emitted from the first conductive base semiconductor layer 140 is 23.5 . Thus, when the outer inclination angle is in the above-mentioned range, light is well emitted to the outside of the first conductive base semiconductor layer 140 without total reflection, and the light extraction efficiency is improved.
제 1 도전형 기저 반도체층(140)은 1μm 이상, 5μm 이하의 두께로 형성될 수 있다. 제 1 도전형 기저 반도체층(140)이 1μm 미만으로 형성되면, 상부에 형성되는 제 1 도전형 추가 반도체층(210)이 불량하게 성장된다. 제 1 도전형 기저 반도체층(140)이 5μm 초과하여 형성되면, 템플릿용 기판(110), 제 2 버퍼층(130) 및 제 1 도전형 기저 반도체층 간의 부정합 및 상이한 열팽창 계수로 인하여, 템플릿용 기판(110)의 휨 현상이 유발되며, 개구부(150)을 제작하기 위해 제 1 도전형 기저 반도체층(140) 상에 배열되는 마스크 패턴(도 3의 참조부호 170)을 형성하기 위한 공정 수율이 저하된다. The first conductive base semiconductor layer 140 may have a thickness of 1 탆 or more and 5 탆 or less. When the first conductive base semiconductor layer 140 is formed to be less than 1 탆, the first conductive type additional semiconductor layer 210 formed on the first conductive base semiconductor layer 140 is poorly grown. If the first conductive base semiconductor layer 140 is formed to have a thickness of more than 5 mu m, mismatching between the template substrate 110, the second buffer layer 130, and the first conductive base semiconductor layer, and different thermal expansion coefficients, The process yield for forming a mask pattern (170 in FIG. 3) arranged on the first conductive base semiconductor layer 140 to fabricate the opening 150 is lowered do.
도 1a 및 1b를 통한 실시예에서는 외측벽의 경사각이 예각인 것을 예시하고 있으나, 이에 제한되지 않고, 분리 용이와 제 1 도전형 기저 반도체층(140)의 손상의 최소화를 달성할 수 있다면, 제 1 도전형 기저 반도체층(140)과 분리층(160)은 실질적인 직각 혹은 둔각의 외측벽을 가져도 무방하다. 1A and 1B illustrate that the inclination angle of the outer wall is an acute angle. However, the present invention is not limited thereto, and if it is possible to achieve easy separation and minimization of damage to the first conductive base semiconductor layer 140, The conductive base semiconductor layer 140 and the isolation layer 160 may have substantially right-angled or obtuse-angled outer walls.
개구부(150)는 레이저 리프트 오프법에 의할 때, 템플릿용 기판(110)과 발광 구조물을 분리하는데 수반되는 열과 가스 압력을 흡수함으로써, 분리층(160)과 템플릿용 기판(110)의 계면에서 분리에 따른 스트레스를 완화시킨다. The opening 150 is formed in the interface between the separation layer 160 and the template substrate 110 by absorbing heat and gas pressure accompanying separation of the template substrate 110 and the light emitting structure, Thereby relieving stress caused by separation.
제 1 도전형 기저 반도체층(140)과 분리층(160)의 역경사 식각법에 의한 식각 결과, 개구부(150)는 템플릿용 기판(110)으로 향하는 하부 영역으로 갈수록 점진적으로 감소되는 폭을 갖도록 식각되어 형성될 수 있다. 도 1a에서와 같이 분리층(160)과 제 1 도전형 기저 반도체층(140)을 연결하는 외측벽이 실질적으로 동일한 경사로 형성되도록, 개구부(150)가 형성될 수 있으며, 도 1b에서와 같이, 분리층(160a) 및 제 1 도전형 기저 반도체층(140a)이 서로 다른 경사의 외측벽을 갖도록, 개구부(150a)이 형성될 수 있다. 도 1b에 의하면, 제 1 버퍼층(120a)의 외측벽이 개구부(150a)와 중첩되는 템플릿용 기판(110)의 표면에 대하여 작은 예각을 갖도록 형성됨으로써, 제 1 버퍼층(120a)이 도 1a보다 작은 템플릿용 기판(110)과의 접촉 면적을 가질 수 있다. 이에 따라, 도 1b의 실시예는 도 1a에 비해 우수한 분리 용이와 손상의 최소화를 실현할 수 있다. As a result of the etching of the first conductive base semiconductor layer 140 and the separation layer 160 by the inverse tilt etching method, the opening 150 is formed to have a gradually decreasing width toward the lower region toward the template substrate 110 And may be formed by etching. As shown in FIG. 1A, the opening 150 may be formed so that the outer walls connecting the isolation layer 160 and the first conductive base semiconductor layer 140 are formed at substantially the same inclination. As shown in FIG. 1B, The opening 150a may be formed so that the layer 160a and the first conductive base semiconductor layer 140a have different inclined outer walls. 1B, the outer wall of the first buffer layer 120a is formed to have a small acute angle with respect to the surface of the template substrate 110 overlapping with the opening 150a, whereby the first buffer layer 120a is formed of a template And a contact area with the substrate 110 for the first substrate. Accordingly, the embodiment of FIG. 1B can realize excellent separation easiness and minimization of damage as compared with FIG. 1A.
개구부(150, 150b)는 도 2a 및 도 2b와 같이 원형 및 다각형, 예컨대 허니콤(honey comb) 등으로 형성될 수 있으나, 이에 한정되지 않고, 전술한 기능을 달성하는 형상이라면 어떠한 형태로도 제작될 수 있다. 또한, 도 2c에서와 같이, 분리층(160)과 제 1 도전형 기저 반도체층(140c)이 수직으로 적층된 패턴들의 각각이 서로 이격되도록, 적층 패턴들 주위의 개구부(150c)는 템플릿용 기판(110)의 상부에 볼 때, 연결되는 구조로 형성될 수 있다. 이에 의하면, 레이저 리프트 오프법에 따른 분리 공정에서 수반되는 열 또는 가스가 발광 구조체의 외부로 용이하게 유출되어, 열과 가스로 인한 제 2 버퍼층(130) 및 제 1 도전형 기저 반도체층(140)의 손상이 더욱 감소될 수 있다. The openings 150 and 150b may be formed of a circular or polygonal shape, such as a honeycomb, as shown in FIGS. 2A and 2B. However, the openings 150 and 150b may be formed in any shape as long as the shape achieves the above- . 2C, the openings 150c around the lamination patterns are formed on the template substrate 110 so that the patterns in which the isolation layer 160 and the first conductive base semiconductor layer 140c are vertically stacked are separated from each other, When viewed on the upper side of the display unit 110, as shown in FIG. Accordingly, the heat or gas involved in the separation process according to the laser lift-off method easily flows out to the outside of the light emitting structure, and the second buffer layer 130 and the first conductive base semiconductor layer 140 The damage can be further reduced.
본 실시예는 개구부(150)가 규칙적인 배열을 갖도록 형성될 수 있는 것을 예시하고 있으나, 불규칙하게 배열될 수도 있다. Although the present embodiment illustrates that the openings 150 may be formed to have a regular arrangement, they may be irregularly arranged.
이에 더하여, 제 1 도전형 기저 반도체층(140)의 상부측 근방에 배치된 개구부(150)는 도 0.5μm 이상, 5μm 이하의 폭(W)으로 형성될 수 있다. In addition, the opening 150 disposed in the vicinity of the upper side of the first conductive base semiconductor layer 140 may have a width W of not less than 0.5 μm and not more than 5 μm.
개구부(150)가 0.5μm 미만으로 형성되면, 제 1 도전형 기저 반도체층(140)의 역경사 식각법(템플릿용 기판(110)의 표면에 대하여 예각을 갖도록 막(film)을 식각)이 원활하게 수행되지 않는다. When the opening 150 is formed to be less than 0.5 탆, the first conductive base semiconductor layer 140 is etched in a reverse arc etching method (etching the film to have an acute angle with respect to the surface of the template substrate 110) .
또한, 개구부(150)가 5μm 초과하여 형성되면, 이웃하는 제 1 도전형 기저 반도체층(140)의 간격이 넓어져, 도 4a에서와 같이 후속 형성되는 제 1 도전형 추가 반도체층(210)의 측방향 성장(lateral growth)에 불량이 발생한다. 구체적으로, 제 1 도전형 추가 반도체층(210)의 형성 과정에 있어서, 템플릿용 기판(110)의 표면의 수직 성장을 통한 제 1 도전형 추가 반도체층(210)이 측방향 성장(lateral growth)보다 빠르게 성장함으로써, 측방향 성장에 의한 제 1 도전형 추가 반도체층(210)이 많은 결함을 포함하여 형성된다. 이로 인하여, 개구부(150)는 원하는 형상을 유지하지 않아, 활성층(230)으로부터 낮은 입사각으로 발산된 광이 제 1 도전형 기저 반도체층(140)의 측벽에서 양호하게 전반사되지 않으며, 제 1 도전형 추가 반도체층(210)은 전위, 피트, 크랙 등의 결함으로 인해 누설 전류와 같은 낮은 전기적 특성을 가진다. If the opening 150 is formed to have a size of more than 5 袖 m, the spacing between the adjacent first conductive base semiconductor layers 140 is widened and the size of the first conductive type additional semiconductor layer 210 Defects occur in the lateral growth. In the process of forming the first conductive type additional semiconductor layer 210, the first conductive type additional semiconductor layer 210 through the vertical growth of the surface of the template substrate 110 is laterally grown, As a result of the faster growth, the first conductivity type additional semiconductor layer 210 due to lateral growth is formed including many defects. Accordingly, the opening 150 does not maintain a desired shape, and light emitted from the active layer 230 at a low incident angle is not totally reflected on the sidewalls of the first conductive base semiconductor layer 140, The additional semiconductor layer 210 has low electrical characteristics such as leakage current due to defects such as dislocation, pits, and cracks.
본 실시예는 기저 반도체층(140)이 n형 불순물을 함유하는 것을 예시하고 있으나, 반도체 소자가 스위칭 혹은 증폭 소자인 경우, 반도체 소자의 설계 사양에 따라, 기저 반도체층(140)이 언도우프드된 상태 혹은 절연을 위한 도핑 상태로 제작될 수 있다. 이 경우에, 제 1 버퍼층(120)이 제 2 버퍼층(130) 및 기저 반도체층(140)보다 치밀도가 낮으므로, 레이저 리프트 오프법에 따른 분리 공정에서의 선택도가 높다. 이에 따라, 제 1 버퍼층(120)가 레이저 리프트 오프법에서 주로 분리 사이트로 기능한다. In this embodiment, the base semiconductor layer 140 includes n-type impurities. However, when the semiconductor element is a switching or amplifying element, depending on the design specifications of the semiconductor element, Or a doped state for isolation. In this case, since the first buffer layer 120 is denser than the second buffer layer 130 and the base semiconductor layer 140, the selectivity in the separation step according to the laser lift-off method is high. Accordingly, the first buffer layer 120 functions mainly as a separation site in the laser lift-off method.
이하, 도 1a, 1b 및 3을 참조하여, 반도체 소자 제조용 템플릿의 제조 방법에 대하여 설명한다. 도 3은 본 발명의 실시예에 따른 반도체 소자 제조용 템플릿을 제조 과정을 나타내는 단면도이다. Hereinafter, a method for manufacturing a template for semiconductor device fabrication will be described with reference to FIGS. 1A, 1B, and 3. FIG. 3 is a cross-sectional view illustrating a process of manufacturing a template for fabricating a semiconductor device according to an embodiment of the present invention.
투명성의 템플릿용 기판(110) 상에 제 1 버퍼막(buffer film; 122)을 형성한다. 제 1 버퍼막(122)은 제 1 도전형 기저 반도체막(a first conductivity type semiconductor film; 142)보다 높은 분리 공정의 선택도를 갖는 물질막으로서, 비도핑된 질화물 반도체막, 제 1 도전형 기저 반도체막(142)와 동일 성분의 비도핑된 물질막, 금속 산화막, 금속 질화막 중에서 어느 하나로 형성될 수 있다. 제 1 버퍼막(122)은 200도 내지 1000도의 온도로 형성될 수 있다. 제 1 버퍼막(122)이 질화물 반도체막 또는 동일 성분의 물질막으로 형성되면, 수소화물 기상 성장법(HVPE; Hydride Vapor Phase Epitaxy) 또는 유기금속 화학 증착법(MOCVD) 등이 적용될 수 있으며, 제 1 버퍼막(122)이 금속 산화막 또는 금속 질화막으로 형성되면, 스퍼터링 또는 E-beam 증착법 등이 적용될 수 있다. A first buffer film 122 is formed on the transparent substrate 110 for a template. The first buffer layer 122 is a material layer having a selectivity of a separation process that is higher than that of the first conductivity type semiconductor film 142. The first buffer layer 122 may be formed of an undoped nitride semiconductor film, A non-doped material layer having the same composition as the semiconductor layer 142, a metal oxide layer, and a metal nitride layer. The first buffer film 122 may be formed at a temperature of 200 degrees to 1000 degrees. When the first buffer film 122 is formed of a nitride semiconductor film or a material film of the same component, hydride vapor phase epitaxy (HVPE) or metal organic chemical vapor deposition (MOCVD) may be applied. If the buffer film 122 is formed of a metal oxide film or a metal nitride film, sputtering or E-beam deposition may be applied.
제 1 버퍼막(122)이 전술의 온도로 형성되면, 복수의 알갱이의 응집체(agglomerate form)로 형성되어 낮은 치밀도 가질 수 있다. 제 1 버퍼막(122)은 10nm 이상, 1μm 이하의 두께로 형성될 수 있다. When the first buffer layer 122 is formed at the above-described temperature, it may be formed into an agglomerate form of a plurality of grains and have a low density. The first buffer layer 122 may have a thickness of 10 nm or more and 1 μm or less.
다음으로, 제 1 버퍼막(122) 상에 제 2 버퍼막(132)을 형성한다. 제 2 버퍼막(132)은 전술한 제 1 버퍼막(122)에서 열거된 막 중에 어느 하나로 형성되며, 제 1 버퍼막(122)보다 높은 온도인 800도 내지 2000도를 갖는 성막 공정을 통해 형성될 수 있다. 이에 따라, 제 2 버퍼막(132)은 제 1 버퍼막(122)에 비해 높은 분리 선택도를 가질 수 있도록 높은 치밀도로 형성될 수 있다. 제 2 버퍼막(132)은 성막 공정을 통해 제 1 버퍼막(122)보다 낮은 두께로 형성되며, 예컨대 1μm 이상, 5μm 이하의 두께로 형성될 수 있다. Next, a second buffer layer 132 is formed on the first buffer layer 122. The second buffer layer 132 is formed of any one of the films listed in the first buffer layer 122 and is formed through a film formation process having a temperature higher than that of the first buffer layer 122, . Accordingly, the second buffer film 132 can be formed with high density so as to have a higher separation selectivity than the first buffer film 122. The second buffer layer 132 may be formed to have a thickness lower than that of the first buffer layer 122 through a film forming process, and may be formed to a thickness of, for example, 1 μm or more and 5 μm or less.
이어서, 제 2 버퍼막(132) 상에 제 1 도전형 기저 반도체막(142)을 형성한다. 제 1 도전형 기저 반도체막(142)는 질화물계 반도체 화합물로 형성된다. 제 1 도전형 기저 반도체층(140)은 3족-5족 등의 화합물 반도체로 구현될 수 있다. Subsequently, a first conductive base semiconductor film 142 is formed on the second buffer film 132. The first conductive base semiconductor film 142 is formed of a nitride-based semiconductor compound. The first conductive base semiconductor layer 140 may be formed of a compound semiconductor such as a Group III-V element.
제 1 도전형 기저 반도체막(142)은 예컨대, 분자선 성장법(MBE; Molecular Beam Epitaxy), 수소화물 기상 성장법(HVPE; Hydride Vapor Phase Epitaxy), 유기금속 화학 증착법(MOCVD), 화학 증착법(CVD; Chemical Vapor Deposition) 및 플라즈마 화학 증착법(PECVD; Plasma-Enhanced Chemical Vapor Deposition) 등의 방법을 이용하여 형성될 수 있으나, 이에 대해 한정하지는 않는다. 또한, 상기 방법의 공정과 동시에 또는 이시에 n형 불순물이 제 1 도전형 기저 반도체막(142)에 도핑될 수 있다. The first conductive base semiconductor layer 142 may be formed by a method such as molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metal organic chemical vapor deposition (MOCVD), chemical vapor deposition , Chemical Vapor Deposition (PECVD), and Plasma Enhanced Chemical Vapor Deposition (PECVD), but the present invention is not limited thereto. In addition, n-type impurities may be doped into the first conductive base semiconductor film 142 simultaneously with or at the same time as the process of the above method.
제 1 및 제 2 버퍼막(132)이 제 1 도전형 기저 반도체막(142)과 유사하게 비도핑된 질화물 반도체막 또는 동일 성분의 비도핑된 물질막으로 형성되면, 제 1 도전형 기저 반도체막(142)은 격자 부정합없이 제 2 버퍼막(132) 상에 양호하게 성장될 수 있다. 제 1 도전형 기저 반도체막(142)은 예컨대 1μm 이상, 5μm 이하의 두께로 형성될 수 있다. When the first and second buffer films 132 are formed of a non-doped nitride semiconductor film similar to the first conductive base semiconductor film 142 or an undoped material film of the same component, The first buffer layer 142 can be well grown on the second buffer layer 132 without lattice mismatch. The first conductive base semiconductor film 142 may be formed to a thickness of, for example, 1 占 퐉 or more and 5 占 퐉 or less.
다음으로, 제 1 도전형 기저 반도체막(142) 상에 소정의 개구 패턴을 가진 마스크 패턴(170)을 배열한다. 도 1a에서 설명한 바와 같이, 개구부(150)의 폭(W)을 0.5μm 이상, 5μm 이하로 형성하기 위해, 개구 패턴은 전술의 폭을 가진다. Next, a mask pattern 170 having a predetermined opening pattern is arranged on the first conductive base semiconductor film 142. 1A, the opening pattern has the width described above in order to form the width W of the opening 150 to 0.5 mu m or more and 5 mu m or less.
이어서, 역경사 식각법을 이용하여 마스크 패턴(170)의 하부에 배치된 제 1 도전형 기저 반도체막(142), 제 2 버퍼막(132) 및 제 1 버퍼막(122)를 순차적으로 식각함으로써, 복수의 개구부(150)를 형성한다. Subsequently, the first conductive base semiconductor film 142, the second buffer film 132, and the first buffer film 122, which are disposed under the mask pattern 170, are sequentially etched by the inverse warp etching method And a plurality of openings 150 are formed.
역경사 식각법의 일례와 관련하여, 척 하부에 인접하게 배치되는 교번 자극을 구비하는 플라즈마 식각 장비가 적용될 수 있다. 이 경우에, 식각용 가스는 Cl. BCl3, Ar, H2, Hbr, N2, O2등의 혼합 가스를 이용할 수 있으며, 템플릿용 기판(110)의 표면이 노출되도록 식각된다. 또한 마스크 패턴(170)과 인접한 부분보다 템플릿용 기판(110)에 인접한 부분에서 많은 식각이 이루어지도록 진행하며, 이는 20~200mT 의 낮은 공정 압력과 낮은 바이어스 50 ~ 400W 사이에서 진행함으로써 가능하다. With respect to an example of a reverse arc etching method, a plasma etching apparatus having an alternating magnetic pole disposed adjacent to the lower portion of the chuck can be applied. In this case, the etching gas is Cl. A mixed gas of BCl 3, Ar, H 2, Hbr, N 2, O 2, or the like can be used and etched so that the surface of the template substrate 110 is exposed. Further, a lot of etching proceeds in a portion adjacent to the template substrate 110, rather than a portion adjacent to the mask pattern 170. This is possible by advancing at a process pressure of 20 to 200 mT and a low bias of 50 to 400 W.
역경사 식각법의 다른 예로서, 건식 식각과 습식 식각을 순차적으로 진행하여 형성할 수 있으며, 제 1 도전형 기저 반도체막(142), 제 2 버퍼막(132) 및 제 1 버퍼막(122) 간의 화학적 식각 속도의 차이를 이용하여 가능하다. The first conductive base semiconductor film 142, the second buffer film 132, and the first buffer film 122 may be formed by sequentially performing dry etching and wet etching, And the difference in chemical etching rate between the electrodes.
상술한 역경사 식각법의 공정 조건을 적절히 적용함에 따라, 도 1a에서와 같이 제 1 도전형 기저 반도체층(140)과 분리층(160)을 연결하는 외측벽의 경사각이 실질적으로 동일한 예각을 갖도록 형성되거나, 도 1b에 도시된 바와 같이, 외측벽의 경사각이 하부로 갈수록 상이한 각도로 형성될 수 있다. 여기서, 제 1 도전형 기저 반도체층(140)의 외측벽은 45도 내지 75도로 형성될 수 있다. 1A, the inclined angles of the outer walls connecting the first conductive base semiconductor layer 140 and the separation layer 160 are formed to have substantially the same acute angle as in the case of the first embodiment, Alternatively, as shown in FIG. 1B, the inclination angle of the outer wall may be formed to be different from the lower angle. Here, the outer wall of the first conductive base semiconductor layer 140 may be formed at 45 degrees to 75 degrees.
또한, 역경사 식각법의 공정 조건이 조절됨으로써, 템플릿용 기판(110)에 인접한 분리층(160)의 제 1 버퍼층(120)은 3μm 이하의 폭으로 형성된다. In addition, the first buffer layer 120 of the isolation layer 160 adjacent to the template substrate 110 is formed with a width of 3 μm or less by controlling the process conditions of the reverse oblique etching method.
본 실시예에서는 외측벽의 경사각이 예각인 것을 예시하고 있으나, 이에 제한되지 않고, 분리 용이와 분리 공정에서의 제 1 도전형 기저 반도체층(140)의 손상의 최소화를 달성할 수 있다면, 제 1 도전형 기저 반도체층(140)과 분리층(160)은 둔각 또는 실질적인 직각의 외측벽을 가질 수 있다. In this embodiment, the inclination angle of the outer wall is an acute angle. However, the present invention is not limited to this, and if the separation easiness and the minimization of the damage of the first conductive base semiconductor layer 140 in the separation process can be achieved, -Type base semiconductor layer 140 and the isolation layer 160 may have an obtuse angle or a substantially perpendicular outer wall.
또한, 개구부(150)는 도 2a 및 도 2b와 같이 원형 및 허니콤과 같은 다각형으로 형성될 수 있거나, 2c에 도시된 바와 같이, 분리층(160)과 제 1 도전형 기저 반도체층(140)이 수직으로 적층된 패턴들의 각각이 서로 이격되도록, 템플릿용 기판(110)의 상부에 볼 때, 연결되는 구조로 형성될 수 있다. 그러나, 이에 한정되지 않고 어떠한 형태로로 제작될 수 있다. The opening 150 may be formed in a polygonal shape such as a circle and a honeycomb as shown in FIGS. 2A and 2B. Alternatively, the isolation layer 160 and the first conductive base semiconductor layer 140 may be formed as shown in FIG. May be formed to have a structure in which each of the vertically stacked patterns is spaced apart from each other and viewed when viewed on top of the template substrate 110. However, the present invention is not limited thereto and can be manufactured in any form.
본 실시예는 기저 반도체층(140)이 n형 불순물을 함유하는 것을 예시하고 있으나, 반도체 소자가 스위칭 혹은 증폭 소자인 경우에, 반도체 소자의 설계 사양에 따라, 기저 반도체층(140)이 언도우프드된 상태 혹은 절연을 위한 도핑상태로 제작될 수 있다. In this embodiment, the base semiconductor layer 140 includes n-type impurities. However, in the case where the semiconductor element is a switching or amplifying element, the base semiconductor layer 140 may be formed in a non- Or in a doped state for isolation.
이하, 도 4a 내지 4d를 참조하여, 반도체 소자 제조용 템플릿을 이용하여 본 발명의 일 실시예에 따른 질화물계 박막을 갖는 발광 소자의 제조 방법에 대하여 설명한다. 도 4a 내지 4d는 본 발명의 일 실시예에 따른 질화물계 박막을 갖는 발광 소자의 제조 방법을 나타내는 단면도들이다. Hereinafter, a method of manufacturing a light emitting device having a nitride-based thin film according to an embodiment of the present invention will be described with reference to FIGS. 4A to 4D using a template for semiconductor device fabrication. 4A to 4D are cross-sectional views illustrating a method of manufacturing a light emitting device having a nitride-based thin film according to an embodiment of the present invention.
도 1a 등에 도시된 반도체 소자 제조용 템플릿(100)을 준비한 후에, 템플릿(100) 상에 제 1 도전형 추가 반도체층(210)을 형성한다. 1A and the like, a first conductive type additional semiconductor layer 210 is formed on the template 100. Then, as shown in FIG.
제 1 도전형 추가 반도체층(210)은 제 1 도전형 기저 반도체층(140)과 마찬가지로, n형 불순물을 포함할 수 있으며, InxAlyGazN (0≤x≤1, 0 ≤y≤1, 0≤z≤1)의 조성식을 갖는 반도체 물질, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN 계 화합물 반도체 중 어느 하나 이상으로 형성될 수 있다. 제 1 도전형 추가 반도체층(210)은 제 1 도전형 기저 반도체층(112)과 동일한 화합물 반도체로 형성될 수 있다. 제 1 도전형 추가 반도체층(210)은 제 1 도전성 기저 반도체막(142)의 성막 공정과 실질적으로 동일한 방법으로 형성될 수 있으며, 이러한 방법의 공정과 동시에 또는 이시에 n형 불순물이 제 1 도전성 추가 반도체층(210)에 도핑될 수 있다. Like the first conductive base semiconductor layer 140, the first conductive type additional semiconductor layer 210 may include an n-type impurity, and InxAlyGazN (0? X? 1, 0? Y? ? 1), GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN based compound semiconductor. The first conductive type additional semiconductor layer 210 may be formed of the same compound semiconductor as the first conductive type base semiconductor layer 112. The first conductive type additional semiconductor layer 210 may be formed in substantially the same manner as the first conductive base semiconductor film 142. When the n-type impurity is simultaneously or simultaneously with the first conductive type semiconductor layer 142, May be doped to the additional semiconductor layer 210.
도 1a에서와 같이, 개구부(150)의 상부 영역의 폭(W)이 5μm 이하이므로, 템플릿용 기판(110)의 표면에서 제 1 도전형 추가 반도체층(210)의 수직 성장하는 측방향 성장에 영향을 미치지 않는다. 이에 따라, 제 1 도전형 추가 반도체층(210)은 원하는 형태로 측방향으로 형성될 수 있다. 1A, since the width W of the upper region of the opening 150 is 5 μm or less, the vertical growth lateral growth of the first conductive type additional semiconductor layer 210 on the surface of the template substrate 110 It does not affect. Accordingly, the first conductive type additional semiconductor layer 210 may be formed laterally in a desired shape.
다음으로 도 4b를 참조하면, 제 1 도전형 추가 반도체층(210) 상에 제 1 중간층(first interlayer; 220), 활성층(230), 제 2 중간층(240), 제 2 도전형 반도체층(250), 반사층(260)을 순차적으로 적층한다.Next, referring to FIG. 4B, a first interlayer 220, an active layer 230, a second intermediate layer 240, a second conductive semiconductor layer 250 (not shown) are formed on the first conductive type additional semiconductor layer 210, And a reflective layer 260 are sequentially stacked.
제 1 중간층(120)은 예컨대, 도전형 클래드층으로서, 활성층(130)의 장벽층의 밴드 갭보다 더 넓은 밴드 갭을 가지는 반도체로 형성될 수 있다. 제 1 중간층(120)은 GaN, AlGaN, InAlGaN 또는 초격자 구조 등을 포함할 수 있고, n형으로 도핑될 수 있다. 또한, 제 1 중간층(220)은 전류 확산층과 전자 주입층으로 형성될 수도 있다. The first intermediate layer 120 may be formed of a semiconductor having a band gap wider than the band gap of the barrier layer of the active layer 130, for example, as a conductive clad layer. The first intermediate layer 120 may include GaN, AlGaN, InAlGaN or a superlattice structure, and may be doped with n-type. In addition, the first intermediate layer 220 may be formed of a current diffusion layer and an electron injection layer.
활성층(230)은 제 1 도전형 반도체층(도 4d의 205 참조)을 통해서 주입되는 전자와 제 2 도전형 반도체층(250)을 통해서 주입되는 정공이 서로 만나서 활성층(발광층) 물질 고유의 에너지 밴드에 의해서 결정되는 에너지를 갖는 빛을 방출하는 층이다. 활성층(230)은 단일 우물 구조(Double Hetero Structure), 다중 우물 구조, 단일 양자 우물 구조, 다중 양자 우물(MQW:Multi Quantum Well) 구조, 양자점 구조 또는 양자선 구조 중 어느 하나를 포함할 수 있다. 활성층(130)은 3족-5족 원소의 화합물 반도체 재료를 이용하여 우물층과 장벽층, 예를 들면 InGaN/GaN, InGaN/InGaN, GaN/AlGaN, InAlGaN/GaN, GaAs(InGaAs),/AlGaAs, GaP(InGaP)/AlGaP 중 어느 하나 이상의 페어(pair) 구조로 형성될 수 있으나 이에 한정되지는 않는다. 우물층은 장벽층의 밴드 갭보다 작은 밴드 갭을 갖는 물질로 형성될 수 있다.Electrons injected through the first conductive type semiconductor layer (see 205 in FIG. 4D) and holes injected through the second conductive type semiconductor layer 250 meet with each other to form an energy band unique to the active layer (light emitting layer) Which emits light having an energy determined by < RTI ID = 0.0 > The active layer 230 may include any one of a double heterostructure, a multi-well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure. InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs), and / AlGaAs (InGaN / GaN) , GaP (InGaP) / AlGaP, but the present invention is not limited thereto. The well layer may be formed of a material having a band gap smaller than the band gap of the barrier layer.
활성층(230)은 유기금속 화학 증착법(MOCVD), 화학 증착법(CVD), 플라즈마 화학 증착법(PECVD), 분자선 성장법(MBE), 수소화물 기상 성장법(HVPE) 등의 방법을 이용하여 형성될 수 있으며, 이에 대해 한정하지는 않는다. 구체적인 예를 들면, 예를 들어 상기 트리메틸 갈륨 가스(TMGa), 암모니아 가스(NH3), 질소 가스(N2), 및 트리메틸 인듐 가스(TMIn)가 주입되어 다중 양자우물구조가 형성될 수 있다.The active layer 230 may be formed by a method such as MOCVD, CVD, PECVD, molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). And is not limited thereto. For example, a trimetalgallium gas (TMGa), an ammonia gas (NH3), a nitrogen gas (N2), and a trimethyl indium gas (TMIn) may be implanted to form a multiple quantum well structure.
제 2 중간층(240)은 예컨대, 제 1 중간층(120)과 실질적으로 동일한 도전형 클래드층일 수 있다.  The second intermediate layer 240 may be, for example, a conductive type cladding layer substantially the same as the first intermediate layer 120.
구체적으로, 제 2 중간층(240)은 전자 차단(electron blocking) 및 활성층의 클래딩(MQW cladding) 역할을 해줌으로써 발광효율을 개선할 수 있다. 예를 들어, 제 2 중간층(240)은 AlxInyGa(1-x-y)N(0≤x≤1,0≤y≤1)계 반도체로 형성될 수 있으며, 활성층(230)의 에너지 밴드 갭보다는 높은 에너지 밴드 갭을 가질 수 있으며, 약 100Å~ 약 600Å의 두께로 형성될 수 있으나 이에 한정되는 것은 아니다. 또한, 제 2 중간층(240)은 AlzGa(1-z)N/GaN(0≤z≤1) 초격자(superlattice)로 형성될 수 있으나 이에 한정되는 것은 아니다. 제 2 중간층(240)은 P형으로 이온주입되어 오버플로우되는 전자를 효율적으로 차단하고, 홀의 주입효율을 증대시킬 수 있다. Specifically, the second intermediate layer 240 may serve as electron blocking and cladding of the active layer (MQW cladding) to improve the light emitting efficiency. For example, the second intermediate layer 240 may be formed of an AlxInyGa (1-xy) N (0? X? 1, 0? Y? 1) semiconductor and may have energy higher than the energy band gap of the active layer 230 Band gap, and may be formed to a thickness of about 100 A to about 600 A, but the present invention is not limited thereto. Also, the second intermediate layer 240 may be formed of AlzGa (1-z) N / GaN (0? Z? 1) superlattice, but is not limited thereto. The second intermediate layer 240 can effectively block the electrons that are ion-implanted into the P-type to overflow and increase the hole injection efficiency.
제 2 중간층(240) 상에 배치되는 제 2 도전형 반도체층(250)은 반도체 화합물로 형성될 수 있다. 제 2 도전형 반도체층(250)은 3족-5족, 2족-6족 등의 화합물 반도체로 구현될 수 있으며, 제2 도전형 불순물이 도핑될 수 있다. 예컨대, InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1)의 조성식을 갖는 반도체 물질 또는 GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN 중 어느 하나 이상으로 형성될 수 있다. 제 2 도전형 반도체층(250)이 P형 반도체층인 경우, 제2 도전형 불순물은 Mg, Zn, Ca, Sr, Ba 등과 같은 P형 도펀트일 수 있다. 제 2 도전형 반도체층(250)은 단층 또는 다층으로 형성될 수 있으며, 이에 대해 한정하지는 않는다.The second conductive semiconductor layer 250 disposed on the second intermediate layer 240 may be formed of a semiconductor compound. The second conductive semiconductor layer 250 may be formed of a compound semiconductor such as Group 3-Group 5, Group 2 or Group 6, and may be doped with a second conductive impurity. For example, a semiconductor material having a composition formula of InxAlyGa1-x-yN (0? X? 1, 0? Y? 1, 0? X + y? 1) or a semiconductor material of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, May be formed of one or more. When the second conductivity type semiconductor layer 250 is a P type semiconductor layer, the second conductivity type impurity may be a P type dopant such as Mg, Zn, Ca, Sr, and Ba. The second conductive semiconductor layer 250 may be formed as a single layer or a multilayer, but the present invention is not limited thereto.
제 2 도전형 반도체층(250)은 예컨대, 분자선 성장법(MBE), 수소화물 기상 성장법(HVPE), 유기금속 화학 증착법(MOCVD), 화학 증착법(CVD) 및 플라즈마 화학 증착법(PECVD) 등의 방법을 이용하여 형성될 수 있으나, 이에 대해 한정하지는 않는다. 또한, 상기 방법의 공정과 동시에 또는 이시에 P형 불순물이 제 2 도전형 반도체층(250)에 도핑될 수 있다. 구체적인 예로서, 챔버에 트리메틸 갈륨 가스(TMGa), 암모니아 가스 (NH3), 질소 가스(N2), 및 마그네슘(Mg)과 같은 P형 불순물을 포함하는 비세틸 사이클로 펜타디에닐 마그네슘(EtCp2Mg) {Mg(C2H5C5H4)2}가 주입됨으로써, P형 GaN층과 같은 제 2 도전형 반도체층(250)이 형성될 수 있다.The second conductive semiconductor layer 250 may be formed by a method such as molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), and plasma chemical vapor deposition Method, but the present invention is not limited thereto. In addition, P-type impurities may be doped into the second conductivity type semiconductor layer 250 simultaneously with or at the same time as the process of the above method. As a specific example, a non-cetyl cyclopentadienyl magnesium (EtCp2Mg) {Mg (Mg) containing a P-type impurity such as trimethyl gallium gas (TMGa), ammonia gas (NH3), nitrogen gas (N2), and magnesium (C 2 H 5 C 5 H 4) 2} is injected, a second conductive semiconductor layer 250 such as a P-type GaN layer can be formed.
제 2 도전형 반도체층(250) 상에 배치되는 반사층(260)은 활성층(230)에 발생한 광을 반사시키는 것으로서, Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf 및 그 조합으로 구성된 그룹으로부터 선택된 물질로 이루어진 적어도 하나의 층을 포함하는 구조로 형성될 수 있다. The reflective layer 260 disposed on the second conductive semiconductor layer 250 reflects light generated in the active layer 230 and may be formed of Ag, Ni, Al, Rh, Pd, Ir, Ru, Au, Hf, and a combination thereof.
다음으로, 반사층(260) 상에 제 1 도전형 추가 반도체층(210)과 연결되는 컨택홀을 채우는 제 1 전극(280)을 형성함과 아울러서, 제 2 도전형 반도체층(250)과 전기적으로 연결되는 제 2 전극(290)을 형성한다. 물론, 제 1 및 제 2 전극(280, 290)은 이격되어 형성된다. 제 1 및 제 2 전극(280, 290)은 도전성 물질 예를 들면 금속으로 형성될 수 있으며, 보다 상세하게는 Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf 및 이들의 선택적인 조합으로 이루어질 수 있고, 단층 또는 다층 구조로 형성될 수 있다. 컨택홀은 주변과의 절연을 위해 측벽에 측벽 절연층(270)을 포함한다. A first electrode 280 is formed on the reflective layer 260 to fill the contact hole connected to the first conductive type additional semiconductor layer 210 and electrically connected to the second conductive type semiconductor layer 250. [ Thereby forming a second electrode 290 to be connected. Of course, the first and second electrodes 280 and 290 are spaced apart. The first and second electrodes 280 and 290 may be formed of a conductive material such as a metal. More specifically, the first and second electrodes 280 and 290 may be formed of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Hf, and an optional combination thereof, and may be formed as a single layer or a multilayer structure. The contact hole includes a sidewall insulation layer 270 on the sidewall for isolation from the surroundings.
이어서, 제 1 및 제 2 전극들(280, 290) 상에 솔더링 등을 통해 서로 이격된 도전성 볼들(300)을 형성한다. Next, conductive balls 300 are formed on the first and second electrodes 280 and 290 by soldering or the like.
다음으로, 도전성 볼들(300)을 외부로 노출시키는 공간부와 도전성 볼들(300) 상에 베이스 기판(310)을 형성한다. 베이스 기판(310)은 인쇄회로기판, 비전도성 수지 기판, 실리콘 기판, 세라믹 기판 및 글래스 기판 중 어느 하나로 구성될 수 있으며, 인쇄회로기판으로 형성되는 경우에, 베이스 기판(310)은 레이저 리프트 오프법에 따른 분리 공정에서 베이스 기판(310)과 연결된 발광 구조체를 지지하는 역할을 담당할 뿐만 아니라, 발광 소자의 최종 구성으로서 분리 공정 후에도 제거되지 않고 잔류한다. Next, a base substrate 310 is formed on the conductive balls 300 and the space for exposing the conductive balls 300 to the outside. The base substrate 310 may be formed of a printed circuit board, a non-conductive resin substrate, a silicon substrate, a ceramic substrate, or a glass substrate. When the base substrate 310 is formed of a printed circuit board, Not only does it serve to support the light emitting structure connected to the base substrate 310 in the separation process according to the present invention but also remains as a final structure of the light emitting device without being removed even after the separation process.
또한, 공간부는 분리 공정 시에 이격된 도전성 볼들(310) 사이에 어떠한 부재를 개재함이 없이, 빈 공간으로 형성되는 부분이다. In addition, the space portion is a portion formed as an empty space without interposing any member between the conductive balls 310 separated during the separation process.
다음으로 도 4c를 참조하면, 레이저 리프트 오프법에 따른 분리 공정(L)에 의해, 분리층(160)의 제 1 버퍼층(120)을 경계로 제 2 버퍼층(130)으로부터 템플릿용 기판(110)을 제거한다. Referring to FIG. 4C, the separation step L according to the laser lift-off method removes the template layer 110 from the second buffer layer 130 with the first buffer layer 120 of the separation layer 160 as a boundary, .
분리 공정(L)은 특정 파장의 레이저를 투명성의 템플릿 기판(110)으로 투과시켜 분리층(160)을 조사함으로써, 제 1 버퍼층(120)을 열화학 분해시킨다. 구체적으로, 레이저 리프트 오프법은 KrF 레이저(248nm) 및 ArF 레이저 (194 nm) 를 이용할 수 있으며, 반도체 소자 제조용 템플릿(100)의 개구부(150)를 통해, 레이저 리프트 오프법 에서 수반되는 열과 가스가 방출됨으로써, 제 1 도전형 기저 반도체층(140)에 유발되는 크랙과 보우(bow) 등의 손상을 방지할 수 있다. 또한, 제 1 버퍼층(120)이 제 2 버퍼층(130)에 비해 낮은 치밀도를 가져, 낮은 출력의 레이저로 템플릿용 기판(110)을 분리할 수 있으므로, 제 1 도전형 기저 반도체층(140)의 손상이 더욱 방지될 수 있다. The separation step (L) thermally decomposes the first buffer layer (120) by irradiating the separation layer (160) with a laser beam of a specific wavelength through the transparent template substrate (110). Specifically, the laser lift-off method can use a KrF laser (248 nm) and an ArF laser (194 nm). Heat and gas accompanying the laser lift-off method are supplied through the opening 150 of the template 100 for manufacturing a semiconductor device The first conductive base semiconductor layer 140 can be protected from damage such as cracks and bow. In addition, since the first buffer layer 120 has a lower density than the second buffer layer 130 and the template substrate 110 can be separated by a laser with a lower output power, the first conductive base semiconductor layer 140, Can be further prevented.
또한, 반도체 소자 제조용 템플릿(100)에서 제 1 도전형 기저 반도체층(140)이 예각의 경사를 가진 요철 형태로 형성됨으로써, 광추출 효율을 극대화하기 위한 돌출 형태의 제 1 도전형 기저 반도체층(140)의 특정 패턴은 식각 등의 추가 공정없이 형성될 수 있다. 더욱이 종래의 식각에 의하면, 돌출 형태의 패턴은 균일하지 않으나, 본 실시예에 따르면, 돌출 형태의 패턴이 전면적으로 매우 균일하게 형성될 수 있다. In addition, in the semiconductor device fabrication template 100, the first conductive base semiconductor layer 140 is formed in a concavo-convex shape having an acute angle of inclination, so that the protruding first conductive base semiconductor layer 140 may be formed without additional processes such as etching. Further, according to the conventional etching, the protruding pattern is not uniform, but according to the present embodiment, the protruding pattern can be formed very uniformly over the entire surface.
이에 더하여, 템플릿용 기판(110)이 개구부(150)에 의해 제 1 버퍼층(120)과 부분 접촉하므로, 분리 공정시에 베이스 기판(310)이 발광 구조체를 지지하는 경우에, 별도의 지지체가 공간부에 개재될 필요가 없다. 상세하게는, 부분 접촉으로 인하여 템플릿용 기판(110)과 분리층(160) 간에 작용되는 분리력이 감소될 수 있으므로, 공간부에 베이스 기판(310)과 발광 구조체에 부착되는 수지 등의 지지체 없이도, 분리 공정은 베이스 기판(310)과 도전성 볼들(300) 간의 부착력만으로도 원활하게 진행될 수 있다. 즉, 분리 공정은 별도의 지지체를 추가하는 과정없이 단순화될 수 있다. In addition, since the template substrate 110 partially contacts the first buffer layer 120 by the opening 150, when the base substrate 310 supports the light emitting structure during the separation process, There is no need to intervene. Particularly, the separating force acting between the template substrate 110 and the separation layer 160 can be reduced due to the partial contact. Therefore, even when the base substrate 310 and the support such as resin adhered to the light emitting structure are not provided in the space, The separation process can proceed smoothly even with the adhesion force between the base substrate 310 and the conductive balls 300. That is, the separation process can be simplified without adding a separate support.
아울러, 발광 구조체와 최종적으로 연결하는 인쇄회로기판 등과 베이스 기판(310)이 분리 공정 후에도 잔류할 수 있으므로, 분리 공정을 위한 임시 지지 기판을 이용하는 것에 비해 공정이 더욱 효율적이다. In addition, since the printed circuit board finally connected to the light emitting structure and the base substrate 310 can remain after the separation process, the process is more efficient than using the temporary support substrate for the separation process.
계속해서, 제 1 도전형 기저 반도체층(140) 상에 잔류된 제 2 버퍼층(130)에 대해 연마법 또는 식각 공정을 수행하여, 제 2 버퍼층(130)의 상면을 평탄화하고, HCl과 초순수등의 혼합 용액을 이용하여 화학적 처리에 의해 분리 공정에서 발생된 이물질을 제거한다. Subsequently, the second buffer layer 130 remaining on the first conductive base semiconductor layer 140 is subjected to a polishing or etching process to planarize the upper surface of the second buffer layer 130, and HCl and ultrapure water The foreign matter generated in the separation step is removed by a chemical treatment using a mixed solution of the organic solvent and the organic solvent.
분리 공정과 이물질 제거 등이 완료된 후에, 잔류된 제 2 버퍼층(130), 제 1 도전형 기저 반도체층(140) 및 제 1 도전형 추가 반도체층(210)은 제 1 도전형 반도체층(205)으로 구성된다. After the separation process and the removal of foreign matter are completed, the remaining second buffer layer 130, the first conductive base semiconductor layer 140, and the first conductive type additional semiconductor layer 210 are separated from the first conductive semiconductor layer 205, .
다음으로 도 4d를 참조하면, 외부로의 광탈출 효과를 극대화하기 위해, 제 1 도전형 반도체층(205) 상에 굴절률이 서로 상이한 제 1 및 제 2 조절층(322, 324)이 포함된 조절층(320)을 형성한다. 제 1 및 제 2 조절층(322, 324)은 제 1 도전형 기저 반도체층(140)으로부터 개구부(150)로 갈수록 굴절률이 작아지는 순서로 배열되고, CVD, 열증착법, 스퍼터 등을 이용하여 적층될 수 있다. 제 1 및 제 2 조절층(312, 314)는 GaN계 제 1 도전형 반도체층(205)보다 낮은 굴절율을 갖는 것으로서, SiN, SiO2, TiO, TiN, ZnO, Al2O3 등으로 형성될 수 있다. Next, referring to FIG. 4D, in order to maximize the light escape effect to the outside, the first and second adjustment layers 322 and 324 having different refractive indexes are arranged on the first conductivity type semiconductor layer 205 Layer 320 is formed. The first and second control layers 322 and 324 are arranged in order of decreasing refractive index from the first conductive base semiconductor layer 140 to the opening 150 and are formed by CVD, thermal evaporation, sputtering, . The first and second control layers 312 and 314 may have a refractive index lower than that of the GaN first conductivity type semiconductor layer 205 and may be formed of SiN, SiO 2, TiO 2, TiN, ZnO, Al 2 O 3, or the like.
이하에서는, 도 4d를 참조하여, 본 발명의 실시예에 따른 질화물계 박막을 갖는 발광 소자에 대하여 설명하기로 한다. 이미 상술한 각 구성의 기술적 의미에 대해서는 생략하고, 각 구성을 개략적으로 언급한다. Hereinafter, a light emitting device having a nitride-based thin film according to an embodiment of the present invention will be described with reference to FIG. 4D. The technical meaning of each of the above-described components is omitted, and each configuration is schematically referred to.
도 4a 내지 도 4d의 제조 방법에 의해 제작된 발광 소자는 개구부(150)를 구비하고, 레이저 리프트 오프법에 의한 분리 공정을 통해 잔류되는 분리층인 제 2 버퍼층(130)을 구비한다. 발광 소자는 개구부(150)를 공유하여 개구부(150)를 통해 외측벽이 노출되며 제 2 버퍼층(130) 하부에 질화물계 반도체로 형성되는 제 1 도전형 기저 반도체층(140)과, 제 1 도전형 추가 반도체층(220)이 순차적 적층된 제 1 도전형 반도체층(205)을 포함한다.The light emitting device manufactured by the manufacturing method of FIGS. 4A to 4D includes an opening 150 and a second buffer layer 130 which is a separation layer remaining through a separation process by a laser lift-off method. The light emitting device includes a first conductive type base semiconductor layer 140 formed by a nitride-based semiconductor at the lower portion of the second buffer layer 130 and an outer side wall exposed through the opening 150 by sharing the opening 150, And an additional semiconductor layer 220 includes a first conductive type semiconductor layer 205 which is sequentially stacked.
여기서, 제 2 버퍼층(130)은 레이저 리프트 오프법을 수행할 때, 제 1 도전형 기저 반도체층(140)보다 높은 분리 공정의 선택도를 갖는다. 예컨대, 제 2 버퍼층(130)은 불순물이 주입되지 않도록 비도핑된 질화물 반도체막, 제 1 도전형 기저 반도체층(140)과 동일 성분의 비도핑된 물질막, 금속 산화막 및 금속 질화막 중에서 어느 하나로 형성될 수 있다. Here, the second buffer layer 130 has a selectivity higher than that of the first conductive base semiconductor layer 140 when the laser lift-off method is performed. For example, the second buffer layer 130 may be formed of any one of a non-doped nitride semiconductor film, a non-doped material layer having the same composition as the first conductive base semiconductor layer 140, a metal oxide film, and a metal nitride film .
제 1 버퍼층(도 4b의 120 참조)이 주로 분리 사이트로 작용하나, 레이저 리프트 오프법에 수반되는 열로 인해 제 2 버퍼층(130)도 일부 제거되고 잔존하는 형태로 존재한다. The first buffer layer (see 120 in FIG. 4B) functions mainly as a separation site, but the second buffer layer 130 is also partially removed due to heat accompanying the laser lift-off method.
제조 과정에서 잔류됨에도, 제 2 버퍼층(130)은 제 1 도전형 반도체층(205)에서의 정전기 방전을 억제시킬 수 있다. 제 1 도전형 반도체층(205)은 고농도의 N형 불순물로 도핑되어 있으므로, 정전기 방전(electrostatic discharge)이 유발될 수 있으나, 제 2 버퍼층(130)은 정전기 방전을 최소화할 수 있다. The second buffer layer 130 can suppress the electrostatic discharge in the first conductive type semiconductor layer 205, although it remains in the manufacturing process. Since the first conductive semiconductor layer 205 is doped with a high concentration of N-type impurities, electrostatic discharge may be induced, but the second buffer layer 130 may minimize electrostatic discharge.
또한, 레이저 리프트 오프법에 수반되는 열에 의해, 제 1 도전형 반도체층(205)의 불순물이 확산되어 제 1 도전형 반도체층(205)에서의 도핑 농도와 전도성이 저하되어, 인가 전압이 상승된다. 그러나, 제 2 버퍼층(130)에 의해 불순물 확산이 저지되어, 도핑 농도와 전도성의 저하를 방지할 수 있다. In addition, impurities of the first conductivity type semiconductor layer 205 are diffused by the heat accompanying the laser lift-off method, so that the doping concentration and conductivity in the first conductivity type semiconductor layer 205 are lowered, and the applied voltage is raised . However, the impurity diffusion is prevented by the second buffer layer 130, so that the doping concentration and the conductivity can be prevented from lowering.
이에 더하여, 제 2 버퍼층(130)은 제 1 도전성 기저 반도체층(140)의 외측벽으로 연장하므로, 제 1 도전성 반도체층(205)의 광추출 효율이 더욱 향상될 수 있다. In addition, since the second buffer layer 130 extends to the outer wall of the first conductive base semiconductor layer 140, the light extraction efficiency of the first conductive semiconductor layer 205 can be further improved.
한편, 개구부(150)와 인접한 제 1 도전형 기저 반도체층(140)의 외측벽의 경사각이 개구부(150)와 중첩되는 제 1 도전형 추가 반도체층(220)의 표면에 대하여 예각을 가질 수 있다. The inclined angle of the outer side wall of the first conductive base semiconductor layer 140 adjacent to the opening 150 may have an acute angle with respect to the surface of the first conductive type additional semiconductor layer 220 which overlaps the opening 150.
개구부(150)는 도 2a, 도 2b에 도시된 형태 뿐만 아니라, 다양한 형상으로 형성될 수 있다. 도 2c의 경우, 제 2 버퍼층(130)과 제 1 도전형 기저 반도체층(140)으로 구성된 적층 패턴들의 각각이 서로 이격되도록, 적층 패턴들 주위의 개구부(150c)는 제 2 버퍼층(130)의 상부에서 볼 때, 연결될 수 있다. The opening 150 may be formed in various shapes as well as the shapes shown in Figs. 2A and 2B. 2C, the openings 150c around the stacked patterns are formed in the second buffer layer 130 so that the stacked patterns composed of the second buffer layer 130 and the first conductive base semiconductor layer 140 are separated from each other. When viewed from above, can be connected.
제 2 버퍼층(130) 및 제 1 도전형 기저 반도체층(140)은 각각 1μm 이상, 5μm 이하의 두께로 형성될 수 있으며, 제 1 도전형 추가 반도체층(220)과 인접한 제 1 도전형 기저 반도체층(140)의 하부측 근방에 배치된 개구부는 0.5μm 이상, 5μm 이하의 폭을 가질 수 있다. The second buffer layer 130 and the first conductive base semiconductor layer 140 may be formed to have a thickness of 1 袖 m or more and 5 袖 m or less, respectively, and the first conductive type base semiconductor layer 140, The opening disposed near the bottom side of the layer 140 may have a width of 0.5 占 퐉 or more and 5 占 퐉 or less.
발광 소자는 제 1 도전형 반도체층(205) 하부에 차례로 적층되는 제 1 중간층(first interlayer; 220), 활성층(230), 제 2 중간층(240), 제 2 도전형 반도체층(250) 및 반사층(260)을 포함한다. The light emitting device includes a first interlayer 220, an active layer 230, a second intermediate layer 240, a second conductive semiconductor layer 250, and a reflective layer 250, which are sequentially stacked under the first conductive semiconductor layer 205. (260).
또한, 발광 소자는 제 1 및 제 2 도전형 반도체층(205, 250)에 각각 연결되는 제 1 및 제 2 전극들(280, 290)과, 제 1 및 제 2 전극들(280, 290)에 따라 서로 이격되게 배치되는 도전성 볼들(300) 및 도전성 볼들(300)에 부착하는 베이스 기판(310)을 포함한다. 베이스 기판(310)은 인쇄회로기판, 비전도성 수지 기판, 실리콘 기판, 세라믹 기판 및 글래스 기판 중 어느 하나일 수 있다. The light emitting device includes first and second electrodes 280 and 290 connected to the first and second conductivity type semiconductor layers 205 and 250 and first and second electrodes 280 and 290 connected to the first and second electrodes 280 and 290, Conductive balls 300 disposed to be spaced apart from each other and a base substrate 310 attached to the conductive balls 300. The base substrate 310 may be any one of a printed circuit board, a nonconductive resin substrate, a silicon substrate, a ceramic substrate, and a glass substrate.
발광 소자는 제 1 도전형 반도체층(205) 상에 적층되며, 굴절률이 서로 상이한 제 1 및 제 2 조절층들(312, 314)을 포함할 수 있으며, 제 1 및 제 2 조절층들(312, 314)은 제 1 도전형 반도체층(205)으로부터 개구부(150)로 갈수록 굴절률이 작아지는 순서로 배열될 수 있다. The light emitting device may include first and second control layers 312 and 314 that are stacked on the first conductive type semiconductor layer 205 and have different refractive indices from each other and the first and second control layers 312 And 314 may be arranged in the order of decreasing refractive index from the first conductivity type semiconductor layer 205 to the opening 150.
도 5a 내지 5c는 본 발명의 다른 실시예에 따른 질화물계 박막을 갖는 발광 소자의 제조 방법을 나타내는 단면도들이다. 5A to 5C are cross-sectional views illustrating a method of manufacturing a light emitting device having a nitride-based thin film according to another embodiment of the present invention.
도 5a를 참조하면, 도 4a 및 4b에서와 같이, 반도체 소자 제조용 템플릿(100)을 이용하여 제 1 도전형 추가 반도체층(210) 상에 제 1 중간층(first interlayer; 220), 활성층(230), 제 2 중간층(240), 제 2 도전형 반도체층(250), 반사층(260)을 순차적으로 적층하고, 제 1 도전형 추가 반도체층(210)과 제 2 도전형 반도체층(250)을 전기적으로 연결하는 제 1 및 제 2 전극들(280, 290)을 형성한다. 4A and 4B, a first interlayer 220, an active layer 230, and a third interlayer are formed on the first conductive type additional semiconductor layer 210 by using the template 100 for fabricating a semiconductor device, The second intermediate layer 240, the second conductive semiconductor layer 250 and the reflective layer 260 are sequentially stacked to form the first conductive type additional semiconductor layer 210 and the second conductive type semiconductor layer 250 electrically The first and second electrodes 280 and 290 are formed.
이어서, 템플릿용 기판(110)과 반대측에 위치된 제 1 및 제 2 전극들(280, 290) 상에 테이프(330)를 통해 제 1 이송용 기판(340)을 부착한다. 제 1 이송용 기판(340)은 실리콘, 글래스, 금속 및 필름 중 어느 하나으로 형성될 수 있다. 본 실시예는 제 1 이송용 기판(340)이 하나의 발광 구조체와 부착된 것을 도시하고 있으나, 실제 제작 과정은 제 1 이송용 기판(340)이 복수의 발광 구조체들과 부착돠어 이들을 동시에 소정 위치로 이동시킬 수 있다. The first transfer substrate 340 is then attached to the first and second electrodes 280 and 290 located on the opposite side of the template substrate 110 through the tape 330. The first transfer substrate 340 may be formed of any one of silicon, glass, metal, and film. Although the first transfer substrate 340 is attached to one light emitting structure in the present embodiment, in the actual manufacturing process, the first transfer substrate 340 is attached to the plurality of light emitting structures, .
도 5b를 참조하면, 레이저 리프트 오프법에 의해 발광 구조체를 템플릿용 기판(110)으로부터 분리한다. 분리 공정은 도 4c에서 상세히 기술하였으므로, 이의 설명은 생략한다. Referring to FIG. 5B, the light emitting structure is separated from the template substrate 110 by a laser lift-off method. Since the separation process has been described in detail with reference to FIG. 4C, a description thereof will be omitted.
본 실시예에서와 같이 개구부(150)에 의해 제 1 버퍼층(120)과 부분 접촉하는 반도체 소자 제조용 템플릿(100)을 이용한 레이저 리프트 오프법을 수행함으로써, 발광 구조체의 템플릿용 기판(110)에 대한 분리력이 개구부가 없는 템플릿에 비해 현저히 감소한다. 이에 따라, 발광 구조체가 약한 부착력으로 제 1 이송용 기판(340)에 접착되더라도, 발광 구조체는 분리시에 제 1 이송용 기판(340)에 안정적으로 고정됨과 아울러서, 분리 후에 복수의 발광 구조체를 원하는 위치에 이송할 수 있다. By performing the laser lift-off method using the template 100 for semiconductor device fabrication that is partially in contact with the first buffer layer 120 by the opening 150 as in the present embodiment, The separating force is significantly reduced compared to the template without the opening. Accordingly, even if the light emitting structure is adhered to the first transfer substrate 340 with a weak adhesive force, the light emitting structure is stably fixed to the first transfer substrate 340 at the time of separation, and a plurality of light emitting structures Position.
도 5c를 참조하면, 발광 구조체가 제 1 이송용 기판(340)에 부착된 상태에서, 제 1 도전형 기저 반도체층(140) 상에 굴절률이 서로 상이한 제 1 및 제 2 조절층(322, 324)이 포함된 조절층(320)을 형성한다. Referring to FIG. 5C, the first and second control layers 322 and 324 (see FIG. 5C) having different refractive indexes are formed on the first conductive base semiconductor layer 140 in a state where the light emitting structure is attached to the first transfer substrate 340. (Not shown).
이어서, 제 1 이송용 기판(340)을 발광 구조체로부터 이탈시키고, 제 1 이송용 기판(340)이 부착된 측의 반대측인 제 1 및 제 2 전극들(280, 290)에 테이프(350)를 통해 제 2 이송용 기판(360)을 부착한다. 제 2 이송용 기판(360)은 제 1 이송용 기판(340)과 동일한 재질로 형성될 수 있으며, 후속 공정을 위해 복수의 발광 구조체를 동시에 이송시킬 수 있다. The first transfer substrate 340 is detached from the light emitting structure and a tape 350 is attached to the first and second electrodes 280 and 290 opposite to the side to which the first transfer substrate 340 is attached The second transfer substrate 360 is attached. The second transfer substrate 360 may be formed of the same material as the first transfer substrate 340, and may transfer a plurality of the light emitting structures simultaneously for a subsequent process.
다음으로, 발광 구조체가 제 2 이송용 기판(360)에 부착되거나 제거된 상태에서, 도 4b에서와 마찬가지로, 제 1 및 제 2 전극들(280, 290)에 이격되어 배치되되 도전성 볼들을 형성하고, 도전성 볼들 상에 베이스 기판을 배치한다. 베이스 기판은 도 4b에서 설명한 기판으로 형성될 수 있다. Next, in the state where the light emitting structure is attached to or removed from the second transfer substrate 360, as in FIG. 4B, the conductive balls are formed apart from the first and second electrodes 280 and 290 , And the base substrate is placed on the conductive balls. The base substrate may be formed of the substrate described in Fig. 4B.
도 6a 및 6b는 본 발명의 다른 실시예에 따른 제조 방법에 제 1 및 제 2 도전형 반도체층 측의 현미경 이미지들이다.6A and 6B are microscope images of the first and second conductivity type semiconductor layers on the manufacturing method according to another embodiment of the present invention.
도 6a는 도 5b에서와 같이, 발광 구조체가 제 1 이송용 기판(340)에 부착된 상태에서 레이저 리프트 오프법에 의해 템플릿용 기판(110)이 분리된 경우에, 제 1 도전형 반도체층(205) 측의 표면에 대한 현미경 이미지이다. 도 6b는 도 5c에서와 같이, 발광 구조체가 제 1 이송용 기판(340)으로부터 이탈되고 제 2 이송용 기판(360)에 부착된 상태에서 제 2 도전형 반도체층(250) 측의 표면에 대한 현미경 이미지이다. 6A, when the template substrate 110 is separated by the laser lift-off method in a state where the light emitting structure is attached to the first transfer substrate 340, the first conductive semiconductor layer 205). ≪ / RTI > 6B shows a state in which the light emitting structure is separated from the first transfer substrate 340 and attached to the second transfer substrate 360 and the surface of the second conductive semiconductor layer 250 It is a microscopic image.
도 6a를 살펴보면, 반도체 소자 제조용 템플릿(100)의 개구부(150)를 통해, 레이저 리프트 오프법에서 수반되는 열과 가스가 방출됨으로써, 제 1 도전형 기저 반도체층(205) 측의 표면에 크랙과 보우 등의 손상이 없음을 확인할 수 있었다.6A, heat and gas accompanying the laser lift-off process are released through the opening 150 of the template 100 for fabricating a semiconductor device, so that cracks and bowling are formed on the surface of the first conductive base semiconductor layer 205 side, And it was confirmed that there was no damage such as damage.
도 6b를 살펴보면, 레이저 리프트 오프법의 진행 중에 제 1 이송용 기판(340)이 안정적으로 부착되어, 제 2 도전형 반도체층(360) 측의 표면에 제 1 이송용 기판(340)의 잔류물과 테이프(330) 등이 전혀 잔존하지 않는 것을 확인할 수 있었다.6B, the first transport substrate 340 stably adheres to the surface of the second conductive type semiconductor layer 360 while the laser lift-off method is in progress, And the tape 330 are not left at all.
도 7a 및 7b는 본 발명의 실시예에 따른 제조 방법에 의한 발광 소자의 제 1 도전형 반도체층의 SEM 이미지들이다. 7A and 7B are SEM images of the first conductivity type semiconductor layer of the light emitting device according to the manufacturing method according to the embodiment of the present invention.
도 7a 및 도 7b에 나타난 발광 소자는 레이저 리프트 오프법에 의해 템플릿용 기판(110)을 제 2 버퍼층(130)으로부터 분리됨으로써 제작되었다. The light emitting device shown in FIGS. 7A and 7B was manufactured by separating the template substrate 110 from the second buffer layer 130 by a laser lift-off method.
SEM 이미지들로 알 수 있듯이, 반도체 소자 제조용 템플릿(100)의 개구부(150)을 통해 분리 공정에서 수반되는 열과 가스가 방출됨으로써, 제 2 버퍼층(130) 또는 제 1 도전형 기저 반도체층(140)의 표면에 크랙, 피트 등의 결정 결함이 발생하지 않음을 확인할 수 있다. As can be seen from the SEM images, the second buffer layer 130 or the first conductive base semiconductor layer 140 is formed by the heat and the gas which are released during the separation process through the opening 150 of the template 100 for fabricating a semiconductor device, Crystal defects such as cracks and pits do not occur on the surface of the substrate.
도 8a 내지 8c는 종래 및 본 발명의 실시예에 따라 제조된 발광 소자들의 일부 구성을 나타내는 단면도들이고, 도 9는 도 8a 내지 8c에 도시된 발광 소자들의 파워 프로파일(power profile)을 나타내는 그래프이다. FIGS. 8A to 8C are cross-sectional views showing a part of the structure of the light emitting devices manufactured according to the conventional and the embodiments of the present invention, and FIG. 9 is a graph showing the power profile of the light emitting devices shown in FIGS. 8A to 8C.
도 8a는 종래의 발광 소자(700a)로서, 평평한 형태의 제 1 도전형 반도체층(710a) 상에 패키지를 위한 인캡슐레이션층(720a)이 적층된 발광 소자(700a)이다. 8A is a conventional light emitting device 700a, which is a light emitting device 700a in which an encapsulation layer 720a for a package is stacked on a flat first conductivity type semiconductor layer 710a.
도 8b는 본 발명의 실시예에 따른 반도체 소자 제조용 템플릿을 이용하여 제조된 발광 소자(700b)로서, 제 1 도전형 추가 반도체층(702), 돌출 형태의 제 1 도전형 기저 반도체층(704) 및 더미 형태로 잔류된 제 2 버퍼층(706)로 구성되는 제 1 도전형 반도체층(710b) 상에 인캡슐레이션층(720b)이 적층된 발광 소자(700b)이다. 8B is a light emitting device 700b manufactured using a template for fabricating a semiconductor device according to an embodiment of the present invention. The light emitting device 700b includes a first conductive type additional semiconductor layer 702, a first conductive type base semiconductor layer 704 having a protruding shape, And a second buffer layer 706 which is left in a dummy shape. The light emitting device 700b is formed by laminating an encapsulation layer 720b on a first conductive type semiconductor layer 710b.
도 8c는 종래의 발광 소자(700c)로서, 돌출 형태의 절연성 기판(730c) 상에 컨포멀하게(conformally) 형성된 제 1 도전형 반도체층(710c)과 인캡슐레이션층(720c)이 조합된 발광 소자(700c)이다. 8C shows a conventional light emitting device 700c in which a first conductivity type semiconductor layer 710c conformally formed on a protruding insulating substrate 730c and an encapsulation layer 720c Element 700c.
도 9에서, x축은 도 6a 내지 6c에 도시된 "O"와 대응하는 "0.0"으로부터 발광 소자 내의 거리이고, y축은 발광 파워이다. In Fig. 9, the x-axis is the distance in the light emitting element from " 0 " corresponding to " 0 " shown in Figs. 6A to 6C and the y-axis is the light emitting power.
도 9를 살펴보면, 도 6b에 따른 발광 소자(700b)의 파워 프로파일(820)가 도 8a에 따른 발광 소자(700a)의 파워 프로파일(810)보다 높은 발광 출력을 가짐을 확인할 수 있다. 더욱이, 도 8c의 발광 소자(700c)는 제 1 도전형 반도체층(710c)이 절연성 기판(730c)의 돌출 패턴에 의해 광추출 효율을 증가하는 구조를 가짐에도 불구하고, 도 8b에 따른 발광 소자(700b)의 파워 프로파일(820)이 도 8c의 발광 소자(700c)의 파워 프로파일(830)보다 높은 발광 출력을 가짐을 확인할 수 있다. Referring to FIG. 9, it can be seen that the power profile 820 of the light emitting device 700b according to FIG. 6b has a higher light output power than the power profile 810 of the light emitting device 700a according to FIG. 8a. 8C has a structure in which the first conductivity type semiconductor layer 710c has a structure in which the light extraction efficiency is increased by the protruding pattern of the insulating substrate 730c. However, in the light emitting device 700c of FIG. It can be seen that the power profile 820 of the light emitting element 700b has a higher light output power than the power profile 830 of the light emitting element 700c of FIG. 8C.
도 10a 내지 10c는 본 발명에 따른 반도체 소자 제조용 템플릿 및 종래 기술에 따른 사파이어 기판과 그 전면을 덮은 질화갈륨막의 조합에 있어서, 레이저 리프트 오프법에 따라 레이저를 조사하는 경우를 상정한 시뮬레이션에 대한 결과들이다.10A to 10C are graphs showing results of simulations assuming that a laser is irradiated according to a laser lift-off method in a combination of a template for fabricating a semiconductor device according to the present invention and a gallium nitride film covering a sapphire substrate according to the prior art, admit.
도 10a 내지 10c의 그래프들은 사파이어 등으로 형성된 템플릿용 기판에 적층된 GaN 막에 대한 레이저 리프트 오프법을 조사하는 경우에, 소정의 분석 모델링식을 통해 도출되는 시뮬레이션 결과들이다. 10A to 10C are simulation results derived from a predetermined analytical modeling equation when a laser lift-off method is applied to a GaN film laminated on a template substrate formed of sapphire or the like.
구체적으로, 도 10a 및 10b는 laser fluence가 0.3J/cm2이고, 펄스폭이 25ns로 출력되는 레이저 리프트 오프법이 적용되는 경우의 모델링식에서 산출된 결과들이다.Specifically, FIGS. 10A and 10B are the results calculated by the modeling equation when the laser lift-off method in which the laser fluence is 0.3 J / cm 2 and the pulse width is 25 ns is applied.
도 10a에서, x축은 시간이고, y축은 레이저가 조사된 부분의 GaN막에서의 온도이다. "910"은 본 실시예에 따른 개구부를 가진 GaN막으로 형성된 반도체 소자 제조용 템플릿에 대하여 레이저 리프트 오프법을 수행할 때, 레이저가 조사된 부분에서 시뮬레이션 결과이다. "920"은 종래 기술에 따른 사파이어 기판의 전면을 덮은 GaN막에서 레이저가 조사된 부분에 관한 것이다. In Fig. 10A, the x-axis is time and the y-axis is the temperature in the GaN film of the portion irradiated with the laser. "910" is a simulation result at a portion irradiated with a laser when a laser lift-off method is performed on a template for fabricating a semiconductor device formed of a GaN film having an opening according to this embodiment. &Quot; 920 " refers to a portion irradiated with a laser in a GaN film covering the entire surface of a sapphire substrate according to the prior art.
이를 살펴보면, 본 실시예에서의 GaN 막에 대한 온도 프로파일이 전 시간에 걸쳐 종래 기술에 비해 낮음을 확인할 수 있다. 이는 본 실시예에서 개구부의 열적 특성이 종래 기술과 상이하여, 분리 과정에 발생하는 열이 개구부에 집중될 수 있기 때문이다. As a result, it can be seen that the temperature profile for the GaN film in this embodiment is lower over the entire time than in the prior art. This is because the thermal characteristics of the openings in the present embodiment are different from those in the prior art, and the heat generated in the separation process can be concentrated in the openings.
도 10b에서, x축은 "0"으로 정해진 레이저의 조사 부분으로부터 GaN막 상의 거리이고, y축은 거리에 따른 온도이다. "930"은 본 실시예에서 레이저 리프트 오프법을 수행할 때의 시뮬레이션 결과이다. "940"은 종래 기술에 의할 때의 시뮬레이션 결과이다. In Fig. 10B, the x-axis is the distance on the GaN film from the irradiated portion of the laser set to " 0 ", and the y-axis is the temperature along the distance. &Quot; 930 " is the simulation result when the laser lift-off method is performed in this embodiment. &Quot; 940 " is a result of simulation according to the prior art.
본 실시예에서의 GaN 막에 대한 온도 프로파일이 조사된 부분을 기준으로 양측에 걸쳐 종래 기술에 비해 낮음을 확인할 수 있다. 이 역시 전술한 이유에 기인한다고 생각된다. It can be confirmed that the temperature profile of the GaN film in this embodiment is lower than that of the prior art over both sides based on the irradiated portion. This is also attributed to the above-mentioned reason.
도 10c는 레이저 리프트 오프법에서 레이저 펄스폭에 따른 laser fluence의 임계값을 산출하는 시뮬레이션 결과이다. x축은 조사되는 레이저의 펄스폭이고, y축은 펄스폭에 따른 laser fluence의 임계값이다. 10C is a simulation result for calculating a threshold value of laser fluence according to the laser pulse width in the laser lift-off method. The x-axis is the pulse width of the irradiated laser, and the y-axis is the threshold of laser fluence with respect to the pulse width.
"950"은 본 실시예에서 레이저 리프트 오프법을 수행할 때의 시뮬레이션 결과이다. "960"은 종래 기술에 의할 때의 시뮬레이션 결과이다. &Quot; 950 " is a simulation result when the laser lift-off method is performed in this embodiment. And " 960 " is the result of simulation according to the prior art.
레이저 펄스폭이 증가할수록 laser fluence의 임계값이 증대함에도, 본 실시예에 따른 GaN 막에서의 laser fluence의 임계값이 전 펄스폭에 걸쳐 종래 기술에 비해 낮음을 확인할 수 있다. 이 역시 전술한 이유에 기인한다고 생각된다. Although the threshold value of laser fluence increases as the laser pulse width increases, it can be seen that the threshold value of laser fluence in the GaN film according to this embodiment is lower than that of the prior art over the entire pulse width. This is also attributed to the above-mentioned reason.
이상에서 대표적인 실시예를 통하여 본 발명에 대하여 상세하게 설명하였으나, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자는 상술한 실시예에 대하여 본 발명의 범주에서 벗어나지 않는 한도 내에서 다양한 변형이 가능함을 이해할 것이다. 그러므로 본 발명의 권리 범위는 설명된 실시예에 국한되어 정해져서는 안 되며, 후술하는 특허청구범위뿐만 아니라 이 특허청구범위와 균등 개념으로부터 도출되는 모든 변경 또는 변형된 형태에 의하여 정해져야 한다.While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, I will understand. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by all changes or modifications derived from the scope of the appended claims and the appended claims.

Claims (16)

  1. 개구부를 구비하고, 레이저 리프트 오프법(laser lift-off method)에 의한 분리 공정을 통해 잔류되는 분리층; A separation layer having an opening and remaining through a separation process by a laser lift-off method;
    상기 개구부를 공유하여 상기 개구부를 통해 외측벽이 노출되며 상기 분리층 상에 질화물계 반도체로 형성되는 제 1 도전형 기저 반도체층(a first conductive base semiconductor layer)과, 상기 제 1 도전형 기저 반도체층 상에 형성되는 제 1 도전형 추가 반도체층을 포함하는 제 1 도전형 반도체층;A first conductive base semiconductor layer formed on the isolation layer, the first conductive base semiconductor layer being formed of a nitride-based semiconductor, the first conductive base semiconductor layer being exposed on the outer wall through the opening, A first conductive type semiconductor layer including a first conductive type additional semiconductor layer formed on the first conductive type semiconductor layer;
    상기 제 1 도전형 반도체층 상에 배치되는 활성층; An active layer disposed on the first conductive semiconductor layer;
    상기 활성층 상에 위치되는 제 2 도전형 반도체층; 및 A second conductive semiconductor layer disposed on the active layer; And
    상기 제 1 도전형 반도체층 및 상기 제 2 도전형 반도체층에 연결되는 전극들을 포함하고, And electrodes connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer,
    상기 분리층은 상기 레이저 리프트 오프법을 수행할 때, 상기 제 1 도전형 기저 반도체층보다 높은 분리 공정의 선택도를 가지며, Wherein the separation layer has a selectivity higher than that of the first conductive base semiconductor layer when the laser lift-off method is performed,
    상기 분리층은 불순물이 주입되지 않도록 비도핑된(undoped) 질화물계 반도체막, 상기 제 1 도전형 기저 반도체층과 동일 성분의 비도핑된 물질막, 금속 산화막 및 금속 질화막 중에서 어느 하나로 형성되는 질화물계 박막을 갖는 발광 소자.  The isolation layer may include a nitride based semiconductor film that is not doped with impurities, a non-doped material film that is the same as the first conductive type base semiconductor layer, a nitride based film that is formed of any one of a metal oxide film and a metal nitride film A light emitting device having a thin film.
  2. 제 1 항에 있어서, The method according to claim 1,
    상기 개구부와 인접한 상기 제 1 도전형 기저 반도체층의 외측벽의 경사각이 상기 개구부와 중첩되는 상기 제 1 도전형 추가 반도체층의 표면에 대하여 예각을 갖는 질화물계 박막을 갖는 발광 소자. And a nitride-based thin film having an acute angle with respect to a surface of the first conductive type additional semiconductor layer in which an inclination angle of an outer wall of the first conductive base semiconductor layer adjacent to the opening overlaps the opening.
  3. 제 1 항에 있어서, The method according to claim 1,
    상기 분리층과 상기 제 1 도전형 기저 반도체층으로 구성된 적층 패턴들의 각각이 서로 이격되도록, 상기 적층 패턴들 주위의 개구부는 상기 분리층의 상부에서 볼 때, 연결되는 질화물계 박막을 갖는 발광 소자. Wherein the opening around the lamination patterns has a nitride-based thin film that is connected when viewed from the top of the isolation layer, such that each of the lamination patterns composed of the isolation layer and the first conductive base semiconductor layer is separated from each other.
  4. 제 1 항에 있어서,The method according to claim 1,
    상기 분리층 및 상기 제 1 도전형 기저 반도체층은 각각 1μm 이상, 5μm 이하의 두께로 형성되는 질화물계 박막을 갖는 발광 소자. Wherein the isolation layer and the first conductive base semiconductor layer each have a thickness of 1 占 퐉 or more and 5 占 퐉 or less.
  5. 제 1 항에 있어서, The method according to claim 1,
    상기 제 1 도전형 추가 반도체층과 인접한 상기 제 1 도전형 기저 반도체층의 상부측 근방에 배치된 개구부는 0.5μm 이상, 5μm 이하의 폭을 갖는 질화물계 박막을 갖는 발광 소자.Wherein the opening disposed near the upper side of the first conductive type base semiconductor layer adjacent to the first conductive type additional semiconductor layer has a nitride based thin film having a width of 0.5 占 퐉 or more and 5 占 퐉 or less.
  6. 제 1 항에 있어서, The method according to claim 1,
    상기 전극들에 이격되어 형성되는 도전성 볼들; 및 Conductive balls spaced apart from the electrodes; And
    상기 도전성 볼들 상에 부착하는 베이스 기판을 포함하고, And a base substrate attached to the conductive balls,
    상기 베이스 기판은 인쇄회로기판, 비전도성 수지 기판, 실리콘 기판, 세라믹 기판 및 글래스 기판 중 어느 하나인 질화물계 박막을 갖는 발광 소자. Wherein the base substrate has a nitride-based thin film that is any one of a printed circuit board, a non-conductive resin substrate, a silicon substrate, a ceramic substrate, and a glass substrate.
  7. 제 1 항에 있어서, The method according to claim 1,
    상기 제 1 도전형 반도체층 상에 적층되며, 굴절률이 서로 상이한 복수의 층을 더 포함하고, Further comprising a plurality of layers stacked on the first conductivity type semiconductor layer and having different refractive indices,
    상기 복수의 층은 상기 제 1 도전형 반도체층으로부터 상기 개구부로 갈수록 굴절률이 작아지는 순서로 배열되는 질화물계 박막을 갖는 발광 소자.Wherein the plurality of layers are arranged in the order of decreasing refractive index from the first conductivity type semiconductor layer to the opening.
  8. 투명성을 갖는 템플릿용 기판과, 상기 템플릿용 기판 상에 형성되는 분리층과, 상기 분리층 상에 질화물계 반도체로 형성되는 제 1 도전형 기저 반도체층과, 상기 템플릿용 기판을 노출시키도록 상기 제 1 도전형 기저 반도체층과 상기 분리층을 관통하는 개구부를 포함하고, 상기 템플릿용 기판과 상기 제 1 도전형 기저 반도체층을 분리하는 레이저 리프트 오프법에 의한 분리 공정을 수행할 때, 상기 분리층이 상기 제 1 도전형 기저 반도체층보다 높은 분리 공정의 선택도를 갖는 반도체 소자 제조용 템플릿을 준비하는 단계;A semiconductor device comprising: a template substrate having transparency; a separation layer formed on the template substrate; a first conductivity type base semiconductor layer formed on the separation layer by a nitride semiconductor; The first conductive base semiconductor layer and the first conductive base semiconductor layer are separated from each other by a laser lift-off method that separates the template substrate and the first conductive base semiconductor layer, Preparing a template for semiconductor device fabrication having selectivity of a separation process higher than that of the first conductive base semiconductor layer;
    상기 제 1 도전형 기저 반도체층 상에 제 1 도전형 추가 반도체층을 형성하는 단계;Forming a first conductive type additional semiconductor layer on the first conductive base semiconductor layer;
    상기 제 1 도전형 추가 반도체층 상에 활성층 및 제 2 도전형 반도체층을 순차적으로 형성하는 단계; 및Sequentially forming an active layer and a second conductive type semiconductor layer on the first conductive type additional semiconductor layer; And
    상기 제 1 도전형 추가 반도체층 및 상기 제 2 도전형 반도체층에 연결되는 전극들을 형성하는 단계를 포함하고, And forming electrodes connected to the first conductive type additional semiconductor layer and the second conductive type semiconductor layer,
    상기 분리층에 대한 레이저 리프트 오프법에 의해, 상기 분리층 상부에 형성된 발광 구조체를 상기 템플릿용 기판으로부터 분리하는 단계를 포함하며, Separating the light emitting structure formed on the isolation layer from the template substrate by a laser lift-off method for the isolation layer,
    상기 분리층은 상기 템플릿용 기판 상에 제공되는 제 1 버퍼층 및 상기 제 1 버퍼층 상에 제공되는 제 2 버퍼층을 포함하고, Wherein the separation layer comprises a first buffer layer provided on the template substrate and a second buffer layer provided on the first buffer layer,
    상기 제 1 및 제 2 버퍼층은 불순물이 주입되지 않도록 비도핑된(undoped) 질화물계 반도체막, 상기 제 1 도전형 기저 반도체층과 동일 성분의 비도핑된 물질막, 금속 산화막, 금속 질화막 중에서 동일하거나 서로 다른 막으로 형성되며, The first and second buffer layers may be formed of an undoped nitride based semiconductor film to prevent impurities from being implanted, a non-doped material layer of the same component as the first conductive type base semiconductor layer, a metal oxide film, Are formed of different films,
    상기 제 1 버퍼층은 상기 제 2 버퍼층보다 낮은 치밀도를 갖는 막으로 형성되고, Wherein the first buffer layer is formed of a film having a lower density than the second buffer layer,
    상기 발광 구조체를 상기 템플릿용 기판으로부터 분리하는 단계에서, 상기 제 1 버퍼층에서 절단되어 상기 제 2 버퍼층이 상기 제 1 도전형 기저 반도체층에 잔류하는 질화물계 박막을 갖는 발광 소자의 제조 방법. And separating the light emitting structure from the substrate for template, wherein the second buffer layer is cut in the first buffer layer to leave a nitride-based thin film remaining in the first conductive base semiconductor layer.
  9. 제 8 항에 있어서, 9. The method of claim 8,
    상기 제 1 버퍼층은 10nm 이상, 1μm 이하의 두께로 형성되고, 상기 제 2 버퍼층 및 상기 제 1 도전형 기저 반도체층은 각각 1μm 이상, 5μm 이하의 두께로 형성되는 질화물계 박막을 갖는 발광 소자의 제조 방법. Wherein the first buffer layer is formed to a thickness of 10 nm or more and 1 μm or less and the second buffer layer and the first conductive base semiconductor layer are each formed to a thickness of 1 μm or more and 5 μm or less, Way.
  10. 제 8 항에 있어서, 9. The method of claim 8,
    상기 분리층과 상기 제 1 도전형 기저 반도체층으로 구성된 적층 패턴들의 각각이 서로 이격되도록, 상기 적층 패턴들 주위의 개구부는 상기 분리층의 상부에서 볼 때, 연결되는 질화물계 박막을 갖는 발광 소자의 제조 방법. The opening portions around the lamination patterns are connected to each other when viewed from the top of the isolation layer such that each of the lamination patterns composed of the isolation layer and the first conductive base semiconductor layer is separated from each other, Gt;
  11. 제 8 항에 있어서, 9. The method of claim 8,
    상기 템플릿용 기판에 인접한 상기 분리층은 3μm 이하의 폭을 갖도록 형성되는 질화물계 박막을 갖는 발광 소자의 제조 방법. Wherein the separation layer adjacent to the substrate for template has a nitride-based thin film formed to have a width of 3 mu m or less.
  12. 제 8 항에 있어서, 9. The method of claim 8,
    상기 제 1 도전형 추가 반도체층과 인접하는 상기 제 1 도전형 기저 반도체층의 상부측 근방에 배치된 개구부는 0.5μm 이상, 5μm 이하의 폭을 갖도록 형성되는 질화물계 박막을 갖는 발광 소자의 제조 방법. Wherein the opening portion disposed in the vicinity of the upper side of the first conductive type base semiconductor layer adjacent to the first conductive type additional semiconductor layer has a nitride-based thin film formed to have a width of 0.5 탆 or more and 5 탆 or less .
  13. 제 8 항에 있어서, 9. The method of claim 8,
    상기 발광 구조체를 상기 템플릿용 기판으로부터 분리하는 단계 전에, Before separating the light emitting structure from the template substrate,
    상기 전극들에 이격되어 형성되는 도전성 볼들을 형성하는 단계; 및 Forming conductive balls spaced apart from the electrodes; And
    상기 도전성 볼들 사이에 상기 도전성 볼들을 외부로 노출시키는 공간부와 상기 도전성 볼들 상에 베이스 기판을 배치하는 단계를 더 포함하고, Further comprising disposing a base substrate on the conductive balls, and a space for exposing the conductive balls to the outside between the conductive balls,
    상기 베이스 기판은 인쇄회로기판, 비전도성 수지 기판, 실리콘 기판, 세라믹 기판 및 글래스 기판 중 어느 하나인 질화물계 박막을 갖는 발광 소자의 제조 방법. Wherein the base substrate has a nitride-based thin film that is any one of a printed circuit board, a non-conductive resin substrate, a silicon substrate, a ceramic substrate, and a glass substrate.
  14. 제 8 항에 있어서,9. The method of claim 8,
    상기 발광 구조체를 상기 템플릿용 기판으로부터 분리하는 단계 전에, Before separating the light emitting structure from the template substrate,
    상기 템플릿용 기판과 반대측에 위치된 상기 발광 구조체 상에 테이프를 통해 제 1 이송용 기판을 부착하는 단계를 더 포함하고, Further comprising the step of attaching a first transfer substrate via a tape onto the light emitting structure located on the side opposite to the template substrate,
    상기 발광 구조체를 상기 템플릿용 기판으로부터 분리하는 단계 후에, After separating the light emitting structure from the template substrate,
    상기 제 1 이송용 기판을 상기 발광 구조체로부터 이탈시키고, 상기 제 1 이송용 기판이 부착된 측의 반대측에 테이프를 통해 제 2 이송용 기판을 부착하는 단계; 및 Removing the first transfer substrate from the light emitting structure and attaching a second transfer substrate through a tape to the opposite side of the side to which the first transfer substrate is attached; And
    상기 발광 구조체가 부착된 상기 제 2 이송용 기판을 소정 위치로 이송하여, 상기 전극들에 이격되게 배치되는 도전성 볼들을 형성함과 아울러서, 상기 도전성 볼들 상의 베이스 기판을 배치하는 단계를 더 포함하는 질화물계 박막을 갖는 발광 소자의 제조 방법. Further comprising the step of transferring the second transfer substrate having the light emitting structure attached thereto to a predetermined position to form conductive balls spaced apart from the electrodes and disposing a base substrate on the conductive balls, Based thin film.
  15. 제 8 항에 있어서,9. The method of claim 8,
    상기 제 1 도전형 기저 반도체층과 상기 제 1 도전형 추가 반도체층 상에 굴절률이 서로 상이한 복수의 층을 형성하는 단계를 더 포함하고, Further comprising forming a plurality of layers having different refractive indices on the first conductive base semiconductor layer and the first conductive type additional semiconductor layer,
    상기 복수의 층은 상기 제 1 도전형 기저 반도체층 및 상기 제 1 도전형 추가 반도체층으로부터 상기 개구부로 갈수로 굴절률이 작아지는 순서로 배열되는 질화물계 박막을 갖는 발광 소자의 제조 방법. Wherein the plurality of layers are arranged in the order of decreasing refractive index from the first conductive base semiconductor layer and the first conductive type additional semiconductor layer toward the opening.
  16. 템플릿용 기판;A template substrate;
    상기 템플릿용 기판 상에 형성되는 분리층; A separation layer formed on the template substrate;
    상기 분리층 상에 질화물계 반도체로 형성되는 기저 반도체층(base semiconductor layer); 및 A base semiconductor layer formed of a nitride-based semiconductor on the isolation layer; And
    상기 템플릿용 기판을 노출시키도록 상기 기저 반도체층과 상기 분리층을 관통하는 개구부를 포함하고, And an opening penetrating the base semiconductor layer and the separation layer to expose the template substrate,
    상기 분리층은 상기 템플릿용 기판과 상기 기저 반도체층을 분리하는 레이저 리프트 오프법을 수행할 때, 상기 기저 반도체층보다 높은 분리 공정의 선택도를 가지며, Wherein the separation layer has a selectivity higher than that of the base semiconductor layer when performing a laser lift-off method for separating the substrate for template and the base semiconductor layer,
    상기 분리층은 불순물이 주입되지 않도록 비도핑된(undoped) 질화물계 반도체막, 상기 기저 반도체층과 동일 성분의 비도핑된 물질막, 금속 산화막 및 금속 질화막 중에서 어느 하나로 형성되는 반도체 소자 제조용 템플릿. Wherein the isolation layer is formed of any one of an undoped nitride based semiconductor film, a non-doped material film having the same composition as the base semiconductor layer, a metal oxide film, and a metal nitride film so as to prevent impurities from being implanted.
PCT/KR2018/008670 2017-08-09 2018-07-31 Light emitting device having nitride-based thin film, manufacturing method therefor and template for manufacturing semiconductor device WO2019031755A1 (en)

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KR100622818B1 (en) * 2005-09-27 2006-09-14 엘지전자 주식회사 Method of fabricating vertical electrode type light emitting diode
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KR20140047870A (en) * 2012-10-15 2014-04-23 서울바이오시스 주식회사 Method of separating growth substrate from epitaxial layer, method of fabricating ligh emitting diode using the same and ligh emitting diode fabricated by the same
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