WO2019029836A1 - Receiver unit for an optocoupler - Google Patents

Receiver unit for an optocoupler Download PDF

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Publication number
WO2019029836A1
WO2019029836A1 PCT/EP2018/000264 EP2018000264W WO2019029836A1 WO 2019029836 A1 WO2019029836 A1 WO 2019029836A1 EP 2018000264 W EP2018000264 W EP 2018000264W WO 2019029836 A1 WO2019029836 A1 WO 2019029836A1
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WO
WIPO (PCT)
Prior art keywords
substrate
ssub
receiver module
supply voltage
metal bond
Prior art date
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PCT/EP2018/000264
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German (de)
French (fr)
Inventor
Thomas Lauermann
Christoph Peper
Daniel Fuhrmann
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Azur Space Solar Power Gmbh
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Publication of WO2019029836A1 publication Critical patent/WO2019029836A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • H01L31/16—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
    • H01L31/167—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/035281—Shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled

Definitions

  • Receiver modules are well known in optocouplers. Simple optocouplers have a transmission module and a receiver module, wherein the two components are galvanically isolated but optically coupled. Such embodiments are known from US 4 996 577. Against this background, the object of the invention is to provide a device which further develops the prior art.
  • a receiver module is provided.
  • the receiver module has an optically operated voltage source based on stacked III-V semiconductor layers.
  • the receiver module is formed on an upper side of a non-Si substrate, wherein the voltage source has a first electrical connection contact on an upper side of the stack and a second electrical connection contact on a lower side of the non-Si substrate.
  • the receiver module comprises a Si substrate with a semiconductor integrated circuit formed on an upper side of the Si substrate.
  • the semiconductor circuit has a first supply voltage terminal and a second supply voltage terminal.
  • the first supply voltage terminal is formed on the upper side of the Si substrate.
  • the first connection contact is connected to the first supply voltage connection, wherein the second supply voltage connection is formed on a lower side of the Si substrate.
  • the two substrates are connected to each other by means of the metal bond frictionally.
  • the second supply voltage terminal is connected to the second terminal contact through the metal bond, so that the generated voltage is applied to the semiconductor circuit.
  • the incident light has a wavelength which is within the absorption spectrum of the III-V semiconductor layers.
  • the photon energy of the light corresponding to the light wavelength is at least equal to or greater than the bandgap energy of the absorption layers of the III-V semiconductor layers and the semiconductor layers comprise at least one pn diode.
  • the voltage source is irradiated with the light of an LED, the emission spectrum being generally Gaussian and having, for example, a half width of 20-30 nm in a typical 850 nm LED.
  • the receiver module is that a semiconductor integrated circuit can be supplied with energy by means of the voltage source, and the semiconductor circuit and the voltage source only form a single, very compact component due to the stack-type structure.
  • the reliability and reliability of the metal bond and the common contact can be substantially increased and the voltage source and the semiconductor circuit can be interconnected cost-effectively.
  • the receiver module is part of an optocoupler and cast with the transmission module in a common housing.
  • the size of the receiver module is a maximum of 15 x 15 mm 2 and a minimum of 300 x 300 pm 2 . It can be seen that the output voltage of the voltage source is in a range from a minimum of 2 V to a maximum of 10 V, depending on the number of stacked pn diodes.
  • the semiconductor circuit can be formed as a turn-off circuit or as a crowbar circuit, which shorts the outputs of the circuit in case of drop in voltage in the voltage source.
  • the semiconductor circuit can also be embodied as a driver circuit or as a driver for another component in the field of power electronics or for energy management or for a charge control for a battery.
  • the second supply voltage connection is connected through the Si substrate to the semiconductor circuit and the first connection contact is connected to the first supply voltage connection by means of an electrical conductor device formed on the outside of the stack and the Si substrate.
  • the semiconductor circuit is supplied exclusively with energy of the voltage source.
  • the non-Si substrate comprises at least Ge or GaAs or InP or GaSb or consists of Ge or GaAs or InP or GaSb.
  • the metal bond is formed over the whole area between the two substrates and contains one or more of the elements gold, silver, copper, lead, tin, indium, zinc, aluminum.
  • the two substrates and the metal bond have four common planar side surfaces.
  • the stack has a quadrangular shape, wherein the side surfaces of the stack are recessed at the top of the non-Si substrate, so that forms a circumferential step-shaped shoulder.
  • the metal bond is formed as a common positive pole.
  • the negative pole is formed by means of a bonding wire on the outside.
  • the Si substrate has an SOI layer structure at the top.
  • a vertical electrical connection is formed from the top side Si substrate to the bottom side of the Si substrate, objected to by the semiconductor circuit.
  • the semiconductor layers of the voltage source comprise a plurality of pn diodes, wherein a tunnel diode is formed between two consecutive pn diodes and the pn diodes each have the same band gap and / or the same material composition.
  • FIG. 1 shows a receiver module in a first embodiment
  • FIG. 2 shows a receiver module in a second embodiment.
  • FIG. 1 shows a receiver module EM in a first embodiment.
  • a receiver module EM is preferably integrated as part of an optocoupler, not shown, together with a transmitting part in a common housing.
  • the receiver module EM comprises an optically operated voltage source SP based on stacked III-V semiconductor layers formed on an upper side OS1 of a non-Si substrate NSSUB.
  • the stacked III-V semiconductor layers comprise at least one pn diode.
  • the voltage source SP has a first electrical connection contact Kl on an upper side OSP1 of the stack of III-V semiconductor layers and a second electrical connection contact K2 on a lower side US1 of the non-Si substrate NSSUB.
  • An irradiation of light L takes place only at the top OSP of the stack.
  • a voltage generated by means of the light L is present between the two connection contacts K1 and K2.
  • the receiver module EM comprises a Si substrate SSUB with a Si layer and an integrated semiconductor device IS formed on an upper side OBS1 of the Si substrate SSUB. It is understood that the semiconductor circuit IS consists of a plurality of components and the components are generally electrically isolated from the potential of the SI substrate.
  • the semiconductor circuit IS is connected to the upper side OBS1 by means of a conductor LI with the Si substrate SSUB.
  • the semiconductor circuit IS has a first supply voltage terminal AS1 and a second supply voltage terminal AS2.
  • the first supply voltage terminal AS1 is formed on the upper side OBS1 of the Si substrate SSUB.
  • the first terminal contact Kl is connected by means of a bonding wire Bl to the first supply voltage terminal ASl. It is understood that in addition to the bonding wire, other electrical connections can be formed.
  • the second supply voltage terminal AS2 is formed on a lower side UBS1 of the Si substrate SSUB.
  • a metal-like surface layer is formed as the metal bond M1.
  • the two substrates NSSUB and SSUB are connected by means of the metal bond Ml frictionally and electrically low impedance to each other.
  • the second supply voltage terminal AS2 is connected to the second terminal contact K2 by means of the metal bond MIB, so that the generated voltage of the voltage source SP is applied to the semiconductor circuit IS as the supply voltage.
  • the metal bond M1 forms a common plus pole, while a common negative terminal is formed outside by means of the bonding wire Bl.
  • a receiver module EM is shown in a second embodiment. Only the differences from the embodiment shown in FIG. 1 will be explained below.
  • the Si substrate SSUB comprises an oxide layer OX formed almost over the entire surface area formed on the Si layer SI, and an active region layer SAKT formed on the oxide layer OX over almost the entire surface.
  • the semiconductor integrated circuit IS is formed within the active area layer SAKT.
  • the semiconductor circuit IS is isolated from the Si layer SI.
  • Such a layer structure is referred to as SOI layer structure.
  • the layers OX and SAKT resting on the Si layer SI are etched away, i. the Si layer Si is exposed to at least one location on the upper surface OBS1.
  • the semiconductor circuit IS can be electrically connected to the Si layer by means of the conductor track LI.
  • the voltage source SP comprises a first diode D1 lying on the non-Si substrate and a second diode D2 and a third diode D3. Between the first diode Dl and the second diode D2, a first tunnel diode TD1 is formed. Between the second diode D2 and the third diode D3, a second tunnel diode TD2 is formed. By means of the tunnel diodes TD1 and TD2, the three diodes Dl, D2 and D3 are connected in series. On the top, i. third diode D3 is formed a passivation layer PAS.
  • the voltage source SP comprises three partial voltage sources designed as diodes D1-D3, whose individual voltages add up to the total voltage.
  • the layers of the voltage source SP ie the stack against the not Si substrate set back on all sides, so that forms a circumferential stepped shoulder STU.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to a receiver unit for an optocoupler. The receiver unit comprises an optically operated voltage source based on III-V semiconductor layers arranged in a stack. The semi-conductor layers are embodied on an upper side of a non-Si substrate. The non-Si substrate is non-positively connected, on the lower side thereof, to a lower side of a Si substrate by means of a metal bond. The Si substrate comprises an integrated semiconductor circuit embodied on an upper side of the Si substrate. The semiconductor circuit comprises two supply voltage connections, one of the supply voltage connections being connected to a connection contact of the optically operated voltage source by the metal bond such that the generated voltage is applied to the semiconductor circuit.

Description

EMPFÄNGERBAUSTEIN FÜR EINEN OPTOKOPPLER  RECEIVER BLOCK FOR AN OPTO-COUPLER
Empfängerbausteine sind bei Optokopplern hinlänglich bekannt. Einfache Optokoppler weisen einen Sendebaustein und einen Empfängerbaustein auf, wobei die beiden Bausteine galvanisch getrennt, jedoch optisch gekoppelt sind. Derartige Ausführungsformen sind aus der US 4 996 577 bekannt. Vor diesem Hintergrund besteht die Aufgabe der Erfindung darin, eine Vorrichtung anzugeben, die den Stand der Technik weiterbildet. Receiver modules are well known in optocouplers. Simple optocouplers have a transmission module and a receiver module, wherein the two components are galvanically isolated but optically coupled. Such embodiments are known from US 4 996 577. Against this background, the object of the invention is to provide a device which further develops the prior art.
Die Aufgabe wird durch einen Empfängerbaustein mit den Merkmalen des Patentanspruchs 1 gelöst. Vorteilhafte Ausgestaltungen der Erfindung sind Ge- genstand von Unteransprüchen. The object is achieved by a receiver module having the features of patent claim 1. Advantageous embodiments of the invention are subject matter of subclaims.
Gemäß dem Gegenstand der Erfindung wird ein Empfängerbaustein bereitgestellt. Der Empfängerbaustein weist eine optisch betriebene Spannungsquelle auf Basis von stapeiförmig angeordneten III-V-Halbleiterschichten auf. According to the subject invention, a receiver module is provided. The receiver module has an optically operated voltage source based on stacked III-V semiconductor layers.
Der Empfängerbaustein ist auf einer Oberseite eines nicht Si-Substrats ausgebildet, wobei die Spannungsquelle an einer Oberseite des Stapels einen ersten elektrischen Anschlusskontakt und an einer Unterseite des nicht Si- Substrates eine zweiten elektrischen Anschlusskontakt aufweist. The receiver module is formed on an upper side of a non-Si substrate, wherein the voltage source has a first electrical connection contact on an upper side of the stack and a second electrical connection contact on a lower side of the non-Si substrate.
Zwischen den beiden Anschlusskontakten liegt eine mittels Lichteinstrahlung auf die Oberseite des Stapels generierte Spannung an. Between the two terminal contacts is applied by means of light irradiation on the top of the stack voltage.
Der Empfängerbaustein umfasst ein Si-Substrat mit einer an einer Oberseite des Si-Substrates ausgebildeten integrierten Halbleiterschaltung. Die Halbleiterschaltung weist einen ersten Versorgungsspannungsanschluss und einen zweiten Versorgungsspannungsanschluss auf. The receiver module comprises a Si substrate with a semiconductor integrated circuit formed on an upper side of the Si substrate. The semiconductor circuit has a first supply voltage terminal and a second supply voltage terminal.
Der erste Versorgungsspannungsanschluss ist an der Oberseite des Si- Substrates ausgebildet. The first supply voltage terminal is formed on the upper side of the Si substrate.
Der erste Anschlusskontakt ist mit dem ersten Versorgungsspannungsanschluss verschaltet, wobei der zweite Versorgungsspannungsanschluss an einer Unterseite des Si-Substrates ausgebildet ist. The first connection contact is connected to the first supply voltage connection, wherein the second supply voltage connection is formed on a lower side of the Si substrate.
Zwischen der Unterseite des nicht Si-Substrats und der Unterseite des Si- Substrats ist ein Metallbond ausgebildet. Between the underside of the non-Si substrate and the bottom of the Si substrate, a metal bond is formed.
Die beiden Substrate sind mittels des Metallbonds kraftschlüssig miteinander verbunden. The two substrates are connected to each other by means of the metal bond frictionally.
Der zweite Versorgungsspannungsanschluss ist mit dem zweiten Anschlusskontakt durch den Metallbond verschaltet, so dass an der Halbleiterschaltung die generierte Spannung anliegt. The second supply voltage terminal is connected to the second terminal contact through the metal bond, so that the generated voltage is applied to the semiconductor circuit.
Es versteht sich, dass das eingestrahlte Licht eine Wellenlänge aufweist, die innerhalb des Absoptionsspektrum der III-V Halbleiterschichten liegt. It is understood that the incident light has a wavelength which is within the absorption spectrum of the III-V semiconductor layers.
Es sei angemerkt, dass vorzugsweise ausschließlich die gesamte Oberseite des Stapels mit Licht bestrahlt ist. Auch versteht es sich, dass die der Lichtwellenlänge entsprechende Photonenenergie des Lichts wenigstens größer oder gleich der Bandlückenenergie der Absorptionsschichten der III-V Halbleiterschichten ist und die Halbleiterschichten wenigstens eine pn-Diode umfassen. It should be noted that preferably only the entire upper side of the stack is irradiated with light. It is also understood that the photon energy of the light corresponding to the light wavelength is at least equal to or greater than the bandgap energy of the absorption layers of the III-V semiconductor layers and the semiconductor layers comprise at least one pn diode.
Es versteht sich des Weiteren, dass die Spannungsquelle mit dem Licht einer LED bestrahlt wird, wobei das Emissionsspektrum im Allgemeinen gaußförmig ist und beispielsweise bei einer typischen 850 nm-LED eine Halbwertsbreite von 20-30 nm aufweist. Ein Vorteil des Empfängerbausteins ist es, dass sich mittels der Spannungsquelle eine integrierte Halbleiterschaltung mit Energie versorgen lässt und die Halbleiterschaltung und die Spannungsquelle durch den stapeiförmigen Auf- bau nur einen einzigen sehr kompakten Baustein ausbilden. Insbesondere lässt sich durch den Metallbond und den gemeinsamen Kontakt die Zuverlässigkeit wesentlich erhöhen und kostengünstig die Spannungsquelle und die Halbleiterschaltung miteinander verschalten. Im Allgemeinen ist der Empfängerbaustein Teil eines Optokopplers und mit dem Sendebaustein in einen gemeinsamen Gehäuse eingegossen. It is further understood that the voltage source is irradiated with the light of an LED, the emission spectrum being generally Gaussian and having, for example, a half width of 20-30 nm in a typical 850 nm LED. One advantage of the receiver module is that a semiconductor integrated circuit can be supplied with energy by means of the voltage source, and the semiconductor circuit and the voltage source only form a single, very compact component due to the stack-type structure. In particular, the reliability and reliability of the metal bond and the common contact can be substantially increased and the voltage source and the semiconductor circuit can be interconnected cost-effectively. In general, the receiver module is part of an optocoupler and cast with the transmission module in a common housing.
Vorzugsweise liegt die Größe des Empfängerbausteins bei maximal 15 x 15 mm2 und minimal 300 x 300 pm2. Es zeigt sich, dass die Ausgangsspannung der Spannungsquelle in einen Bereich von minimal 2 V bis maximal 10 V liegt, je nach Anzahl der aufeinander gestapelten pn-Dioden. Preferably, the size of the receiver module is a maximum of 15 x 15 mm 2 and a minimum of 300 x 300 pm 2 . It can be seen that the output voltage of the voltage source is in a range from a minimum of 2 V to a maximum of 10 V, depending on the number of stacked pn diodes.
In einer Ausführungsform lässt sich die Halbleiterschaltung als Turn-Off- Schaltung oder als Crowbar-Schaltung ausbilden, welche bei Abfall der in der Spannungsquelle Spannung die Ausgänge der Schaltung kurzschließt. In one embodiment, the semiconductor circuit can be formed as a turn-off circuit or as a crowbar circuit, which shorts the outputs of the circuit in case of drop in voltage in the voltage source.
Auch lässt sich die Halbleiterschaltung als eine Treiberschaltung oder als eine Ansteuerung für ein weiteres Bauteil aus dem Bereich der Leistungselektronik oder für ein Energiemanagement oder für eine Laderegelung für eine Batterie ausbilden. The semiconductor circuit can also be embodied as a driver circuit or as a driver for another component in the field of power electronics or for energy management or for a charge control for a battery.
In einer Weiterbildung ist der zweite Versorgungsspannungsanschluss durch das Si-Substrat hindurch mit der Halbleiterschaltung verbunden ist und der erste Anschlusskontakt mit dem ersten Versorgungsspannungsanschluss mittels einer an der Außenseite des Stapels und des Si-Substrates ausgebil- deten elektrischen Leitervorrichtung verschaltet ist. In a development, the second supply voltage connection is connected through the Si substrate to the semiconductor circuit and the first connection contact is connected to the first supply voltage connection by means of an electrical conductor device formed on the outside of the stack and the Si substrate.
In einer Ausführungsform ist die Halbleiterschaltung ausschließlich mit Energie der Spannungsquelle versorgt. Vorzugsweise umfasst das nicht Si-Substrat wenigstens Ge oder GaAs oder InP oder GaSb oder besteht aus Ge oder GaAs oder InP oder GaSb. In one embodiment, the semiconductor circuit is supplied exclusively with energy of the voltage source. Preferably, the non-Si substrate comprises at least Ge or GaAs or InP or GaSb or consists of Ge or GaAs or InP or GaSb.
In einer Weiterbildung ist der Metallbond ganzflächig zwischen den beiden Substraten ausgebildet und enthält eines oder mehrere der Elemente Gold, Silber, Kupfer, Blei, Zinn, Indium, Zink, Aluminium. In one development, the metal bond is formed over the whole area between the two substrates and contains one or more of the elements gold, silver, copper, lead, tin, indium, zinc, aluminum.
In einer Ausführungsform weisen die beiden Substrate und der Metallbond vier gemeinsame plane Seitenflächen auf. In einer Weiterbildung weist der der Stapel eine viereckige Form auf, wobei die Seitenflächen des Stapels an der Oberseite des nicht Si-Substrates zurückversetzt sind, so dass sich ein umlaufender stufenförmiger Absatz ausbildet. In one embodiment, the two substrates and the metal bond have four common planar side surfaces. In a development, the stack has a quadrangular shape, wherein the side surfaces of the stack are recessed at the top of the non-Si substrate, so that forms a circumferential step-shaped shoulder.
Vorzugsweise ist der Metallbond als gemeinsamer Pluspol ausgebildet. Der Minuspol ist mittels eines Bonddrahtes an der Außenseite ausgebildet. Preferably, the metal bond is formed as a common positive pole. The negative pole is formed by means of a bonding wire on the outside.
In einer Ausführungsform weist das Si-Substrat an der Oberseite einen SOI Schichtaufbau auf. An der Oberseite von der Halbleiterschaltung ist beanstandet von der Halbleiterschaltung eine vertikale elektrische Verbindung von der Oberseite Si-Substrats zu der Unterseite des Si-Substrates ausgebildet. In one embodiment, the Si substrate has an SOI layer structure at the top. At the top of the semiconductor circuit, a vertical electrical connection is formed from the top side Si substrate to the bottom side of the Si substrate, objected to by the semiconductor circuit.
In einer Weiterbildung umfassen die Halbleiterschichten der Spannungsquelle mehrere pn-Dioden, wobei zwischen zwei aufeinanderfolgenden pn- Dioden eine Tunneldiode ausgebildet ist und die pn-Dioden jeweils den gleichen Bandabstand und / oder die gleich Materialzusammensetzung aufweisen. In one development, the semiconductor layers of the voltage source comprise a plurality of pn diodes, wherein a tunnel diode is formed between two consecutive pn diodes and the pn diodes each have the same band gap and / or the same material composition.
Die Erfindung wird nachfolgend unter Bezugnahme auf die Zeichnungen nä- her erläutert. Hierbei werden gleichartige Teile mit identischen Bezeichnungen beschriftet. Die dargestellten Ausführungsformen sind stark schematisiert, d.h. die Abstände und die lateralen und die vertikalen Erstreckungen sind nicht maßstäblich und weisen, sofern nicht anders angegeben, auch keine ableitbaren geometrischen Relationen zueinander auf. Darin zeigen, die Figur 1 einen Empfängerbaustein in einer ersten Ausführungsform, The invention will be explained in more detail below with reference to the drawings. Here similar parts are labeled with identical names. The illustrated embodiments are highly schematic, ie the distances and the lateral and vertical extensions are not to scale and, unless otherwise indicated, also have no derivable geometrical relations to one another. Show in it, the FIG. 1 shows a receiver module in a first embodiment,
Figur 2 einen Empfängerbaustein in einer zweiten Ausführungsform. 2 shows a receiver module in a second embodiment.
Die Abbildung der Figur 1 zeigt einen Empfängerbaustein EM in einer ersten Ausführungsform. Ein derartiger Empfängerbaustein EM ist vorzugsweise als Teil eines nicht dargestellten Optokopplers zusammen mit einem Sendeteil in einem gemeinsamen Gehäuse integriert. The illustration of FIG. 1 shows a receiver module EM in a first embodiment. Such a receiver module EM is preferably integrated as part of an optocoupler, not shown, together with a transmitting part in a common housing.
Der Empfängerbaustein EM umfasst eine optisch betriebene Spannungsquelle SP auf Basis von stapeiförmig angeordneten III-V-Halbleiterschichten ausge- bildet auf einer Oberseite OS1 eines nicht Si-Substrats NSSUB auf. Die stapeiförmig angeordneten III-V-Halbleiterschichten umfassen wenigstens eine pn-Diode. The receiver module EM comprises an optically operated voltage source SP based on stacked III-V semiconductor layers formed on an upper side OS1 of a non-Si substrate NSSUB. The stacked III-V semiconductor layers comprise at least one pn diode.
Die Spannungsquelle SP weist an einer Oberseite OSPl des Stapels der III-V Halbleiterschichten einen ersten elektrischen Anschlusskontakt Kl und an einer Unterseite US1 des nicht Si-Substrates NSSUB eine zweiten elektrischen Anschlusskontakt K2 auf. Eine Einstrahlung von Licht L findet nur an der Oberseite OSPl des Stapels statt. Bei einer Lichteinstrahlung L auf die Oberseite des Stapels liegt zwischen den beiden Anschlusskontakten Kl und K2 eine mittels des Lichtes L generierte Spannung an. The voltage source SP has a first electrical connection contact Kl on an upper side OSP1 of the stack of III-V semiconductor layers and a second electrical connection contact K2 on a lower side US1 of the non-Si substrate NSSUB. An irradiation of light L takes place only at the top OSP of the stack. In the case of light irradiation L on the top side of the stack, a voltage generated by means of the light L is present between the two connection contacts K1 and K2.
Der Empfängerbaustein EM umfasst ein Si-Substrat SSUB mit einer Si- Schicht und eine an einer Oberseite OBS1 des Si-Substrates SSUB ausgebildeten integrierten Halbleiterschajtung IS. Es versteht sich, dass die Halbleiterschaltung IS aus einer Vielzahl von Bauelementen besteht und die Bauelemente im Allgemeinen gegen das Potential des Sl-Substrates elektrisch isoliert sind. Die Halbleiterschaltung IS ist an der Oberseite OBS1 mittels einer Leiterbahn LI mit dem Si-Substrat SSUB verschaltet. Die Halbleiterschaltung IS weist einen ersten Versorgungsspannungsanschluss ASl und einen zweiten Versorgungsspannungsanschluss AS2 auf. The receiver module EM comprises a Si substrate SSUB with a Si layer and an integrated semiconductor device IS formed on an upper side OBS1 of the Si substrate SSUB. It is understood that the semiconductor circuit IS consists of a plurality of components and the components are generally electrically isolated from the potential of the SI substrate. The semiconductor circuit IS is connected to the upper side OBS1 by means of a conductor LI with the Si substrate SSUB. The semiconductor circuit IS has a first supply voltage terminal AS1 and a second supply voltage terminal AS2.
Der erste Versorgungsspannungsanschluss ASl ist an der Oberseite OBS1 des Si-Substrates SSUB ausgebildet. The first supply voltage terminal AS1 is formed on the upper side OBS1 of the Si substrate SSUB.
Der erste Anschlusskontakt Kl ist mittels eines Bonddrahtes Bl mit dem ersten Versorgungsspannungsanschluss ASl verschaltet. Es versteht sich, dass sich außer dem Bonddraht auch andere elektrische Verbindungen ausbilden lassen. The first terminal contact Kl is connected by means of a bonding wire Bl to the first supply voltage terminal ASl. It is understood that in addition to the bonding wire, other electrical connections can be formed.
Der zweite Versorgungsspannungsanschluss AS2 ist an einer Unterseite UBS1 des Si-Substrates SSUB ausgebildet. The second supply voltage terminal AS2 is formed on a lower side UBS1 of the Si substrate SSUB.
Zwischen der Unterseite US1 des nicht Si-Substrats NSSUB und der Untersei- te UBS1 des Si-Substrats SSUB ist als Metallbond Ml eine ganzflächige Metallschicht ausgebildet. Between the lower side US1 of the non-Si substrate NSSUB and the lower side UBS1 of the Si substrate SSUB, a metal-like surface layer is formed as the metal bond M1.
Die beiden Substrate NSSUB und SSUB sind mittels des Metallbonds Ml kraftschlüssig und elektrisch niederohmig miteinander verbunden. The two substrates NSSUB and SSUB are connected by means of the metal bond Ml frictionally and electrically low impedance to each other.
Der zweite Versorgungsspannungsanschluss AS2 ist mit dem zweiten Anschlusskontakt K2 mittels des Metallbonds MIB verschaltet, so dass an der Halbleiterschaltung IS als Versorgungsspannung die generierte Spannung der Spannungsquelle SP anliegt. The second supply voltage terminal AS2 is connected to the second terminal contact K2 by means of the metal bond MIB, so that the generated voltage of the voltage source SP is applied to the semiconductor circuit IS as the supply voltage.
Indem die beiden Substrate NSSUB und SSUB mittels des Metallbonds Ml miteinander verschaltet sind, fließt ein Strom ISP durch die beiden Substrate NSSUB und SSUB über die Leiterbahn LI hin zu der integrierten Halbeliterschaltung IS. Vorzugsweise bildet der Metallbond Ml ein gemeinsamer Plus- pol aus, während ein gemeinsamer Minuspol außerhalb mittels des Bonddrahtes Bl ausgebildet ist. Since the two substrates NSSUB and SSUB are interconnected by means of the metal bond M1, a current ISP flows through the two substrates NSSUB and SSUB via the conductor LI to the integrated semiconductor circuit IS. Preferably, the metal bond Ml forms a common plus pole, while a common negative terminal is formed outside by means of the bonding wire Bl.
In der Abbildung der Figur 2 ist ein Empfängerbaustein EM in einer zweiten Ausführungsform dargestellt. Nachfolgend werden nur die Unterschiede zu der Ausführungsform dargestellt in der Figur 1 erläutert. In the figure of Figure 2, a receiver module EM is shown in a second embodiment. Only the differences from the embodiment shown in FIG. 1 will be explained below.
Das Si-Substrat SSUB umfasst eine auf der Si-Schicht SI ausgebildete nahezu ganzflächig ausgebildete Oxidschicht OX und eine auf der Oxidschicht OX nahezu ganzflächig ausgebildete Aktivgebietsschicht SAKT. Die integrierte Halbleiterschaltung IS innerhalb der Aktivgebietsschicht SAKT ausgebildet. Hierdurch ist die Halbleiterschaltung IS von der Si-Schicht SI isoliert. Ein derartiger Schichtaufbau wird als SOI-Schichtaufbau bezeichnet. Um die Halbleiterschaltung IS mit dem Strom ISP zu versorgen, sind die auf der Si-Schicht SI aufliegenden Schichten OX und SAKT weggeätzt, d.h. die Si-Schicht Si ist an wenigstens eine Stelle an der Oberseite OBS1 freigelegt. Hierdurch lässt sich mittels der Leiterbahn LI die Halbleiterschaltung IS mit der Si-Schicht elektrisch verbinden. The Si substrate SSUB comprises an oxide layer OX formed almost over the entire surface area formed on the Si layer SI, and an active region layer SAKT formed on the oxide layer OX over almost the entire surface. The semiconductor integrated circuit IS is formed within the active area layer SAKT. As a result, the semiconductor circuit IS is isolated from the Si layer SI. Such a layer structure is referred to as SOI layer structure. In order to supply the semiconductor circuit IS with the current ISP, the layers OX and SAKT resting on the Si layer SI are etched away, i. the Si layer Si is exposed to at least one location on the upper surface OBS1. As a result, the semiconductor circuit IS can be electrically connected to the Si layer by means of the conductor track LI.
Die Spannungsquelle SP umfasst eine auf dem nicht Si-Substrat aufliegende erste Diode Dl und eine zweite Diode D2 und eine dritte Diode D3. Zwischen der ersten Diode Dl und der zweiten Diode D2 ist eine erste Tunneldiode TD1 ausgebildet. Zwischen der zweiten Diode D2 und der dritten Diode D3 ist eine zweite Tunneldiode TD2 ausgebildet. Mittels der Tunneldioden TD1 und TD2 sind die drei Dioden Dl, D2 und D3 in Serie geschaltet. Auf der obersten, d.h. dritten Diode D3 ist eine Passivierungsschicht PAS ausgebildet. The voltage source SP comprises a first diode D1 lying on the non-Si substrate and a second diode D2 and a third diode D3. Between the first diode Dl and the second diode D2, a first tunnel diode TD1 is formed. Between the second diode D2 and the third diode D3, a second tunnel diode TD2 is formed. By means of the tunnel diodes TD1 and TD2, the three diodes Dl, D2 and D3 are connected in series. On the top, i. third diode D3 is formed a passivation layer PAS.
Anders ausgedrückt die Spannungsquelle SP umfasst drei als Dioden D1-D3 ausgebildete Teilspannungsquellen, deren einzelnen Spannungen sich zu der Gesamtspannung addieren. In other words, the voltage source SP comprises three partial voltage sources designed as diodes D1-D3, whose individual voltages add up to the total voltage.
Insbesondere um Kurzschlüsse an den seitlichen Flächen zu vermeiden, sind die Schichten der Spannungsquelle SP, d.h. der Stapel gegenüber dem nicht Si-Substrat an allen Seiten zurückversetzt, sodass sich eine umlaufende stufenförmige Absatz STU ausbildet. In particular, in order to avoid short circuits on the lateral surfaces, the layers of the voltage source SP, ie the stack against the not Si substrate set back on all sides, so that forms a circumferential stepped shoulder STU.

Claims

Patentansprüche claims
Empfängerbaustein (EM) aufweisend Receiver module (EM) having
eine optisch betriebene Spannungsquelle auf Basis von stapeiförmig angeordneten III-V-Halbleiterschichten ausgebildet auf einer Oberseite eines nicht Si-Substrats, wobei an optically powered voltage source based on stapeiförmig arranged III-V semiconductor layers formed on an upper surface of a non-Si substrate, wherein
die Spannungsquelle (SP) an einer Oberseite (OSP1) des Stapels einen ersten elektrischen Anschlusskontakt (Kl) und an einer Unterseite (USl) des nicht Si-Substrates (NSSUB) eine zweiten elektrischen Anschlusskontakt (K2) aufweist, wobei zwischen den beiden Anschlusskontakten (Kl, K2) eine mittels Einstrahlung von Licht (L) auf die Oberseite (OSP1) des Stapels generierte Spannung anliegt, the voltage source (SP) has a first electrical connection contact (K1) on an upper side (OSP1) of the stack and a second electrical connection contact (K2) on a lower side (US1) of the non-Si substrate (NSSUB), wherein between the two connection contacts ( Kl, K2) a voltage generated by the irradiation of light (L) on the top (OSP1) of the stack voltage is applied,
ein Si-Substrat (SSUB) mit einer an einer Oberseite (OBS1) des Si- Substrates (SSUB) ausgebildeten integrierten Halbleiterschaltung (IS), wobei die Halbleiterschaltung (IS) einen ersten Versorgungsspannungs- anschluss (AS1) und einen zweiten Versorgungsspannungsanschluss (AS2) aufweist und der erste Versorgungsspannungsanschluss (AS1) an der Oberseite (OBS1) des Si-Substrates (SSUB) ausgebildet ist, und der erste Anschlusskontakt (Kl) mit dem ersten Versorgungsspannungsanschluss (AS1) verschaltet ist, a Si substrate (SSUB) having a semiconductor integrated circuit (IS) formed on an upper side (OBS1) of the Si substrate (SSUB), the semiconductor circuit (IS) having a first supply voltage connection (AS1) and a second supply voltage connection (AS2) and the first supply voltage connection (AS1) is formed on the upper side (OBS1) of the Si substrate (SSUB), and the first connection contact (Kl) is connected to the first supply voltage connection (AS1),
dadurch gekennzeichnet, dass characterized in that
der zweite Versorgungsspannungsanschluss (AS2) an einer Unterseite des Si-Substrates (UBS1) ausgebildet ist, und the second supply voltage terminal (AS2) is formed on an underside of the Si substrate (UBS1), and
zwischen der Unterseite (USl) des nicht Si-Substrats (NSSUB) und der Unterseite (UBS1) des Si-Substrats (SSUB) ein Metallbond (MIB) ausgebildet ist und die beiden Substrate (NSSUB, SSUB) mittels des Metallbonds (MIB) kraftschlüssig miteinander verbunden sind und der zweite Versorgungsspannungsanschluss (AS2) mit dem zweiten Anschlusskontakt (K2) durch den Metallbond (MIB) verschaltet ist, so dass an der Halbleiterschaltung (IS) die generierte Spannung anliegt. between the underside (USL) of the non-Si substrate (NSSUB) and the underside (UBS1) of the Si substrate (SSUB) a metal bond (MIB) is formed and the two substrates (NSSUB, SSUB) by means of the metal bond (MIB) frictionally are interconnected and the second supply voltage terminal (AS2) to the second terminal contact (K2) through the metal bond (MIB) is connected, so that at the semiconductor circuit (IS), the generated voltage is applied.
2. Empfängerbaustein (EM) nach Anspruch 1, dadurch gekennzeichnet, dass der zweite Versorgungsspannungsanschluss (AS2) durch das Si- Substrat (SSUB) hindurch mit der Halbleiterschaltung (IS) verbunden ist und der erste Anschlusskontakt (Kl) mit dem ersten Versorgungsspannungsanschluss (AS2) mittels einer an der Außenseite des Stapels und des Si-Substrates (SSUB) vorzugsweise als Bonddraht (Mlb) ausgebildeten elektrischen Leitervorrichtung verschaltet ist. 2. receiver module (EM) according to claim 1, characterized in that the second supply voltage terminal (AS2) through the Si substrate (SSUB) through to the semiconductor circuit (IS) is connected and the first terminal contact (Kl) with the first supply voltage terminal (AS2 ) is connected by means of a on the outside of the stack and the Si substrate (SSUB) preferably designed as a bonding wire (Mlb) electrical conductor device.
3. Empfängerbaustein (EM) nach Anspruch 1 oder Anspruch 2, dadurch gekennzeichnet, dass die Halbleiterschaltung (IS) ausschließlich mit Energie der Spannungsquelle versorgt ist. 3. receiver module (EM) according to claim 1 or claim 2, characterized in that the semiconductor circuit (IS) is supplied exclusively with energy of the voltage source.
4. Empfängerbaustein (EM) nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, dass das nicht Si-Substrat (NSSUB) wenigstens Ge o- der GaAs oder InP oder GaSb umfasst oder aus Ge oder GaAs oder InP oder GaSb besteht. 4. receiver module (EM) according to one of claims 1 to 3, characterized in that the non-Si substrate (NSSUB) at least Ge or GaAs or InP or GaSb comprises or consists of Ge or GaAs or InP or GaSb.
5. Empfängerbaustein (EM) nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass der Metallbond (M1B) ganzflächig zwischen den beiden Substraten (SSUB, NSSUB) ausgebildet ist und eines oder mehrere der Elemente Gold, Silber, Kupfer, Blei, Zinn, Indium, Zink, Aluminium enthält. 5. receiver module (EM) according to one of claims 1 to 4, characterized in that the metal bond (M1B) over the entire surface between the two substrates (SSUB, NSSUB) is formed and one or more of the elements gold, silver, copper, lead, tin , Indium, zinc, aluminum.
6. Empfängerbaustein (EM) nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass die beiden Substrate (SSUB, NSSUB) und der Metallbond vier gemeinsame plane Seitenflächen aufweisen. 6. receiver module (EM) according to one of claims 1 to 5, characterized in that the two substrates (SSUB, NSSUB) and the metal bond have four common planar side surfaces.
7. Empfängerbaustein (EM) nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, dass an der Stapel eine viereckige Form aufweist und die Seitenflächen des Stapels an der Oberseite des nicht Si-Substrates (SSUB) zurückversetzt sind, so dass sich ein umlaufender stufenförmiger Absatz (STU) ausbildet. 7. receiver module (EM) according to one of claims 1 to 6, characterized in that at the stack has a quadrangular shape and the side surfaces of the stack at the top of the non-Si substrate (SSUB) are set back, so that a circumferential step-shaped Sales (STU) trains.
8. Empfängerbaustein (EM) nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, dass der Metallbond (M1B) als gemeinsamer Pluspol ausgebildet ist und der Minuspol mittels eines Bonddrahtes (Bl) an der Außenseite ausgebildet ist. 8. receiver module (EM) according to one of claims 1 to 7, characterized in that the metal bond (M1B) is designed as a common positive pole and the negative pole by means of a bonding wire (Bl) is formed on the outside.
9. Empfängerbaustein (EM) nach einem der Ansprüche 1 bis 8, dadurch gekennzeichnet, dass das Si-Substrat (SSUB) an der Oberseite einen SOI Schichtaufbau aufweist und an der Oberseite (OBSl) beanstandet von der Halbleiterschaltung (IS) eine vertikale elektrische Verbindung von der Oberseite Si-Substrats (SSUB) zu der Unterseite (UBS1) des Si- Substrates (SSUB) ausgebildet ist. 9. receiver module (EM) according to one of claims 1 to 8, characterized in that the Si substrate (SSUB) at the top has a SOI layer structure and at the top (OBSl) from the semiconductor circuit (IS) a vertical electrical connection from the top Si substrate (SSUB) to the bottom (UBS1) of the Si substrate (SSUB) is formed.
Empfängerbaustein (EM) nach einem der Ansprüche 1 bis 9, dadurch gekennzeichnet, dass die Halbleiterschichten der Spannungsquelle mehrere pn-Dioden (D1-D3) umfassen, wobei zwischen zwei aufeinanderfolgenden pn-Dioden (D1-D3) jeweils eine Tunneldiode (Tdl, TD2) ausgebildet ist und die pn-Dioden (D1-D3) jeweils den gleichen Bandabstand aufweisen. Receiver module (EM) according to one of claims 1 to 9, characterized in that the semiconductor layers of the voltage source comprise a plurality of pn diodes (D1-D3), wherein between two consecutive pn diodes (D1-D3) each have a tunnel diode (Tdl, TD2 ) is formed and the pn diodes (D1-D3) each have the same band gap.
PCT/EP2018/000264 2017-08-09 2018-05-18 Receiver unit for an optocoupler WO2019029836A1 (en)

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