WO2019023945A1 - 流道结构器件及其制造方法 - Google Patents

流道结构器件及其制造方法 Download PDF

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Publication number
WO2019023945A1
WO2019023945A1 PCT/CN2017/095501 CN2017095501W WO2019023945A1 WO 2019023945 A1 WO2019023945 A1 WO 2019023945A1 CN 2017095501 W CN2017095501 W CN 2017095501W WO 2019023945 A1 WO2019023945 A1 WO 2019023945A1
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Prior art keywords
substrate
layer
trench
structure device
flow channel
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PCT/CN2017/095501
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English (en)
French (fr)
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云全新
林建勋
李汉东
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深圳华大基因研究院
完整基因有限公司
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Priority to CN201780090926.6A priority Critical patent/CN110753580B/zh
Priority to PCT/CN2017/095501 priority patent/WO2019023945A1/zh
Publication of WO2019023945A1 publication Critical patent/WO2019023945A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L3/00—Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate

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  • the present invention relates to the field of semiconductor technology, and in particular, to a flow channel structure device and a method of fabricating the same.
  • Micro-nano flow control analysis technology based on micro-nano flow channel is being studied and applied more and more in the fields of biochemical analysis and gene sequencing.
  • the combination of micro-nano channel devices and integrated circuits (ICs) will also help to improve the automation and miniaturization of micro-analysis systems and better expand their application space.
  • electrode materials need to be embedded in the micro-nano flow channels, and in some designs, nano-flow channels with high aspect ratios are required.
  • electron beam lithography or laser lithography may be employed, and an anisotropic etching process is combined to realize a nano flow channel.
  • direct electron beam or laser lithography methods are inefficient, have poor dimensional adjustability, and are difficult to achieve high aspect ratios on metallic materials, usually only about one.
  • the side wall method can also be used to implement the above micro-nano flow path structure.
  • the sidewall method must rely on the side wall support structure of the semiconductor material to achieve structural interconnection and signal extraction, which will bring more parasitic effects, and ultimately affect the quality of the detection signal, and the process thermal budget is high, which is not conducive to integration with CMOS chips.
  • most electrode extractions in the prior art rely on spliced metal interconnects (e.g., typically aluminum and copper) or semiconductor interconnects (e.g., typically polysilicon) to form an alloy structure with the electrode material.
  • the alloy structure has the following disadvantages: (1) The alloy process requires an additional heat treatment process, which will increase the process heat budget, which is not conducive to process integration on the IC chip.
  • a typical polysilicon interconnect process for example, a polysilicon deposition process is required (the temperature is usually high). At 600 ° C), ion implantation and activation (usually above 550 ° C) and metal semiconductor alloys (usually above 400 ° C) and other high thermal budget technology; (2) alloy body will introduce additional contact resistance, which Will reduce device performance.
  • the nanogap structure can also be realized by adjusting the metal sputtering angle.
  • the particle sputtering direction is at an angle to the surface of the substrate substrate, and the groove can be prepared in advance by adjusting the angle.
  • a dead angle of sputtering is generated at the bottom to obtain a nano-gap flow path structure, but process controllability and dimensional adjustability are poor.
  • the inventors of the present invention have found that there is a problem in the above prior art, and thus propose a new technical solution to at least one of the problems.
  • a method of fabricating a flow path structure device comprising: providing a first substrate; forming a first trench in the first substrate; forming on the first substrate a material layer, wherein a portion of the material layer is formed in the first trench to form a second trench; a sacrificial layer is formed on the material layer, the sacrificial layer including being filled in the second trench a first portion; the first substrate after the sacrificial layer is formed is bonded to the second substrate such that the material layer is between the first substrate and the second substrate; A back side of a substrate is subjected to a thinning treatment to expose the first portion of the sacrificial layer; and the first portion is removed by a selective etching process to form a flow path.
  • the method further includes Forming a capping layer on the back side of the first substrate after the thinning process, wherein the capping layer covers the first portion of the sacrificial layer.
  • the material of the cap layer comprises: an insulating dielectric material or a semiconductor material; the cap layer has a thickness ranging from 1 nanometer to 10 micrometers.
  • a selective etching solution is injected from an edge side of the second trench to remove the first portion.
  • the method before removing the first portion by a selective etch process, the method further includes etching the cap layer to form a via hole penetrating the cap layer and exposing the first portion Wherein in the step of removing the first portion by a selective etching process, a selective etching solution is injected from the via hole to remove the first portion.
  • the sacrificial layer in the step of forming a sacrificial layer on the material layer, further includes: a second portion formed outside the second trench.
  • the method further comprising: removing the second portion of the sacrificial layer a portion to expose a portion of the material layer that is outside the first trench; wherein, in the step of bonding the first substrate after forming the sacrificial layer to the second substrate, A portion of the material layer outside the first trench is bonded to the second substrate.
  • the selective etching process further removes a portion of the second portion corresponding to the flow channel, thereby causing the The second part is broken.
  • the step of forming a first trench in the first substrate comprises: forming a patterned mask layer on the first substrate; etching the mask layer as a mask The first substrate to form a first trench; and the mask layer is removed.
  • the material of the material layer comprises: a metal material or a semiconductor material; wherein a portion of the material layer in the first trench serves as an electrode of the flow channel structure device; A portion of the layer between the first substrate and the second substrate serves as a lead of the electrode.
  • the material of the material layer comprises: an insulating dielectric material.
  • the first trench has a width ranging from 10 nanometers to 100 micrometers, the first trench has a depth ranging from 10 nanometers to 1 millimeter; and the material layer has a thickness ranging from 1 nanometer to 50 nanometers. Micrometers; the width of the flow channel ranges from 0.1 nanometers to 1 micrometer; the thickness of the sacrificial layer is greater than one-half of the width of the flow channel.
  • a first trench is formed in the first substrate, and then a material layer filling the first trench is formed on the first substrate to form a second trench; and then formed on the material layer a sacrificial layer to fill the second trench; then bonding the first substrate to the second substrate; thinning the back side of the first substrate to expose the first portion of the sacrificial layer; and utilizing selective etching
  • the process removes the first portion to form a flow path.
  • the above manufacturing method of the present invention can form a flow path structure device having a vertical flow path, and the above manufacturing method can reduce the process heat budget and facilitate integration of the flow path structure device and the CMOS chip.
  • the above manufacturing method can realize a flow structure of a high aspect ratio.
  • the material of the material layer may be a metal material or a semiconductor material
  • a portion of the material layer in the first trench may be used as an electrode embedded in the flow channel.
  • the portion of the material layer in the first trench and the portion outside the first trench are formed together.
  • a portion of the material layer in the first trench serves as an electrode
  • a portion of the material layer outside the first trench ie, a portion between the first substrate and the second substrate
  • Electrode lead Line which reduces contact resistance.
  • a flow path structure device comprising: a first substrate formed with a groove penetrating the first substrate; a second substrate, and the first substrate And a material layer, wherein a portion of the material layer is on a sidewall of the trench and forms a flow channel, and another portion of the material layer is located on the first substrate and the second substrate between.
  • the flow channel structure device further includes: a cap layer on the first substrate, wherein the cap layer overlies the flow channel.
  • the material of the cap layer comprises: an insulating dielectric material or a semiconductor material; the cap layer has a thickness ranging from 1 nanometer to 10 micrometers.
  • the flow channel structure device further includes a through hole penetrating the cap layer and communicating to the flow channel.
  • the flow channel structure device further includes a sacrificial layer between the material layer and the second substrate.
  • the sacrificial layer is broken at a location corresponding to the flow channel.
  • the material of the material layer comprises: a metal material or a semiconductor material; wherein a portion of the material layer on a sidewall of the trench serves as an electrode of the flow channel structure device; A portion of the material layer between the first substrate and the second substrate serves as a lead of the electrode.
  • the material of the material layer comprises: an insulating dielectric material.
  • the trench has a width ranging from 10 nanometers to 100 micrometers, the trench has a depth ranging from 10 nanometers to 1 millimeter; and the material layer has a thickness ranging from 1 nanometer to 50 micrometers;
  • the width of the flow channel ranges from 0.1 nanometers to 1 micrometer; the thickness of the sacrificial layer is greater than one-half of the width of the flow channel.
  • the flow path structure device of the above embodiment of the present invention has a vertical flow path, which can increase the manufacturing density of the flow path on the chip, can improve application throughput, and reduce manufacturing and application costs.
  • the above-described flow path structure device can realize a flow structure of a high aspect ratio.
  • the material layer is made of a metal material or a semiconductor material
  • the portion between the second substrate and the second substrate can serve as a lead for the electrode, which can lower the contact resistance.
  • a flow path sensor comprising: a flow path structure device as described above.
  • a biochemical analysis apparatus comprising: a flow path structure device as described above.
  • a chip for molecular detection comprising: a flow path structure device, a signal collection unit, and a signal processing unit as described above; wherein a sample to be detected is added to the flow path In the flow channel of the structural device, in the case where the electrode of the flow channel structure device is electrically excited, the target molecule in the sample to be detected generates an electrical signal or an optical signal under electrical excitation; the signal collecting unit is used for Collecting the electrical signal or the optical signal and transmitting the electrical signal or the optical signal to the signal processing unit; the signal processing unit is configured to perform signal processing on the electrical signal or the optical signal Identifying information about the target molecule.
  • a method of molecular detection comprising: performing molecular detection using a chip as described above.
  • the step of performing molecular detection using the chip comprises: processing a sample to be detected; adding the sample to be detected to the chip; applying an electrode in a flow channel structure device in the chip Electrically exciting such that the target molecule in the sample to be detected generates an electrical signal or an optical signal under electrical excitation; and the signal processing unit of the chip obtains the electrical signal or the light through the signal collecting unit And signaling the electrical signal or the optical signal to identify information of the target molecule.
  • the application of molecular detection is realized by using a chip including the flow path structure device of the embodiment of the present invention.
  • FIG. 1 is a flow chart showing a method of fabricating a flow path structure device in accordance with one embodiment of the present invention.
  • FIG. 2 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • FIG. 3 is a view schematically showing a manufacturing process of a flow path structure device according to an embodiment of the present invention. A cross-sectional view of the structure of the stage.
  • FIG. 4 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • Fig. 5 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • Fig. 6 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • Fig. 7 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • Fig. 8 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • Figure 9 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • Figure 10 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • Figure 11 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 12 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 13 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Fig. 14 is a plan view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 15 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 16 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 17 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • Figure 18 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • 19 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • 20 is a structural view schematically showing a chip for molecular detection according to an embodiment of the present invention.
  • 21 is a flow chart showing a molecular detection method according to an embodiment of the present invention.
  • FIG. 1 is a flow chart showing a method of fabricating a flow path structure device in accordance with one embodiment of the present invention.
  • 2 to 10 are cross-sectional views schematically showing the structure of several stages in the manufacturing process of the flow path structure device according to an embodiment of the present invention. The manufacturing process of the flow path structure device according to an embodiment of the present invention will be described in detail below with reference to FIG. 1 and FIGS. 2 to 10.
  • step S101 a first substrate is provided.
  • the first substrate 21 may include: a semiconductor substrate (eg, silicon, germanium, etc.), an insulating substrate (eg, quartz, silicon nitride, etc.), collected Become a wafer of IC circuits or any combination of these substrates.
  • a semiconductor substrate eg, silicon, germanium, etc.
  • an insulating substrate eg, quartz, silicon nitride, etc.
  • step S102 a first trench is formed in the first substrate.
  • the process of implementing this step S102 according to an embodiment of the present invention will be described in detail below with reference to FIGS. 3 through 5.
  • the step S102 may include forming a patterned mask layer 22 on the first substrate 21 as shown in FIG.
  • the patterned mask layer 22 can be obtained on the first substrate 21 using a photolithography process.
  • the material of the mask layer may include a photoresist or the like.
  • the lithography process may include: optical lithography, electron beam lithography, nanoimprint lithography, or focused ion beam lithography.
  • the step S102 may further include: etching the first substrate 21 to form the first trench 31 by using the mask layer 22 as a mask as shown in FIG. 4 .
  • an anisotropic etch process can be used to etch the first substrate to form the first trench.
  • the anisotropic etching process may include a dry etching process or a wet etching process.
  • the first trench 31 may have a width ranging from 10 nanometers to 100 micrometers.
  • the width of the first trench 31 may be 100 nanometers, 500 nanometers, 1 micrometer, 10 micrometers, or 50 micrometers.
  • the first trench 31 may have a depth ranging from 10 nanometers to 1 millimeter.
  • the depth of the first trench 31 may be 100 nanometers, 500 nanometers, 1 micrometer, 10 micrometers, 100 micrometers, or 500 micrometers, or the like.
  • the step S102 may further include removing the mask layer 22 as shown in FIG.
  • the first trench 31 is formed in the first substrate 21.
  • step S103 a material layer is formed on the first substrate, wherein a portion of the material layer is formed in the first trench to form a second trench.
  • Fig. 6 is a cross-sectional view schematically showing the structure of the step S103 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • a material layer 43 can be formed on the first substrate 21 by, for example, a deposition process. A portion of the material layer 43 is formed in the first trench 31, and the width of the first trench 31 is reduced to form the second trench 32.
  • another portion of the material layer 43 is formed outside the first trench 31, that is, the other portion is formed on the upper surface of the first substrate 21.
  • the material of the material layer 43 may include: a metal material (eg, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metals) or a semiconductor material (eg, polysilicon, amorphous silicon) , indium tin oxide or the like or a combination of various semiconductor materials).
  • a metal material eg, gold, platinum, silver, titanium, titanium nitride, or the like, or a combination of metals
  • a semiconductor material eg, polysilicon, amorphous silicon
  • the material layer 43 is made of a conductive material such as a metal material or a semiconductor material
  • a portion of the material layer 43 in the first trench 31 may serve as an electrode of the flow channel structure device;
  • a portion of the material layer 43 outside the first trench i.e., a portion between the first substrate and the second substrate (which will be described later) serves as a lead of the electrode.
  • the material The material of the material layer 43 may include: an insulating dielectric material (for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination of a plurality of insulating dielectric materials). This makes it possible to form a flow path structure device surrounded by an insulating medium in a subsequent step.
  • the material layer 43 may have a thickness ranging from 1 nanometer to 50 micrometers.
  • the material layer 43 may have a thickness of 10 nanometers, 100 nanometers, 500 nanometers, 1 micrometer or 10 micrometers, or the like.
  • the second trench 32 may have a width ranging from 0.1 nanometers to 1 micrometer.
  • the second trench 32 may have a width of 1 nm, 10 nm, 100 nm, or 500 nm, and the like.
  • the second trench is used to form a flow channel, and the width of the second trench is the width of the flow channel.
  • step S104 a sacrificial layer is formed on the material layer, the sacrificial layer including a first portion filled in the second trench.
  • Fig. 7 is a cross-sectional view schematically showing the structure of the step S104 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • a sacrificial layer 45 is formed on the material layer 43 to fill the second trenches 32.
  • the sacrificial layer 45 may include a first portion 451 that is filled in the second trench 32.
  • the sacrificial layer 45 may further include a second portion 452 formed outside the second trench 32.
  • the second portion 452 is formed on the material layer 43 above the upper surface of the first substrate 21.
  • the material of the sacrificial layer 45 may include: a metal material (eg, chromium, aluminum, titanium, or the like, or a combination of metal materials), a semiconductor material (eg, polysilicon, amorphous silicon, indium tin oxide, etc.) Or a combination of a plurality of semiconductor materials) or an insulating dielectric material (for example, a combination of silicon dioxide or silicon nitride or the like) or the like.
  • the material of the sacrificial layer 45 is not limited to metal or non-metal.
  • the main basis and standard of selection is the corrosion selectivity between the material of the sacrificial layer 45 and the material of the material layer 43 as the damascene electrode. Generally, the corrosion selectivity ratio is as large as possible. . For example, when some metal materials are used as the electrodes, the corresponding sacrificial layer materials may be selected to match other materials having a high corrosion selectivity.
  • the thickness of the sacrificial layer 45 may be determined according to the width of the second trench (ie, the width of the runner formed in the subsequent step) to ensure that the second trench 32 is filled.
  • the width and thickness of the second trench 32 are determined by design requirements and are obtained by filling the first trench by the material layer 43, that is, the second trench corresponds to the two-layer material layer 43 filled in the first trench.
  • the thickness of the sacrificial layer 45 is greater than 1/2 (one-half) of the width of the slit to ensure that the sacrificial layer 45 can completely fill the gap. That is, the thickness of the sacrificial layer 45 is greater than one-half the width of the flow channel (which will be formed in a subsequent step).
  • the sacrificial layer 45 may be formed by a process such as physical deposition (for example, sputtering), chemical deposition (for example, CVD (Chemical Vapor Deposition)), or electroplating.
  • physical deposition for example, sputtering
  • chemical deposition for example, CVD (Chemical Vapor Deposition)
  • electroplating for example, electroplating
  • step S105 the first substrate after forming the sacrificial layer is bonded to the second substrate such that the material layer is located between the first substrate and the second substrate.
  • Figure 8 is a cross-sectional view schematically showing the structure of the flow path structure device in the manufacturing process of step S105 according to an embodiment of the present invention.
  • the first substrate 21 after forming the sacrificial layer is bonded to the second substrate 47 such that the material layer 43 is located between the first substrate 21 and the second substrate 47, for example, the material A portion of the layer 43 outside the first trench 31 is located between the first substrate 21 and the second substrate 47.
  • the second portion 452 of the sacrificial layer 45 is bonded to the second substrate 47.
  • the second substrate 47 may include: a semiconductor substrate (eg, silicon, germanium, etc.), an insulating substrate (eg, quartz, silicon nitride, etc.), a wafer with integrated IC circuitry, or these liners Any combination of the bottom.
  • a semiconductor substrate eg, silicon, germanium, etc.
  • an insulating substrate eg, quartz, silicon nitride, etc.
  • a wafer with integrated IC circuitry e.g., silicon, germanium, etc.
  • step S106 the back surface of the first substrate is subjected to a thinning process to expose the first portion of the sacrificial layer.
  • Figure 9 is a cross-sectional view schematically showing the structure of the flow path structure device in the manufacturing process of step S106 in accordance with one embodiment of the present invention.
  • the back surface of the first substrate 21 is thinned, for example, by a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the material layer 43 that is, the portion of the exposed material layer 43 in the first trench 31, is also exposed.
  • step S107 the first portion is removed by a selective etching process to form a flow path.
  • Figure 10 is a cross-sectional view schematically showing the structure of the step S107 in the manufacturing process of the flow path structure device according to an embodiment of the present invention.
  • the first portion 451 of the sacrificial layer 45 is removed by a selective etching process to form the flow channel 50.
  • the flow channel 50 may have a width ranging from 0.1 nanometers to 1 micrometer.
  • the width of the flow channel 50 may be 1 nm, 10 nm, 100 nm, or 500 nm, and the like.
  • the thickness of the sacrificial layer 45 is greater than one-half of the width of the flow channel.
  • a method of manufacturing a flow path structure device has been provided.
  • a first trench is formed in the first substrate, and then a material layer filling the first trench is formed on the first substrate to form a second trench; then a sacrificial layer is formed on the material layer, thereby Filling the second trench; then bonding the first substrate to the second substrate; thinning the back surface of the first substrate to expose the first portion of the sacrificial layer; and removing the first portion by a selective etching process Part of it to form a flow path.
  • the manufacturing method of the present invention can form a flow path structure device having a vertical flow path (i.e., the flow path is perpendicular to the upper or lower surface of the second substrate).
  • the flow channel may be an open space in a direction perpendicular to the substrate or may be provided with a transparent material so as not to affect the optical signal. Transmission.
  • the effective surface area of a single flow channel can be the cross-sectional area of the flow channel, which can greatly increase the manufacturing density of the flow channel on the chip, and reduce manufacturing and application costs.
  • the above manufacturing method of the embodiment of the present invention can reduce the process heat budget.
  • the process of the present invention involves relatively low process temperatures (temperatures ranging from room temperature to 350 ° C) and short heat treatment times, thereby reducing the process thermal budget to facilitate integration of the flow channel structure device with the CMOS chip.
  • the above manufacturing method can realize a flow structure of a high aspect ratio.
  • a flow path structure having a width of 10 nm and an aspect ratio of 100:1 can be realized.
  • the aspect ratio of the flow channel structure achieved by the method of the embodiment of the present invention may range from 1:1 to 100,000:1.
  • the material of the material layer may be a conductive material such as a metal material or a semiconductor material (for example, a doped semiconductor material)
  • the above manufacturing method may realize forming one electrode, one pair of electrodes or more pairs of electrodes in the flow channel.
  • a layer of electrodes ie, a layer of a material using a metal or a semiconductor material
  • Two electrodes on both sides of the flow channel (for example, a portion of the material layer on the left side of the flow channel may be referred to as a first electrode, and a portion of the material layer on the right side of the flow channel may be referred to as a second electrode), the two electrodes Can be used as a pair of working electrodes.
  • more pairs of electrodes may be formed on both sides of the flow channel.
  • a plurality of material layer portions distributed along the second trench may be formed by a patterning process in the process of forming a material layer, and then passed through the subsequent process. In the process, each material layer portion forms a pair of electrodes respectively on both sides of the flow channel, so that the plurality of material layer portions form a plurality of pairs of electrodes on both sides of the flow channel.
  • a portion of the material layer in the first trench and a portion outside the first trench are formed together.
  • a portion of the first trench of the material layer serves as an electrode
  • a portion of the material layer outside the first trench ie, a portion located between the first substrate and the second substrate
  • Lead wires in particular, can be made of an all-metal joint structure, which can reduce contact resistance and lead resistance.
  • a flow path structure device is also formed by the manufacturing method of the embodiment of the present invention.
  • the flow path structure device may include a first substrate 21 formed with a groove 31 penetrating the first substrate.
  • the width of the trench 31 may range from 10 nanometers to 100 micrometers, and the depth of the trench 31 may range from 10 nanometers to 1 millimeter.
  • the flow path structure device may further include a second substrate 47 bonded to the first substrate 21.
  • the flow channel structure device may further include: a material layer 43 in which a portion of the material layer 43 is located on the sidewall of the trench 31 and forms a flow channel 50, and another portion of the material layer 43 is located on the first substrate 21 and the second Between the substrates 47.
  • the material of the material layer 43 may include a metal material or a semiconductor material.
  • a portion of the material layer 43 on the side wall of the trench 31 serves as an electrode of the flow path structure device; a portion of the material layer 43 between the first substrate 21 and the second substrate 47 As the lead of the electrode.
  • the material of the material layer 43 may include: an insulating dielectric material.
  • an insulating dielectric material as the material layer, the flow channel structure device can be applied to some cases where it is not necessary to apply an electrode in the flow channel.
  • a specific insulating dielectric material is required as a material layer to modify the flow channel surface.
  • the material layer 43 may have a thickness ranging from 1 nanometer to 50 micrometers. In one embodiment, the flow channel 50 may have a width ranging from 0.1 nanometers to 1 micrometer.
  • the flow channel structure device may further include a sacrificial layer 45 between the material layer 43 and the second substrate 47.
  • the first substrate 21 is bonded to the second substrate 47 through the sacrificial layer 45.
  • the thickness of the sacrificial layer 45 is greater than one-half of the width of the flow channel 50.
  • the flow path structure device of the above embodiment of the present invention has a vertical flow path, for example, the flow path may be an open space in a direction perpendicular to the surface of the second substrate or may be provided with a transparent material, so that this does not affect the transmission of the optical signal.
  • the effective surface area of the single flow channel can be the cross-sectional area of the flow channel (the cross-sectional area of the flow channel refers to the cross-sectional area of the flow channel taken perpendicular to the depth direction), and the flow path
  • the manufacturing density of the runners can increase the application flux (ie, the number of runners per unit area), as well as reduce manufacturing and application costs.
  • the above-described flow path structure device can realize a flow structure of a high aspect ratio.
  • the material layer is made of a conductive material such as a metal material or a semiconductor material (for example, a doped semiconductor material)
  • a conductive material such as a metal material or a semiconductor material (for example, a doped semiconductor material)
  • the electrode in the flow channel, that is, a portion of the material layer in the first trench can be used as The electrode, and a portion of the material layer between the first substrate and the second substrate can serve as a lead of the electrode, and since the lead and the electrode are formed together by, for example, a deposition process, the contact resistance can be lowered.
  • Figure 11 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • the selective etching process in the step of removing the first portion by the selective etching process (ie, step S107), the selective etching process further removes the second portion 452 of the sacrificial layer 45. Corresponding At the portion of the flow passage 50, the second portion 452 is broken.
  • the material layer is made of a metal or a semiconductor material as an electrode
  • the material of the sacrificial layer is also made of a conductive material such as a metal or a semiconductor
  • a portion of the second portion of the sacrificial layer corresponding to the flow channel is also removed to break the second portion of the sacrificial layer.
  • a flow path structure device as shown in Fig. 11 is also formed.
  • the flow path structure device shown in FIG. 11 has the same or similar structure as the flow path structure device shown in FIG. 10 (not described herein again), and FIG. 10
  • the difference in the illustrated flow path structure device is that the sacrificial layer 45 of the flow path structure device of Fig. 11 is broken at a position corresponding to the flow path 50.
  • Figure 12 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • the manufacturing method may further include: as shown in FIG. 12, for example, after the thinning process by a deposition process A capping layer 60 is formed on the back side of the first substrate 21, wherein the capping layer 60 covers the first portion 451 of the sacrificial layer 45. Furthermore, the cap layer 60 can also cover the material layer 43. After the subsequent formation of the flow channel, in the subsequent step of forming the flow channel, the cap layer may be closed above the flow channel to achieve a closed flow path, and the surface of the first substrate may be prevented from coming into contact with the fluid. Parasitic reactions.
  • the cap layer overlies the flow path such that for applications requiring fluid (e.g., liquid) to flow in the flow channel, the flow path of the embodiment covered with the cap layer is more susceptible to controlling the flow of these fluids.
  • the cap layer can also function to passivate the back surface of the first substrate and the surface of the material layer.
  • the material of the capping layer 60 may include: an insulating dielectric material (eg, silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide or tantalum oxide, etc.) or a semiconductor material. (for example, polysilicon or amorphous silicon, etc.).
  • the capping layer 60 may have a thickness ranging from 1 nanometer to 10 micrometers.
  • the capping layer 60 may have a thickness of 10 nanometers, 100 nanometers, 500 nanometers, 1 micrometer, or 5 micrometers, and the like.
  • Figure 13 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • a selective etching liquid may be injected from the edge side of the second trench 32 to remove the sacrificial layer 45.
  • the first portion 451 forms a flow channel 50.
  • the plane-extending material layer is bordered, so At the boundary of the material layer, that is, at the edge side (not shown) of the second trench, there will be an opening, so that a selective etching solution can be injected from the edge side of the second trench to remove the sacrificial layer. first part.
  • a flow path structure device as shown in Fig. 13 is also formed.
  • the flow path structure device shown in FIG. 13 has the same or similar structure as that of the flow path structure device shown in FIG. 10 (not described herein again), and FIG. 10
  • the difference in the illustrated flow path structure device is that the flow path structure device shown in FIG. 13 may further include: a cap layer 60 on the first substrate 21, wherein the cap layer 60 covers the flow path 50.
  • the cap layer can also cover the material layer 43.
  • the material of the capping layer 60 may include: an insulating dielectric material or a semiconductor material.
  • the capping layer 60 can have a thickness ranging from 1 nanometer to 10 micrometers.
  • the cap layer can be closed above the flow channel to achieve a closed flow path, and can also avoid parasitic reactions that may be caused by the surface of the first substrate contacting the fluid. Moreover, for applications requiring fluid (e.g., liquid) to flow in the flow channel, the flow path of the embodiment covered with a cap layer is more susceptible to controlling the flow of these fluids. In addition, the cap layer can also function to passivate the back surface of the first substrate and the surface of the material layer.
  • the process steps previously described may also be utilized such that the sacrificial layer 45 of the runner structure device, such as the one shown in FIG. 13, is broken at a position corresponding to the flow channel 50 (not shown in FIG. 13).
  • Fig. 14 is a plan view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • the manufacturing method may further include etching the capping layer 60 to form a capping layer 60 as shown in FIG. And the through hole 61 of the first portion 451 (of the sacrificial layer 45) is exposed.
  • a selective etching liquid is injected from the through hole 61 to remove the first portion 451.
  • the selective etching liquid is facilitated to be injected into the second trench, thereby more conveniently removing the first portion of the sacrificial layer to form Flow path.
  • a flow path structure device according to an embodiment of the present invention is also formed.
  • the flow path structure device is different from the flow path structure device shown in FIG. 13 except that it has the same or similar structure as the flow path structure device shown in FIG. 13 (the details are not described herein again): the flow of this embodiment
  • the track structure device may further include a through hole 61 penetrating the cap layer 60 and communicating to the flow path 50 (not shown in FIG. 14).
  • 15 to 18 are diagrams schematically showing the manufacture of a flow path structure device according to another embodiment of the present invention. A cross-sectional view of the structure of several stages in the process.
  • the manufacturing method may further include: removing the sacrifice as shown in FIG.
  • the second portion 452 of layer 45 exposes portions of material layer 43 that are outside of first trench 31.
  • dry etching, chemical mechanical polishing, or the like can be used to remove the second portion of the sacrificial layer.
  • the back surface of the first substrate 21 is subjected to a thinning treatment, for example, by a CMP process to expose the first portion 451 of the sacrificial layer 45.
  • a thinning treatment for example, by a CMP process to expose the first portion 451 of the sacrificial layer 45.
  • the first portion 451 of the sacrificial layer 45 is removed by a selective etching process, thereby forming the flow channel 50.
  • the second portion of the sacrificial layer (ie, the portion in the non-flow path region) is removed before bonding the first substrate to the second substrate, which can reduce the second portion due to the sacrificial layer Partial corrosion is not complete and may pose a short circuit risk.
  • the etching process since the etching process may be isotropic, that is, in the case of downward etching, lateral etching is also performed to both sides, which may cause the sacrificial layer to be in the opposite region of the non-electrode ( For example, between the first substrate and the second substrate, a parasitic flow path is generated, which brings additional errors in practical applications. Therefore, the sacrificial layer is used before the first substrate is bonded to the second substrate. The second part is removed and the possibility of parasitic flow path generation can also be reduced.
  • a flow path structure device as shown in Fig. 18 is also formed.
  • the flow path structure device may include a first substrate 21 formed with a groove 31 penetrating the first substrate.
  • the flow path structure device may further include a second substrate 47 bonded to the first substrate 21.
  • the flow channel structure device may further include: a material layer 43 in which a portion of the material layer 43 is located on the sidewall of the trench 31 and forms a flow channel 50, and another portion of the material layer 43 is located on the first substrate 21 and the second Between the substrates 47.
  • the first substrate 21 is bonded to the second substrate 47 through the material layer 43.
  • the flow path structure device shown in Fig. 18 is different from the flow path structure device shown in Fig. 10 in that the flow path structure device shown in Fig. 18 does not include a sacrificial layer.
  • 19 is a cross-sectional view schematically showing the structure of one stage in the manufacturing process of the flow path structure device according to another embodiment of the present invention.
  • the manufacturing method may include: after removing the second portion 452 of the sacrificial layer 45, the portion of the material layer 43 outside the first trench 31 and the second substrate 47 are bonded.
  • the back surface of the first substrate 21 is thinned by, for example, a CMP process to expose the first portion of the sacrificial layer 45.
  • a capping layer 60 is formed on the back surface of the first substrate 21 after the thinning treatment, wherein the capping layer covers the flow channel 50; and then the sacrificial layer 45 is removed by a selective etching process.
  • a portion 451 forms a flow channel 50 as shown in FIG.
  • a flow path structure device as shown in Fig. 19 is also formed.
  • the flow path structure device shown in FIG. 19 has the same or similar structure as that of the flow path structure device shown in FIG. 18 (not described herein again), and FIG.
  • the flow path structure device is different from the flow path structure device shown in FIG. 18 in that the flow path structure device shown in FIG. 19 may further include: a cap layer 60 on the first substrate 21, wherein the cap layer 60 covers the flow path 50. Furthermore, the cap layer can also cover the material layer 43.
  • the flow path of the embodiment of the present invention may be a nano flow channel.
  • the invention has the following advantages: (1) a nano-channel structure with high aspect ratio can be realized, and the size controllability is good; (2) an all-metal conductive electrode mosaic structure can be realized; (3) the nano-channel structure can be effectively improved; Manufacturability, reducing the manufacturing cost of the nanochannel structure; (4) has a low thermal budget and is compatible with integrated circuit processes.
  • the flow channel structure device described above may have a damascene electrode structure and may have different biochemical analysis and fluid processing functions. For example, by applying electrical excitation through an electrode, an electrical or electrochemical reaction can occur in the flow channel, an electrical signal or an optical signal can be generated, and a specific molecular species can be identified by the acquired electrical signal or optical signal; further, by identifying multiple Different molecular species can perform functions such as gene sequencing.
  • a flow channel sensor is also provided.
  • the flow path sensor may include: a flow path structure device as described above (for example, a flow path structure device as shown in FIG. 10, FIG. 11, FIG. 13, FIG. 18, or FIG. 19).
  • a biochemical analysis device may include: a flow path structure device as described above (for example, a flow path structure device as shown in FIG. 10, FIG. 11, FIG. 13, FIG. 18, or FIG. 19).
  • the chip 200 may include a flow path structure device 2001, a signal collection unit 2002, and a signal processing unit 2003.
  • the flow path structure device 2001 includes an electrode.
  • the flow path structure device may be a flow path structure device as shown in FIG. 10, FIG. 11, FIG. 13, FIG. 18 or FIG. Wherein the sample to be detected is added to the flow channel of the flow channel structure device, and the electrode to be detected is applied when the electrode of the flow channel structure device is electrically excited.
  • the target molecule in the sample generates an electrical or optical signal under electrical excitation.
  • the signal collection unit 2002 can be used to collect the electrical signal or the optical signal and transmit the electrical signal or the optical signal to the signal processing unit 2003.
  • the signal processing unit 2003 can be configured to perform signal processing on the electrical signal or the optical signal to identify information of the target molecule.
  • a molecular detection method is also provided.
  • the method can include performing molecular detection using a chip as described above (eg, a chip as shown in FIG. 20).
  • 21 is a flow chart showing a molecular detection method according to an embodiment of the present invention. The step of performing molecular detection using a chip will be described below with reference to FIG.
  • step S2101 the sample to be tested is processed.
  • the test sample can be subjected to chemical treatment or other treatment.
  • step S2102 the sample to be detected is added to the chip.
  • a sample to be tested is added to the flow path of the flow channel structure device of the chip.
  • step S2103 electrical excitation is applied to the electrodes in the flow channel structure device in the chip such that the target molecules in the sample to be detected generate an electrical or optical signal under electrical excitation.
  • step S2104 the signal processing unit of the chip obtains an electrical signal or an optical signal through the signal collecting unit, and performs signal processing on the electrical signal or the optical signal to identify the information of the target molecule.
  • the application of molecular detection is realized by using a chip including the flow path structure device of the embodiment of the present invention.

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Abstract

一种流道结构器件及其制造方法，涉及半导体技术领域。该方法包括：提供第一基片（21）；在该第一基片（21）中形成第一沟槽（31）；在该第一基片（21）上形成材料层（43），其中该材料层（43）的一部分形成在该第一沟槽（31）中以形成第二沟槽（32）；在该材料层（43）上形成牺牲层（45），该牺牲层（45）包括填充在该第二沟槽（32）中的第一部分（451）；将形成该牺牲层（45）后的第一基片（21）与第二基片（47）键合，使得该材料层（43）位于该第一基片（21）与该第二基片（47）之间；对该第一基片（21）的背面进行减薄处理，以露出该牺牲层（45）的第一部分（451）；以及利用选择性刻蚀工艺去除该第一部分（451），从而形成流道（50）。该方法可以实现具有垂直流道的流道结构器件。

Description

流道结构器件及其制造方法 技术领域
本发明涉及半导体技术领域，特别涉及一种流道结构器件及其制造方法。
背景技术
基于微纳流道的微纳流控分析技术，在生化分析、基因测序等领域，正受到越来越多的研究和应用。微纳流道器件与集成电路(Integrated Circuit，简称为IC)的结合，也将有助于提升微分析系统的自动化和小型化，更好地拓展其应用空间。在某些应用中，需要在微纳流道中嵌入电极材料，在某些设计中，需要具有高深宽比的纳米流道。
传统方法中，可以采用电子束光刻或者激光光刻，并结合各向异性刻蚀工艺实现纳米流道。但是直接电子束或激光光刻方法的效率低、尺寸可调性差，且在金属材料上很难实现高深宽比，通常只有1左右。
现有技术中也可以采用侧墙法实现上述微纳流道结构。但是侧墙法必须依赖半导体材料侧墙支撑结构实现结构互联与信号引出，这会带来更多寄生效应，并最终会影响检测信号的质量，且工艺热预算高，不利于与CMOS芯片的集成。例如，现有技术中大部分电极引出需要依赖拼接的金属互联线(例如典型材料是铝和铜)或半导体互连线(例如典型材料是多晶硅)与电极材料形成合金结构引出。但是合金结构存在以下缺点：(1)合金过程需要额外热处理工艺，将增加工艺热预算，不利于在IC芯片上实施工艺集成，以典型的多晶硅互联工艺为例，需要多晶硅沉积工艺(温度通常高于600℃)、离子注入与激活(通常需要550℃以上)以及金属半导体合金(通常需要400℃以上)等热预算比较高的工艺技术；(2)合金体将会引入额外的接触电阻，这将会降低器件性能。此外，现有技术中还存在金属引线的横向流道结构，但是这样的横向流道结构中，金属电极分别在流道的上下两侧相对分布，会影响其应用范围，比如，其无法用于包含发光的应用，因为光信号将被上下电极挡住。而且，这样的横向流道结构还限制了在芯片上的制造密度。
现有技术中还可以通过调节金属溅射角度实现纳米间隙结构。在该溅射工艺中，粒子溅射方向与衬底基片表面存在一定角度，通过调整角度，可以在预先制备的沟槽 底部产生溅射的死角，从而获得纳米间隙流道结构，但工艺可控性和尺寸可调性差。
发明内容
本发明的发明人发现上述现有技术中存在问题，并因此针对所述问题中的至少一个问题提出了一种新的技术方案。
根据本发明的第一方面，提供了一种流道结构器件的制造方法，包括：提供第一基片；在所述第一基片中形成第一沟槽；在所述第一基片上形成材料层，其中所述材料层的一部分形成在所述第一沟槽中以形成第二沟槽；在所述材料层上形成牺牲层，所述牺牲层包括填充在所述第二沟槽中的第一部分；将形成所述牺牲层后的第一基片与第二基片键合，使得所述材料层位于所述第一基片与所述第二基片之间；对所述第一基片的背面进行减薄处理，以露出所述牺牲层的第一部分；以及利用选择性刻蚀工艺去除所述第一部分，从而形成流道。
在一个实施例中，在对所述第一基片的背面进行减薄处理的步骤中，还露出所述材料层；在利用选择性刻蚀工艺去除所述第一部分之前，所述方法还包括：在减薄处理后的所述第一基片的背面上形成盖帽层，其中，所述盖帽层覆盖所述牺牲层的第一部分。
在一个实施例中，所述盖帽层的材料包括：绝缘介质材料或半导体材料；所述盖帽层的厚度范围为1纳米至10微米。
在一个实施例中，在利用选择性刻蚀工艺去除所述第一部分的步骤中，从所述第二沟槽的边缘侧面注入选择性刻蚀液以去除所述第一部分。
在一个实施例中，在利用选择性刻蚀工艺去除所述第一部分之前，所述方法还包括：对所述盖帽层进行刻蚀以形成贯穿所述盖帽层且露出所述第一部分的通孔；其中，在利用选择性刻蚀工艺去除所述第一部分的步骤中，从所述通孔注入选择性刻蚀液以去除所述第一部分。
在一个实施例中，在所述材料层上形成牺牲层的步骤中，所述牺牲层还包括：形成在所述第二沟槽之外的第二部分。
在一个实施例中，在将形成所述牺牲层后的第一基片与第二基片键合的步骤中，将所述牺牲层的所述第二部分与所述第二基片键合。
在一个实施例中，在所述第一基片上形成材料层的步骤中，所述材料层的另一部 分形成在所述第一沟槽之外；在将形成所述牺牲层后的第一基片与第二基片键合之前，所述方法还包括：去除所述牺牲层的所述第二部分，以露出所述材料层的在所述第一沟槽之外的部分；其中，在将形成所述牺牲层后的第一基片与第二基片键合的步骤中，将所述材料层的在所述第一沟槽之外的部分与所述第二基片键合。
在一个实施例中，在利用选择性刻蚀工艺去除所述第一部分的步骤中，所述选择性刻蚀工艺还去除所述第二部分的对应于所述流道的部分，从而使得所述第二部分断开。
在一个实施例中，在所述第一基片中形成第一沟槽的步骤包括：在所述第一基片上形成图案化的掩模层；以所述掩模层作为掩模，刻蚀所述第一基片以形成第一沟槽；以及去除所述掩模层。
在一个实施例中，所述材料层的材料包括：金属材料或半导体材料；其中，所述材料层的在所述第一沟槽中的部分作为所述流道结构器件的电极；所述材料层的在所述第一基片与所述第二基片之间的部分作为所述电极的引线。
在一个实施例中，所述材料层的材料包括：绝缘介质材料。
在一个实施例中，所述第一沟槽的宽度范围为10纳米至100微米，所述第一沟槽的深度范围为10纳米至1毫米；所述材料层的厚度范围为1纳米至50微米；所述流道的宽度范围为0.1纳米至1微米；所述牺牲层的厚度大于所述流道宽度的二分之一。
在本发明的上述制造方法中，在第一基片中形成第一沟槽，然后在第一基片上形成填充第一沟槽的材料层，从而形成第二沟槽；然后在材料层上形成牺牲层，从而填充第二沟槽；然后将第一基片与第二基片键合；对第一基片的背面进行减薄处理，以露出牺牲层的第一部分；以及利用选择性刻蚀工艺去除该第一部分，从而形成流道。本发明的上述制造方法可以形成具有垂直流道的流道结构器件，而且上述制造方法能够降低工艺热预算，便于流道结构器件与CMOS芯片的集成。
进一步地，上述制造方法可以实现高深宽比的流道结构。
进一步地，在上述制造方法中，由于材料层的材料可以为金属材料或半导体材料，因此可以将该材料层的在第一沟槽中的部分作为嵌入在流道中的电极。
进一步地，在上述制造方法中，材料层在第一沟槽中的部分和在第一沟槽之外的部分是一起形成的。在该材料层的在第一沟槽中的部分作为电极的情况下，该材料层在第一沟槽之外的部分(即位于第一基片与第二基片之间的部分)可以作为电极的引 线，这可以降低接触电阻。
根据本发明的第二方面，提供了一种流道结构器件，包括：第一基片，其形成有贯穿所述第一基片的沟槽；第二基片，与所述第一基片键合；以及材料层，其中所述材料层的一部分位于所述沟槽的侧壁上并形成流道，所述材料层的另一部分位于所述第一基片与所述第二基片之间。
在一个实施例中，所述流道结构器件还包括：在所述第一基片上的盖帽层，其中，所述盖帽层覆盖在所述流道之上。
在一个实施例中，所述盖帽层的材料包括：绝缘介质材料或半导体材料；所述盖帽层的厚度范围为1纳米至10微米。
在一个实施例中，所述流道结构器件还包括：贯穿所述盖帽层且连通到所述流道的通孔。
在一个实施例中，所述流道结构器件还包括：在所述材料层与所述第二基片之间的牺牲层。
在一个实施例中，所述牺牲层在对应于所述流道的位置断开。
在一个实施例中，所述材料层的材料包括：金属材料或半导体材料；其中，所述材料层的在所述沟槽的侧壁上的部分作为所述流道结构器件的电极；所述材料层的在所述第一基片与所述第二基片之间的部分作为所述电极的引线。
在一个实施例中，所述材料层的材料包括：绝缘介质材料。
在一个实施例中，所述沟槽的宽度范围为10纳米至100微米，所述沟槽的深度范围为10纳米至1毫米；所述材料层的厚度范围为1纳米至50微米；所述流道的宽度范围为0.1纳米至1微米；所述牺牲层的厚度大于所述流道宽度的二分之一。
本发明上述实施例的流道结构器件具有垂直流道，这可以提高在芯片上的流道的制造密度，可以提高应用通量，降低制造和应用成本等。
进一步地，上述流道结构器件可以实现高深宽比的流道结构。
进一步地，在材料层采用金属材料或半导体材料的情况下，可以实现在流道中嵌入电极，即该材料层的第一沟槽中的部分可以作为电极，而该材料层的在第一基片与第二基片之间的部分可以作为电极的引线，这可以降低接触电阻。
根据本发明的第三方面，提供了一种流道传感器，包括：如前所述的流道结构器件。
根据本发明的第四方面，提供了一种生物化学分析设备，包括：如前所述的流道结构器件。
根据本发明的第五方面，提供了一种用于分子检测的芯片，包括：如前所述流道结构器件、信号收集单元和信号处理单元；其中，待检测样品被加入到所述流道结构器件的流道中，在所述流道结构器件的电极被施加电激励情况下，所述待检测样品中的目标分子在电激励作用下产生电信号或光信号；所述信号收集单元用于收集所述电信号或所述光信号，并将所述电信号或所述光信号传输到所述信号处理单元；所述信号处理单元用于对所述电信号或所述光信号进行信号处理，识别出所述目标分子的信息。
根据本发明的第六方面，提供了一种分子检测方法，包括：使用如前所述的芯片进行分子检测。
在一个实施例中，使用所述芯片进行分子检测的步骤包括：对待检测样品进行处理；将所述待检测样品加入到所述芯片中；对所述芯片中的流道结构器件中的电极施加电激励，使得所述待检测样品中的目标分子在电激励作用下产生电信号或光信号；以及所述芯片的所述信号处理单元通过所述信号收集单元获得所述电信号或所述光信号，并对所述电信号或所述光信号进行信号处理，识别出所述目标分子的信息。
在上述实施例中，通过使用包含本发明实施例的流道结构器件的芯片实现了分子检测的应用。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例，并且连同说明书一起用于解释本发明的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本发明，其中：
图1是示出根据本发明一个实施例的流道结构器件的制造方法的流程图。
图2是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图3是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中一个 阶段的结构的横截面图。
图4是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图5是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图6是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图7是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图8是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图9是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图10是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图11是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图12是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图13是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图14是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的俯视图。
图15是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图16是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图17是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图18是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图19是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
图20是示意性地示出根据本发明一个实施例的用于分子检测的芯片的结构图。
图21是示出根据本发明一个实施例的分子检测方法的流程图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
图1是示出根据本发明一个实施例的流道结构器件的制造方法的流程图。图2至图10是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中若干阶段的结构的横截面图。下面结合图1以及图2至图10详细描述根据本发明一个实施例的流道结构器件的制造过程。
如图1所示，在步骤S101，提供第一基片。
图2是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S101的结构的横截面图。如图2所示，提供第一基片21。例如，该第一基片21可以包括：半导体衬底(例如硅、锗等)、绝缘衬底(例如石英、氮化硅等)、已集 成了IC电路的晶圆或者这些衬底的任意组合。
回到图1，在步骤S102，在第一基片中形成第一沟槽。下面结合图3至图5详细描述根据本发明一个实施例的实现该步骤S102的过程。
在一个实施例中，该步骤S102可以包括：如图3所示，在第一基片21上形成图案化的掩模层22。例如，可以在第一基片21上利用光刻工艺获得图案化的掩模层22。该掩模层的材料可以包括光刻胶等。该光刻工艺可以包括：光学光刻、电子束光刻、纳米压印光刻或者聚焦离子束光刻等。
接下来，该步骤S102还可以包括：如图4所示，以掩模层22作为掩模，刻蚀第一基片21以形成第一沟槽31。例如，可以采用各向异性刻蚀工艺来刻蚀第一基片以形成该第一沟槽。该各向异性刻蚀工艺可以包括：干法刻蚀工艺或湿法腐蚀工艺等。在一个实施例中，该第一沟槽31的宽度范围可以为10纳米至100微米。例如，该第一沟槽31的宽度可以为100纳米、500纳米、1微米、10微米或50微米等。在一个实施例中，该第一沟槽31的深度范围可以为10纳米至1毫米。例如，该第一沟槽31的深度可以为100纳米、500纳米、1微米、10微米、100微米或500微米等。
接下来，该步骤S102还可以包括：如图5所示，去除掩模层22。至此，在第一基片21中形成第一沟槽31。
回到图1，在步骤S103，在第一基片上形成材料层，其中该材料层的一部分形成在第一沟槽中以形成第二沟槽。
图6是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S103的结构的横截面图。如图6所示，例如可以通过淀积工艺在第一基片21上形成材料层43。该材料层43的一部分形成在第一沟槽31中，将该第一沟槽31的宽度缩小，从而形成第二沟槽32。在该步骤S103中，如图6所示，该材料层43的另一部分形成在第一沟槽31之外，即该另一部分形成在第一基片21的上表面上。
在一个实施例中，该材料层43的材料可以包括：金属材料(例如，金、铂、银、钛、氮化钛等或者多种金属的组合)或半导体材料(例如，多晶硅、非晶硅、氧化铟锡等或者多种半导体材料的组合)。在后续形成流道结构器件之后，在材料层43采用金属材料或半导体材料等导电材料的情况下，该材料层43的在第一沟槽31中的部分可以作为流道结构器件的电极；该材料层43的在第一沟槽之外的部分(即在第一基片与第二基片(后面将描述)之间的部分)作为电极的引线。在另一个实施例中，该材 料层43的材料可以包括：绝缘介质材料(例如氧化硅、氮化硅、氮氧化硅等或者多种绝缘介质材料的组合)。这样可以在后续步骤形成绝缘介质包围的流道结构器件。
在一个实施例中，该材料层43的厚度范围可以为1纳米至50微米。例如，该材料层43的厚度可以为10纳米、100纳米、500纳米、1微米或10微米等。在一个实施例中，该第二沟槽32的宽度范围可以为0.1纳米至1微米。例如，该第二沟槽32的宽度可以为1纳米、10纳米、100纳米或500纳米等。在后面的步骤中，该第二沟槽用于形成流道，该第二沟槽的宽度即为流道的宽度。
回到图1，在步骤S104，在材料层上形成牺牲层，该牺牲层包括填充在第二沟槽中的第一部分。
图7是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S104的结构的横截面图。如图7所示，在材料层43上形成牺牲层45以填充第二沟槽32。该牺牲层45可以包括填充在第二沟槽32中的第一部分451。该牺牲层45还可以包括：形成在第二沟槽32之外的第二部分452。如图7所示，该第二部分452形成在第一基片21的上表面之上的材料层43上。
在一个实施例中，该牺牲层45的材料可以包括：金属材料(例如，铬、铝、钛等或多种金属材料的组合)、半导体材料(例如，多晶硅、非晶硅、氧化铟锡等或多种半导体材料的组合)或绝缘介质材料(例如二氧化硅或氮化硅等或多种绝缘介质材料的组合)等。该牺牲层45的材料不限于金属或非金属，其选取的主要依据和标准是牺牲层45的材料与作为镶嵌电极的材料层43的材料之间的腐蚀选择性，一般腐蚀选择比越大越好。例如，当采用一些金属材料作为电极时，相应的牺牲层材料可以选择其它具有高腐蚀选择比的材料来与之匹配。
在一个实施例中，该牺牲层45的厚度可以根据第二沟槽的宽度(即后续步骤中所形成的流道的宽度)来确定，以确保将第二沟槽32填充满。该第二沟槽32的宽度和厚度由设计需求而定，并通过材料层43填充第一沟槽而获得，即该第二沟槽对应于第一沟槽中填充的两侧材料层43之间所夹的缝隙。而牺牲层45的厚度大于该缝隙宽度的1/2(二分之一)，以保证牺牲层45能够完全填充该缝隙。即该牺牲层45的厚度大于流道(在后续步骤中将形成)宽度的二分之一。
在本发明的实施例中，可以采用物理沉积(例如溅射)、化学沉积(例如CVD(Chemical Vapor Deposition，化学气相沉积))或者电镀等工艺形成该牺牲层45。
回到图1，在步骤S105，将形成牺牲层后的第一基片与第二基片键合，使得该材料层位于第一基片与第二基片之间。
图8是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S105的结构的横截面图。如图8所示，将形成牺牲层后的第一基片21与第二基片47键合，使得该材料层43位于第一基片21与第二基片47之间，例如使得该材料层43的在第一沟槽31之外的部分位于该第一基片21与第二基片47之间。在一个实施例中，在该步骤S105中，如图8所示，将该牺牲层45的第二部分452与第二基片47键合。在一个实施例中，该第二基片47可以包括：半导体衬底(例如硅、锗等)、绝缘衬底(例如石英、氮化硅等)、已集成了IC电路的晶圆或者这些衬底的任意组合。
回到图1，在步骤S106，对第一基片的背面进行减薄处理，以露出牺牲层的第一部分。
图9是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S106的结构的横截面图。如图9所示，在将第一基片21与第二基片47键合之后，例如通过化学机械抛光(Chemical Mechanical Polishing，简称为CMP)工艺对第一基片21的背面进行减薄处理，以露出牺牲层45的第一部分451。在该减薄处理的步骤中，如图9所示，还露出材料层43，即露出材料层43在第一沟槽31中的部分。
回到图1，在步骤S107，利用选择性刻蚀工艺去除第一部分，从而形成流道。
图10是示意性地示出根据本发明一个实施例的流道结构器件的制造过程中在步骤S107的结构的横截面图。如图10所示，利用选择性刻蚀工艺去除牺牲层45的第一部分451，从而形成流道50。在一个实施例中，该流道50的宽度范围可以为0.1纳米至1微米。例如，该流道50的宽度可以为1纳米、10纳米、100纳米或500纳米等。在一个实施例中，牺牲层45的厚度大于该流道宽度的二分之一。
至此，提供了根据本发明一个实施例的流道结构器件的制造方法。在该方法中，在第一基片中形成第一沟槽，然后在第一基片上形成填充第一沟槽的材料层，从而形成第二沟槽；然后在材料层上形成牺牲层，从而填充第二沟槽；然后将第一基片与第二基片键合；对第一基片的背面进行减薄处理，以露出牺牲层的第一部分；以及利用选择性刻蚀工艺去除该第一部分，从而形成流道。本发明的制造方法可以形成具有垂直流道(即该流道垂直于第二基片的上表面或下表面)的流道结构器件。例如，该流道在垂直于基片的方向上可以为开放空间或可以设置透明材料，这样不会影响光信号 的传输。此外，采用垂直流道，可以使得单个流道的有效表面积是流道的截面积，可以大大提高在芯片上的流道的制造密度，降低制造和应用成本等。
本发明实施例的上述制造方法能够降低工艺热预算。例如，本发明的方法所涉及的工艺温度比较低(温度范围在室温至350℃之间)，而且热处理过程时间短，因此降低了工艺热预算，以便于流道结构器件与CMOS芯片的集成。
进一步地，上述制造方法可以实现高深宽比的流道结构。例如可以实现宽度为10nm、深宽比为100:1的流道结构。本发明实施例的方法所实现的流道结构的深宽比的范围可以为1:1至100000:1。
进一步地，由于材料层的材料可以为金属材料或半导体材料(例如掺杂的半导体材料)等导电材料，因此上述制造方法可以实现在流道中形成1个电极、1对电极或更多对电极。如图6所示，最初形成的是一层电极(即采用金属或半导体材料的材料层)，如果不进行后续的工艺处理，可以认为是只有一个电极；而经过后续的工艺之后，可以形成分别在流道两侧的两个电极(例如可以将在流道左侧的材料层的部分称为第一电极，在流道右侧的材料层的部分称为第二电极)，这两个电极可以作为一对工作电极。此外，还可以在流道两侧形成更多对电极，例如可以在形成材料层的过程中，通过图案化工艺形成沿着第二沟槽分布的多个材料层部分，然后经过后续的上述工艺过程，每一个材料层部分形成一对分别在流道两侧的电极，从而多个材料层部分形成多对在流道两侧的电极。
进一步地，在上述制造方法中，例如通过淀积工艺，材料层在第一沟槽中的部分和在第一沟槽之外的部分是一起形成的。在材料层的第一沟槽中的部分作为电极的情况下，该材料层在第一沟槽之外(即位于第一基片与第二基片之间的部分)的部分可以实现电极的引线，尤其可以采用全金属连接结构，这可以降低接触电阻和引线电阻。
由本发明实施例的制造方法，还形成了根据本发明一个实施例的流道结构器件。例如，如图10所示，该流道结构器件可以包括：第一基片21，该第一基片21形成有贯穿该述第一基片的沟槽31。例如，该沟槽31的宽度范围可以为10纳米至100微米，该沟槽31的深度范围可以为10纳米至1毫米。如图10所示，该流道结构器件还可以包括：第二基片47，与该第一基片21键合。该流道结构器件还可以包括：材料层43，其中该材料层43的一部分位于沟槽31的侧壁上并形成流道50，该材料层43的另一部分位于第一基片21与第二基片47之间。
在一个实施例中，该材料层43的材料可以包括：金属材料或半导体材料。在这样的情况下，该材料层43的在沟槽31的侧壁上的部分作为流道结构器件的电极；该材料层43的在第一基片21与第二基片47之间的部分作为该电极的引线。
在另一个实施例中，该材料层43的材料可以包括：绝缘介质材料。利用绝缘介质材料作为材料层，可以将流道结构器件应用到某些不需要在流道中施加电极的情况，例如在一些情况下，需要用特定的绝缘介质材料作为材料层来修饰流道表面以获得某些特定效果，比如获得疏水表面或亲水表面等，此外，还可以应用于流体形成与控制等。
在一个实施例中，该材料层43的厚度范围可以为1纳米至50微米。在一个实施例中，该流道50的宽度范围可以为0.1纳米至1微米。
在一个实施例中，如图10所示，该流道结构器件还可以包括：在材料层43与第二基片47之间的牺牲层45。该第一基片21通过该牺牲层45来实现与第二基片47键合。例如，该牺牲层45的厚度大于流道50的宽度的二分之一。
本发明上述实施例的流道结构器件具有垂直流道，例如该流道在垂直于第二基片表面的方向上可以为开放空间或可以设置透明材料，因此这不会影响光信号的传输。此外，采用垂直流道，可以使得单个流道的有效表面积是流道的截面积(该流道的截面积是指流道在垂直于深度方向上截取的横截面积)，而且该流道的截面积远小于上面所述的电极的面积(该电极的面积是指电极在深度方向和长度方向上的延展面积，即电极的面积＝电极的深度×电极的长度)，可以大大提高在芯片上的流道的制造密度，可以提高应用通量(即单位面积的流道数量)，以及降低制造和应用成本等。
进一步地，上述流道结构器件可以实现高深宽比的流道结构。
进一步地，在材料层采用金属材料或半导体材料(例如掺杂的半导体材料)等导电材料的情况下，可以实现在流道中嵌入电极，即该材料层的在第一沟槽中的部分可以作为电极，而该材料层的在第一基片与第二基片之间的部分可以作为电极的引线，由于该引线与电极是通过例如淀积工艺而一起形成的，因此可以降低接触电阻。
图11是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
在本发明的一个实施例中，如图11所示，在利用选择性刻蚀工艺去除第一部分的步骤(即步骤S107)中，该选择性刻蚀工艺还去除牺牲层45的第二部分452的对应 于流道50的部分，从而使得第二部分452断开。在该实施例中，在材料层采用金属或半导体材料作为电极的情况下，当该牺牲层的材料也采用金属或半导体等导电材料时，为了防止牺牲层将流道两侧的电极短路，因此在进行该选择性刻蚀的过程中，还去除该牺牲层的第二部分的对应于流道的部分，从而将该牺牲层的第二部分断开。
由上述制造方法，还形成了如图11所示的流道结构器件。在本发明的一个实施例中，该图11所示的流道结构器件除了具有与图10所示的流道结构器件相同或相似的结构(这里不再赘述)之外，其与图10所示的流道结构器件的区别是：该图11的流道结构器件的牺牲层45在对应于流道50的位置断开。
图12是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
在本发明的一个实施例中，在利用选择性刻蚀工艺去除第一部分(即步骤S107)之前，所述制造方法还可以包括：如图12所示，例如通过淀积工艺在减薄处理后的第一基片21的背面上形成盖帽层60，其中，该盖帽层60覆盖牺牲层45的第一部分451。此外，该盖帽层60还可以覆盖材料层43。在后续形成流道后，在后续形成流道的步骤中，该盖帽层可以使得流道的上方被封闭，实现封闭性流道，还可以避免第一基片的表面与流体接触所可能带来的寄生反应。而且该盖帽层覆盖在流道之上，这样对于一些需要流体(例如液体)在流道中流动的应用，该实施例的覆盖有盖帽层的流道更容易控制这些流体的流动。此外，该盖帽层还可以起到对第一基片的背面和材料层的表面钝化的作用。
在一个实施例中，该盖帽层60的材料可以包括：绝缘介质材料(例如，氧化硅、氮化硅、氮氧化硅、硼磷硅玻璃、氧化铝、氧化钛或氧化钽等)或半导体材料(例如，多晶硅或非晶硅等)。在一个实施例中，该盖帽层60的厚度范围可以为1纳米至10微米。例如，该盖帽层60的厚度可以为10纳米、100纳米、500纳米、1微米或5微米等。
图13是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
在本发明的一个实施例中，在利用选择性刻蚀工艺去除第一部分的步骤中，如图13所示，可以从第二沟槽32的边缘侧面注入选择性刻蚀液以去除牺牲层45的第一部分451，从而形成流道50。在实际平面结构中，平面延伸的材料层是有边界的，因此 在材料层的边界处，即在第二沟槽的边缘侧面(图中未示出)处将会存在开口，因此可以从第二沟槽的边缘侧面注入选择性刻蚀液以去除牺牲层的第一部分。
由上述制造方法，还形成了如图13所示的流道结构器件。在本发明的一个实施例中，该图13所示的流道结构器件除了具有与图10所示的流道结构器件相同或相似的结构(这里不再赘述)之外，其与图10所示的流道结构器件的区别是：该图13所示的流道结构器件还可以包括：在第一基片21上的盖帽层60，其中，该盖帽层60覆盖在流道50之上。此外，该盖帽层还可以覆盖材料层43。例如，盖帽层60的材料可以包括：绝缘介质材料或半导体材料。例如，该盖帽层60的厚度范围可以为1纳米至10微米。该盖帽层可以使得流道的上方被封闭，实现封闭性流道，还可以避免第一基片的表面与流体接触所可能带来的寄生反应。而且对于一些需要流体(例如液体)在流道中流动的应用，该实施例的覆盖有盖帽层的流道更容易控制这些流体的流动。此外，该盖帽层还可以起到对第一基片的背面和材料层的表面钝化的作用。
在一个实施例中，还可以利用前面所述的工艺步骤使得例如如图13所示的流道结构器件的牺牲层45在对应于流道50的位置断开(图13未示出)。
图14是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的俯视图。
在本发明的另一个实施例中，在利用选择性刻蚀工艺去除第一部分之前，所述制造方法还可以包括：如图14所示，对盖帽层60进行刻蚀以形成贯穿该盖帽层60且露出(牺牲层45的)第一部分451的通孔61。其中，在利用选择性刻蚀工艺去除该第一部分的步骤中，从该通孔61注入选择性刻蚀液以去除该第一部分451。本领域技术人员应该理解，该通孔的数量、形状或大小等均可以根据设计需要来确定，本发明的范围并不仅限于图14所示的通孔的数量、形状或大小等。在该实施例中通过在盖帽层60上形成通孔，从而在选择性刻蚀工艺中，有利于选择性刻蚀液向第二沟槽注入，从而更方便地去除牺牲层的第一部分以形成流道。
由上述制造方法，还形成了根据本发明一个实施例的流道结构器件。该流道结构器件除了具有与图13所示的流道结构器件相同或相似的结构(这里不再赘述)之外，其与图13所示的流道结构器件区别是：该实施例的流道结构器件还可以包括：贯穿盖帽层60且连通到流道50(图14中未示出)的通孔61。
图15至图18是示意性地示出根据本发明另一个实施例的流道结构器件的制造过 程中若干阶段的结构的横截面图。
在本发明的一个实施例中，在将形成牺牲层后的第一基片与第二基片键合(即步骤S105)之前，所述制造方法还可以包括：如图15所示，去除牺牲层45的第二部分452，以露出材料层43的在第一沟槽31之外的部分。例如可以采用干法刻蚀、化学机械抛光等工艺来去除牺牲层的该第二部分。接下来，在将形成牺牲层后的第一基片与第二基片键合的步骤中，如图16所示，将该材料层43的在第一沟槽31之外的部分与第二基片47键合。接下来，如图17所示，例如通过CMP工艺对第一基片21的背面进行减薄处理，以露出牺牲层45的第一部分451。接下来，如图18所示，利用选择性刻蚀工艺去除牺牲层45的第一部分451，从而形成流道50。
在上述实施例中，在将第一基片与第二基片键合之前，将牺牲层的第二部分(即在非流道区域的部分)去除，这能够减小由于牺牲层的第二部分腐蚀不完全而可能带来的短路风险。此外，在选择性刻蚀的过程中，由于腐蚀过程可能是各向同性的，即在向下腐蚀时，也会向两侧进行横向腐蚀，这样可能会使得牺牲层在非电极相对的区域(例如第一基片与第二基片之间)产生寄生的流道，在实际应用将带来额外的误差，因此，在将第一基片与第二基片键合之前，将牺牲层的第二部分去除，还可以减小寄生流道产生的可能性。
由上述制造方法，还形成了如图18所示的流道结构器件。如图18所示，该流道结构器件可以包括：第一基片21，该第一基片21形成有贯穿该述第一基片的沟槽31。该流道结构器件还可以包括：第二基片47，与该第一基片21键合。该流道结构器件还可以包括：材料层43，其中该材料层43的一部分位于沟槽31的侧壁上并形成流道50，该材料层43的另一部分位于第一基片21与第二基片47之间。在该实施例中，如图18所示，该第一基片21通过该材料层43来实现与第二基片47键合。与图10所示的流道结构器件相比，图18所示的流道结构器件的区别之处在于：图18所示的流道结构器件不包括牺牲层。
图19是示意性地示出根据本发明另一个实施例的流道结构器件的制造过程中一个阶段的结构的横截面图。
在本发明的一个实施例中，所述制造方法可以包括：在去除牺牲层45的第二部分452之后，将材料层43的在第一沟槽31之外的部分与第二基片47键合；接下来，例如通过CMP工艺对第一基片21的背面进行减薄处理，以露出牺牲层45的第一部分 451；接下来，在减薄处理后的第一基片21的背面上形成盖帽层60，其中，该盖帽层覆盖在流道50之上；然后利用选择性刻蚀工艺去除牺牲层45的第一部分451，从而形成流道50，如图19所示。
由上述制造方法，还形成了如图19所示的流道结构器件。在本发明的一个实施例中，该图19所示的流道结构器件除了具有与图18所示的流道结构器件相同或相似的结构(这里不再赘述)之外，该图19所示的流道结构器件与图18所示的流道结构器件的区别是：该图19所示的流道结构器件还可以包括：在第一基片21上的盖帽层60，其中，该盖帽层60覆盖在流道50之上。此外，该盖帽层还可以覆盖材料层43。
至此，提供了根据本发明一些实施例的制造方法和由这些制造方法所形成的流道结构器件。本发明实施例的流道可以是纳米流道。本发明具有以下优点：(1)可以实现高深宽比的纳米流道结构，尺寸可控性好；(2)可以实现全金属导电电极镶嵌结构；(3)可以有效提升纳米流道结构的可制造性，降低纳米流道结构制造成本；(4)具有低热预算，可以与集成电路工艺兼容。
在本发明的一些实施例中，上述流道结构器件可以具有镶嵌电极结构，可以具有不同的生化分析与流体处理功能。比如，通过电极施加电激励，流道中可以发生电的或电化学的反应，可以产生电信号或光信号，可以通过获取的电信号或者光信号识别特定的分子种类；再进一步，通过识别多种不同分子种类，可以实现诸如基因测序等功能。
在本发明的实施例中，还提供了一种流道传感器。该流道传感器可以包括：如前所述的流道结构器件(例如，如图10、图11、图13、图18或图19所示的流道结构器件)。
在本发明的实施例中，还提供了一种生物化学分析设备。该生物化学分析设备可以包括：如前所述的流道结构器件(例如，如图10、图11、图13、图18或图19所示的流道结构器件)。
图20是示意性地示出根据本发明一个实施例的用于分子检测的芯片的结构图。如图20所示，该芯片200可以包括：流道结构器件2001、信号收集单元2002和信号处理单元2003。该流道结构器件2001包括电极。例如该流道结构器件可以为如图10、图11、图13、图18或图19所示的流道结构器件。其中，待检测样品被加入到该流道结构器件的流道中，在该流道结构器件的电极被施加电激励情况下，该待检测 样品中的目标分子在电激励作用下产生电信号或光信号。
该信号收集单元2002可以用于收集该电信号或该光信号，并将该电信号或该光信号传输到该信号处理单元2003。
该信号处理单元2003可以用于对该电信号或该光信号进行信号处理，识别出目标分子的信息。
在本发明的实施例中，还提供了一种分子检测方法。该方法可以包括：使用如前所述的芯片(例如如图20所示的芯片)进行分子检测。
图21是示出根据本发明一个实施例的分子检测方法的流程图。下面结合图21来描述使用芯片进行分子检测的步骤。
在步骤S2101，对待检测样品进行处理。例如可以对待检测样品进行化学处理或其他处理。
在步骤S2102，将待检测样品加入到芯片中。例如将待检测样品加入到该芯片的流道结构器件的流道中。
在步骤S2103，对芯片中的流道结构器件中的电极施加电激励，使得待检测样品中的目标分子在电激励作用下产生电信号或光信号。
在步骤S2104，芯片的信号处理单元通过信号收集单元获得电信号或光信号，并对该电信号或该光信号进行信号处理，识别出目标分子的信息。
在上述实施例中，通过使用包含本发明实施例的流道结构器件的芯片实现了分子检测的应用。
至此，已经详细描述了本发明。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (27)

  1. 一种流道结构器件的制造方法，其特征在于，包括：
    提供第一基片；
    在所述第一基片中形成第一沟槽；
    在所述第一基片上形成材料层，其中所述材料层的一部分形成在所述第一沟槽中以形成第二沟槽；
    在所述材料层上形成牺牲层，所述牺牲层包括填充在所述第二沟槽中的第一部分；
    将形成所述牺牲层后的第一基片与第二基片键合，使得所述材料层位于所述第一基片与所述第二基片之间；
    对所述第一基片的背面进行减薄处理，以露出所述牺牲层的第一部分；以及
    利用选择性刻蚀工艺去除所述第一部分，从而形成流道。
  2. 根据权利要求1所述的方法，其特征在于，
    在对所述第一基片的背面进行减薄处理的步骤中，还露出所述材料层；
    在利用选择性刻蚀工艺去除所述第一部分之前，所述方法还包括：在减薄处理后的所述第一基片的背面上形成盖帽层，其中，所述盖帽层覆盖所述牺牲层的第一部分。
  3. 根据权利要求2所述的方法，其特征在于，
    所述盖帽层的材料包括：绝缘介质材料或半导体材料；
    所述盖帽层的厚度范围为1纳米至10微米。
  4. 根据权利要求2所述的方法，其特征在于，
    在利用选择性刻蚀工艺去除所述第一部分的步骤中，从所述第二沟槽的边缘侧面注入选择性刻蚀液以去除所述第一部分。
  5. 根据权利要求2所述的方法，其特征在于，
    在利用选择性刻蚀工艺去除所述第一部分之前，所述方法还包括：对所述盖帽层进行刻蚀以形成贯穿所述盖帽层且露出所述第一部分的通孔；
    其中，在利用选择性刻蚀工艺去除所述第一部分的步骤中，从所述通孔注入选择性刻蚀液以去除所述第一部分。
  6. 根据权利要求1或2所述的方法，其特征在于，
    在所述材料层上形成牺牲层的步骤中，所述牺牲层还包括：形成在所述第二沟槽之外的第二部分。
  7. 根据权利要求6所述的方法，其特征在于，
    在将形成所述牺牲层后的第一基片与第二基片键合的步骤中，将所述牺牲层的所述第二部分与所述第二基片键合。
  8. 根据权利要求6所述的方法，其特征在于，
    在所述第一基片上形成材料层的步骤中，所述材料层的另一部分形成在所述第一沟槽之外；
    在将形成所述牺牲层后的第一基片与第二基片键合之前，所述方法还包括：去除所述牺牲层的所述第二部分，以露出所述材料层的在所述第一沟槽之外的部分；
    其中，在将形成所述牺牲层后的第一基片与第二基片键合的步骤中，将所述材料层的在所述第一沟槽之外的部分与所述第二基片键合。
  9. 根据权利要求6所述的方法，其特征在于，
    在利用选择性刻蚀工艺去除所述第一部分的步骤中，所述选择性刻蚀工艺还去除所述第二部分的对应于所述流道的部分，从而使得所述第二部分断开。
  10. 根据权利要求1所述的方法，其特征在于，在所述第一基片中形成第一沟槽的步骤包括：
    在所述第一基片上形成图案化的掩模层；
    以所述掩模层作为掩模，刻蚀所述第一基片以形成第一沟槽；以及
    去除所述掩模层。
  11. 根据权利要求1所述的方法，其特征在于，
    所述材料层的材料包括：金属材料或半导体材料；
    其中，所述材料层的在所述第一沟槽中的部分作为所述流道结构器件的电极；所述材料层的在所述第一基片与所述第二基片之间的部分作为所述电极的引线。
  12. 根据权利要求1所述的方法，其特征在于，
    所述材料层的材料包括：绝缘介质材料。
  13. 根据权利要求1所述的方法，其特征在于，
    所述第一沟槽的宽度范围为10纳米至100微米，所述第一沟槽的深度范围为10纳米至1毫米；
    所述材料层的厚度范围为1纳米至50微米；
    所述流道的宽度范围为0.1纳米至1微米；
    所述牺牲层的厚度大于所述流道宽度的二分之一。
  14. 一种流道结构器件，其特征在于，包括：
    第一基片，其形成有贯穿所述第一基片的沟槽；
    第二基片，与所述第一基片键合；以及
    材料层，其中所述材料层的一部分位于所述沟槽的侧壁上并形成流道，所述材料层的另一部分位于所述第一基片与所述第二基片之间。
  15. 根据权利要求14所述的流道结构器件，其特征在于，还包括：
    在所述第一基片上的盖帽层，其中，所述盖帽层覆盖在所述流道之上。
  16. 根据权利要求15所述的流道结构器件，其特征在于，
    所述盖帽层的材料包括：绝缘介质材料或半导体材料；
    所述盖帽层的厚度范围为1纳米至10微米。
  17. 根据权利要求15所述的流道结构器件，其特征在于，还包括：
    贯穿所述盖帽层且连通到所述流道的通孔。
  18. 根据权利要求14所述的流道结构器件，其特征在于，还包括：
    在所述材料层与所述第二基片之间的牺牲层。
  19. 根据权利要求18所述的流道结构器件，其特征在于，
    所述牺牲层在对应于所述流道的位置断开。
  20. 根据权利要求14所述的流道结构器件，其特征在于，
    所述材料层的材料包括：金属材料或半导体材料；
    其中，所述材料层的在所述沟槽的侧壁上的部分作为所述流道结构器件的电极；所述材料层的在所述第一基片与所述第二基片之间的部分作为所述电极的引线。
  21. 根据权利要求14所述的流道结构器件，其特征在于，
    所述材料层的材料包括：绝缘介质材料。
  22. 根据权利要求18所述的流道结构器件，其特征在于，
    所述沟槽的宽度范围为10纳米至100微米，所述沟槽的深度范围为10纳米至1毫米；
    所述材料层的厚度范围为1纳米至50微米；
    所述流道的宽度范围为0.1纳米至1微米；
    所述牺牲层的厚度大于所述流道宽度的二分之一。
  23. 一种流道传感器，其特征在于，包括：如权利要求14至22任意一项所述的流道结构器件。
  24. 一种生物化学分析设备，其特征在于，包括：如权利要求14至22任意一项所述的流道结构器件。
  25. 一种用于分子检测的芯片，其特征在于，包括：如权利要求20所述流道结构器件、信号收集单元和信号处理单元；
    其中，待检测样品被加入到所述流道结构器件的流道中，在所述流道结构器件的电极被施加电激励情况下，所述待检测样品中的目标分子在电激励作用下产生电信号或光信号；
    所述信号收集单元用于收集所述电信号或所述光信号，并将所述电信号或所述光信号传输到所述信号处理单元；
    所述信号处理单元用于对所述电信号或所述光信号进行信号处理，识别出所述目标分子的信息。
  26. 一种分子检测方法，其特征在于，包括：使用如权利要求25所述的芯片进行分子检测。
  27. 根据权利要求26所述的分子检测方法，其特征在于，使用所述芯片进行分子检测的步骤包括：
    对待检测样品进行处理；
    将所述待检测样品加入到所述芯片中；
    对所述芯片中的流道结构器件中的电极施加电激励，使得所述待检测样品中的目标分子在电激励作用下产生电信号或光信号；以及
    所述芯片的所述信号处理单元通过所述信号收集单元获得所述电信号或所述光信号，并对所述电信号或所述光信号进行信号处理，识别出所述目标分子的信息。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110562911A (zh) * 2019-09-18 2019-12-13 北京理工大学 一种利用支撑层的微纳结构成形制造方法
CN113237932A (zh) * 2021-05-07 2021-08-10 中国工程物理研究院电子工程研究所 一种对电极型纳米电学传感器的制备方法
WO2023123314A1 (zh) * 2021-12-31 2023-07-06 京东方科技集团股份有限公司 微纳流控基板、芯片、制备方法及系统

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6167910B1 (en) * 1998-01-20 2001-01-02 Caliper Technologies Corp. Multi-layer microfluidic devices
CN101445218A (zh) * 2008-12-30 2009-06-03 北京大学 一种钛可动器件的制作方法
CN102303843A (zh) * 2011-08-15 2012-01-04 中国科学技术大学 纳米流体通道及其制作方法
CN104124201A (zh) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 导电结构的形成方法
CN104190484A (zh) * 2014-09-16 2014-12-10 山东华芯半导体有限公司 一种适于生物分子检测的芯片单元的制备方法
CN104237313A (zh) * 2013-06-18 2014-12-24 国际商业机器公司 用于生物检测的纳米通道方法和结构
CN105158310A (zh) * 2015-09-21 2015-12-16 东南大学 一种基于微孔电极的微流控检测芯片及其应用
US9295989B2 (en) * 2013-09-26 2016-03-29 Canon Kabushiki Kaisha Channel device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6167910B1 (en) * 1998-01-20 2001-01-02 Caliper Technologies Corp. Multi-layer microfluidic devices
CN101445218A (zh) * 2008-12-30 2009-06-03 北京大学 一种钛可动器件的制作方法
CN102303843A (zh) * 2011-08-15 2012-01-04 中国科学技术大学 纳米流体通道及其制作方法
CN104124201A (zh) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 导电结构的形成方法
CN104237313A (zh) * 2013-06-18 2014-12-24 国际商业机器公司 用于生物检测的纳米通道方法和结构
US9295989B2 (en) * 2013-09-26 2016-03-29 Canon Kabushiki Kaisha Channel device
CN104190484A (zh) * 2014-09-16 2014-12-10 山东华芯半导体有限公司 一种适于生物分子检测的芯片单元的制备方法
CN105158310A (zh) * 2015-09-21 2015-12-16 东南大学 一种基于微孔电极的微流控检测芯片及其应用

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110562911A (zh) * 2019-09-18 2019-12-13 北京理工大学 一种利用支撑层的微纳结构成形制造方法
CN113237932A (zh) * 2021-05-07 2021-08-10 中国工程物理研究院电子工程研究所 一种对电极型纳米电学传感器的制备方法
CN113237932B (zh) * 2021-05-07 2023-09-19 中国工程物理研究院电子工程研究所 一种对电极型纳米电学传感器的制备方法
WO2023123314A1 (zh) * 2021-12-31 2023-07-06 京东方科技集团股份有限公司 微纳流控基板、芯片、制备方法及系统

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