WO2019021873A1 - Semiconductor device and solid-state imaging device - Google Patents

Semiconductor device and solid-state imaging device Download PDF

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Publication number
WO2019021873A1
WO2019021873A1 PCT/JP2018/026596 JP2018026596W WO2019021873A1 WO 2019021873 A1 WO2019021873 A1 WO 2019021873A1 JP 2018026596 W JP2018026596 W JP 2018026596W WO 2019021873 A1 WO2019021873 A1 WO 2019021873A1
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semiconductor
semiconductor chip
chip
semiconductor substrates
substrates
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PCT/JP2018/026596
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French (fr)
Japanese (ja)
Inventor
庄子　礼二郎
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2019021873A1 publication Critical patent/WO2019021873A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures

Definitions

  • the present technology relates to a lamination technology in a semiconductor device.
  • the present invention relates to a semiconductor device in which a plurality of semiconductor substrates are stacked.
  • a wafer laminating technique in which a plurality of wafers are bonded by dielectric bonding or hybrid bonding (CuCu bonding) or the like (see, for example, Patent Document 1).
  • TSV Through Silicon Via
  • the conduction between the wafers is ensured by through holes (TSV: Through Silicon Via) formed after bonding in the case of insulating film bonding, and provided in the bonding interface in the case of hybrid bonding. Secured by copper pad.
  • TSV Through Silicon Via
  • a chip stacking technique in which another chip is connected to a stacked wafer or chip by using a connection terminal such as a solder bump or a copper pillar to secure conduction (see, for example, Patent Document 2). ).
  • the present technology is produced in view of such a situation, and it is an object of the present invention to efficiently conduct conduction between semiconductor substrates when laminating a plurality of semiconductor substrates.
  • the present technology has been made to solve the above-described problems, and the first side surface thereof includes a plurality of semiconductor substrates stacked vertically and joined to each other, and a junction surface of the plurality of semiconductor substrates.
  • a semiconductor device including a connection substrate provided on different side surfaces to electrically connect the wirings of the plurality of semiconductor substrates. This brings about the effect
  • each of the plurality of semiconductor substrates has a wiring layer, and an end of the wiring layer forms a connection terminal, and is connected to the connection substrate through the connection terminal.
  • connection substrate may include a connection terminal, and the connection substrate may be connected to the plurality of semiconductor substrates via the connection terminal. This brings about the effect
  • connection terminal of the connection substrate may be formed of a solder bump or a copper pillar.
  • a plurality of connection substrates may be provided on the same side surface of the plurality of semiconductor substrates, or may be provided on different side surfaces of the plurality of semiconductor substrates.
  • each of the plurality of semiconductor substrates may be a semiconductor chip or a semiconductor wafer.
  • a first semiconductor substrate including a photoelectric conversion unit that outputs a pixel signal, and a signal processing circuit that is stacked and joined to the first semiconductor substrate and processes the pixel signal. And the bonding surface of the first and second semiconductor substrates, and electrically connecting the wirings of the first and second semiconductor substrates to each other. It is a solid-state imaging device provided with the connection substrate which transmits a signal. This brings about the effect
  • the present technology it is possible to achieve an excellent effect that conduction between semiconductor substrates can be efficiently performed when stacking a plurality of semiconductor substrates.
  • the effect described here is not necessarily limited, and may be any effect described in the present disclosure.
  • FIG. 1 is a diagram illustrating a configuration example of a solid-state imaging device which is an example of a semiconductor device according to an embodiment of the present technology.
  • the solid-state imaging device includes a pixel area 10 and a peripheral circuit unit.
  • the peripheral circuit unit includes a vertical drive circuit 20, a horizontal drive circuit 30, a control circuit 40, a column signal processing circuit 50, and an output circuit 60.
  • the pixel area 10 is a pixel array in which a plurality of pixels 11 including photoelectric conversion units are arranged in a two-dimensional array.
  • the pixel 11 includes, for example, a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors.
  • the plurality of pixel transistors can be configured by, for example, three transistors: a transfer transistor, a reset transistor, and an amplification transistor. Moreover, it is possible to add four selection transistors and to configure four transistors.
  • the vertical drive circuit 20 drives the pixels 11 in units of rows.
  • the vertical drive circuit 20 is configured of, for example, a shift register.
  • the vertical drive circuit 20 selects a pixel drive line and supplies a pulse for driving the pixel 11 to the selected pixel drive line.
  • the vertical drive circuit 20 sequentially scans the pixels 11 of the pixel area 10 in the vertical direction sequentially in row units, and a pixel signal based on the signal charge generated according to the light reception amount in the photoelectric conversion unit of each pixel 11 Are supplied to the column signal processing circuit 50 via the vertical signal line (VSL) 19.
  • VSL vertical signal line
  • the horizontal drive circuit 30 drives the column signal processing circuit 50 in units of columns.
  • the horizontal drive circuit 30 is configured of, for example, a shift register.
  • the horizontal drive circuit 30 sequentially selects each of the column signal processing circuits 50 by sequentially outputting horizontal scanning pulses, and pixel signals from each of the column signal processing circuits 50 are transmitted via the horizontal signal line 59.
  • the output circuit 60 is made to output.
  • the control circuit 40 controls the entire solid-state imaging device.
  • the control circuit 40 receives an input clock and data instructing an operation mode and the like, and outputs data such as internal information of the solid-state imaging device. That is, the control circuit 40 generates clock signals and control signals that become the reference of operations of the vertical drive circuit 20, the column signal processing circuit 50, the horizontal drive circuit 30, etc. based on the vertical synchronization signal, the horizontal synchronization signal and the master clock. Generate Then, these signals are input to the vertical drive circuit 20, the column signal processing circuit 50, the horizontal drive circuit 30, and the like.
  • the column signal processing circuit 50 is disposed, for example, for each column of the pixels 11, and performs signal processing such as noise removal for each pixel column on signals output from the pixels 11 for one row. That is, the column signal processing circuit 50 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise unique to the pixel 11, signal amplification, AD (Analog to Digital) conversion, and the like.
  • a horizontal selection switch (not shown) is connected between the output stage of the column signal processing circuit 50 and the horizontal signal line 59.
  • the output circuit 60 performs signal processing on signals sequentially supplied from each of the column signal processing circuits 50 through the horizontal signal line 59 and outputs the processed signals. At this time, the output circuit 60 buffers the signal from the column signal processing circuit 50.
  • the output circuit 60 may perform black level adjustment, column variation correction, various digital signal processing, and the like on the signal from the column signal processing circuit 50.
  • FIG. 2 is a diagram showing an example of division of a semiconductor substrate of a solid-state imaging device which is an example of the semiconductor device according to the embodiment of the present technology.
  • A in the same figure shows a first example.
  • the first example is composed of a first semiconductor chip 110 and a second semiconductor chip 120.
  • the pixel region 111 and the control circuit 112 are mounted on the first semiconductor chip 110.
  • On the second semiconductor chip 120 a logic circuit 121 including a signal processing circuit is mounted. Then, by electrically connecting the first semiconductor chip 110 and the second semiconductor chip 120 to each other, a solid-state imaging device as one semiconductor device is configured.
  • the second example is composed of a first semiconductor chip 110 and a second semiconductor chip 120.
  • the pixel region 111 is mounted on the first semiconductor chip 110.
  • a control circuit 122 and a logic circuit 121 including a signal processing circuit are mounted on the second semiconductor chip 120. Then, by electrically connecting the first semiconductor chip 110 and the second semiconductor chip 120 to each other, a solid-state imaging device as one semiconductor device is configured.
  • the third example is configured of a first semiconductor chip 110 and a second semiconductor chip 120.
  • a pixel region 111 and a control circuit 112 for controlling the pixel region 111 are mounted on the first semiconductor chip 110.
  • a logic circuit 121 including a signal processing circuit and a control circuit 122 for controlling the logic circuit 121 are mounted on the second semiconductor chip 120. Then, by electrically connecting the first semiconductor chip 110 and the second semiconductor chip 120 to each other, a solid-state imaging device as one semiconductor device is configured.
  • the semiconductor device is divided into a plurality of semiconductor substrates.
  • segmented semiconductor substrates and connecting wiring between semiconductor substrates is demonstrated.
  • a technique of laminating a plurality of semiconductor chips is illustrated as an example of a semiconductor substrate, but the same can be applied to a technique of laminating a plurality of wafers (also referred to as a semiconductor wafer or silicon wafer).
  • FIG. 3 is a view showing an example of the laminated structure of the semiconductor device according to the embodiment of the present technology.
  • the first semiconductor chip 110 and the second semiconductor chip 120 are vertically stacked, and connection terminals are formed on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120 using the cross sections of the wiring layers. Then, side chips 210 for electrically connecting the connection terminals are provided on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120.
  • the side chip 210 is a chip for electrically connecting and conducting the first semiconductor chip 110 and the second semiconductor chip 120. That is, the side chip 210 transmits the signal output from the first semiconductor chip 110 to the second semiconductor chip 120.
  • the side chip 210 may include only connection wiring, and may include a circuit having some function. For example, an AD conversion circuit in a solid-state imaging device may be provided.
  • the first semiconductor chip 110 and the second semiconductor chip 120 are an example of the semiconductor substrate described in the claims. Further, the side chip 210 is an example of the connection board described in the claims.
  • FIG. 4 is a view showing an example of the connection structure of the semiconductor device according to the embodiment of the present technology.
  • connection terminal 119 is formed on the first semiconductor chip 110 using the cross section of the end portion of the wiring layer in the first semiconductor chip 110.
  • connection terminal 129 is also formed on the second semiconductor chip 120 using the cross section of the end portion of the wiring layer in the second semiconductor chip 120.
  • the connection terminals 119 and 129 are exposed on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120 by scraping the end portions of the first semiconductor chip 110 and the second semiconductor chip 120. .
  • connection terminals 119 and 129 are exposed on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120, it is necessary to polish and planarize the side surfaces.
  • conventional wafer polishing techniques can be used.
  • Solder bumps or copper pillars are formed on the side chips 210 as connection terminals 219.
  • the side chip 210 connects between the connection terminal 119 of the first semiconductor chip 110 and the connection terminal 129 of the second semiconductor chip 120. Thereby, the conduction between the first semiconductor chip 110 and the second semiconductor chip 120 is secured via the side chip 210.
  • At least one layer may be provided for the connection terminals 119 and the connection terminals 129 in the first semiconductor chip 110 and the second semiconductor chip 120.
  • the multilayer structure can improve the area efficiency available in the first semiconductor chip 110 and the second semiconductor chip 120, and can reduce the chip area.
  • the first semiconductor chip 110 and the column signal processing circuit 50 and the like are provided in the second semiconductor chip 120 as the chip division mode, the first semiconductor chip 110 and the second semiconductor chip 120 The vertical signal line 19 will pass through during this time. As the number of pixels in the pixel area 10 increases, the bit width of the vertical signal line 19 also increases. If the through holes (TSVs) are provided on the surface between the chips as in the prior art, a large area is required for that, which may limit the mounted circuit. In this respect, according to this embodiment, the side surface of the first semiconductor chip 110 and the second semiconductor chip 120 is used, so that the restriction on the area can be avoided.
  • TSVs through holes
  • the side chip 210 in order for the side chip 210 to transmit the pixel signal output from the first semiconductor chip 110 through the vertical signal line 19 to the second semiconductor chip 120, it is necessary to provide a through hole on the bonding surface of both chips. Absent. When the pixel region 10 is provided in the first semiconductor chip 110 disposed in the upper portion as described above, it is assumed that a microlens (not shown) is further provided thereon.
  • a connection terminal is provided on the surface where the first semiconductor chip 110 and the second semiconductor chip 120 are in contact with each other. There is no need. Therefore, it is sufficient to simply bond the first semiconductor chip 110 and the second semiconductor chip 120 by insulating film bonding, adhesive bonding, or the like.
  • the side chip 210 can ensure conduction between the first semiconductor chip 110 and the second semiconductor chip 120, and can realize high functionality by chip on chip conversion.
  • the two-layer stacked structure of the first semiconductor chip 110 and the second semiconductor chip 120 has been described, but as described later, the same technique is applied to a multilayer stacked structure of three or more layers. It can correspond.
  • the side chip 210 may be provided at any side surface of the first semiconductor chip 110 and the second semiconductor chip 120.
  • connection terminals 119 and 129 are provided on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120, and both are electrically connected via the side chip 210.
  • TSV copper-to-copper bonding
  • Cu-Cu bonding copper-to-copper bonding
  • connection terminals at the interface between the upper and lower chips it is not necessary to provide connection terminals at the interface between the upper and lower chips, but simply bonding them by insulating film bonding or adhesive bonding. Good.
  • FIG. 5 is a view showing an example of a laminated structure of a semiconductor device in a first modified example of the embodiment of the present technology.
  • the semiconductor device of the first modification has a structure in which a first semiconductor chip 110, a second semiconductor chip 120, and a third semiconductor chip 130 are stacked.
  • a side chip 210 is provided on the side surface of the first to third semiconductor chips 110 to 130.
  • the side chip 210 in the first modification electrically connects the connection terminals of the first to third semiconductor chips 110 to 130 as in the above-described embodiment.
  • the side chip 210 in the first modification may include only the connection wiring, as in the above-described embodiment, or may include a circuit having some function.
  • the first semiconductor chip 110 in the uppermost layer has the pixel region 10
  • the second semiconductor chip 120 has the column signal processing circuit 50, etc. It is assumed that a memory is provided in the third semiconductor chip 130 of FIG. At this time, it is assumed that a microlens (not shown) is further provided thereon.
  • the second semiconductor chip 120 disposed on the inner side is a connection terminal of a signal from the upper first semiconductor chip 110, and a lower third semiconductor chip. Two wiring layers are required separately for connection of signals from 130.
  • one side chip 210 is provided on one side of the first to third semiconductor chips 110 to 130, and the connection terminals are provided between It can be conducted.
  • FIG. 6 is a view showing an example of a laminated structure of a semiconductor device in a second modified example of the embodiment of the present technology.
  • the semiconductor device of the second modification has a structure in which the first semiconductor chip 110, the second semiconductor chip 120, and the third semiconductor chip 130 are stacked in the same manner as the first modification. Also, two side chips 210 and 220 are provided on the side surfaces of the first to third semiconductor chips 110 to 130.
  • the side chip 210 electrically connects the connection terminals of the first semiconductor chip 110 and the second semiconductor chip 120.
  • the side chip 220 electrically connects the connection terminals of the second semiconductor chip 120 and the third semiconductor chip 130. That is, the two side chips 210 and 220 electrically connect the connection terminals between different chips.
  • the signal terminals of the side chips 210 and 220 can be dispersed to reduce the number of terminals.
  • two side chips 210 and 220 are provided on one side of the first to third semiconductor chips 110 to 130, and There can be conduction between them.
  • FIG. 7 is a view showing an example of a laminated structure of a semiconductor device in a third modified example of the embodiment of the present technology.
  • the semiconductor device of the third modification has a structure in which the first semiconductor chip 110, the second semiconductor chip 120, and the third semiconductor chip 130 are stacked in the same manner as the first modification. Then, two side chips 210 and 220 are provided on different side surfaces of the first to third semiconductor chips 110 to 130.
  • the side chip 210 electrically connects between the connection terminals of the first semiconductor chip 110 and the second semiconductor chip 120, and the side chip 220 generates the second semiconductor chip 120 and the third semiconductor chip. Conduction between the 130 connection terminals.
  • the side tips 210 and 220 are provided on different sides. Thereby, as compared with the second modification, the arrangement of the signal terminals of the side chips 210 and 220 can be dispersed to increase the freedom of the floor arrangement.
  • side chips 210 and 220 are provided on different side surfaces of the first to third semiconductor chips 110 to 130, and between the connection terminals are provided. It can be conducted.
  • the present technology can also be configured as follows. (1) A plurality of semiconductor substrates stacked one on top of the other and joined together A semiconductor device comprising: a connection substrate which is provided on a side surface different from a bonding surface of the plurality of semiconductor substrates and which electrically connects the wirings of the plurality of semiconductor substrates. (2) Each of the plurality of semiconductor substrates has a wiring layer, and an end of the wiring layer forms a connection terminal, and is connected to the connection substrate through the connection terminal according to the above (1) Semiconductor device. (3) The semiconductor device according to (1) or (2), wherein the connection substrate includes a connection terminal and is connected to the plurality of semiconductor substrates via the connection terminal.
  • connection terminal of the connection substrate is formed of a solder bump or a copper pillar.
  • a plurality of connection substrates are provided on the same side surface of the plurality of semiconductor substrates.
  • the connection substrate is provided on a plurality of different side surfaces of the plurality of semiconductor substrates.
  • each of the plurality of semiconductor substrates is a semiconductor chip.
  • each of the plurality of semiconductor substrates is a semiconductor wafer.
  • a first semiconductor substrate including a photoelectric conversion unit that outputs a pixel signal
  • a second semiconductor substrate including a signal processing circuit which is stacked and joined to the first semiconductor substrate and processes the pixel signal;
  • a connection substrate which is provided on a side surface different from the bonding surface of the first and second semiconductor substrates, electrically connects the wirings of the first and second semiconductor substrates, and transmits the pixel signal.

Abstract

The present invention efficiently achieves electrical conduction between semiconductor substrates in cases where a plurality of semiconductor substrates are laminated. A semiconductor device according to the present invention is provided with a plurality of semiconductor substrates (110, 120) and a connection substrate (210). The plurality of semiconductor substrates are laminated one upon another and bonded with each other. The connection substrate is provided on lateral surfaces of the plurality of semiconductor substrates, said lateral surfaces being different from bonding surfaces. The connection substrate electrically connects the wiring lines of the plurality of semiconductor substrates to each other. Consequently, the plurality of semiconductor substrates are electrically connected to each other without being provided with connection terminals on the bonding surfaces.

Description

半導体装置および固体撮像装置Semiconductor device and solid-state imaging device
　本技術は、半導体装置における積層技術に関する。詳しくは、複数の半導体基板を積層した半導体装置に関する。 The present technology relates to a lamination technology in a semiconductor device. Specifically, the present invention relates to a semiconductor device in which a plurality of semiconductor substrates are stacked.
　従来、半導体装置において高速化や多機能化を実現するための技術として、各種デバイスを積層化する手法が提案されている。例えば、複数のウェハーを絶縁膜接合（Dielectric Bonding）またはハイブリッド接合（Hybrid Bonding：ＣｕＣｕ接合）などによって貼り合わせるウェハー積層技術が知られている（例えば、特許文献１参照。）。このウェハー積層技術においては、各ウェハー間の導通は、絶縁膜接合の場合は貼り合わせ後に形成される貫通孔（ＴＳＶ：Through Silicon Via）により確保され、ハイブリッド接合の場合は接合界面に設けられた銅パッドにより確保される。また、積層されたウェハーまたはチップ上に、別のチップを半田バンプや銅ピラー等の接続端子を用いて接続し、導通を確保するチップ積層技術が知られている（例えば、特許文献２参照。）。 2. Description of the Related Art Conventionally, as a technique for realizing high speed and multifunctionality in a semiconductor device, a method of laminating various devices has been proposed. For example, a wafer laminating technique is known in which a plurality of wafers are bonded by dielectric bonding or hybrid bonding (CuCu bonding) or the like (see, for example, Patent Document 1). In this wafer lamination technology, the conduction between the wafers is ensured by through holes (TSV: Through Silicon Via) formed after bonding in the case of insulating film bonding, and provided in the bonding interface in the case of hybrid bonding. Secured by copper pad. There is also known a chip stacking technique in which another chip is connected to a stacked wafer or chip by using a connection terminal such as a solder bump or a copper pillar to secure conduction (see, for example, Patent Document 2). ).
特開２０１５－０６５４７９号公報JP, 2015-065479, A 特開２０１６－１７１２９７号公報JP, 2016-171297, A
　上述の従来のウェハー積層技術では、各ウェハー間を、ＴＳＶによる接続またはハイブリッド接合により接続する必要があり、工程数の増加や、接合面の平坦性の欠如による接合不良などの問題が生じるおそれがある。また、上述の従来のチップ積層技術では、特にイメージセンサーへのチップ積層の場合には、チップ搭載部分の面積確保に伴うチップ面積の増大（理収ロス）や、裏面積層構造に伴う工程数増加や技術難易度の増加が生じ得る。 In the above-mentioned conventional wafer lamination technology, it is necessary to connect the respective wafers by TSV connection or hybrid junction, which may cause problems such as an increase in the number of processes and junction failure due to lack of flatness of the junction surface. is there. Further, in the above-described conventional chip stacking technology, particularly in the case of chip stacking on an image sensor, the chip area increases (margin loss) associated with securing the chip mounting area, and the number of processes associated with the back surface stacking structure increases. And technical difficulties may arise.
　本技術はこのような状況に鑑みて生み出されたものであり、複数の半導体基板を積層する際の半導体基板間の導通を効率よく行うことを目的とする。 The present technology is produced in view of such a situation, and it is an object of the present invention to efficiently conduct conduction between semiconductor substrates when laminating a plurality of semiconductor substrates.
　本技術は、上述の問題点を解消するためになされたものであり、その第１の側面は、上下に積層されて互いに接合された複数の半導体基板と、上記複数の半導体基板の接合面とは異なる側面に設けられて上記複数の半導体基板の配線間を電気的に接続する接続基板とを具備する半導体装置である。これにより、複数の半導体基板の接合面とは異なる側面において配線間を電気的に接続させるという作用をもたらす。 The present technology has been made to solve the above-described problems, and the first side surface thereof includes a plurality of semiconductor substrates stacked vertically and joined to each other, and a junction surface of the plurality of semiconductor substrates. Is a semiconductor device including a connection substrate provided on different side surfaces to electrically connect the wirings of the plurality of semiconductor substrates. This brings about the effect | action of electrically connecting between wiring in the side different from the joint surface of several semiconductor substrates.
　また、この第１の側面において、上記複数の半導体基板の各々は、配線層を有し、上記配線層の端部が接続端子を形成し、その接続端子を介して上記接続基板と接続するようにしてもよい。これにより、配線層の端部の接続端子を介して複数の半導体基板を導通させるという作用をもたらす。 In the first aspect, each of the plurality of semiconductor substrates has a wiring layer, and an end of the wiring layer forms a connection terminal, and is connected to the connection substrate through the connection terminal. You may This brings about the effect | action of electrically connecting a several semiconductor substrate via the connection terminal of the edge part of a wiring layer.
　また、この第１の側面において、上記接続基板は、接続端子を備え、その接続端子を介して上記複数の半導体基板と接続するようにしてもよい。これにより、接続基板の接続端子を介して複数の半導体基板を導通させるという作用をもたらす。 In the first aspect, the connection substrate may include a connection terminal, and the connection substrate may be connected to the plurality of semiconductor substrates via the connection terminal. This brings about the effect | action of making several semiconductor substrates conduct via the connection terminal of a connection board | substrate.
　また、この第１の側面において、上記接続基板の接続端子は、半田バンプまたは銅ピラーにより形成されてもよい。 In addition, in the first side surface, the connection terminal of the connection substrate may be formed of a solder bump or a copper pillar.
　また、この第１の側面において、上記接続基板は、上記複数の半導体基板の同じ側面に複数個設けられてもよく、また、上記複数の半導体基板の異なる複数の側面にそれぞれ設けられてもよい。 In addition, in the first aspect, a plurality of connection substrates may be provided on the same side surface of the plurality of semiconductor substrates, or may be provided on different side surfaces of the plurality of semiconductor substrates. .
　また、この第１の側面において、上記複数の半導体基板の各々は、半導体チップであってもよく、また、半導体ウェハーであってもよい。 In the first aspect, each of the plurality of semiconductor substrates may be a semiconductor chip or a semiconductor wafer.
　また、本技術の第２の側面は、画素信号を出力する光電変換部を含む第１の半導体基板と、上記第１の半導体基板に積層されて接合され、上記画素信号を処理する信号処理回路を含む第２の半導体基板と、上記第１および第２の半導体基板の接合面とは異なる側面に設けられて上記第１および第２の半導体基板の配線間を電気的に接続して上記画素信号を伝送する接続基板とを具備する固体撮像装置である。これにより、第１および第２の半導体基板の接合面とは異なる側面において配線間を電気的に接続させて画素信号を伝送するという作用をもたらす。 Further, according to a second aspect of the present technology, there is provided a first semiconductor substrate including a photoelectric conversion unit that outputs a pixel signal, and a signal processing circuit that is stacked and joined to the first semiconductor substrate and processes the pixel signal. And the bonding surface of the first and second semiconductor substrates, and electrically connecting the wirings of the first and second semiconductor substrates to each other. It is a solid-state imaging device provided with the connection substrate which transmits a signal. This brings about the effect | action of electrically connecting between wiring in the side different from the joint surface of a 1st and 2nd semiconductor substrate, and transmitting a pixel signal.
　本技術によれば、複数の半導体基板を積層する際の半導体基板間の導通を効率よく行うことができるという優れた効果を奏し得る。なお、ここに記載された効果は必ずしも限定されるものではなく、本開示中に記載されたいずれかの効果であってもよい。 According to the present technology, it is possible to achieve an excellent effect that conduction between semiconductor substrates can be efficiently performed when stacking a plurality of semiconductor substrates. In addition, the effect described here is not necessarily limited, and may be any effect described in the present disclosure.
本技術の実施の形態における半導体装置の一例である固体撮像装置の構成例を示す図である。It is a figure showing an example of composition of a solid-state imaging device which is an example of a semiconductor device in an embodiment of this art. 本技術の実施の形態における半導体装置の一例である固体撮像装置の半導体基板の分割例を示す図である。It is a figure showing an example of division of a semiconductor substrate of a solid-state imaging device which is an example of a semiconductor device in an embodiment of this art. 本技術の実施の形態における半導体装置の積層構造の一例を示す図である。It is a figure showing an example of the lamination structure of the semiconductor device in an embodiment of this art. 本技術の実施の形態における半導体装置の接続構造の一例を示す図である。It is a figure showing an example of the connection structure of the semiconductor device in an embodiment of this art. 本技術の実施の形態の第１の変形例における半導体装置の積層構造の一例を示す図である。It is a figure which shows an example of the laminated structure of the semiconductor device in the 1st modification of embodiment of this technique. 本技術の実施の形態の第２の変形例における半導体装置の積層構造の一例を示す図である。It is a figure which shows an example of the laminated structure of the semiconductor device in the 2nd modification of embodiment of this technique. 本技術の実施の形態の第３の変形例における半導体装置の積層構造の一例を示す図である。It is a figure which shows an example of the laminated structure of the semiconductor device in the 3rd modification of embodiment of this technique.
　以下、本技術を実施するための形態（以下、実施の形態と称する）について説明する。説明は以下の順序により行う。
　１．実施の形態
　２．変形例 Hereinafter, modes for implementing the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order.
1. Embodiment 2. Modified example
　＜１．実施の形態＞
　［固体撮像装置の構成］
　図１は、本技術の実施の形態における半導体装置の一例である固体撮像装置の構成例を示す図である。この固体撮像装置は、画素領域１０および周辺回路部からなる。周辺回路部は、垂直駆動回路２０と、水平駆動回路３０と、制御回路４０と、カラム信号処理回路５０と、出力回路６０とを備える。 <1. Embodiment>
[Configuration of solid-state imaging device]
FIG. 1 is a diagram illustrating a configuration example of a solid-state imaging device which is an example of a semiconductor device according to an embodiment of the present technology. The solid-state imaging device includes a pixel area 10 and a peripheral circuit unit. The peripheral circuit unit includes a vertical drive circuit 20, a horizontal drive circuit 30, a control circuit 40, a column signal processing circuit 50, and an output circuit 60.
　画素領域１０は、光電変換部を含む複数の画素１１を、２次元アレイ状に配列した画素アレイである。この画素１１は、光電変換部となる例えばフォトダイオードと、複数の画素トランジスタを含む。ここで、複数の画素トランジスタは、例えば、転送トランジスタ、リセットトランジスタおよび増幅トランジスタの３つのトランジスタにより構成することができる。また、選択トランジスタを追加して４つのトランジスタにより構成することもできる。 The pixel area 10 is a pixel array in which a plurality of pixels 11 including photoelectric conversion units are arranged in a two-dimensional array. The pixel 11 includes, for example, a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors. Here, the plurality of pixel transistors can be configured by, for example, three transistors: a transfer transistor, a reset transistor, and an amplification transistor. Moreover, it is possible to add four selection transistors and to configure four transistors.
　垂直駆動回路２０は、行単位で画素１１を駆動するものである。この垂直駆動回路２０は、例えばシフトレジスタによって構成される。この垂直駆動回路２０は、画素駆動配線を選択して、その選択された画素駆動配線に画素１１を駆動するためのパルスを供給する。これにより、垂直駆動回路２０は、画素領域１０の各画素１１を行単位で順次垂直方向に選択走査し、各画素１１の光電変換部において受光量に応じて生成された信号電荷に基づく画素信号を、垂直信号線（ＶＳＬ）１９を介して、カラム信号処理回路５０に供給する。 The vertical drive circuit 20 drives the pixels 11 in units of rows. The vertical drive circuit 20 is configured of, for example, a shift register. The vertical drive circuit 20 selects a pixel drive line and supplies a pulse for driving the pixel 11 to the selected pixel drive line. Thus, the vertical drive circuit 20 sequentially scans the pixels 11 of the pixel area 10 in the vertical direction sequentially in row units, and a pixel signal based on the signal charge generated according to the light reception amount in the photoelectric conversion unit of each pixel 11 Are supplied to the column signal processing circuit 50 via the vertical signal line (VSL) 19.
　水平駆動回路３０は、列単位にカラム信号処理回路５０を駆動するものである。この水平駆動回路３０は、例えばシフトレジスタによって構成される。この水平駆動回路３０は、水平走査パルスを順次出力することによって、カラム信号処理回路５０の各々を順番に選択し、カラム信号処理回路５０の各々から画素信号を、水平信号線５９を介して、出力回路６０に出力させる。 The horizontal drive circuit 30 drives the column signal processing circuit 50 in units of columns. The horizontal drive circuit 30 is configured of, for example, a shift register. The horizontal drive circuit 30 sequentially selects each of the column signal processing circuits 50 by sequentially outputting horizontal scanning pulses, and pixel signals from each of the column signal processing circuits 50 are transmitted via the horizontal signal line 59. The output circuit 60 is made to output.
　制御回路４０は、固体撮像装置の全体を制御するものである。この制御回路４０は、入力クロックと、動作モードなどを指令するデータとを受け取り、固体撮像装置の内部情報などのデータを出力する。すなわち、この制御回路４０は、垂直同期信号、水平同期信号およびマスタクロックに基いて、垂直駆動回路２０、カラム信号処理回路５０および水平駆動回路３０などの動作の基準となるクロック信号や制御信号を生成する。そして、これらの信号を垂直駆動回路２０、カラム信号処理回路５０および水平駆動回路３０等に入力する。 The control circuit 40 controls the entire solid-state imaging device. The control circuit 40 receives an input clock and data instructing an operation mode and the like, and outputs data such as internal information of the solid-state imaging device. That is, the control circuit 40 generates clock signals and control signals that become the reference of operations of the vertical drive circuit 20, the column signal processing circuit 50, the horizontal drive circuit 30, etc. based on the vertical synchronization signal, the horizontal synchronization signal and the master clock. Generate Then, these signals are input to the vertical drive circuit 20, the column signal processing circuit 50, the horizontal drive circuit 30, and the like.
　カラム信号処理回路５０は、画素１１の例えば列ごとに配置され、１行分の画素１１から出力される信号に対し、画素列ごとにノイズ除去などの信号処理を行うものである。すなわち、このカラム信号処理回路５０は、画素１１固有の固定パターンノイズを除去するためのＣＤＳ（Correlated Double Sampling）や、信号増幅、ＡＤ（Analog to Digital）変換等の信号処理を行う。カラム信号処理回路５０の出力段には、図示しない水平選択スイッチが水平信号線５９との間に接続される。 The column signal processing circuit 50 is disposed, for example, for each column of the pixels 11, and performs signal processing such as noise removal for each pixel column on signals output from the pixels 11 for one row. That is, the column signal processing circuit 50 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise unique to the pixel 11, signal amplification, AD (Analog to Digital) conversion, and the like. A horizontal selection switch (not shown) is connected between the output stage of the column signal processing circuit 50 and the horizontal signal line 59.
　出力回路６０は、カラム信号処理回路５０の各々から水平信号線５９を通して順次に供給される信号に対し、信号処理を行って出力するものである。その際、この出力回路６０は、カラム信号処理回路５０からの信号をバッファリングする。また、この出力回路６０は、カラム信号処理回路５０からの信号に対して、黒レベル調整、列ばらつき補正、各種デジタル信号処理などを行うようにしてもよい。 The output circuit 60 performs signal processing on signals sequentially supplied from each of the column signal processing circuits 50 through the horizontal signal line 59 and outputs the processed signals. At this time, the output circuit 60 buffers the signal from the column signal processing circuit 50. The output circuit 60 may perform black level adjustment, column variation correction, various digital signal processing, and the like on the signal from the column signal processing circuit 50.
　図２は、本技術の実施の形態における半導体装置の一例である固体撮像装置の半導体基板の分割例を示す図である。 FIG. 2 is a diagram showing an example of division of a semiconductor substrate of a solid-state imaging device which is an example of the semiconductor device according to the embodiment of the present technology.
　同図におけるａは、第１の例を示す。この第１の例は、第１の半導体チップ１１０と第２の半導体チップ１２０とから構成される。第１の半導体チップ１１０には、画素領域１１１と制御回路１１２が搭載される。第２の半導体チップ１２０には、信号処理回路を含むロジック回路１２１が搭載される。そして、第１の半導体チップ１１０と第２の半導体チップ１２０とが相互に電気的に接続されることにより、１つの半導体装置としての固体撮像装置が構成される。 "A" in the same figure shows a first example. The first example is composed of a first semiconductor chip 110 and a second semiconductor chip 120. The pixel region 111 and the control circuit 112 are mounted on the first semiconductor chip 110. On the second semiconductor chip 120, a logic circuit 121 including a signal processing circuit is mounted. Then, by electrically connecting the first semiconductor chip 110 and the second semiconductor chip 120 to each other, a solid-state imaging device as one semiconductor device is configured.
　同図におけるｂは、第２の例を示す。この第２の例は、第１の半導体チップ１１０と第２の半導体チップ１２０とから構成される。第１の半導体チップ１１０には、画素領域１１１が搭載される。第２の半導体チップ１２０には、制御回路１２２と、信号処理回路を含むロジック回路１２１が搭載される。そして、第１の半導体チップ１１０と第２の半導体チップ１２０とが相互に電気的に接続されることにより、１つの半導体装置としての固体撮像装置が構成される。 B in the same figure shows the 2nd example. The second example is composed of a first semiconductor chip 110 and a second semiconductor chip 120. The pixel region 111 is mounted on the first semiconductor chip 110. A control circuit 122 and a logic circuit 121 including a signal processing circuit are mounted on the second semiconductor chip 120. Then, by electrically connecting the first semiconductor chip 110 and the second semiconductor chip 120 to each other, a solid-state imaging device as one semiconductor device is configured.
　同図におけるｃは、第３の例を示す。この第３の例は、第１の半導体チップ１１０と第２の半導体チップ１２０とから構成される。第１の半導体チップ１１０には、画素領域１１１と、その画素領域１１１を制御する制御回路１１２とが搭載される。第２の半導体チップ１２０には、信号処理回路を含むロジック回路１２１と、そのロジック回路１２１を制御する制御回路１２２とが搭載される。そして、第１の半導体チップ１１０と第２の半導体チップ１２０とが相互に電気的に接続されることによって、１つの半導体装置としての固体撮像装置が構成される。 C in the same figure shows the 3rd example. The third example is configured of a first semiconductor chip 110 and a second semiconductor chip 120. A pixel region 111 and a control circuit 112 for controlling the pixel region 111 are mounted on the first semiconductor chip 110. On the second semiconductor chip 120, a logic circuit 121 including a signal processing circuit and a control circuit 122 for controlling the logic circuit 121 are mounted. Then, by electrically connecting the first semiconductor chip 110 and the second semiconductor chip 120 to each other, a solid-state imaging device as one semiconductor device is configured.
　これらの例において半導体装置は複数の半導体基板に分割されて構成される。以下では、これらの分割された半導体基板を積層して、半導体基板間の配線を接続するための技術について説明する。なお、ここでは、半導体基板の一例として複数の半導体チップを積層する技術を例示するが、複数のウェハー（半導体ウェハーまたはシリコンウェハーとも称する。）を積層する技術についても同様に適用することができる。 In these examples, the semiconductor device is divided into a plurality of semiconductor substrates. Below, the technique for laminating | stacking these divided | segmented semiconductor substrates and connecting wiring between semiconductor substrates is demonstrated. Here, a technique of laminating a plurality of semiconductor chips is illustrated as an example of a semiconductor substrate, but the same can be applied to a technique of laminating a plurality of wafers (also referred to as a semiconductor wafer or silicon wafer).
　［積層構造］
　図３は、本技術の実施の形態における半導体装置の積層構造の一例を示す図である。 [Laminated structure]
FIG. 3 is a view showing an example of the laminated structure of the semiconductor device according to the embodiment of the present technology.
　この実施の形態における半導体装置では、第１の半導体チップ１１０と、第２の半導体チップ１２０とを上下に積層し、その側面にそれらの配線層の断面を用いて接続端子を形成する。そして、これら接続端子の間を導通させるための側面チップ２１０を、第１の半導体チップ１１０および第２の半導体チップ１２０の側面に設ける。 In the semiconductor device according to this embodiment, the first semiconductor chip 110 and the second semiconductor chip 120 are vertically stacked, and connection terminals are formed on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120 using the cross sections of the wiring layers. Then, side chips 210 for electrically connecting the connection terminals are provided on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120.
　側面チップ２１０は、第１の半導体チップ１１０と第２の半導体チップ１２０との間を電気的に接続して導通させるためのチップである。すなわち、この側面チップ２１０は、第１の半導体チップ１１０から出力される信号を第２の半導体チップ１２０に伝送する。この側面チップ２１０は、接続配線のみを備えてもよく、また、何らかの機能を有する回路を備えてもよい。例えば、固体撮像装置におけるＡＤ変換回路を備えるようにしてもよい。 The side chip 210 is a chip for electrically connecting and conducting the first semiconductor chip 110 and the second semiconductor chip 120. That is, the side chip 210 transmits the signal output from the first semiconductor chip 110 to the second semiconductor chip 120. The side chip 210 may include only connection wiring, and may include a circuit having some function. For example, an AD conversion circuit in a solid-state imaging device may be provided.
　なお、第１の半導体チップ１１０および第２の半導体チップ１２０は、特許請求の範囲に記載の半導体基板の一例である。また、側面チップ２１０は、特許請求の範囲に記載の接続基板の一例である。 The first semiconductor chip 110 and the second semiconductor chip 120 are an example of the semiconductor substrate described in the claims. Further, the side chip 210 is an example of the connection board described in the claims.
　図４は、本技術の実施の形態における半導体装置の接続構造の一例を示す図である。 FIG. 4 is a view showing an example of the connection structure of the semiconductor device according to the embodiment of the present technology.
　第１の半導体チップ１１０には、その第１の半導体チップ１１０における配線層の端部の断面を用いて、接続端子１１９が形成される。また、第２の半導体チップ１２０にも、その第２の半導体チップ１２０における配線層の端部の断面を用いて、接続端子１２９が形成される。これら接続端子１１９および１２９は、第１の半導体チップ１１０および第２の半導体チップ１２０の端部を削り取ることにより、第１の半導体チップ１１０および第２の半導体チップ１２０の側面に露出したものである。 The connection terminal 119 is formed on the first semiconductor chip 110 using the cross section of the end portion of the wiring layer in the first semiconductor chip 110. The connection terminal 129 is also formed on the second semiconductor chip 120 using the cross section of the end portion of the wiring layer in the second semiconductor chip 120. The connection terminals 119 and 129 are exposed on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120 by scraping the end portions of the first semiconductor chip 110 and the second semiconductor chip 120. .
　なお、第１の半導体チップ１１０および第２の半導体チップ１２０の側面において接続端子１１９および１２９を露出させる際、側面を研磨して平坦化する必要がある。この平坦化のためには、通常のウェハーを研磨する技術を利用することができる。 When the connection terminals 119 and 129 are exposed on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120, it is necessary to polish and planarize the side surfaces. For this planarization, conventional wafer polishing techniques can be used.
　側面チップ２１０には、半田バンプまたは銅ピラーを接続端子２１９として形成する。この側面チップ２１０は、第１の半導体チップ１１０の接続端子１１９と第２の半導体チップ１２０の接続端子１２９との間を接続する。これにより、側面チップ２１０を介して第１の半導体チップ１１０と第２の半導体チップ１２０との間の導通が確保される。 Solder bumps or copper pillars are formed on the side chips 210 as connection terminals 219. The side chip 210 connects between the connection terminal 119 of the first semiconductor chip 110 and the connection terminal 129 of the second semiconductor chip 120. Thereby, the conduction between the first semiconductor chip 110 and the second semiconductor chip 120 is secured via the side chip 210.
　第１の半導体チップ１１０および第２の半導体チップ１２０における接続端子１１９および接続端子１２９は、少なくとも１層が設けられていればよい。ただし、多層にすることにより、第１の半導体チップ１１０および第２の半導体チップ１２０において利用可能な面積効率を向上させ、チップ面積を削減することができる。 At least one layer may be provided for the connection terminals 119 and the connection terminals 129 in the first semiconductor chip 110 and the second semiconductor chip 120. However, the multilayer structure can improve the area efficiency available in the first semiconductor chip 110 and the second semiconductor chip 120, and can reduce the chip area.
　チップ分割態様として、画素領域１０を第１の半導体チップ１１０に設け、カラム信号処理回路５０等を第２の半導体チップ１２０に設けた場合、第１の半導体チップ１１０と第２の半導体チップ１２０との間に垂直信号線１９が通過することになる。画素領域１０における画素数が多いほど、この垂直信号線１９のビット幅も多くなる。従来のように貫通孔（ＴＳＶ）をチップ間の面に設けるとすると、そのために多くの面積が必要になり、搭載される回路に制約が生じるおそれがある。その点、この実施の形態によれば、第１の半導体チップ１１０および第２の半導体チップ１２０の側面を利用するため、面積上の制約を回避することができる。すなわち、第１の半導体チップ１１０から垂直信号線１９を介して出力される画素信号を、側面チップ２１０が第２の半導体チップ１２０に伝送するため、両チップの接合面に貫通孔を設ける必要はない。なお、このように上部に配置される第１の半導体チップ１１０に画素領域１０を設けた場合、さらにその上に（図示しない）マイクロレンズを設けることが想定される。 When the pixel area 10 is provided in the first semiconductor chip 110 and the column signal processing circuit 50 and the like are provided in the second semiconductor chip 120 as the chip division mode, the first semiconductor chip 110 and the second semiconductor chip 120 The vertical signal line 19 will pass through during this time. As the number of pixels in the pixel area 10 increases, the bit width of the vertical signal line 19 also increases. If the through holes (TSVs) are provided on the surface between the chips as in the prior art, a large area is required for that, which may limit the mounted circuit. In this respect, according to this embodiment, the side surface of the first semiconductor chip 110 and the second semiconductor chip 120 is used, so that the restriction on the area can be avoided. That is, in order for the side chip 210 to transmit the pixel signal output from the first semiconductor chip 110 through the vertical signal line 19 to the second semiconductor chip 120, it is necessary to provide a through hole on the bonding surface of both chips. Absent. When the pixel region 10 is provided in the first semiconductor chip 110 disposed in the upper portion as described above, it is assumed that a microlens (not shown) is further provided thereon.
　側面チップ２１０によって第１の半導体チップ１１０と第２の半導体チップ１２０との間の導通を確保するため、第１の半導体チップ１１０と第２の半導体チップ１２０とが接する面には接続端子を設ける必要はない。したがって、第１の半導体チップ１１０と第２の半導体チップ１２０との間は、絶縁膜接合や接着剤接合などにより、単に貼り合わせるだけでよい。 In order to ensure conduction between the first semiconductor chip 110 and the second semiconductor chip 120 by the side chip 210, a connection terminal is provided on the surface where the first semiconductor chip 110 and the second semiconductor chip 120 are in contact with each other. There is no need. Therefore, it is sufficient to simply bond the first semiconductor chip 110 and the second semiconductor chip 120 by insulating film bonding, adhesive bonding, or the like.
　また、この側面チップ２１０により、第１の半導体チップ１１０と第２の半導体チップ１２０との間の導通を確保するとともに、チップ・オン・チップ化による高機能化を実現することができる。 Further, the side chip 210 can ensure conduction between the first semiconductor chip 110 and the second semiconductor chip 120, and can realize high functionality by chip on chip conversion.
　なお、この実施の形態では、第１の半導体チップ１１０および第２の半導体チップ１２０の２層の積層構造について説明したが、後述するように、３層以上の多層積層構造にも同様の技術によって対応することができる。また、側面チップ２１０を設ける位置は、第１の半導体チップ１１０および第２の半導体チップ１２０における何れの側面であってもよい。 In this embodiment, the two-layer stacked structure of the first semiconductor chip 110 and the second semiconductor chip 120 has been described, but as described later, the same technique is applied to a multilayer stacked structure of three or more layers. It can correspond. Further, the side chip 210 may be provided at any side surface of the first semiconductor chip 110 and the second semiconductor chip 120.
　このように、本技術の実施の形態では、第１の半導体チップ１１０および第２の半導体チップ１２０の側面に接続端子１１９および１２９を設け、側面チップ２１０を介して両者を導通させる。これにより、ＴＳＶや銅同士の接合（ＣｕＣｕ接合）を用いることなく確保することができ、ＴＳＶ形成やＣｕＣｕ接合用パッドの形成が不要となる。 As described above, in the embodiment of the present technology, the connection terminals 119 and 129 are provided on the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120, and both are electrically connected via the side chip 210. As a result, it is possible to secure without using TSV or copper-to-copper bonding (Cu-Cu bonding), and it becomes unnecessary to form the TSV or the Cu-Cu bonding pad.
　また、上下チップとは別の機能を持った側面チップ２１０を側面に接続することにより、従来のチップ・オン・チップ構造と同様に、高速化や多機能化を図ることが可能となる。 Further, by connecting the side chip 210 having a function different from that of the upper and lower chips to the side surface, it becomes possible to achieve high speed and multi-functionalization as in the conventional chip-on-chip structure.
　また、この実施の形態では、側面チップ２１０によって上下チップの導通を確保するため、上下チップ間の界面には接続端子を設ける必要はなく、絶縁膜接合や接着剤接合により、単に貼り合わせるだけでよい。 Further, in this embodiment, in order to ensure the conduction of the upper and lower chips by the side chip 210, it is not necessary to provide connection terminals at the interface between the upper and lower chips, but simply bonding them by insulating film bonding or adhesive bonding. Good.
　また、上下チップ間の界面には平坦性が要求されないため、ウェハー・オン・ウェハーの場合は、平坦化を確保するためのＣＭＰ（Chemical Mechanical Polishing）などの研磨工程の要求精度を緩和することができる。 In addition, since the interface between the upper and lower chips is not required to have flatness, in the case of a wafer on wafer, the required accuracy of the polishing process such as CMP (Chemical Mechanical Polishing) for securing planarization should be relaxed. it can.
　また、イメージセンサーを積層する場合、受光面側にチップを積層する必要がなくなり、チップ搭載部分の面積確保に伴うチップ面積の増大（理収ロス）を抑制することができる。 Moreover, when laminating an image sensor, it is not necessary to laminate a chip on the light receiving surface side, and it is possible to suppress an increase in chip area (reasonable loss) associated with securing the area of the chip mounting portion.
　また、裏面積層の必要もなくなるため、裏面積層に必要とされていた裏面ＴＳＶの形成も不要となる。 Further, since the back surface lamination is not necessary, the formation of the back surface TSV required for the back surface lamination is also unnecessary.
　＜２．変形例＞
　上述の実施の形態では２つのチップを積層した２層の積層構造について説明したが、以下に示す変形例のように、この技術は３層以上の多層積層構造にも適用することができる。 <2. Modified example>
Although the above-mentioned embodiment explained the lamination structure of two layers which laminated two chips, like the modification shown below, this art is applicable also to the multilayer lamination structure of three or more layers.
　［第１の変形例］
　図５は、本技術の実施の形態の第１の変形例における半導体装置の積層構造の一例を示す図である。この第１の変形例の半導体装置は、第１の半導体チップ１１０、第２の半導体チップ１２０および第３の半導体チップ１３０を積層した構造となっている。そして、第１乃至第３の半導体チップ１１０乃至１３０の側面には、側面チップ２１０が設けられる。 [First Modification]
FIG. 5 is a view showing an example of a laminated structure of a semiconductor device in a first modified example of the embodiment of the present technology. The semiconductor device of the first modification has a structure in which a first semiconductor chip 110, a second semiconductor chip 120, and a third semiconductor chip 130 are stacked. A side chip 210 is provided on the side surface of the first to third semiconductor chips 110 to 130.
　この第１の変形例における側面チップ２１０は、上述の実施の形態のものと同様に、第１乃至第３の半導体チップ１１０乃至１３０の接続端子の間を導通させる。この第１の変形例における側面チップ２１０は、上述の実施の形態のものと同様に、接続配線のみを備えてもよく、また、何らかの機能を有する回路を備えてもよい。 The side chip 210 in the first modification electrically connects the connection terminals of the first to third semiconductor chips 110 to 130 as in the above-described embodiment. The side chip 210 in the first modification may include only the connection wiring, as in the above-described embodiment, or may include a circuit having some function.
　このような３層の積層構造を固体撮像装置に適用した場合、例えば最上層の第１の半導体チップ１１０に画素領域１０を、第２の半導体チップ１２０にカラム信号処理回路５０等を、最下層の第３の半導体チップ１３０にはメモリを設けることが想定される。このとき、さらにその上に（図示しない）マイクロレンズを設けることが想定される。 When such a three-layer stacked structure is applied to a solid-state imaging device, for example, the first semiconductor chip 110 in the uppermost layer has the pixel region 10, the second semiconductor chip 120 has the column signal processing circuit 50, etc. It is assumed that a memory is provided in the third semiconductor chip 130 of FIG. At this time, it is assumed that a microlens (not shown) is further provided thereon.
　このような３層の積層構造を想定した場合、内側に配置される第２の半導体チップ１２０は、上側の第１の半導体チップ１１０からの信号の接続端子と、下側の第３の半導体チップ１３０からの信号の接続端子とのために、別々に２つの配線層が必要になる。 Assuming such a three-layer stacked structure, the second semiconductor chip 120 disposed on the inner side is a connection terminal of a signal from the upper first semiconductor chip 110, and a lower third semiconductor chip. Two wiring layers are required separately for connection of signals from 130.
　このように、本技術の実施の形態の第１の変形例では、第１乃至第３の半導体チップ１１０乃至１３０の一側面に、１つの側面チップ２１０を設けて、これらの接続端子の間を導通させることができる。 Thus, in the first modified example of the embodiment of the present technology, one side chip 210 is provided on one side of the first to third semiconductor chips 110 to 130, and the connection terminals are provided between It can be conducted.
　［第２の変形例］
　図６は、本技術の実施の形態の第２の変形例における半導体装置の積層構造の一例を示す図である。この第２の変形例の半導体装置は、第１の変形例と同様に、第１の半導体チップ１１０、第２の半導体チップ１２０および第３の半導体チップ１３０を積層した構造となっている。そして、第１乃至第３の半導体チップ１１０乃至１３０の側面には、２つの側面チップ２１０および２２０が設けられる。 Second Modified Example
FIG. 6 is a view showing an example of a laminated structure of a semiconductor device in a second modified example of the embodiment of the present technology. The semiconductor device of the second modification has a structure in which the first semiconductor chip 110, the second semiconductor chip 120, and the third semiconductor chip 130 are stacked in the same manner as the first modification. Also, two side chips 210 and 220 are provided on the side surfaces of the first to third semiconductor chips 110 to 130.
　この第２の変形例において、側面チップ２１０は、第１の半導体チップ１１０および第２の半導体チップ１２０の接続端子の間を導通させる。一方、側面チップ２２０は、第２の半導体チップ１２０および第３の半導体チップ１３０の接続端子の間を導通させる。すなわち、２つの側面チップ２１０および２２０は、それぞれ異なるチップ間の接続端子を導通させる。これにより、第１の変形例と比べて、側面チップ２１０および２２０のそれぞれの信号端子を分散させて、端子数を減らすことができる。 In the second modified example, the side chip 210 electrically connects the connection terminals of the first semiconductor chip 110 and the second semiconductor chip 120. On the other hand, the side chip 220 electrically connects the connection terminals of the second semiconductor chip 120 and the third semiconductor chip 130. That is, the two side chips 210 and 220 electrically connect the connection terminals between different chips. As a result, compared to the first modification, the signal terminals of the side chips 210 and 220 can be dispersed to reduce the number of terminals.
　このように、本技術の実施の形態の第２の変形例では、第１乃至第３の半導体チップ１１０乃至１３０の一側面に、２つの側面チップ２１０および２２０を設けて、これらの接続端子の間を導通させることができる。 Thus, in the second modified example of the embodiment of the present technology, two side chips 210 and 220 are provided on one side of the first to third semiconductor chips 110 to 130, and There can be conduction between them.
　［第３の変形例］
　図７は、本技術の実施の形態の第３の変形例における半導体装置の積層構造の一例を示す図である。この第３の変形例の半導体装置は、第１の変形例と同様に、第１の半導体チップ１１０、第２の半導体チップ１２０および第３の半導体チップ１３０を積層した構造となっている。そして、２つの側面チップ２１０および２２０が、第１乃至第３の半導体チップ１１０乃至１３０の異なる側面に設けられる。 Third Modified Example
FIG. 7 is a view showing an example of a laminated structure of a semiconductor device in a third modified example of the embodiment of the present technology. The semiconductor device of the third modification has a structure in which the first semiconductor chip 110, the second semiconductor chip 120, and the third semiconductor chip 130 are stacked in the same manner as the first modification. Then, two side chips 210 and 220 are provided on different side surfaces of the first to third semiconductor chips 110 to 130.
　この第３の変形例において、側面チップ２１０は第１の半導体チップ１１０および第２の半導体チップ１２０の接続端子の間を導通させ、側面チップ２２０は第２の半導体チップ１２０および第３の半導体チップ１３０の接続端子の間を導通させる。この点は、上述の第２の変形例と同様である。ただし、この第３の変形例では、側面チップ２１０および２２０は互いに異なる側面に設けられる。これにより、第２の変形例と比べて、側面チップ２１０および２２０のそれぞれの信号端子の配置を分散させて、フロア配置の自由度を増すことができる。 In the third modification, the side chip 210 electrically connects between the connection terminals of the first semiconductor chip 110 and the second semiconductor chip 120, and the side chip 220 generates the second semiconductor chip 120 and the third semiconductor chip. Conduction between the 130 connection terminals. This point is the same as the second modification described above. However, in the third modification, the side tips 210 and 220 are provided on different sides. Thereby, as compared with the second modification, the arrangement of the signal terminals of the side chips 210 and 220 can be dispersed to increase the freedom of the floor arrangement.
　このように、本技術の実施の形態の第３の変形例では、第１乃至第３の半導体チップ１１０乃至１３０の異なる側面に、側面チップ２１０および２２０を設けて、これらの接続端子の間を導通させることができる。 Thus, in the third modified example of the embodiment of the present technology, side chips 210 and 220 are provided on different side surfaces of the first to third semiconductor chips 110 to 130, and between the connection terminals are provided. It can be conducted.
　なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。 Note that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the invention-specifying matters in the claims have correspondence relationships. Similarly, the invention specific matter in the claims and the matter in the embodiment of the present technology with the same name as this have a correspondence relation, respectively. However, the present technology is not limited to the embodiments, and can be embodied by variously modifying the embodiments without departing from the scope of the present technology.
　なお、本明細書に記載された効果はあくまで例示であって、限定されるものではなく、また、他の効果があってもよい。 In addition, the effect described in this specification is an illustration to the last, is not limited, and may have other effects.
　なお、本技術は以下のような構成もとることができる。
（１）上下に積層されて互いに接合された複数の半導体基板と、
　前記複数の半導体基板の接合面とは異なる側面に設けられて前記複数の半導体基板の配線間を電気的に接続する接続基板と
を具備する半導体装置。
（２）前記複数の半導体基板の各々は、配線層を有し、前記配線層の端部が接続端子を形成し、その接続端子を介して前記接続基板と接続する前記（１）に記載の半導体装置。
（３）前記接続基板は、接続端子を備え、その接続端子を介して前記複数の半導体基板と接続する前記（１）または（２）に記載の半導体装置。
（４）前記接続基板の接続端子は、半田バンプまたは銅ピラーにより形成される前記（３）に記載の半導体装置。
（５）前記接続基板は、前記複数の半導体基板の同じ側面に複数個設けられる前記（１）から（４）のいずれかに記載の半導体装置。
（６）前記接続基板は、前記複数の半導体基板の異なる複数の側面にそれぞれ設けられる前記（１）から（４）のいずれかに記載の半導体装置。
（７）前記複数の半導体基板の各々は、半導体チップである前記（１）から（６）のいずれかに記載の半導体装置。
（８）前記複数の半導体基板の各々は、半導体ウェハーである前記（１）から（６）のいずれかに記載の半導体装置。
（９）画素信号を出力する光電変換部を含む第１の半導体基板と、
　前記第１の半導体基板に積層されて接合され、前記画素信号を処理する信号処理回路を含む第２の半導体基板と、
　前記第１および第２の半導体基板の接合面とは異なる側面に設けられて前記第１および第２の半導体基板の配線間を電気的に接続して前記画素信号を伝送する接続基板と
を具備する固体撮像装置。 The present technology can also be configured as follows.
(1) A plurality of semiconductor substrates stacked one on top of the other and joined together
A semiconductor device comprising: a connection substrate which is provided on a side surface different from a bonding surface of the plurality of semiconductor substrates and which electrically connects the wirings of the plurality of semiconductor substrates.
(2) Each of the plurality of semiconductor substrates has a wiring layer, and an end of the wiring layer forms a connection terminal, and is connected to the connection substrate through the connection terminal according to the above (1) Semiconductor device.
(3) The semiconductor device according to (1) or (2), wherein the connection substrate includes a connection terminal and is connected to the plurality of semiconductor substrates via the connection terminal.
(4) The semiconductor device according to (3), wherein the connection terminal of the connection substrate is formed of a solder bump or a copper pillar.
(5) The semiconductor device according to any one of (1) to (4), wherein a plurality of connection substrates are provided on the same side surface of the plurality of semiconductor substrates.
(6) The semiconductor device according to any one of (1) to (4), wherein the connection substrate is provided on a plurality of different side surfaces of the plurality of semiconductor substrates.
(7) The semiconductor device according to any one of (1) to (6), wherein each of the plurality of semiconductor substrates is a semiconductor chip.
(8) The semiconductor device according to any one of (1) to (6), wherein each of the plurality of semiconductor substrates is a semiconductor wafer.
(9) A first semiconductor substrate including a photoelectric conversion unit that outputs a pixel signal,
A second semiconductor substrate including a signal processing circuit which is stacked and joined to the first semiconductor substrate and processes the pixel signal;
A connection substrate which is provided on a side surface different from the bonding surface of the first and second semiconductor substrates, electrically connects the wirings of the first and second semiconductor substrates, and transmits the pixel signal. Solid-state imaging device.
　１０　画素領域
　１１　画素
　１９　垂直信号線（ＶＳＬ：Vertical Signal Line）
　２０　垂直駆動回路
　３０　水平駆動回路
　４０　制御回路
　５０　カラム信号処理回路
　５９　水平信号線
　６０　出力回路
　１１０、１２０、１３０　半導体チップ
　１１１　画素領域
　１１２、１２２　制御回路
　１２１　ロジック回路
　１１９、１２９　接続端子
　２１０、２２０　側面チップ
　２１９　接続端子 10 pixel area 11 pixels 19 vertical signal line (VSL: Vertical Signal Line)
Reference Signs List 20 vertical drive circuit 30 horizontal drive circuit 40 control circuit 50 column signal processing circuit 59 horizontal signal line 60 output circuit 110, 120, 130 semiconductor chip 111 pixel area 112, 122 control circuit 121 logic circuit 119, 129 connection terminal 210, 220 side surface Chip 219 connection terminal

Claims (9)

  1. 　上下に積層されて互いに接合された複数の半導体基板と、
    　前記複数の半導体基板の接合面とは異なる側面に設けられて前記複数の半導体基板の配線間を電気的に接続する接続基板と
    を具備する半導体装置。     A plurality of semiconductor substrates stacked one on top of the other and joined together;
    A semiconductor device comprising: a connection substrate which is provided on a side surface different from a bonding surface of the plurality of semiconductor substrates and which electrically connects the wirings of the plurality of semiconductor substrates.
  2. 　前記複数の半導体基板の各々は、配線層を有し、前記配線層の端部が接続端子を形成し、その接続端子を介して前記接続基板と接続する請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein each of the plurality of semiconductor substrates has a wiring layer, and an end of the wiring layer forms a connection terminal, and is connected to the connection substrate through the connection terminal.
  3. 　前記接続基板は、接続端子を備え、その接続端子を介して前記複数の半導体基板と接続する請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the connection substrate includes a connection terminal, and is connected to the plurality of semiconductor substrates via the connection terminal.
  4. 　前記接続基板の接続端子は、半田バンプまたは銅ピラーにより形成される請求項３記載の半導体装置。 The semiconductor device according to claim 3, wherein the connection terminal of the connection substrate is formed of a solder bump or a copper pillar.
  5. 　前記接続基板は、前記複数の半導体基板の同じ側面に複数個設けられる請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein a plurality of connection substrates are provided on the same side surface of the plurality of semiconductor substrates.
  6. 　前記接続基板は、前記複数の半導体基板の異なる複数の側面にそれぞれ設けられる請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the connection substrate is provided on a plurality of different side surfaces of the plurality of semiconductor substrates.
  7. 　前記複数の半導体基板の各々は、半導体チップである請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein each of the plurality of semiconductor substrates is a semiconductor chip.
  8. 　前記複数の半導体基板の各々は、半導体ウェハーである請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein each of the plurality of semiconductor substrates is a semiconductor wafer.
  9. 　画素信号を出力する光電変換部を含む第１の半導体基板と、
    　前記第１の半導体基板に積層されて接合され、前記画素信号を処理する信号処理回路を含む第２の半導体基板と、
    　前記第１および第２の半導体基板の接合面とは異なる側面に設けられて前記第１および第２の半導体基板の配線間を電気的に接続して前記画素信号を伝送する接続基板と
    を具備する固体撮像装置。     A first semiconductor substrate including a photoelectric conversion unit that outputs a pixel signal;
    A second semiconductor substrate including a signal processing circuit which is stacked and joined to the first semiconductor substrate and processes the pixel signal;
    A connection substrate which is provided on a side surface different from the bonding surface of the first and second semiconductor substrates, electrically connects the wirings of the first and second semiconductor substrates, and transmits the pixel signal. Solid-state imaging device.
PCT/JP2018/026596 2017-07-25 2018-07-13 Semiconductor device and solid-state imaging device WO2019021873A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05268535A (en) * 1992-03-24 1993-10-15 Toshiba Corp Visual sensor
US5714802A (en) * 1991-06-18 1998-02-03 Micron Technology, Inc. High-density electronic module
JP2012054450A (en) * 2010-09-02 2012-03-15 Sony Corp Semiconductor device, method of manufacturing the same, and electronic apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5714802A (en) * 1991-06-18 1998-02-03 Micron Technology, Inc. High-density electronic module
JPH05268535A (en) * 1992-03-24 1993-10-15 Toshiba Corp Visual sensor
JP2012054450A (en) * 2010-09-02 2012-03-15 Sony Corp Semiconductor device, method of manufacturing the same, and electronic apparatus

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