WO2019006829A1 - 一种薄膜晶体管及其制备方法、显示器 - Google Patents

一种薄膜晶体管及其制备方法、显示器 Download PDF

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Publication number
WO2019006829A1
WO2019006829A1 PCT/CN2017/097967 CN2017097967W WO2019006829A1 WO 2019006829 A1 WO2019006829 A1 WO 2019006829A1 CN 2017097967 W CN2017097967 W CN 2017097967W WO 2019006829 A1 WO2019006829 A1 WO 2019006829A1
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Prior art keywords
layer
pattern layer
thin film
film transistor
gate insulating
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French (fr)
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谢华飞
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/557,452 priority Critical patent/US20190013412A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor, a method for fabricating the same, and a display.
  • quantum dots Since the discovery of colloidal quantum dots with quantum size effects, they have been widely used in the field of electronics and optoelectronics in the form of thin films. Based on the adjustable size of the energy gap, small exciton binding energy, high electroluminescence and photoluminescence efficiency and inexpensive solution process, quantum dots have been successfully applied in thin-film optoelectronic devices such as solar cells and light-emitting diodes. . However, the charge transfer performance and application of quantum dots in thin film transistors have rarely been reported, far behind commercial silicon transistors and organic field effect transistors.
  • Semiconductor quantum dot colloids can achieve effective overlap and overlap of quantum confinement electron or hole wave functions through self-assembly and close packing, which will form a new type of "artificial film".
  • This solid film not only retains the unique properties of quantum dot materials.
  • the tunability also has high carrier mobility and electrical conductivity.
  • transistors with quantum dots as carrier transport layers have the advantages of simple preparation process, low cost, good weight and good flexibility, especially for silicon quantum dots, and silicon quantum dots are in three.
  • the strong quantum confinement of carriers (such as electrons, holes and excitons) in a silicon quantum dot structure makes its electrical and optical properties greatly The changes can be widely applied in micro-nano electronic devices, optoelectronic devices and thermoelectric devices.
  • the invention mainly provides a thin film transistor, a preparation method thereof and a display, aiming at solving the problem of how to prepare a thin film transistor by using silicon quantum dots.
  • a technical solution adopted by the present invention is to provide a method for fabricating a thin film transistor, the method comprising: sequentially forming a bottom gate pattern layer on a substrate and bottom gate insulation covering the bottom gate pattern layer a layer; a source pattern layer and a drain pattern layer are formed over the substrate; and a channel region is formed between the source pattern layer and the drain pattern layer; and the solution is formed by a solution containing silicon quantum dots Forming an active layer in the channel region; wherein the forming the active layer in the channel region by the solution containing the silicon quantum dots comprises: using the spin coating method to include the silicon quantum in the channel region The solution of the dots is spin-coated to form a silicon quantum dot film layer; the silicon quantum dot film layer is evaporated under low temperature to form a silicon quantum dot active layer.
  • a thin film transistor including: a source pattern layer and a drain pattern layer above the substrate, the source pattern layer and The drain pattern layers are spaced apart and form a channel region therebetween; an active layer in the channel region, the active layer comprising silicon quantum dots.
  • another technical solution adopted by the present invention is to provide a display including the above-described thin film transistor.
  • the present invention forms a source pattern layer and a drain pattern layer over the substrate, and a channel region is formed between the source pattern layer and the drain pattern layer;
  • the method of forming an active layer in a channel region by using a solution containing silicon quantum dots, preparing an active layer in a thin film transistor using a silicon quantum dot as a material, enriching a preparation material of the thin film transistor, and improving mobility of the silicon-based thin film transistor It is beneficial to improve the electrical uniformity of large-area silicon-based thin film transistors.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a thin film transistor provided by the present invention
  • FIG. 2 is a schematic structural view of a first embodiment of a thin film transistor provided by the present invention.
  • FIG. 3 is a schematic diagram of a specific process of step S13 in FIG. 1;
  • FIG. 4 is a schematic flow chart of a second embodiment of a method for fabricating a thin film transistor according to the present invention.
  • FIG. 5 is a schematic structural view of a second embodiment of a thin film transistor provided by the present invention.
  • FIG. 6 is a schematic flow chart of a third embodiment of a method for fabricating a thin film transistor provided by the present invention.
  • FIG. 7 is a schematic structural view of a third embodiment of a thin film transistor provided by the present invention.
  • a first embodiment of a method for fabricating a thin film transistor provided by the present invention includes:
  • a metal film can be sputtered on the substrate 101 by physical vapor deposition, and then the bottom gate pattern layer 102 is formed by a photolithography process of photoresist coating, exposure, development, and lift-off. Further, a certain thickness of the insulating material layer may be deposited on the substrate 101 by physical vapor deposition or plasma vapor deposition to form the bottom gate insulating layer 103.
  • the substrate 101 is a quartz substrate, a glass substrate or a silicon wafer substrate including but not limited to;
  • the metal is a conductive metal including, but not limited to, aluminum, silver, copper, ITO, gold or titanium, and the insulating material is including but not limited to An insulating material of silicon oxide, aluminum oxide, silicon nitride or ionic gel;
  • the bottom gate insulating layer 103 has a thickness of 200 nm.
  • the substrate 101 after the above step S11 is immersed and rinsed with a solution of acetone, methanol and isopropyl alcohol, and baked in a vapor deposition machine after baking at a certain temperature, and then a mask is used by thermal evaporation.
  • a metal material layer is deposited on the bottom gate insulating layer 103 to form a source pattern layer 104 and a drain pattern layer 105.
  • the material of the metal material layer is a conductive metal including, but not limited to, aluminum, silver, copper, ITO, gold or titanium; the formed metal material layer has a thickness of 100 nm.
  • a channel region (not shown) is formed between the source pattern layer 104 and the drain pattern layer 105.
  • the silicon quantum dots can be prepared by using methods including, but not limited to, mechanical grinding, liquid phase synthesis, electrochemical etching, single crystal silicon electrolysis, high temperature gas phase reduction of reducing atmosphere, and thermal decomposition.
  • Silicon quantum dots of the diameter here, the mechanical grinding method is taken as an example for explanation: First, the preliminary preparation is carried out: the large silicon wafer is cut into a cross-sectional size of 1.2 cm.
  • the burr can be opened in an argon atmosphere glove box.
  • the preliminary sample of the obtained silicon powder is taken out; finally, a solution is formed: the formed sample is dispersed in n-hexane, and then filtered with a 100 nm filter to obtain a certain concentration of the silicon quantum dot solution.
  • the concentration of silicon quantum dots in the silicon quantum dot solution is 2.5 mg/ml.
  • the step S13 may specifically include:
  • a solution containing silicon quantum dots may be dropped into the channel region in a glove box containing a high purity inert gas, and a silicon quantum dot film layer of a certain thickness may be formed for a certain period of time by spin coating.
  • the inert gas is nitrogen
  • the number of revolutions of the spin coating method is 3000 rpm
  • the spin coating time is 30 s.
  • S132 The silicon quantum dot film layer is evaporated by a low temperature vacuum to form a silicon quantum dot active layer.
  • the silicon quantum dot film layer is vacuum baked, for example, by baking the silicon quantum dot film layer in a vacuum environment at 80 ° C, and the active layer 106 is obtained after about 12 hours.
  • silicon oxide is deposited on the bottom gate insulating layer 103, the source pattern layer 104, the drain pattern layer 105, and the active layer 106 by chemical vapor deposition to form a cover source pattern layer 104 and a drain pattern layer. 105 and a protective layer 107 of the active layer 106.
  • the via hole 1071 communicating with the source pattern layer 104 or the drain pattern layer 105 is etched in the protective layer 107 by a photolithography process of photoresist coating, exposure, development, and lift-off, which is illustrated in the embodiment of the present embodiment.
  • the via is connected to the drain pattern layer 105 as an example.
  • steps S21, S22, and S23 in the second embodiment of the method for fabricating the thin film transistor provided by the present invention are the same as steps S11, S12, and S13 in the first embodiment, and are not described herein again.
  • Embodiments also include:
  • insulating material layer may be deposited on the bottom gate insulating layer 203, the source pattern layer 204, the drain pattern layer 205, and the active layer 206 by physical vapor deposition or plasma vapor deposition to form a top gate. Insulation layer 208.
  • the insulating material is an insulating material including, but not limited to, silicon oxide, aluminum oxide, silicon nitride or ionic gel, and the top gate insulating layer 208 is formed to have a thickness of 300 nm.
  • a metal film can be sputtered on the top gate insulating layer 208 by physical vapor deposition, and then subjected to a photolithography process of exposure, development, etching, and lift-off to form a top gate pattern layer 209.
  • the metal is a conductive metal including, but not limited to, aluminum, silver, copper, ITO, gold or titanium.
  • a protective layer 207 is formed on the top gate insulating layer 208 and the top gate pattern layer 209.
  • silicon oxide is deposited on the top gate insulating layer 208 by chemical vapor deposition to form a protective layer 207 covering the top gate insulating layer 208 and the top gate pattern layer 209.
  • a via 2071 communicating with the source pattern layer 204 or the drain pattern layer 205 is etched in the protective layer 207 and the top gate insulating layer 208 by a photolithography process of photoresist coating, exposure, development, and lift-off.
  • a third embodiment of a method for fabricating a thin film transistor provided by the present invention includes:
  • the source pattern layer 302 and the drain pattern layer 303 are formed on the substrate 301 in the embodiment, and the forming method is the same as the step S12 in the first embodiment, and details are not described herein again.
  • S32 forming an active layer 304 in a channel region (indicated in the figure) by a solution containing silicon quantum dots;
  • This step S32 is the same as step S13 in the first embodiment described above, and details are not described herein again.
  • insulating material layer may be deposited on the substrate 301 by physical vapor deposition or plasma vapor deposition to form the top gate insulating layer 305;
  • the insulating material is an insulating material including, but not limited to, silicon oxide, aluminum oxide, silicon nitride or ionic gel.
  • a metal film can be sputtered on the top gate insulating layer 305 by physical vapor deposition, and then subjected to a photolithography process of exposure, development, etching, and lift-off to form the top gate pattern layer 306.
  • the metal is a conductive metal including, but not limited to, aluminum, silver, copper, ITO, gold or titanium.
  • silicon oxide is deposited on the top gate insulating layer 305 by chemical vapor deposition to form a protective layer 307 covering the top gate insulating layer 305 and the top gate pattern layer 306.
  • S36 a via 3071 extending through the protective layer 307 and the top gate insulating layer 305 and communicating with the source pattern layer 302 or the drain pattern layer 303 is formed.
  • a via 3071 communicating with the source pattern layer 302 or the drain pattern layer 303 is etched in the protective layer 307 and the top gate insulating layer 305 by a photolithography process of photoresist coating, exposure, development, and lift-off.
  • a first embodiment of a thin film transistor provided by the present invention includes a bottom gate pattern layer 102, a bottom gate insulating layer 103, a source pattern layer 104, a drain pattern layer 105, an active layer 106, and a substrate layer 101.
  • Protective layer 107 is provided.
  • the bottom gate pattern layer 102 and the bottom gate insulating layer 103 are sequentially formed on the substrate 101 and the bottom gate insulating layer 103 covers the bottom gate pattern layer 102; the source pattern layer 104 and the drain pattern layer 105 are formed on the bottom gate insulating layer 103.
  • a channel region is formed between and between the active layer 106, and includes a silicon quantum dot; the protective layer 107 covers the source pattern layer 104, the drain pattern layer 105, and the active layer 106, and the protective layer 107
  • a via hole 1071 penetrating the protective layer 107 and communicating with the source pattern layer 104 or the drain pattern layer 105 is provided.
  • each layer in this embodiment is prepared by using the corresponding steps in the first embodiment of the method for fabricating the above-mentioned thin film transistor, and details are not described herein again.
  • the second embodiment of the thin film transistor provided by the present invention further includes a top gate insulating layer 208 and a top gate pattern layer 209.
  • the other structures in this embodiment are the same as those of the first embodiment of the thin film transistor described above, and are not described herein again.
  • the top gate insulating layer 208 is formed on the bottom gate insulating layer 203 and covers the source pattern layer 204, the drain pattern layer 205, and the active layer 206.
  • the top gate pattern layer 209 is formed on the top gate insulating layer 208.
  • each layer in this embodiment is prepared by using the corresponding steps in the second embodiment of the method for fabricating the above-mentioned thin film transistor, and details are not described herein again.
  • a third embodiment of a thin film transistor includes a source pattern layer 302 and a drain pattern layer 303, an active layer 304, a cover source pattern layer 302, and a drain pattern layer formed over the substrate 301.
  • each layer in this embodiment is prepared by using the corresponding steps in the third embodiment of the method for preparing a thin film transistor, and details are not described herein again.
  • the present invention also provides a display comprising the thin film transistor of any of the above embodiments.
  • the present invention forms a source pattern layer and a drain pattern layer over the substrate, and a channel region is formed between the source pattern layer and the drain pattern layer; and the solution containing the silicon quantum dots is formed.
  • a method of forming an active layer in a channel region, using a solution spin coating method to prepare an active layer in a thin film transistor using a silicon quantum dot as a material the process is simple and the production cost is reduced, the preparation material of the thin film transistor is enriched, and silicon is improved.
  • the mobility of the base thin film transistor is advantageous for improving the electrical uniformity of the large-area silicon-based thin film transistor.

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  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管及其制备方法、显示器，该方法包括在基板（101）的上方形成源极图案层（104）及漏极图案层（105），且源极图案层及漏极图案层之间形成沟道区；通过含有硅量子点的溶液在沟道区中形成有源层（106）。通过使用溶液旋涂法以硅量子点为材料制备薄膜晶体管中的有源层，制程简单而降低了生产成本，丰富了薄膜晶体管的制备材料，提高硅基薄膜晶体管的迁移率，有利于提高大面积硅基薄膜晶体管的电性均一性。

Description

一种薄膜晶体管及其制备方法、显示器
【技术领域】
本发明涉及显示技术领域，特别是涉及一种薄膜晶体管及其制备方法、显示器。
【背景技术】
自从发现胶体量子点具有量子尺寸效应以来，其以薄膜的形式在电子和光电子领域得到了极大的应用。基于大小可调的能隙、小的激子结合能、高的电致和光致发光效率和廉价的溶液制程等优势，量子点已经成功的在太阳能电池、发光二极管等薄膜光电子器件方面实现了应用。然而，量子点在薄膜晶体管中的电荷传输性能和应用还鲜有报道，远远落后于商业硅晶体管和有机场效应晶体管。
半导体量子点胶体通过自组装紧密堆积实现量子限域电子或空穴波函数的有效交叠和重合，将会形成一种新型的“人造薄膜”，这种固体薄膜不仅保留了量子点材料性能独特的可调性，同时，也具有较高的载流子迁移率和电传导能力。与硅类晶体管相比，以量子点作为载流子传输层的晶体管具有溶液制程制备过程简单、成本较低、重量亲且柔性好等优点，尤其是硅量子点，硅量子点为在三个维度皆小于100nm、呈单一硅面的晶格分布的硅单晶，硅量子点结构中载流子(如电子、空穴和激子)强量子限制作用使得其电学和光学性质发生了很大的变化，可在微纳电子器件、光电子器件以及热电器件等方面得到广阔的应用。
【发明内容】
本发明主要提供一种薄膜晶体管及其制备方法、显示器，旨在解决如何使用硅量子点制备薄膜晶体管的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种薄膜晶体管的制备方法，所述方法包括：在基板上依次形成底栅图案层及覆盖所述底栅图案层的底栅绝缘层；在所述基板的上方形成源极图案层及漏极图案层，且所述源极图案层及所述漏极图案层之间形成沟道区；通过含有硅量子点的溶液在所述沟道区中形成有源层；其中，所述通过含有硅量子点的溶液在所述沟道区中形成有源层包括：使用旋涂法在所述沟道区中将所述含有硅量子点的溶液旋涂形成硅量子点膜层；低温真空蒸发所述硅量子点膜层以形成硅量子点有源层。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种薄膜晶体管，所述薄膜晶体管包括：位于基板的上方的源极图案层及漏极图案层，所述源极图案层及所述漏极图案层间隔设置且两者之间形成沟道区；位于所述沟道区中的有源层，所述有源层包括硅量子点。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种显示器，所述显示器包括上述的薄膜晶体管。
本发明的有益效果是：区别于现有技术的情况，本发明通过在基板的上方形成源极图案层及漏极图案层，且源极图案层及漏极图案层之间形成沟道区；通过含有硅量子点的溶液在沟道区中形成有源层的方法，使用硅量子点为材料制备薄膜晶体管中的有源层，丰富了薄膜晶体管的制备材料，提高硅基薄膜晶体管的迁移率，有利于提高大面积硅基薄膜晶体管的电性均一性。
【附图说明】
图1是本发明提供的薄膜晶体管的制备方法第一实施例的流程示意图；
图2是本发明提供的薄膜晶体管第一实施例的结构示意图；
图3是图1中步骤S13的具体流程示意图；
图4是本发明提供的薄膜晶体管的制备方法第二实施例的流程示意图；
图5是本发明提供的薄膜晶体管第二实施例的结构示意图；
图6是本发明提供的薄膜晶体管的制备方法第三实施例的流程示意图；
图7是本发明提供的薄膜晶体管第三实施例的结构示意图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种薄膜晶体管及其制备方法、显示器做进一步详细描述。
共同参阅图1和图2，本发明提供的一种薄膜晶体管的制备方法第一实施例包括：
S11：在基板101上依次形成底栅图案层102及覆盖底栅图案层102的底栅绝缘层103；
具体地，在将基板101清洗干净之后，可通过物理气相沉积法在基板101上溅射一层金属膜，然后通过光阻涂布、曝光、显影及剥离的光刻工艺形成底栅图案层102；进一步地可通过物理气相沉积法或等离子体气相沉积法在基板101上沉积一定厚度的绝缘材料层，以形成底栅绝缘层103。
可选的，基板101是包括但不限于的石英基板、玻璃基板或硅片基板；金属是包括但不限于铝、银、铜、ITO、金或钛的导电金属，绝缘材料是包括但不限于的氧化硅、氧化铝、氮化硅或离子凝胶的绝缘材料；底栅绝缘层103的厚度为200nm。
S12：在基板101的上方形成源极图案层104及漏极图案层105；
具体地，将完成上述步骤S11后的基板101用丙酮、甲醇和异丙醇的溶液浸泡冲洗，并在一定温度下烘烤之后置入蒸镀机中，进而通过热蒸镀法使用掩膜板在底栅绝缘层103上沉积金属材料层，以形成源极图案层104及漏极图案层105。
可选的，金属材料层的材料是包括但不限于铝、银、铜、ITO、金或钛的导电金属；形成的金属材料层的厚度为100nm。
其中，源极图案层104及漏极图案层105之间形成沟道区（图中未标示）。
S13：通过含有硅量子点的溶液在沟道区中形成有源层106；
其中，硅量子点可使用包括但不限于机械研磨法、液相合成法、电化学刻蚀法、单晶硅电解法、还原性气氛的高温气相还原法和热分解法等方法制备出不同粒径的硅量子点，在此，以机械研磨法为例进行说明：首先，进行前期制备：将大块硅片裁剪成截面尺寸为1.2cm ×1.2cm的小块硅片，然后使用浓硫酸和双氧水的混合溶液浸泡两小时，最后使用离子水冲洗之后将小块硅片置于乙醇中保存；然后，进行机械研磨：将保存的小块硅片在40％浓度的氢氟酸溶液中浸泡1分钟后用离子水冲洗三遍，然后在氩气手套箱中置入两块小块硅片于二氧化锆冲磨罐中并密封，将密封的二氧化锆冲磨罐置于高能纳米冲击磨摆臂中进行高能纳米冲磨机循环水的高速冲磨，在冲磨四小时之后将冲磨罐在氩气气氛的手套箱中打开，取出所得到硅粉体初步样品；最后，形成溶液：将形成的样品分散在正己烷中，然后用100nm过滤器过滤之后，即可得到一定浓度的硅量子点溶液。
可选的，该硅量子点溶液中硅量子点的浓度为2.5mg/ml。
参阅图3，该步骤S13可具体包括：
S131：使用旋涂法在沟道区中将含有硅量子点的溶液旋涂形成硅量子点膜层；
具体地，可在含高纯惰性气体的手套箱中，将含有硅量子点的溶液滴加至沟道区中，并使用旋涂法在一定时间内形成一定厚度的硅量子点膜层。
可选的，惰性气体为氮气，旋涂法的转数为3000rpm，旋涂时间为30s。
S132：低温真空蒸发硅量子点膜层以形成硅量子点有源层。
具体地，对硅量子点膜层进行真空烘烤，比如在在80℃的真空环境对硅量子点膜层进行烘烤，在大概12小时之后即可得到有源层106。
S14：在源极图案层104、漏极图案层105及有源层106的上方形成保护层107；
可选的，通过化学气相沉积法在底栅绝缘层103、源极图案层104、漏极图案层105及有源层106上沉积氧化硅，以形成覆盖源极图案层104、漏极图案层105及有源层106的保护层107。
S15：开设贯穿保护层107且连通源极图案层104或漏极图案层105的过孔1071；
具体地，通过光阻涂布、曝光、显影及剥离的光刻工艺在保护层107中蚀刻出与源极图案层104或漏极图案层105连通的过孔1071，本实施例图示中以过孔与漏极图案层105连通为例。
共同参阅图4及图5，本发明提供的薄膜晶体管的制备方法第二实施例中步骤S21、S22和S23与上述第一实施例中步骤S11、S12和S13相同，在此不再赘述，本实施例还包括：
S24：形成覆盖源极图案层204、漏极图案层205及有源层206的顶栅绝缘层208；
具体地，可通过物理气相沉积法或等离子体气相沉积法在底栅绝缘层203、源极图案层204、漏极图案层205及有源层206上沉积一定厚度的绝缘材料层以形成顶栅绝缘层208。
可选的，绝缘材料是包括但不限于的氧化硅、氧化铝、氮化硅或离子凝胶的绝缘材料，形成的顶栅绝缘层208的厚度为300nm。
S25：在顶栅绝缘层208上形成顶栅图案层209；
具体地，可通过物理气相沉积法在顶栅绝缘层208上溅射一层金属膜，然后经过曝光、显影、刻蚀和剥离的光刻工艺，以形成顶栅图案层209。
可选的，金属是包括但不限于铝、银、铜、ITO、金或钛的导电金属。
S26：在顶栅绝缘层208及顶栅图案层209上形成保护层207。
具体地，通过化学气相沉积法在顶栅绝缘层208上沉积氧化硅，以形成覆盖顶栅绝缘层208及顶栅图案层209的保护层207。
S27：开设贯穿保护层207及顶栅绝缘层208且连通源极图案层204或漏极图案层205的过孔2071。
具体地，通过光阻涂布、曝光、显影及剥离的光刻工艺在保护层207及顶栅绝缘层208中蚀刻出与源极图案层204或漏极图案层205连通的过孔2071。
共同参阅图6及图7，本发明提供的薄膜晶体管的制备方法第三实施例包括：
S31：在基板301的上方形成源极图案层302及漏极图案层303；
其中，本实施例中的源极图案层302与漏极图案层303形成于基板301上，形成方法可与上述第一实施例中步骤S12相同，在此不再赘述。
S32：通过含有硅量子点的溶液在沟道区（图中为标示）中形成有源层304；
该步骤S32与上述第一实施例中的步骤S13相同，在此不再赘述。
S33：形成覆盖源极图案层302、漏极图案层303及有源层304的顶栅绝缘层305；
具体地，可通过物理气相沉积法或等离子体气相沉积法在基板301上沉积一定厚度的绝缘材料层以形成顶栅绝缘层305；
可选的，绝缘材料是包括但不限于的氧化硅、氧化铝、氮化硅或离子凝胶的绝缘材料。
S34：在顶栅绝缘层305上形成顶栅图案层306；
具体地，可通过物理气相沉积法在顶栅绝缘层305上溅射一层金属膜，然后经过曝光、显影、刻蚀和剥离的光刻工艺，以形成顶栅图案层306。
可选的，金属是包括但不限于铝、银、铜、ITO、金或钛的导电金属。
S35：在顶栅绝缘层305及顶栅图案层306上形成保护层307；
可选的，通过化学气相沉积法在顶栅绝缘层305上沉积氧化硅，以形成覆盖顶栅绝缘层305及顶栅图案层306的保护层307。
S36：开设贯穿保护层307及顶栅绝缘层305且连通源极图案层302或漏极图案层303的过孔3071。
具体地，通过光阻涂布、曝光、显影及剥离的光刻工艺在保护层307及顶栅绝缘层305中蚀刻出与源极图案层302或漏极图案层303连通的过孔3071。
参阅图2，本发明提供的薄膜晶体管第一实施例包括在位于基板101上方的底栅图案层102、底栅绝缘层103、源极图案层104、漏极图案层105、有源层106及保护层107。
其中，底栅图案层102及底栅绝缘层103依次形成于基板101上且底栅绝缘层103覆盖底栅图案层102；源极图案层104和漏极图案层105形成于底栅绝缘层103上且之间形成有沟道区，有源层106位于沟道区中，且包括硅量子点；保护层107覆盖源极图案层104、漏极图案层105及有源层106，保护层107设有贯穿保护层107且连通源极图案层104或漏极图案层105的过孔1071。
本实施例中各层结构采用上述薄膜晶体管的制备方法第一实施例中相对应的步骤制备而成，在此不再赘述。
参阅图5，本发明提供的薄膜晶体管第二实施例进一步包括顶栅绝缘层208及顶栅图案层209，本实施例中其他结构与上述薄膜晶体管第一实施例相同，在此不再赘述。
其中，顶栅绝缘层208形成于底栅绝缘层203上且覆盖源极图案层204、漏极图案层205及有源层206，顶栅图案层209形成于顶栅绝缘层208上。
本实施例中各层结构采用上述薄膜晶体管的制备方法第二实施例中相对应的步骤制备而成，在此不再赘述。
参阅图7，本发明提供的薄膜晶体管第三实施例包括在基板301的上方形成的源极图案层302及漏极图案层303、有源层304、覆盖源极图案层302、漏极图案层303及有源层304的顶栅绝缘层305、形成于顶栅绝缘层305上的顶栅图案层、形成于源极图案层302、漏极图案层303及有源层304上方的保护层307。
本实施例中各层结构采用上述薄膜晶体管的制备方法第三实施例中相对应的步骤制备而成，在此不再赘述。
本发明还提供了一种显示器，该显示器包括上述任一实施例中的薄膜晶体管。
别于现有技术的情况，本发明通过在基板的上方形成源极图案层及漏极图案层，且源极图案层及漏极图案层之间形成沟道区；通过含有硅量子点的溶液在沟道区中形成有源层的方法，使用溶液旋涂法以硅量子点为材料制备薄膜晶体管中的有源层，制程简单而降低了生产成本，丰富了薄膜晶体管的制备材料，提高硅基薄膜晶体管的迁移率，有利于提高大面积硅基薄膜晶体管的电性均一性。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种薄膜晶体管的制备方法，其中，所述方法包括：
    在基板上依次形成底栅图案层及覆盖所述底栅图案层的底栅绝缘层；
    在所述基板的上方形成源极图案层及漏极图案层，且所述源极图案层及所述漏极图案层之间形成沟道区；
    通过含有硅量子点的溶液在所述沟道区中形成有源层；
    其中，所述通过含有硅量子点的溶液在所述沟道区中形成有源层包括：
    使用旋涂法在所述沟道区中将所述含有硅量子点的溶液旋涂形成硅量子点膜层；
    低温真空蒸发所述硅量子点膜层以形成硅量子点有源层。
  2. 根据权利要求1所述的方法，其中，所述方法进一步包括：
    形成覆盖所述源极图案层、所述漏极图案层及所述有源层的顶栅绝缘层；
    在所述顶栅绝缘层上形成顶栅图案层。
  3. 根据权利要求2所述的方法，其中，所述方法还包括：
    在所述源极图案层、所述漏极图案层及所述有源层的上方形成保护层；
    开设贯穿所述保护层且连通所述源极图案层或所述漏极图案层的过孔。
  4. 根据权利要求1所述的方法，其中，所述在基板上依次形成底栅图案层及覆盖所述底栅图案层的底栅绝缘层包括：
    通过物理气相沉积法在所述基板上溅射一层金属膜，并通过光刻工艺以形成所述底栅图案层；
    通过等离子体气相沉积法在所述基板上沉积绝缘材料层以形成所述底栅绝缘层。
  5. 根据权利要求3所述的方法，其中，所述在所述源极图案层、所述漏极图案层及所述有源层的上方形成保护层包括：
    通过化学气相沉积法在所述底栅绝缘层、所述源极图案层、所述漏极图案层及所述有源层上沉积氧化硅，以形成所述保护层。
  6. 根据权利要求3所述的方法，其中，所述在所述源极图案层、所述漏极图案层及所述有源层的上方形成保护层包括：
    通过化学气相沉积法在所述顶栅绝缘层上沉积氧化硅，以形成覆盖所述顶栅绝缘层及所述顶栅图案层的保护层。
  7. 根据权利要求6所述的方法，其中，所述开设贯穿所述保护层且连通所述源极图案层或所述漏极图案层的过孔包括：
    通过光刻工艺在所述保护层及所述顶栅绝缘层中蚀刻出与所述源极图案层或所述漏极图案层连通的所述过孔。
  8. 根据权利要求1所述的方法，其中，所述含有硅量子点的溶液中的硅量子点的浓度为2.5mg/ml。
  9. 根据权利要求1所述的方法，其中，所述旋涂法的转数为3000rpm，旋涂时间为30s。
  10. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    位于基板的上方的源极图案层及漏极图案层，所述源极图案层及所述漏极图案层间隔设置且两者之间形成沟道区；
    位于所述沟道区中的有源层，所述有源层包括硅量子点。
  11. 根据权利要求10所述的薄膜晶体管，其中，所述薄膜晶体管进一步包括在所述基板上依次形成的底栅图案层及覆盖所述底栅图案层的底栅绝缘层，所述源极图案层及所述漏极图案层形成于所述底栅绝缘层上。
  12. 根据权利要求10所述的薄膜晶体管，其中，所述薄膜晶体管进一步包括在顶栅绝缘层及顶栅图案层，所述顶栅绝缘层覆盖所述源极图案层、所述漏极图案层及所述有源层，所述顶栅图案层形成于所述顶栅绝缘层上。
  13. 根据权利要求12所述的薄膜晶体管，其中，所述薄膜晶体管进一步包括保护层，所述保护层形成于所述源极图案层、所述漏极图案层及所述有源层的上方，所述保护层设有贯穿所述保护层且连通所述源极图案层或所述漏极图案层的过孔。
  14. 一种显示器，其中，所述显示器包括权利要求10所述的薄膜晶体管。
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