WO2019004991A1 - Assemblages de calculateurs quantiques - Google Patents

Assemblages de calculateurs quantiques Download PDF

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Publication number
WO2019004991A1
WO2019004991A1 PCT/US2017/039167 US2017039167W WO2019004991A1 WO 2019004991 A1 WO2019004991 A1 WO 2019004991A1 US 2017039167 W US2017039167 W US 2017039167W WO 2019004991 A1 WO2019004991 A1 WO 2019004991A1
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WO
WIPO (PCT)
Prior art keywords
die
package substrate
quantum
face
assembly
Prior art date
Application number
PCT/US2017/039167
Other languages
English (en)
Inventor
Adel A. ELSHERBINI
James S. Clarke
Johanna M. Swan
Shawna M. LIFF
Javier A. FALCON
Ye Seul Nam
Jeanette M. Roberts
Roman CAUDILLO
Original Assignee
Intel Corporation
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Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/039167 priority Critical patent/WO2019004991A1/fr
Publication of WO2019004991A1 publication Critical patent/WO2019004991A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates

Definitions

  • Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.
  • FIGS. 1-7, 8A-8B, and 9-10 are side cross-sectional views of example quantum computing (QC) assemblies, in accordance with various embodiments.
  • FIGS. 11-14 are perspective views of conductive structures that may be included in a QC assembly, in accordance with various embodiments.
  • FIG. 15 is a block diagram of an example superconducting qubit-type quantum device, in accordance with various embodiments.
  • FIGS. 16 and 17 illustrate example physical layouts of superconducting qubit-type quantum devices, in accordance with various embodiments.
  • FIGS. 18A-C are cross-sectional views of a spin qubit-type quantum device, in accordance with various embodiments.
  • FIGS. 19A-C are cross-sectional views of various examples of quantum well stacks that may be used in a spin qubit-type quantum device, in accordance with various embodiments.
  • FIG. 20 is a top view of a wafer and dies that may be included in any of the QC assemblies disclosed herein.
  • FIG. 21 is a block diagram of an example quantum computing device that may include any of the QC assemblies disclosed herein, in accordance with various embodiments.
  • a QC assembly may include a package substrate having a first face and an opposing second face, a quantum processing die coupled to the first face of the package substrate, and a control die coupled to the second face of the package substrate.
  • the package substrate may include conductive structures electrically coupling the quantum processing die to the control die.
  • interconnect techniques and arrangements such as those in which the die and its control circuitry are side-by-side on a face of a standard printed circuit board (PCB) or an interposer, may be limited in the density of interconnects that can be achieved per layer of metal, and thus may require tens, hundreds, or thousands of layers. Further, as the diameter of interconnects shrink, their resistance increases, causing signal problems. Increased resistance may also cause heat generation that is beyond the dissipation capacity of the refrigeration systems used to keep the quantum processing dies at cryogenic temperatures during operation.
  • QC assemblies in which quantum processing dies are connected to control circuitry with high density, "vertical" interconnects.
  • Various ones of the embodiments disclosed herein may achieve a higher interconnect density than previously achieved, with increased manufacturing tolerance, and/or without excessive heat generation.
  • the phrase "A and/or B” means (A), (B), or (A and B).
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.
  • FIGS. 18A-C may be referred to as "FIG. 18"
  • the collection of drawings of FIGS. 19A-C may be referred to as "FIG. 19.”
  • a "magnet line” refers to a magnetic field-generating structure to influence (e.g., change, reset, scramble, or set) the spin states of quantum dots.
  • a magnet line is a conductive structure that is proximate to an area of quantum dot formation and selectively conductive of a current pulse that generates a magnetic field to influence a spin state of a quantum dot in the area.
  • FIGS. 1-10 are side cross-sectional views of example QC assemblies 100, in accordance with various embodiments. Examples of different ones of the elements included in a QC assembly 100 may be discussed with reference to a particular figure, but this is simply for ease of illustration, and any of the examples of a particular element disclosed herein may be used in any of the
  • FIG. 1 illustrates a QC assembly including a package substrate 102 having a first face 126, and a second opposing face 128.
  • a quantum processing (QP) die 104 may be mechanically and electrically coupled to the first face 126, and a control die 103 may be mechanically and electrically coupled to the second face 128.
  • QP quantum processing
  • the package substrate 102 may include conductive contacts (not shown) at the first face 126 that may be coupled to corresponding conductive contacts (not shown) on the QP die 104 by a set of interconnects 132; similarly, the package substrate 102 may include conductive contacts (not shown) at the second face 128 that may be coupled to corresponding conductive contacts (not shown) of the control die 103 by another set of
  • the conductive contacts disclosed herein may be formed of any suitable conductive material (e.g., a superconducting material), and may take any suitable form, such as solder bond pads, posts, or bumps.
  • the conductive contacts may include multiple layers of material that may be selected to serve different purposes.
  • the conductive contacts may be formed of aluminum, and may include a layer of gold (e.g., with a thickness of less than 1 micron) between the aluminum and the adjacent interconnect to limit the oxidation of the surface of the contacts and improve the adhesion and wetting with adjacent solder.
  • Alternate materials for the surface finish include palladium, platinum, silver, and tin.
  • the conductive contacts may be formed of aluminum, and may include a layer of a barrier metal such as nickel, as well as a layer of gold, or other appropriate material, wherein the layer of barrier metal is disposed between the aluminum and the layer of gold, and the layer of gold is disposed between the barrier metal and the adjacent interconnect.
  • the gold, or other surface finish may protect the barrier metal surface from oxidation before assembly, and the barrier metal may limit the diffusion of solder from the adjacent interconnects into the aluminum. Any suitable technique may be used to form the interconnects 132, such as thermal compression bonding or through the use of a mechanical fixture.
  • the package substrate 102 may include conductive structures 107 to electrically couple the control die 103 to the QP die 104.
  • the conductive structures 107 are drawn only partially to indicate that their arrangement within the package substrate 102 may vary.
  • the conductive structures 107 may include one or more conductive vias, one or more conductive lines, or a combination of conductive vias and conductive lines, for example. Any of the conductive vias discussed herein may be formed using any suitable technique, such as lithographic patterning, laser drilling, or mechanical drilling.
  • the conductive structures 107 may include a superconducting material, such as aluminum, niobium, tin, titanium, osmium, zinc, molybdenum, tantalum, vanadium, or composites of such materials (e.g., niobium titanium, niobium aluminum, titanium nitride, or niobium tin).
  • the conductive structures 107 may include non-superconducting materials, such as copper.
  • the package substrate 102 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide.
  • the package substrate 102 may be formed of alternate rigid or flexible materials that may include silicon, germanium, and other group lll-V and group IV materials.
  • the conductive structures 107 in the package substrate 102 may include through-silicon vias (TSVs).
  • TSVs through-silicon vias
  • Other dielectric materials that may be included in a package substrate 102 may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride.
  • the package substrate 102 may be a flexible circuit board.
  • the package substrate 102 may include wires (e.g., braided wires) arranged in a desired pattern to provide the conductive structures 107, then embedded in epoxy.
  • the package substrate 102 may be a PCB including multiple layers of metal traces (oriented in planes parallel to the x-z plane in FIG. 1) separated from one another by layers of dielectric material.
  • the PCB of the package substrate 102 may be used at an orientation that is rotated by 90 degrees from the traditional orientation of a PCB (in which the traces are oriented in planes parallel to the x-y plane in FIG. 1).
  • PCB techniques may be used to form traces in multiple metal layers such that at least some of the traces are exposed at opposing side faces of the PCB.
  • the PCB may be "rotated" so that one of the side faces provides the first face 126 and the other of the side faces provides the second face 128; the QP die 104 may then be soldered or otherwise coupled to the first face 126, and the control die 103 may then be soldered or otherwise coupled to the second face 128.
  • the traces that provide the conductive structures 107 in the package substrate 102 may have a diameter between 10 microns and 200 microns (e.g., between 50 microns and 80 microns), and the pitch may be twice the diameter.
  • the package substrate 102 may include embedded devices (not shown), such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and/or memory devices.
  • the package substrate 102 may not include any active or passive embedded devices, and may only provide conductive pathways between the first face 126 and the second face 128.
  • the interconnects 132 may take any suitable form, such as solder balls (as shown in FIG. 1), male and female portions of a socket, a conductive adhesive, and/or any other suitable electrical coupling structure.
  • the interconnects 132 may include flip chip (or controlled collapse chip connection, (C4)) solder bumps disposed initially on the QP die 104 or on the package substrate 102.
  • the interconnects 132 may include an indium-based solder (e.g., a solder including indium or an indium alloy). Indium-based solders may be advantageous for quantum computing applications because they are superconducting and ductile at cryogenic temperatures.
  • the dimensions of the individual interconnects 132 in each QC assembly 100 may be selected as appropriate. For example, when a signal pathway through an interconnect 132 is to be used for critical signals requiring lower loss lines, a larger interconnect 132 may be used; smaller interconnects 132 may be used for other signal pathways to increase or maximize the routing density.
  • the conductive adhesive may be an anisotropic conductive film (ACF).
  • An ACF may include particles of conductive material suspended in an insulating material; when the ACF is compressed at one location, enough of the conductive particles may be brought into contact to form a conductive bridge through the ACF at that location.
  • the conductive contacts on either side of the ACF e.g., the package substrate 102 and a control die 103/QP die 104) may include protrusions or other features that compress the ACF to provide an electrical pathway.
  • the conductive adhesive may include conductive particles (e.g., silver) suspended in a compliant silicone or polymer matrix.
  • Compliant interconnects 132 e.g., those that deform under mechanical stress
  • a set of interconnects 132 may permit ready decoupling of the connected structures.
  • the interconnects 132 between the QP die 104 and the package substrate 102 include an ACF
  • the QP die 104 may be mechanically detached from the ACF, leaving the ACF on the package substrate 102.
  • the ACF remaining on the package substrate 102 may be cleaned, and another QP die 104 (or another component) may be brought into contact with the ACF.
  • the interconnects 132 may include a set of male/female sockets or other connectors that permit detachment and reattachment.
  • the interconnects 132 may be less readily decoupled (e.g., when the interconnects 132 include solder), or when the interconnects 132 are surrounded by an underfill or encapsulant material (not shown).
  • the interconnects 132 between the package substrate 102 and the QP die 104 need not take the same form as the interconnects 132 between the package substrate 102 and the control die 103.
  • the interconnects 132 between the package substrate 102 and the QP die 104 may include an ACF, and the interconnects 132 between the package substrate 102 and the control die 103 may include solder balls.
  • any different sets of interconnects 132 in any QC assembly 100 disclosed herein may take the same form, or may take different forms.
  • the control die 103 may include one or more non-quantum circuits for controlling the operation of the QP die 104.
  • the control die 103 may provide peripheral logic to support the operation of the QP die 104.
  • the control die 103 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc.
  • the control that the control die 103 may exercise over the operation of the QP die 104 may depend on the type of qubits implemented by the QP die 104. For example, if the QP die 104 implements superconducting qubits (discussed below with reference to FIGS. 15-17), the control die 103 may provide and/or detect appropriate currents in any of the flux bias lines, microwave lines, and/or drive lines to initialize and manipulate the superconducting dots.
  • the control die 103 may also perform conventional computing functions to supplement the computing functions that may be provided by the QP die 104.
  • the control die 103 may interface with one or more of the other components of a quantum computing device, such as the quantum computing device discussed below with reference to FIG. 21, in a conventional manner, and may serve as an interface between the QP die 104 and conventional components.
  • the control die 103 may be implemented in or may be used to implement the non- quantum processing device 2028 described below with reference to FIG. 21.
  • control die 103 may include radio frequency (F) devices, amplifiers, power management devices, antennas, arrays, sensors, microelectromechanical systems (MEMS) devices, mixers, multiplexers, analog-to-digital converters, digital-to-analog converters, and/or analog-to-digital converters, for example.
  • F radio frequency
  • MEMS microelectromechanical systems
  • mixers multiplexers
  • analog-to-digital converters digital-to-analog converters
  • analog-to-digital converters for example.
  • the control die 103 may generate more heat during operation than the QP die 104.
  • the QP die 104 may include circuitry for performing quantum computations.
  • the QP die 104 may be a superconducting qubit-type quantum device (examples of which are discussed in further detail below with reference to FIGS. 15-17) or a spin qubit-type quantum device (examples of which are discussed in further detail below with reference to FIGS. 18-19).
  • Limiting differential expansion and contraction may help preserve the mechanical and electrical integrity of the QC assembly 100 as the QC assembly 100 is fabricated (and exposed to higher temperatures) and used in a cooled environment (and exposed to lower, cryogenic temperatures).
  • thermal expansion and contraction in the package substrate 102, the control die 103, and/or the QP die 104 may be managed by maintaining an approximately uniform density of the conductive material in these elements (so that different portions of these elements expand and contract uniformly), using reinforced dielectric materials as the insulating material (e.g., dielectric materials with silicon dioxide fillers), or utilizing stiffer materials as the insulating material (e.g., a prepreg material including glass cloth fibers).
  • reinforced dielectric materials e.g., dielectric materials with silicon dioxide fillers
  • stiffer materials as the insulating material
  • the elements of the QC assembly 100 may have any suitable dimensions.
  • the package substrate 102, the control die 103, and the QP die 104 may have x- y footprints with side dimensions between 2 millimeters and 100 millimeters.
  • a thickness of the control die 103 and/or the QP die 104 may be between 50 microns and 700 microns (e.g., between 100 microns and 200 microns).
  • the height 133 of the package substrate 102 may be selected to allow the QC assembly 100 to be inserted into a dilution refrigerator or other cryogenic refrigeration system so that the QP die 104 is in a lower, colder stage of the refrigerator (e.g., on the order of 10 milliKelvin) while the control die 103 is in a higher, warmer stage of the refrigerator (e.g., on the order of 4 Kelvin).
  • lower (colder) stages have less heat dissipation capacity (e.g., on the order of 10 milliwatt to 1 microwatt) than higher (warmer) stages (e.g., on the order of 1 W).
  • the control die 103 may generate more heat than the QP die 104, and the control die 103 may not require the low temperatures of the lower stage, it may be desirable to select the height 133 of the package substrate 102 to allow the QP die 104 to be positioned in a colder stage than the control die 103.
  • the height 133 of the package substrate 102 may be between 10 centimeters and 1 meter). More generally, the height 133 of the package substrate 102 may be between 2 millimeters and 1 meter.
  • the conductive structures 107 included in a package substrate 102 may have any desired pattern.
  • the package substrate 102 may include linear pathways between the first face 126 and the second face 128.
  • FIG. 2 illustrates an example of such a QC assembly 100 including a plurality of parallel, linear conductive structures 107 extending between the first face 126 and the second face 128.
  • the conductive structures 107 may take any suitable form, such as any of the forms discussed above.
  • Any of the package substrates 102 disclosed herein may include conductive structures 107 that extend linearly between the first face 126 and the second face 128, as illustrated in FIG. 2. Such linear pathways may advantageously exhibit reduced cross-talk relative to pathways that include angles.
  • the diameter of the linear conductive structures 107 may be between 40 microns and 200 microns (e.g., between 40 microns and 200 microns, or approximately 50 microns).
  • the linear conductive structures 107 may be spaced at a pitch of 50 microns, and may have a diameter up to 40 microns.
  • the conductive structures 107 included in a package substrate 102 may include linear pathways between the first face 126 and the second face 128 (formed, e.g., by vias or other structures), and the pitch of these linear pathways may be greater than the pitch of the conductive contacts at the first face 126 and the second face 128 such that multiple linear pathways contact each conductive contact at the first face 126 and the second face 128.
  • Such approaches may be more tolerant of misalignment of the conductive contacts during manufacturing (since there are multiple linear pathways that contact any particular conductive contact).
  • any of the package substrates 102 disclosed herein may include conductive structures 107 that have any suitable arrangement or routing between the first face 126 and the second face 128.
  • a package substrate 102 may be provided by multiple package sub- substrates.
  • FIG. 3 illustrates a QC assembly 100 in which the package substrate 102 includes five package sub-substrates 102A-102E arranged in a stack between the control die 103 and the QP die 104.
  • the "bottommost" package sub-substrate 102E may be coupled to the control die 103 through a set of interconnects 132
  • the "topmost" package sub-substrate 102A may be coupled to the QP die 104 through a set of interconnects 132
  • the package sub-substrates 102A-102E may be coupled to each other via sets of interconnects 132, as shown.
  • the package sub-substrates 102A-102E may include conductive structures 107 arranged in any desired manner (e.g., the linear pathways illustrated in FIG. 3) to route electrical signals between the control die 103 and the QP die 104, as discussed above.
  • the package sub-substrates 102A-102E may be formed in accordance with any of the embodiments of the package substrates 102 discussed above (e.g., as a PCB, with wires embedded in an epoxy, etc.). Additionally, although a particular number of package sub-substrates are depicted in FIG. 3, this is simply for illustrative purposes, and a package substrate 102 may be provided by any suitable number of package sub-substrates.
  • any of the embodiments of the QC assemblies 100 disclosed herein may include a package substrate 102 that includes multiple package sub-substrates (e.g., the embodiments discussed below with reference to FIGS. 5-10).
  • Multiple package sub-substrates when used with a compliant interconnect 132 (e.g., a soft solder), may help with mechanical reliability of the package substrate 102 during thermal changes (e.g., cooling) since the sub-substrates can move relative to each other.
  • some or all of the package sub-substrates may be formed of a compliant material (e.g., a compliant dielectric) to provide mechanical stress relief (at the potential cost of reduced electrical performance).
  • the package sub-substrates may all take the same form. An example of this is illustrated in FIG. 3, in which all the package sub-substrates 102A-102E have the same pattern of conductive structures 107 therein, among other commonalities.
  • a package substrate 102 includes multiple package sub-substrates, one or more of the package sub- substrates may have a different structure than others of the package sub-substrates. For example, FIG. 3
  • FIG. 4 illustrates a QC assembly 100 in which the "topmost" package sub-substrate 102A has a fan- out arrangement of conductive structures 107 in which the pitch of the conductive structures 107 is increased between the face of the package sub-substrate 102A closest to the QP die 104 and the face of the package sub-substrate 102A farthest from the QP die 104 (and closest to the package sub-substrate 102B).
  • the "bottommost" package sub-substrate 102E has a fan-out arrangement of conductive structures 107 in which the pitch of the conductive structures 107 is increased between the face of the package sub-substrate 102E closest to the control die 103 and the face of the package sub-substrate 102E farthest from the control die 103 (and closest to the package sub-substrate 102D). Fanning out a small pitch to a larger pitch may be desirable to simplify assembly, account for misalignments and manufacturing tolerances, improve interconnect reliability, improve the overall structural rigidity, and/or reduce losses by increasing the diameter of conductive pathways.
  • the package sub-substrates 102B, 102C, and 102D all have the same structure (e.g., with linear conductive structures 107 connecting opposite faces).
  • the QC assembly 100 of FIG. 4 is simply illustrative of embodiments in which different ones of the package sub-substrates have different structures, and any other suitable variation may be implemented.
  • the package sub-substrates maybe all be the same size or may have different sizes depending on the electrical or mechanical design criteria.
  • multiple QP dies 104 may be coupled to the first face 126 of the package substrate 102, and/or multiple control dies 103 may be coupled to the second face 128 of the package substrate 102.
  • FIG. 5 illustrates an embodiment in which two control dies
  • FIG. 6 illustrates an embodiment in which two QP dies, 104-1 and
  • QC assemblies 100 are coupled to the first face 126 of the package substrate 102 (with a single control die 103 at the second face 128).
  • QC assemblies 100 may also include multiple QP dies 104 and multiple control dies 103, as desired.
  • the package substrate 102 of FIG. 5 may include conductive structures 107 between the control dies 103-1 and 103-2, while in other embodiments, the package substrate 102 may not include conductive structures 107 between the control dies 103- 1 and 103-2.
  • the control dies 103-1 and 103-2 may not be in direct communication with each other, or may be in communication via another circuit component (e.g., the circuit components 105 discussed below).
  • the package substrate 102 of FIG. 6 may include conductive structures 107 between the QP dies 104-1 and 104-2, while in other embodiments, the package substrate 102 may not include conductive structures 107 between the QP dies 104-1 and 104-2.
  • Any of the embodiments of the QC assemblies 100 disclosed herein may include more than one QP die 104 and/or more than one control die 103.
  • the control die 103 may be electrically coupled to one or more additional components. These additional components may provide signals to and/or receive signals from the control die 103, may provide signals to and/or receive signals from the QP die 104 through the control die 103, or a combination thereof.
  • FIG. 7 illustrates an embodiment in which the control die 103 is coupled to a circuit component.
  • the control die 103 is a "two-sided die" (having conductive contacts at two opposing faces), with one face in conductive contact with the package substrate 102, and the opposite face in conductive contact with the circuit component 105.
  • the interconnects 132 that couple the control die 103 to the circuit component 105 may take the form of any of the interconnects 132 disclosed herein (e.g., a detachable coupling, solder, etc.).
  • the circuit component 105 may be a circuit board (e.g., a PCB). In some embodiments, the circuit component 105 may be an additional substrate, and may take the form of any of the package substrates 102 disclosed herein. In some embodiments, the circuit component 105 may be a flexible circuit board or flexible connector (e.g., with electrical traces in or on a compliant insulating material). In some embodiments, the circuit component 105 may be a connector for a cable (not shown) that can extend outside the refrigerator during operation of the QC assembly 100. Electrical signals may be provided to and/or received from the control die 103 by the circuit component 105. In some embodiments, electrical signals may be provided to and/or received from the QP die 104 by the circuit component 105 through conductive structures 107 that extend directly through the control die 103 to the package substrate 102 (examples of which are illustrated in FIG. 7).
  • circuit component 105 may also be coupled to a circuit component 105, and thus may be in
  • FIG. 8A illustrates a QC assembly 100 that includes an auxiliary die 111 coupled to the circuit component 105 through a set of interconnects 132.
  • the circuit component 105 may include conductive structures 107 to conductively couple the auxiliary die 111 to the control die 103, as desired.
  • the auxiliary die 111 may include any of the components discussed above with reference to the control die 103.
  • the auxiliary die 111 and the control die 103 together may provide control and support functions during the operation of the QP die 104.
  • FIG. 8B illustrates a QC assembly 100 that includes an auxiliary die 111 and a package substrate 102 coupled to a first face 137 of a circuit component 105, and a control die 103 coupled to a second face 139 of the circuit component 105.
  • the circuit component 105 may include conductive structures 107 (e.g., through-silicon vias) that conductively couple the control die 103 to the package substrate 102, and conductive structures 107 that conductively couple the auxiliary die 111 to the control die 103.
  • a QC assembly 100 may include multiple package substrates 102.
  • FIG. 9 illustrates a QC assembly 100 in which a package substrate 102-1 is coupled between a QP die 104 and a control die 103-1 (with sets of interconnects 132), and another package substrate 102-2 is coupled between the control die 103-1 and another control die 103-2 (with sets of interconnects 132).
  • the control die 103-2 is coupled to a circuit component 105, to which an auxiliary die 111 is also coupled.
  • the control dies 103-1 and 103-2 may include any of the components discussed above with reference to the control die 103.
  • the auxiliary die 111 and the control dies 103-1 and 103-2 together may provide control and support functions during the operation of the QP die 104.
  • FIG. 6 illustrates one example of a QC assembly 100 that includes multiple QP dies 104
  • FIG. 10 illustrates another example of a QC assembly 100 that includes multiple QP dies 104.
  • control dies 103-1 and 103-2 are coupled to the circuit component 105 (along with an auxiliary die 111).
  • a package substrate 102-1 is coupled to the control die 103-1, and a QP die 104-1 is coupled to the package substrate 102-1; similarly, a package substrate 102-2 is coupled to the control die 103-2, and a QP die 104-2 is coupled to the package substrate 102-2.
  • the circuit component 105 may include conductive structures 107 between the auxiliary die 111 and the control die 103-1, as well as between the auxiliary die 111 and the control die 103-2.
  • the QP die 104-1/package substrate 102-1/control die 103-1 may operate independently or in conjunction with the QP die 104-2/package substrate 102-2/control die 103-2. Any combination of auxiliary dies 111, package substrates 102, QP dies 104, and control dies 103 may be included in a QC assembly 100, in accordance with the present disclosure.
  • the package substrates 102 may include conductive structures 107 that have any suitable structure.
  • the conductive structures 107 may include signal pathways and shield structures that shield the signal pathways.
  • the shield structures may be coupled to ground or another suitable reference.
  • FIGS. 11-14 are perspective views of conductive structures 107 that may be included in a QC assembly 100 (e.g., in a package substrate 102), in accordance with various embodiments.
  • the conductive structures 107 of FIGS. 11-14 each include at least one signal pathway 107-1; in some embodiments, the diameter of the signal pathway 107-1 may between 20 microns and 200 microns (e.g., 40 microns).
  • the conductive structures 107 of FIGS. 11-14 each include a shield structure 107-2; in the QC assembly 100, during operation, the shield structures 107-2 may be coupled to ground or another suitable reference.
  • FIG. 11 illustrates a conductive structure 107 having a signal pathway 107-1 surrounded by a shield structure 107-2.
  • the shield structure 107-2 may take the form of a cage.
  • the shield structure 107-2 of FIG. 11 may include rectangular frame portions (formed in different layers of a multilayer package substrate 102) coupled together by intervening conductive vias.
  • the signal pathway 107-1 may also include a conductive via, with sphere- or disc-shaped solder at either end. Any of the conductive vias discussed herein may be created by laser-drilling (e.g., to form cylindrical vias in organic substrates) or by lithography (e.g., to form shapes other than cylinders).
  • FIG. 12 illustrates a conductive structure 107 having a signal pathway 107-1 surrounded by a shield structure 107-2.
  • the shield structure 107-2 may take the form of a wall.
  • the shield structure 107-2 of FIG. 12 may include a substantially solid rectangular wall around the signal pathway 107-1.
  • the rectangular wall may, in some embodiments, be formed using lithographically defined vias (e.g., using a photo-definable dielectric, or an etched dielectric).
  • the signal pathway 107-1 may also include a conductive via, with shaped solder at either end.
  • FIG. 13 illustrates a conductive structure 107 having a signal pathway 107-1 surrounded by a shield structure 107-2.
  • the shield structure 107-2 may take the form of multiple conductive vias (with shaped solder at either end) arranged around a signal pathway 107-1 (also taking the form of a conductive via with shaped solder).
  • a rectangular frame (formed, for example, in a single metal layer of a multilayer package substrate 102) may couple the different conductive vias of the shield structures 107-2.
  • FIG. 14 illustrates a conductive structure 107 having a signal pathway 107-1 surrounded by a shield structure 107-2.
  • the shield structure 107-2 may take the form of a regular lattice; the signal pathways 107-1 may take the form of conductive vias extending through openings in the lattice.
  • the conductive structure 107 of FIG. 14 may be formed using any suitable technique, such as stereolithography.
  • the embodiments of FIGS. 11-14 may be operated as coaxial cables, which may be particularly advantageous when the QP die 104 is a superconducting qubit-type quantum device. In some variants of the conductive structures 107 of FIGS.
  • multiple signal pathways 107-1 may share the interior of a shield structure 107-2 (e.g., multiple signal pathways 107-1 may extend through the "cage" of the shield structure 107-2 of FIG. 11) to provide a twinaxial or multiaxial cable, as desired.
  • the conductive structures 107 may provide strong isolation and good signal fidelity during operation of the QC assembly 100. Any suitable techniques may be used to form the conductive structures 107 disclosed herein, such as stereolithography (discussed above), electroplating, embedding wires in epoxy, PCB techniques (e.g., including turning a PCB "on its side” to create vertical conductive pathways from previously horizontal traces), etc.
  • the QP die(s) 104 included in a QC assembly 100 may take any form.
  • FIGS. 15-17 discuss example embodiments in which the QP die 104 is a superconducting qubit-type quantum device
  • FIGS. 18-19 discuss example embodiments in which the QP die 104 is a spin qubit-type quantum device.
  • superconducting qubit-type quantum devices may be based on the Josephson effect, a macroscopic quantum phenomenon in which a supercurrent (a current that, due to zero electrical resistance, flows for indefinitely long without any voltage applied) flows across a device known as a Josephson junction.
  • superconducting qubit-type quantum devices may include charge qubits, flux qubits, and phase qubits.
  • Transmons a type of charge qubit with the name being an abbreviation of "transmission line shunted plasma oscillation qubits," may exhibit reduced sensitivity to charge noise, and thus may be particularly advantageous.
  • Transmon-type quantum devices may include inductors, capacitors, and at least one nonlinear element (e.g., a Josephson junction) to achieve an effective two-level quantum state system.
  • Josephson junctions may provide the central circuit elements of a superconducting qubit- type quantum device.
  • a Josephson junction may include two superconductors connected by a weak link.
  • a Josephson junction may be implemented as a thin layer of an insulating material, referred to as a barrier or a tunnel barrier and serving as the "weak link" of the junction, sandwiched between two layers of superconductor.
  • Josephson junctions may act as
  • Josephson junctions may similarly provide the non-linearity necessary for forming an effective two-level quantum state to act as a qubit.
  • FIG. 15 is a block diagram of an example superconducting quantum circuit 300 that may be included in a QP die 104.
  • a superconducting quantum circuit 300 includes two or more qubits, 302-1 and 302-2.
  • Qubits 302-1 and 302-2 may be identical and thus the discussion of FIG. 15 may refer generally to the "qubits 302"; the same applies to Josephson junctions 304-1 and 304-2, which may generally be referred to as "Josephson junctions 304,” and to circuit elements 306-1 and 306-2, which may generally be referred to as "circuit elements 306.”
  • FIG. 15 is a block diagram of an example superconducting quantum circuit 300 that may be included in a QP die 104.
  • a superconducting quantum circuit 300 includes two or more qubits, 302-1 and 302-2.
  • Qubits 302-1 and 302-2 may be identical and thus the discussion of FIG. 15 may refer generally to the "qubits 302"; the same applies to Josephson junctions
  • each of the superconducting qubits 302 may include one or more Josephson junctions 304 connected to one or more other circuit elements 306, which, in combination with the Josephson junction(s) 304, may form a nonlinear circuit providing a unique two-level quantum state for the qubit.
  • the circuit elements 306 could be, for example, capacitors in transmons or superconducting loops in flux qubits.
  • a superconducting quantum circuit 300 may include circuitry 308 for providing external control of qubits 302 and circuitry 310 for providing internal control of qubits 302.
  • external control refers to controlling the qubits 302 from outside of the QP die 104 that includes the qubits 302, including control by a user of a quantum computer
  • internal control refers to controlling the qubits 302 within QP die 104.
  • qubits 302 are transmon qubits
  • external control may be implemented by means of flux bias lines (also known as “flux lines” and “flux coil lines”) and by means of readout and drive lines (also known as "microwave lines” since qubits are typically designed to operate with microwave signals), described in greater detail below.
  • flux bias lines also known as “flux lines” and “flux coil lines”
  • readout and drive lines also known as “microwave lines” since qubits are typically designed to operate with microwave signals
  • internal control lines for such qubits may be implemented by means of resonators (e.g., coupling and readout resonators, also described in greater detail below).
  • FIG. 16 illustrates an example of a physical layout 311 of a superconducting quantum circuit where qubits are implemented as transmons. Similarly to FIG. 15, FIG. 16 illustrates two qubits 302. In addition, FIG. 16 illustrates flux bias lines 312, microwave lines 314, a coupling resonator 316, a readout resonator 318, and conductive contacts 320 and 322. The flux bias lines 312 and the microwave lines 314 may be viewed as examples of the external control circuitry 308 shown in FIG. 15.
  • Running a current through the flux bias lines 312, provided from the conductive contacts 320, enables the tuning of the frequency of the corresponding qubits 302 to which each line 312 is connected. For example, a magnetic field is created by running the current in a particular flux bias line 312. If such a magnetic field is in sufficient proximity to the qubit 302, the magnetic field couples to the qubit 302, thereby changing the spacing between the energy levels of the qubit 302. This, in turn, changes the frequency of the qubit 302 since the frequency is related to the spacing between the energy levels via Planck's equation. Provided there is sufficient multiplexing, different currents can be sent down each of the flux lines 312, allowing for independent tuning of the various qubits 302.
  • the qubit frequency may be controlled to bring the frequency either closer to or further away from another resonant element, such as a coupling resonator 316 as shown in FIG. 16 that connects two or more qubits 302 together.
  • another resonant element such as a coupling resonator 316 as shown in FIG. 16 that connects two or more qubits 302 together.
  • a first qubit 302 e.g. the qubit 302 shown on the left side of FIG. 16
  • a second qubit 302 e.g. the qubit 302 shown on the right side of FIG. 16
  • both qubits 302 may be tuned at nearly the same frequency.
  • two qubits 302 could interact via a coupling resonator 316 at specific frequencies, but these three elements do not have to be tuned to be at nearly the same frequency with one another. Interactions between the qubits 302 can similarly be reduced or prevented by controlling the current in the appropriate flux bias lines.
  • the state(s) of each qubit 302 may be read by way of its corresponding readout resonator 318. As discussed below, the qubit 302 may induce a resonant frequency in the readout resonator 318. This resonant frequency is then passed to the microwave lines 314 and communicated to the conductive contacts 322.
  • a readout resonator 318 may be provided for each qubit.
  • the readout resonator 318 may be a transmission line that includes a capacitive connection to ground on one side and is either shorted to ground on the other side (for a quarter-wavelength resonator) or has a capacitive connection to ground (for a half-wavelength resonator), which results in oscillations within the transmission line (resonance).
  • the resonant frequency of the oscillations may be close to the frequency of the qubit 302.
  • the readout resonator 318 may be coupled to the qubit 302 by being in sufficient proximity to the qubit 302 (e.g., through capacitive or inductive coupling).
  • changes in the state of the qubit 302 may result in changes of the resonant frequency of the readout resonator 318.
  • changes in the resonant frequency of the readout resonator 318 may induce changes in the current in the microwave line 314, and that current can be read externally via the conductive contacts 322.
  • the coupling resonator 316 may be used to couple different qubits together to realize quantum logic gates.
  • the coupling resonator 316 may be similar to the readout resonator 318 in that it is a transmission line that may include capacitive connections to ground on both sides (for a half-wavelength resonator), which may result in oscillations within the coupling resonator 316.
  • Each side of the coupling resonator 316 may be coupled (again, either capacitively or inductively) to a respective qubit 302 by being in sufficient proximity to the qubit 302.
  • each side of the coupling resonator 316 couples with a respective different qubit 302, the two qubits 302 may be coupled together through the coupling resonator 316. In this manner, a state of one qubit 302 may depend on the state of the other qubit 302, and vice versa. Thus, coupling resonators 316 may be employed to use a state of one qubit 302 to control a state of another qubit 302.
  • the microwave line 314 may be used to not only readout the state of the qubits 302 as described above, but also to control the state of the qubits 302.
  • the line 314 may operate in a half-duplex mode in which, at some times, it is configured to readout the state of the qubits 302, and, at other times, it is configured to control the state of the qubits 302.
  • microwave lines such as the line 314 shown in FIG. 16 may be used to only readout the state of the qubits as described above, while separate drive lines (such as the drive lines 324 shown in FIG. 16) may be used to control the state of the qubits 302.
  • the microwave lines used for readout may be referred to as readout lines (e.g., the readout line 314)
  • microwave lines used for controlling the state of the qubits may be referred to as drive lines (e.g., the drive lines 324).
  • the drive lines 324 may control the state of their respective qubits 302 by providing (e.g., using conductive contacts 326 as shown in FIG. 16) a microwave pulse at the qubit frequency, which in turn stimulates a transition between the states of the qubit 302. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the states of the qubit 302.
  • Flux bias lines, microwave lines, coupling resonators, drive lines, and readout resonators together form interconnects for supporting propagation of microwave signals.
  • any other connections for providing direct electrical interconnection between different quantum circuit elements and components such as connections from Josephson junction electrodes to capacitor plates or to superconducting loops of superconducting quantum interference devices (SQUIDS) or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, are also referred to herein as interconnects.
  • SQUIDS superconducting quantum interference devices
  • Non-quantum circuit elements may also be provided between quantum circuit elements and components and non-quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit.
  • Examples of non-quantum circuit elements that may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog-to-digital converters, mixers, multiplexers, amplifiers, etc. In some embodiments, these non-quantum elements may be included in the control die 103.
  • Coupling resonators and readout resonators may be configured for capacitive coupling to other circuit elements at one or both ends to have resonant oscillations, whereas flux bias lines and microwave lines may be similar to conventional microwave transmission lines because there is no resonance in these lines.
  • Each one of these interconnects may be implemented as any suitable architecture of a microwave transmission line, such as a coplanar waveguide, a stripline, a microstrip line, or an inverted microstrip line.
  • Typical materials to make the interconnects include aluminum, niobium, niobium nitride, titanium nitride, molybdenum rhenium, and niobium titanium nitride, all of which are particular types of superconductors. However, in various embodiments, other suitable superconductors and alloys of superconductors may be used as well.
  • the interconnects as shown in FIG. 16 could have different shapes and layouts.
  • some interconnects may comprise more curves and turns while other interconnects may comprise fewer curves and turns, and some interconnects may comprise substantially straight lines.
  • various interconnects may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using a bridge to bridge one interconnect over the other, for example.
  • FIG. 16 further illustrates ground contacts 328, connecting to the ground plane.
  • ground contacts 328 may be used when a QP die 104 supports propagation of microwave signals to suppress microwave parallel plate modes, cross-coupling between circuit blocks, and/or substrate resonant modes.
  • providing ground pathways may improve signal quality, enable fast pulse excitation, and improve the isolation between the different lines.
  • ground contacts 328 Only two ground contacts are labeled in FIG. 16 with the reference numeral 328, but all white circles shown throughout FIG. 16 may illustrate exemplary locations of ground conductive contacts.
  • the illustration of the location and the number of the ground contacts 328 in FIG. 16 is purely illustrative and, in various embodiments, ground contacts 328 may be provided at different places, as known in microwave engineering. More generally, any number of qubits 302, flux bias lines 312, microwave lines 314, coupling resonators 316, readout resonators 318, drive lines 324, contacts 320, 322, 326, and 328, and other components discussed herein with reference to the superconducting quantum circuit 300 may be included in a QP die 104.
  • FIGS. 15 and 16 illustrate examples of quantum circuits comprising only two qubits 302, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure.
  • FIGS. 15 and 16 may illustrate various features specific to transmon-type quantum devices
  • the QP dies 104 may include quantum circuits implementing other types of superconducting qubits.
  • the face of the QP die 104 closest to the package substrate 102, and the face of the control die 103 closest to the package substrate 102 may be coated with a solder resist material (not shown).
  • the solder resist may include silicon nitride, aluminum oxide, or silicon oxide, for example. Because the solder resist material may be lossy, it may be advantageous to avoid using solder resist material proximate to or around the interconnects 132 in some
  • FIG. 17 illustrates the superconducting qubit-type quantum device 300 of FIG. 16 with an example area 382 around the resonator 316 in which no solder resist is provided.
  • positioning a lossy material close to the resonators 116 may create spurious two-level systems that may compromise performance of the QP die 104 (e.g., by leading to qubit decoherence).
  • the QP die 104 may include spin qubit-type quantum devices.
  • FIG. 18 depicts cross-sectional views of an example spin qubit-type quantum device 700, in accordance with various embodiments.
  • FIG. 18B illustrates the spin qubit-type quantum device 700 taken along the section A-A of FIG. 18A (while FIG. 18A illustrates the spin qubit-type quantum device 700 taken along the section C-C of FIG. 18B), and
  • FIG. 18C illustrates the spin qubit-type quantum device 700 taken along the section B-B of FIG. 18A with a number of components not shown to more readily illustrate how the gates 706/708 and the magnet line 721 may be patterned (while FIG.
  • FIG. 18A illustrates a spin qubit-type quantum device 700 taken along the section D-D of FIG. 18C).
  • FIG. 18A indicates that the cross-section illustrated in FIG. 18B is taken through the fin 704-1, an analogous cross-section taken through the fin 704-2 may be identical, and thus the discussion of FIG. 18B refers generally to the "fin 704."
  • the spin qubit- type quantum device 700 is simply illustrative, and other spin qubit-type quantum devices may be included in a QP die 104.
  • the spin qubit-type quantum device 700 may include a base 702 and multiple fins 704 extending away from the base 702.
  • the base 702 and the fins 704 may include a substrate and a quantum well stack (not shown in FIG. 18, but discussed below with reference to the substrate 744 and the quantum well stack 746), distributed in any of a number of ways between the base 702 and the fins 704.
  • the base 702 may include at least some of the substrate, and the fins 704 may each include a quantum well layer of the quantum well stack (discussed below with reference to the quantum well layer 752).
  • the total number of fins 704 included in the spin qubit-type quantum device 700 is an even number, with the fins 704 organized into pairs including one active fin 704 and one read fin 704, as discussed in detail below.
  • the fins 704 may be arranged in pairs in a line (e.g., 2N fins total may be arranged in a lx2N line, or a 2xN line) or in pairs in a larger array (e.g., 2N fins total may be arranged as a 4xN/2 array, a 6xN/3 array, etc.).
  • the discussion herein will largely focus on a single pair of fins 704 for ease of illustration, but all the teachings of the present disclosure apply to spin qubit-type quantum devices 700 with more fins 704.
  • each of the fins 704 may include a quantum well layer (not shown in FIG. 18, but discussed below with reference to the quantum well layer 752).
  • the quantum well layer included in the fins 704 may be arranged normal to the z-direction, and may provide a layer in which a two-dimensional electron gas (2DEG) may form to enable the generation of a quantum dot during operation of the spin qubit-type quantum device 700, as discussed in further detail below.
  • the quantum well layer itself may provide a geometric constraint on the z-location of quantum dots in the fins 704, and the limited extent of the fins 704 (and therefore the quantum well layer) in the y- direction may provide a geometric constraint on the y-location of quantum dots in the fins 704.
  • the fins 704 may take any suitable values.
  • the fins 704 may each have a width 762 between 10 nanometers and 30 nanometers.
  • the fins 704 may each have a height 764 between 200 nanometers and 400 nanometers (e.g., between 250 nanometers and 350 nanometers, or equal to 300 nanometers).
  • the fins 704 may be arranged in parallel, as illustrated in FIGS. 18A and 18C, and may be spaced apart by an insulating material 728, which may be disposed on opposite faces of the fins 704.
  • the insulating material 728 may be a dielectric material, such as silicon oxide.
  • the fins 704 may be spaced apart by a distance 760 between 100 nanometers and 250 nanometers.
  • Multiple gates may be disposed on each of the fins 704.
  • three gates 706 and two gates 708 are shown as distributed on the top of the fin 704. This particular number of gates is simply illustrative, and any suitable number of gates may be used.
  • the gate 708-1 may be disposed between the gates 706-1 and 706-2, and the gate 708-2 may be disposed between the gates 706-2 and 706-3.
  • Each of the gates 706/708 may include a gate dielectric 714; in the embodiment illustrated in FIG. 18B, the gate dielectric 714 for all the gates 706/708 is provided by a common layer of gate dielectric material. In other embodiments, the gate dielectric 714 for each of the gates 706/708 may be provided by separate portions of gate dielectric 714. In some embodiments, the gate dielectric 714 may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the fin 704 and the corresponding gate metal).
  • the gate dielectric 714 may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric 714 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • Examples of materials that may be used in the gate dielectric 714 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric 714 to improve the quality of the gate dielectric 714.
  • Each of the gates 706 may include a gate metal 710 and a hardmask 716.
  • the hardmask 716 may be formed of silicon nitride, silicon carbide, or another suitable material.
  • the gate metal 710 may be disposed between the hardmask 716 and the gate dielectric 714, and the gate dielectric 714 may be disposed between the gate metal 710 and the fin 704. Only one portion of the hardmask 716 is labeled in FIG. 18B for ease of illustration.
  • the gate metal 710 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride.
  • the hardmask 716 may not be present in the spin qubit-type quantum device 700 (e.g., a hardmask like the hardmask 716 may be removed during processing, as discussed below).
  • the sides of the gate metal 710 may be substantially parallel, as shown in FIG. 18B, and insulating spacers 734 may be disposed on the sides of the gate metal 710 and the hardmask 716.
  • the spacers 734 may be thicker closer to the fin 704 and thinner farther away from the fin 704.
  • the spacers 734 may have a convex shape.
  • the spacers 734 may be formed of any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride).
  • the gate metal 710 may be any suitable metal, such as titanium nitride.
  • Each of the gates 708 may include a gate metal 712 and a hardmask 718.
  • the hardmask 718 may be formed of silicon nitride, silicon carbide, or another suitable material.
  • the gate metal 712 may be disposed between the hardmask 718 and the gate dielectric 714, and the gate dielectric 714 may be disposed between the gate metal 712 and the fin 704.
  • the hardmask 718 may extend over the hardmask 716 (and over the gate metal 710 of the gates 706), while in other embodiments, the hardmask 718 may not extend over the gate metal 710.
  • the gate metal 712 may be a different metal from the gate metal 710; in other embodiments, the gate metal 712 and the gate metal 710 may have the same material composition.
  • the gate metal 712 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride.
  • the hardmask 718 may not be present in the spin qubit-type quantum device 700 (e.g., a hardmask like the hardmask 718 may be removed during processing, as discussed below).
  • the gate 708-1 may extend between the proximate spacers 734 on the sides of the gate 706- 1 and the gate 706-2, as shown in FIG. 18B.
  • the gate metal 712 of the gate 708-1 may extend between the spacers 734 on the sides of the gate 706-1 and the gate 706-2.
  • the gate metal 712 of the gate 708-1 may have a shape that is substantially complementary to the shape of the spacers 734, as shown.
  • the gate 708-2 may extend between the proximate spacers 734 on the sides of the gate 706-2 and the gate 706-3.
  • the gate dielectric 714 may extend at least partially up the sides of the spacers 734, and the gate metal 712 may extend between the portions of gate dielectric 714 on the spacers 734.
  • the gate metal 712 like the gate metal 710, may be any suitable metal, such as titanium nitride.
  • the dimensions of the gates 706/708 may take any suitable values.
  • the z-height 766 of the gate metal 710 may be between 40 nanometers and 75 nanometers (e.g., approximately 50 nanometers); the z-height of the gate metal 712 may be in the same range.
  • the z-height of the gate metal 712 may be greater than the z-height of the gate metal 710.
  • the length 768 of the gate metal 710 i.e., in the x-direction
  • the distance 770 between adjacent ones of the gates 706 may be between 40 nanometers and 60 nanometers (e.g., 50 nanometers).
  • the thickness 772 of the spacers 734 may be between 1 nanometer and 10 nanometers (e.g., between 3 nanometers and 5 nanometers, between 4 nanometers and 6 nanometers, or between 4 nanometers and 7 nanometers).
  • the length of the gate metal 712 may depend on the dimensions of the gates 706 and the spacers 734, as illustrated in FIG. 18B.
  • the gates 706/708 on one fin 704 may extend over the insulating material 728 beyond their respective fins 704 and towards the other fin 704, but may be isolated from their counterpart gates by the intervening insulating material 730 and spacers 734.
  • the "outermost” gates 706 may have a greater length 768 than the "inner” gates 706 (e.g., the gate 706-2 in the embodiment illustrated in FIG. 18B).
  • Such longer “outside” gates 706 may provide spatial separation between the doped regions 740 and the areas under the gates 708 and the inner gates 706 in which quantum dots 742 may form, and thus may reduce the perturbations to the potential energy landscape under the gates 708 and the inner gates 706 caused by the doped regions 740.
  • the gates 706 and 708 may be alternatingly arranged along the fin 704 in the x-direction.
  • voltages may be applied to the gates 706/708 to adjust the potential energy in the quantum well layer (not shown) in the fin 704 to create quantum wells of varying depths in which quantum dots 742 may form.
  • Only one quantum dot 742 is labeled with a reference numeral in FIGS. 18B and 18C for ease of illustration, but five are indicated as dotted circles in each fin 704.
  • the location of the quantum dots 742 in FIG. 18B is not intended to indicate a particular geometric positioning of the quantum dots 742.
  • the spacers 734 may themselves provide "passive" barriers between quantum wells under the gates 706/708 in the quantum well layer, and the voltages applied to different ones of the gates 706/708 may adjust the potential energy under the gates 706/708 in the quantum well layer;
  • the fins 704 may include doped regions 740 that may serve as a reservoir of charge carriers for the spin qubit-type quantum device 700.
  • an n-type doped region 740 may supply electrons for electron-type quantum dots 742
  • a p-type doped region 740 may supply holes for hole-type quantum dots 742.
  • an interface material 741 may be disposed at a surface of a doped region 740, as shown. The interface material 741 may facilitate electrical coupling between a conductive contact (e.g., a conductive via 736, as discussed below) and the doped region 740.
  • the interface material 741 may be any suitable metal-semiconductor ohmic contact material; for example, in embodiments in which the doped region 740 includes silicon, the interface material 741 may include nickel silicide, aluminum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tungsten silicide, or platinum silicide. In some embodiments, the interface material 741 may be a non-silicide compound, such as titanium nitride. In some embodiments, the interface material 741 may be a metal (e.g., aluminum, tungsten, or indium). [0087] The spin qubit-type quantum devices 700 disclosed herein may be used to form electron- type or hole-type quantum dots 742.
  • the polarity of the voltages applied to the gates 706/708 to form quantum wells/barriers depend on the charge carriers used in the spin qubit-type quantum device 700.
  • the charge carriers are electrons (and thus the quantum dots 742 are electron-type quantum dots)
  • amply negative voltages applied to a gate 706/708 may increase the potential barrier under the gate 706/708
  • amply positive voltages applied to a gate 706/708 may decrease the potential barrier under the gate 706/708 (thereby forming a potential well in which an electron-type quantum dot 742 may form).
  • amply positive voltages applied to a gate 706/708 may increase the potential barrier under the gate 706/708, and amply negative voltages applied to a gate 706 and 708 may decrease the potential barrier under the gate 706/708 (thereby forming a potential well in which a hole-type quantum dot 742 may form).
  • the spin qubit-type quantum devices 700 disclosed herein may be used to form electron-type or hole-type quantum dots.
  • Voltages may be applied to each of the gates 706 and 708 separately to adjust the potential energy in the quantum well layer under the gates 706 and 708, and thereby control the formation of quantum dots 742 under each of the gates 706 and 708. Additionally, the relative potential energy profiles under different ones of the gates 706 and 708 allow the spin qubit-type quantum device 700 to tune the potential interaction between quantum dots 742 under adjacent gates. For example, if two adjacent quantum dots 742 (e.g., one quantum dot 742 under a gate 706 and another quantum dot 742 under a gate 708) are separated by only a short potential barrier, the two quantum dots 742 may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each gate 706/708 may be adjusted by adjusting the voltages on the respective gates 706/708, the differences in potential between adjacent gates 706/708 may be adjusted, and thus the interaction tuned.
  • two adjacent quantum dots 742 e.g., one quantum dot 7
  • the gates 708 may be used as plunger gates to enable the formation of quantum dots 742 under the gates 708, while the gates 706 may be used as barrier gates to adjust the potential barrier between quantum dots 742 formed under adjacent gates 708.
  • the gates 708 may be used as barrier gates, while the gates 706 are used as plunger gates.
  • quantum dots 742 may be formed under all the gates 706 and 708, or under any desired subset of the gates 706 and 708.
  • Conductive vias and lines may contact the gates 706/708 and the doped regions 740 to enable electrical connection to the gates 706/708 and the doped regions 740 to be made in desired locations.
  • the gates 706 may extend away from the fins 704, and conductive vias 720 may contact the gates 706 (and are drawn in dashed lines in FIG. 18B to indicate their location behind the plane of the drawing).
  • the conductive vias 720 may extend through the hardmask 716 and the hardmask 718 to contact the gate metal 710 of the gates 706.
  • the gates 708 may extend away from the fins 704, and conductive vias 722 may contact the gates 708 (also drawn in dashed lines in FIG. 18B to indicate their location behind the plane of the drawing).
  • the conductive vias 722 may extend through the hardmask 718 to contact the gate metal 712 of the gates 708. Conductive vias 736 may contact the interface material 741 and may thereby make electrical contact with the doped regions 740.
  • the spin qubit-type quantum device 700 may include further conductive vias and/or lines (not shown) to make electrical contact to the gates 706/708 and/or the doped regions 740, as desired.
  • the conductive vias and lines included in a spin qubit- type quantum device 700 may include any suitable materials, such as copper, tungsten (deposited, e.g., by chemical vapor deposition (CVD)), or a superconductor (e.g., aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium).
  • CVD chemical vapor deposition
  • a bias voltage may be applied to the doped regions 740 (e.g., via the conductive vias 736 and the interface material 741) to cause current to flow through the doped regions 740.
  • this voltage may be positive; when the doped regions 740 are doped with a p-type material, this voltage may be negative.
  • the magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts).
  • the spin qubit-type quantum device 700 may include one or more magnet lines 721.
  • a single magnet line 721 is illustrated in FIG. 18 proximate to the fin 704-1.
  • the magnet line 721 may be formed of a conductive material, and may be used to conduct current pulses that generate magnetic fields to influence the spin states of one or more of the quantum dots 742 that may form in the fins 704.
  • the magnet line 721 may conduct a pulse to reset (or "scramble") nuclear and/or quantum dot spins.
  • the magnet line 721 may conduct a pulse to initialize an electron in a quantum dot in a particular spin state.
  • the magnet line 721 may conduct current to provide a continuous, oscillating magnetic field to which the spin of a qubit may couple.
  • the magnet line 721 may provide any suitable combination of these embodiments, or any other appropriate functionality.
  • the magnet line 721 may be formed of copper. In some embodiments, the magnet line 721 may be formed of copper.
  • the magnet line 721 may be formed of a superconductor, such as aluminum.
  • the magnet line 721 illustrated in FIG. 18 is non-coplanar with the fins 704, and is also non-coplanar with the gates 706/708.
  • the magnet line 721 may be spaced apart from the gates 706/708 by a distance 767.
  • the distance 767 may take any suitable value (e.g., based on the desired strength of the magnetic field interaction with the quantum dots 742); in some embodiments, the distance 767 may be between 25 nanometers and 1 micron (e.g., between 50 nanometers and 200 nanometers).
  • the magnet line 721 may be formed of a magnetic material.
  • a magnetic material such as cobalt
  • the magnet line 721 may have any suitable dimensions.
  • the magnet line 721 may have a thickness 769 between 25 nanometers and 100 nanometers.
  • the magnet line 721 may have a width 771 between 25 nanometers and 100 nanometers.
  • the width 771 and thickness 769 of a magnet line 721 may be equal to the width and thickness, respectively, of other conductive lines in the spin qubit-type quantum device 700 (not shown) used to provide electrical interconnects, as known in the art.
  • the magnet line 721 may have a length 773 that may depend on the number and dimensions of the gates 706/708 that are to form quantum dots 742 with which the magnet line 721 is to interact.
  • the magnet line 721 illustrated in FIG. 18 is substantially linear, but this need not be the case; the magnet lines 721 disclosed herein may take any suitable shape.
  • Conductive vias 723 may contact the magnet line 721.
  • the conductive vias 720, 722, 736, and 723 may be electrically isolated from each other by an insulating material 730.
  • the insulating material 730 may be any suitable material, such as an interlayer dielectric (ILD). Examples of the insulating material 730 may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride.
  • ILD interlayer dielectric
  • conductive vias and lines may be formed in an iterative process in which layers of structures are formed on top of each other.
  • the conductive vias 720/722/736/723 may have a width that is 20 nanometers or greater at their widest point (e.g., 30 nanometers), and a pitch of 80 nanometers or greater (e.g., 100 nanometers).
  • conductive lines (not shown) included in the spin qubit-type quantum device 700 may have a width that is 100 nanometers or greater, and a pitch of 100 nanometers or greater.
  • the particular arrangement of conductive vias shown in FIG. 18 is simply illustrative, and any electrical routing arrangement may be implemented.
  • the structure of the fin 704-1 may be the same as the structure of the fin 704-2; similarly, the construction of gates 706/708 on the fin 704-1 may be the same as the construction of gates 706/708 on the fin 704-2.
  • the gates 706/708 on the fin 704-1 may be mirrored by corresponding gates 706/708 on the parallel fin 704-2, and the insulating material 730 may separate the gates 706/708 on the different fins 704-1 and 704-2.
  • quantum dots 742 formed in the fin 704-1 (under the gates 706/708) may have counterpart quantum dots 742 in the fin 704-2 (under the corresponding gates 706/708).
  • the quantum dots 742 in the fin 704-1 may be used as "active" quantum dots in the sense that these quantum dots 742 act as qubits and are controlled (e.g., by voltages applied to the gates 706/708 of the fin 704-1) to perform quantum computations.
  • the quantum dots 742 in the fin 704-2 may be used as "read” quantum dots in the sense that these quantum dots 742 may sense the quantum state of the quantum dots 742 in the fin 704-1 by detecting the electric field generated by the charge in the quantum dots 742 in the fin 704-1, and may convert the quantum state of the quantum dots 742 in the fin 704-1 into electrical signals that may be detected by the gates 706/708 on the fin 704-2.
  • Each quantum dot 742 in the fin 704-1 may be read by its corresponding quantum dot 742 in the fin 704-2.
  • the spin qubit-type quantum device 700 enables both quantum computation and the ability to read the results of a quantum computation.
  • the base 702 and the fin 704 of a spin qubit-type quantum device 700 may be formed from a substrate 744 and a quantum well stack 746 disposed on the substrate 744.
  • the quantum well stack 746 may include a quantum well layer in which a 2DEG may form during operation of the spin qubit-type quantum device 700.
  • the quantum well stack 746 may take any of a number of forms, several of which are illustrated in FIG. 19.
  • the various layers in the quantum well stacks 746 discussed below may be grown on the substrate 744 (e.g., using epitaxial processes).
  • FIG. 19A is a cross-sectional view of a quantum well stack 746 including only a quantum well layer 752.
  • the quantum well layer 752 may be disposed on the substrate 744, and may be formed of a material such that, during operation of the spin qubit-type quantum device 700, a 2DEG may form in the quantum well layer 752 proximate to the upper surface of the quantum well layer 752.
  • the gate dielectric 714 of the gates 706/708 may be disposed on the upper surface of the quantum well layer 752.
  • the gate dielectric 714 may be formed of silicon oxide; in such an arrangement, during use of the spin qubit-type quantum device 700, a 2DEG may form in the intrinsic silicon at the interface between the intrinsic silicon and the silicon oxide.
  • the quantum well layer 752 of FIG. 19A is formed of intrinsic silicon may be particularly advantageous for electron- type spin qubit-type quantum devices 700.
  • the quantum well layer 752 of FIG. 19A may be formed of intrinsic germanium, and the gate dielectric 714 may be formed of germanium oxide; in such an arrangement, during use of the spin qubit-type quantum device 700, a 2DEG may form in the intrinsic germanium at the interface between the intrinsic germanium and the germanium oxide.
  • the quantum well layer 752 may be strained, while in other embodiments, the quantum well layer 752 may not be strained.
  • the thicknesses (i.e., z-heights) of the layers in the quantum well stack 746 of FIG. 19A may take any suitable values.
  • the thickness of the quantum well layer 752 e.g., intrinsic silicon or germanium
  • the thickness of the quantum well layer 752 may be between 0.8 microns and 1.2 microns.
  • FIG. 19B is a cross-sectional view of a quantum well stack 746 including a quantum well layer 752 and a barrier layer 754.
  • the quantum well stack 746 may be disposed on a substrate 744 such that the barrier layer 754 is disposed between the quantum well layer 752 and the substrate 744.
  • the barrier layer 754 may provide a potential barrier between the quantum well layer 752 and the substrate 744.
  • the quantum well layer 752 of FIG. 19B may be formed of a material such that, during operation of the spin qubit-type quantum device 700, a 2DEG may form in the quantum well layer 752 proximate to the upper surface of the quantum well layer 752.
  • the quantum well layer 752 of FIG. 19B may be formed of silicon, and the barrier layer 754 may be formed of silicon germanium.
  • the germanium content of this silicon germanium may be 20-80% (e.g., 30%).
  • the barrier layer 754 may be formed of silicon germanium (with a germanium content of 20-80% (e.g., 70%)).
  • the thicknesses (i.e., z-heights) of the layers in the quantum well stack 746 of FIG. 19B may take any suitable values.
  • the thickness of the barrier layer 754 may be between 0 nanometers and 400 nanometers.
  • the thickness of the quantum well layer 752 e.g., silicon or germanium
  • the thickness of the quantum well layer 752 may be between 5 nanometers and 30 nanometers.
  • FIG. 19C is a cross-sectional view of a quantum well stack 746 including a quantum well layer 752 and a barrier layer 754-1, as well as a buffer layer 776 and an additional barrier layer 754-2.
  • the quantum well stack 746 may be disposed on the substrate 744 such that the buffer layer 776 is disposed between the barrier layer 754-1 and the substrate 744.
  • the buffer layer 776 may be formed of the same material as the barrier layer 754, and may be present to trap defects that form in this material as it is grown on the substrate 744. In some embodiments, the buffer layer 776 may be grown under different conditions (e.g., deposition temperature or growth rate) from the barrier layer 754-1.
  • the barrier layer 754-1 may be grown under conditions that achieve fewer defects than the buffer layer 776.
  • the silicon germanium of the buffer layer 776 may have a germanium content that varies from the substrate 744 to the barrier layer 754-1; for example, the silicon germanium of the buffer layer 776 may have a germanium content that varies from zero percent at the silicon substrate 744 to a nonzero percent (e.g., 30%) at the barrier layer 754-1.
  • the thicknesses (i.e., z- heights) of the layers in the quantum well stack 746 of FIG. 19C may take any suitable values.
  • the thickness of the buffer layer 776 may be between 0.3 microns and 4 microns (e.g., 0.3-2 microns, or 0.5 microns).
  • the thickness of the barrier layer 754-1 e.g., silicon germanium
  • the thickness of the quantum well layer 752 e.g., silicon or germanium
  • the barrier layer 754-2 like the barrier layer 754-1, may provide a potential energy barrier around the quantum well layer 752, and may take the form of any of the embodiments of the barrier layer 754-1.
  • the thickness of the barrier layer 754-2 (e.g., silicon germanium) may be between 25 nanometers and 75 nanometers (e.g., 32 nanometers).
  • the quantum well layer 752 of FIG. 19C may be formed of a material such that, during operation of the spin qubit-type quantum device 700, a 2DEG may form in the quantum well layer 752 proximate to the upper surface of the quantum well layer 752.
  • the quantum well layer 752 of FIG. 19C may be formed of silicon, and the barrier layer 754-1 and the buffer layer 776 may be formed of silicon germanium.
  • the silicon germanium of the buffer layer 776 may have a germanium content that varies from the substrate 744 to the barrier layer 754-1; for example, the silicon germanium of the buffer layer 776 may have a germanium content that varies from zero percent at the silicon substrate 744 to a nonzero percent (e.g., 30%) at the barrier layer 754-1. In other embodiments, the buffer layer 776 may have a germanium content equal to the germanium content of the barrier layer 754-1 but may be thicker than the barrier layer 754-1 to absorb the defects that arise during growth.
  • the quantum well layer 752 of FIG. 19C may be formed of germanium, and the buffer layer 776 and the barrier layer 754-1 may be formed of silicon germanium.
  • the silicon germanium of the buffer layer 776 may have a germanium content that varies from the substrate 744 to the barrier layer 754-1; for example, the silicon germanium of the buffer layer 776 may have a germanium content that varies from zero percent at the substrate 744 to a nonzero percent (e.g., 70%) at the barrier layer 754-1.
  • the barrier layer 754-1 may in turn have a germanium content equal to the nonzero percent.
  • the buffer layer 776 may have a germanium content equal to the germanium content of the barrier layer 754-1 but may be thicker than the barrier layer 754-1 to absorb the defects that arise during growth. In some embodiments of the quantum well stack 746 of FIG. 19C, the buffer layer 776 and/or the barrier layer 754-2 may be omitted.
  • FIG. 20 is a top view of a wafer 450 and dies 452 that may be formed from the wafer 450; the dies 452 may be the QP dies 104 discussed herein.
  • the wafer 450 may include semiconductor material and may include one or more dies 452 having conventional and/or quantum computing device elements formed on a surface of the wafer 450.
  • Each of the dies 452 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum computing device. After the fabrication of the semiconductor product is complete, the wafer 450 may undergo a singulation process in which each of the dies 452 is separated from one another to provide discrete "chips" of the semiconductor product.
  • a die 452 may include one or more quantum computing devices (e.g., the devices discussed above with reference to FIGS. 15-19) and/or supporting circuitry to route electrical signals to the quantum computing devices (e.g., interconnects including conductive vias and lines, or control circuitry), as well as any other IC components.
  • the wafer 450 or the die 452 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 452. For example, a memory array formed by multiple memory devices may be formed on a same die 452 as a processing device (e.g., the processing device 2002 of FIG. 21) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • a memory device e.g., a static random access memory (SRAM) device
  • a logic device e.g., AND, OR, NAND, or NOR gate
  • FIG. 21 is a block diagram of an example quantum computing device 2000 that may include any of the QC assemblies 100 disclosed herein.
  • a number of components are illustrated in FIG. 21 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application.
  • some or all the components included in the quantum computing device 2000 may be attached to one or more PCBs (e.g., a motherboard).
  • various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die.
  • the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 21, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components.
  • the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled.
  • the quantum computing device 2000 may not include an audio input device 2024 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2024 or audio output device 2008 may be coupled.
  • the quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices).
  • processing device e.g., one or more processing devices
  • the term "processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices).
  • the quantum processing device 2026 may include one or more of the QP dies 104 disclosed herein, and may perform data processing by performing operations on the qubits that may be generated in the QP dies 104, and monitoring the result of those operations. For example, as discussed above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of qubits may be read.
  • the quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc.
  • the quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.
  • the processing device 2002 may include a non-quantum processing device 2028.
  • the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026.
  • the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, control the performance of any of the operations discussed herein, etc.
  • the non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026.
  • the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the
  • the non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute
  • DSPs digital signal processors
  • ASICs application-specific ICs
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute
  • the quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid state memory
  • solid state memory solid state memory
  • hard drive solid state memory
  • the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004.
  • the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-M RAM).
  • eDRAM embedded dynamic random access memory
  • STT-M RAM spin transfer torque magnetic random access memory
  • the quantum computing device 2000 may include a cooling apparatus 2030.
  • the cooling apparatus 2030 may maintain the quantum processing device 2026 at a predetermined low temperature during operation to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 Kelvin or less.
  • the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature.
  • the cooling apparatus 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.
  • the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips).
  • the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (I EEE) standards including Wi-Fi (I EEE 802.11 family), I EEE 802.16 standards (e.g., I EEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (U M B) project (also referred to as "3GPP2”), etc.).
  • I EEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and
  • the communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (U MTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • U MTS Universal Mobile Telecommunications System
  • High Speed Packet Access HSPA
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • the communication chip 2012 may operate in accordance with other wireless protocols in other embodiments.
  • the quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless
  • the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet).
  • the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless
  • a second communication chip 2012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
  • GPS global positioning system
  • EDGE EDGE
  • GPRS global positioning system
  • CDMA Code Division Multiple Access
  • WiMAX Long Term Evolution
  • LTE Long Term Evolution
  • EV-DO EV-DO
  • a first communication chip 2012 may be dedicated to wireless communications
  • a second communication chip 2012 may be dedicated to wired communications.
  • the quantum computing device 2000 may include battery/power circuitry 2014.
  • the battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).
  • the quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above).
  • the display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
  • LCD liquid crystal display
  • the quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above).
  • the audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
  • the quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above).
  • the audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (M I DI) output).
  • M I DI musical instrument digital interface
  • the quantum computing device 2000 may incl ude a GPS device 2018 (or corresponding interface circuitry, as discussed above).
  • the GPS device 2018 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.
  • the quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above).
  • Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
  • the quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above).
  • Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • RFID radio frequency identification
  • Example 1 is a quantum computing (QC) assembly, including: a package substrate having a first face and an opposing second face; a quantum processing die coupled to the first face of the package substrate; and a control die coupled to the second face of the package substrate; wherein the package substrate includes conductive structures electrically coupling the quantum processing die to the control die.
  • QC quantum computing
  • Example 2 may include the subject matter of Example 1, and may further specify that the package substrate includes a printed circuit board.
  • Example 3 may include the subject matter of Example 1, and may further specify that the package substrate includes a semiconductor interposer.
  • Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the conductive structures have a diameter between 10 microns and 80 microns.
  • Example 5 may include the subject matter of any of Examples 1-4, and may further specify that the conductive structures include one or more coaxial arrangements or one or more twinaxial arrangements.
  • Example 6 may include the subject matter of any of Examples 1-5, and may further specify that the package substrate includes a stack of multiple sub-substrates.
  • Example 7 may include the subject matter of Example 6, and may further specify that the stack includes a first sub-substrate closest to the quantum processing die, and conductive structures in the first sub-substrate fan out connections from the quantum processing die to a larger pitch.
  • Example 8 may include the subject matter of any of Examples 6-7, and may further specify that some but not all of the sub-substrates in the stack have a same arrangement of conductive structures therein.
  • Example 9 may include the subject matter of any of Examples 6-8, and may further specify that at least one of the sub-substrates includes a compliant dielectric.
  • Example 10 may include the subject matter of any of Examples 1-9, and may further specify that the conductive structures extend linearly between the first face and the second face.
  • Example 11 may include the subject matter of any of Examples 1-10, and may further specify that the quantum processing die is coupled to the package substrate with a solder or a conductive adhesive.
  • Example 12 may include the subject matter of Example 11, and may further specify that the quantum processing die is coupled to the package substrate with an indium solder.
  • Example 13 may include the subject matter of any of Examples 1-12, and may further specify that the control die is coupled to the package substrate with a solder or a conductive adhesive.
  • Example 14 may include the subject matter of Example 13, and may further specify that the control die is coupled to the package substrate with an indium solder.
  • Example 15 may include the subject matter of any of Examples 1-14, and may further specify that the conductive structures include a superconducting material.
  • Example 16 may include the subject matter of Example 15, and may further specify that the quantum processing die is coupled to the package substrate with a solder that includes a superconducting material.
  • Example 17 may include the subject matter of any of Examples 1-16, and may further specify that the conductive structures include copper.
  • Example 18 may include the subject matter of Example 17, and may further specify that the quantum processing die is coupled to the package substrate with a solder that includes a superconducting material.
  • Example 19 may include the subject matter of any of Examples 1-18, and may further specify that the conductive structures include signal pathways surrounded by a conductive shield.
  • Example 20 may include the subject matter of any of Examples 1-19, and may further specify that the conductive structures have a pitch between 50 microns and 100 microns.
  • Example 21 may include the subject matter of any of Examples 1-20, and may further specify that the control die includes a multiplexer or a filter.
  • Example 22 may include the subject matter of any of Examples 1-21, and may further specify that the quantum processing die includes one or more Josephson junctions.
  • Example 23 may include the subject matter of any of Examples 1-22, and may further specify that the quantum processing die includes a quantum well stack.
  • Example 24 may include the subject matter of any of Examples 1-23, and may further specify that the quantum processing die is a first quantum processing die, and the QC assembly further includes a second quantum processing die coupled to the first face of the package substrate.
  • Example 25 may include the subject matter of any of Examples 1-24, and may further specify that the control die is a first control die, and the QC assembly further includes a second control die coupled to the second face of the package substrate.
  • Example 26 may include the subject matter of any of Examples 1-25, and may further include a circuit component coupled to the control die.
  • Example 27 may include the subject matter of Example 26, and may further specify that the control die has a first face and an opposing second face, the first face of the control die is coupled to the second face of the package substrate, and the circuit component is coupled to the second face of the control die.
  • Example 28 may include the subject matter of any of Examples 26-27, and may further specify that the circuit component includes a circuit board or a cable.
  • Example 29 may include the subject matter of any of Examples 26-28, and may further specify that the circuit component is flexible.
  • Example 30 may include the subject matter of any of Examples 26-29, and may further include:
  • an auxiliary die coupled to the circuit component, wherein the circuit component includes conductive structures to route signals between the auxiliary die and the control die.
  • Example 31 may include the subject matter of Example 30, and may further specify that the auxiliary die includes optical components, decompression circuitry, or a frequency converter.
  • Example 32 may include the subject matter of any of Examples 26-31, and may further specify that the circuit component is coupled between the control die and the package substrate.
  • Example 33 may include the subject matter of any of Examples 1-32, and may further specify that the package substrate is a first package substrate, the control die is a first control die, and the QC assembly further includes: a second package substrate having a first face and an opposing second face, wherein the first control die is coupled to the first face of the second package substrate; and a second control die coupled to the second face of the second package substrate.
  • Example 34 may include the subject matter of Example 33, and may further specify that the second control die includes a multiplexer or a filter.
  • Example 35 may include the subject matter of any of Examples 33-34, and may further include a circuit component coupled to the second control die.
  • Example 36 may include the subject matter of Example 35, and may further specify that the second control die has a first face and an opposing second face, the first face of the second control die is coupled to the second face of the second package substrate, and the circuit component is coupled to the second face of the second control die.
  • Example 37 may include the subject matter of any of Examples 35-36, and may further specify that the circuit component includes a circuit board or a cable.
  • Example 38 may include the subject matter of any of Examples 35-37, and may further specify that the circuit component is flexible.
  • Example 39 may include the subject matter of any of Examples 35-38, and may further include an auxiliary die coupled to the circuit component, wherein the circuit component includes conductive structures to route signals between the auxiliary die and the second control die.
  • Example 40 may include the subject matter of Example 39, and may further specify that the auxiliary die includes optical components, decompression circuitry, or a frequency converter.
  • Example 41 may include the subject matter of any of Examples 1-40, and may further specify that the coupling between the quantum processing die and the package substrate is detachable.
  • Example 42 may include the subject matter of Example 41, and may further specify that the quantum processing die is coupled to the package substrate with an anisotropic conductive film.
  • Example 43 may include the subject matter of any of Examples 1-42, and may further specify that the quantum processing die is a first quantum processing die, the control die is a first control die, the package substrate is a first package substrate, and the QC assembly further includes: a circuit component coupled to the first control die; a second package substrate having a first face and an opposing second face; a second quantum processing die coupled to the first face of the second package substrate; and a second control die coupled to the second face of the second package substrate; wherein the second package substrate includes conductive structures electrically coupling the second quantum processing die to the second control die, and the circuit component is also coupled to the second control die.
  • Example 44 may include the subject matter of Example 43, and may further include an auxiliary die coupled to the circuit component, wherein the circuit component includes conductive structures to route signals between the auxiliary die and the first control die, and between the auxiliary die and the second control die.
  • Example 45 is a method of manufacturing a quantum computing (QC) package, including: forming a package substrate having a first face and an opposing second face; coupling a quantum processing die to the first face of the package substrate; and coupling a control die to the second face of the package substrate; wherein the package substrate includes conductive structures that, upon coupling the quantum processing die and the control die to the package substrate, electrically couple the quantum processing die and the control die.
  • QC quantum computing
  • Example 46 may include the subject matter of Example 45, and may further specify that forming the package substrate includes forming the conductive structures by stereolithography or electroplating.
  • Example 47 may include the subject matter of Example 45, and may further specify that forming the package substrate includes embedding wires in an epoxy.
  • Example 48 may include the subject matter of Example 45, and may further specify that: forming the package substrate includes forming traces in multiple layers in a printed circuit board, wherein at least some of the traces are exposed at opposing first and second side faces of the printed circuit board; coupling the quantum processing die to the first face of the package substrate includes coupling the quantum processing die to the first side face of the printed circuit board; and coupling the control die to the second face of the package substrate includes coupling the control die to the second side face of the printed circuit board.
  • Example 49 may include the subject matter of any of Examples 45-48, and may further specify that the conductive structures include signal pathways surrounded by shielding structures.
  • Example 50 may include the subject matter of Example 49, and may further specify that the shielding structures include vias.
  • Example 51 is a method of operating a quantum computing assembly, including: providing electrical signals, by a control die in the quantum computing assembly, to a quantum processing die through conductive structures in a package substrate, wherein the electrical signals are to cause the quantum processing die to carry out one or more quantum processing operations; and receiving electrical signals, by the control die from the quantum processing die, representative of the quantum processing operations; wherein the package substrate has a first face and an opposing second face, the quantum processing die is coupled to the first face of the package substrate, and the control die is coupled to the second face of the package substrate.
  • Example 52 may include the subject matter of Example 51, and may further specify that the control die is to provide radio frequency signals to the quantum processing die.
  • Example 53 may include the subject matter of any of Examples 51-52, and may further specify that the quantum processing die includes one or more Josephson junctions.
  • Example 54 may include the subject matter of any of Examples 51-53, and may further specify that the quantum processing die includes a quantum well stack.
  • Example 55 is a quantum computing (QC) device, including: a package substrate having a first face and an opposing second face; a quantum processing die coupled to the first face of the package substrate; one or more control dies, coupled to the second face of the package substrate, to control electrical signals applied to and read from the quantum processing die through conductive structures in the package substrate; and a memory device to store data generated during operation of the quantum processing die.
  • QC quantum computing
  • Example 56 may include the subject matter of Example 55, and may further include a cooling apparatus to maintain a temperature of the quantum processing die below 5 Kelvin.
  • Example 57 may include the subject matter of any of Examples 55-56, and may further specify that the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing die.

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Abstract

La présente invention concerne des assemblages de calculateurs quantiques (QC), ainsi que des dispositifs et des procédés associés. Dans certains modes de réalisation, un assemblage QC peut comprendre un substrat de boîtier ayant une première face et une seconde face opposée, une puce de traitement quantique couplée à la première face du substrat de boîtier, et une puce de commande couplée à la seconde face du substrat de boîtier. Le substrat de boîtier peut comprendre des structures conductrices couplant électriquement la puce de traitement quantique à la puce de commande.
PCT/US2017/039167 2017-06-25 2017-06-25 Assemblages de calculateurs quantiques WO2019004991A1 (fr)

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US11450765B2 (en) 2018-09-27 2022-09-20 Intel Corporation Quantum dot devices with diodes for electrostatic discharge protection
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US11658212B2 (en) 2019-02-13 2023-05-23 Intel Corporation Quantum dot devices with conductive liners
US11699747B2 (en) 2019-03-26 2023-07-11 Intel Corporation Quantum dot devices with multiple layers of gate metal
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US11875225B2 (en) 2019-06-17 2024-01-16 International Business Machines Corporation Superconducting interposer for the transmission of quantum information for quantum error correction
US11011693B2 (en) 2019-06-24 2021-05-18 Intel Corporation Integrated quantum circuit assemblies for cooling apparatus
US11957066B2 (en) 2019-09-04 2024-04-09 Intel Corporation Stackable in-line filter modules for quantum computing
US11387324B1 (en) 2019-12-12 2022-07-12 Intel Corporation Connectivity in quantum dot devices
EP4195283A1 (fr) * 2021-12-08 2023-06-14 Imec VZW Puce de bits quantiques avec des plaquettes empilées et son procédé de fabrication

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