WO2018236358A1

WO2018236358A1 - Double patterning enabled by sputter defined ion implant features

Info

Publication number: WO2018236358A1
Application number: PCT/US2017/038384
Authority: WO
Inventors: Aaron D. Lilak; Manish Chandhok; Anant H. Jahagirdar
Original assignee: Intel Corporation
Priority date: 2017-06-20
Filing date: 2017-06-20
Publication date: 2018-12-27

Abstract

Double patterning approaches based on sputter defined ion implant features, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a plurality of semiconductor fins. Individual ones of the plurality of semiconductor fins have xenon (Xe) or krypton (Kr) atoms therein. A concentration of the Xe or Kr atoms along sidewalls of the individual ones of the plurality of semiconductor fins is greater than a concentration of the Xe or Kr atoms in centers of the individual ones of the plurality of semiconductor fins. A concentration of the Xe or Kr atoms in upper portions of the plurality of semiconductor fins is greater than a concentration of the Xe or Kr atoms in lower portions of the plurality of semiconductor fins.

Description

DOUBLE PATTERNING ENABLED BY SPUTTER DEFINED ION IMPLANT FEATURES

TECHNICAL FIELD

Embodiments of the disclosure are in the field of semiconductor devices and processing and, in particular, double patterning approaches based on sputter defined ion implant features, and integrated circuit structures resulting therefrom.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with the existing high-yielding bulk silicon substrate infrastructure.

Scaling multi-gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.

BRIEF DESCRIPTION OF THE DRAWINGS

Figures 1 A-1D illustrate cross-sectional views of various operations in a method of fabricating semiconductor fins using a double patterning approach based on sputter defined ion implant features, in accordance with an embodiment of the present disclosure.

Figure 2 is a schematic showing a calculation of implant orientation for a representative structure, in accordance with an embodiment of the present disclosure.

Figure 3 A illustrates a cross-sectional view of a non-planar integrated circuit structure, in accordance with an embodiment of the present disclosure. Figure 3B illustrates a plan view taken along the a-a' axis of the non-planar integrated circuit structure of Figure 3 A, in accordance with an embodiment of the present disclosure.

Figure 4 is a plot showing a sputtering yield simulation, in accordance with one or more embodiments of the present disclosure.

Figures 5A and 5B illustrate cross-sectional views of various operations in another method of fabricating semiconductor fins using a double patterning approach based on sputter defined ion implant features, in accordance with another embodiment of the present disclosure.

Figure 6 illustrates a cross-sectional view of a stack of metallization layers in an integrated circuit, in accordance with an embodiment of the present disclosure.

Figure 7 illustrates a computing device in accordance with one implementation of an embodiment of the present disclosure.

Figure 8 illustrates an interposer that includes one or more embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

Double patterning approaches based on sputter defined ion implant features, and integrated circuit structures resulting therefrom, are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Embodiments described herein may be directed to front-end-of-line (FEOL)

semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back end of line (BEOL)

semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

One or more embodiments described herein is directed to processes and structures based on and resulting from self-aligned double patterning approaches enabled by sputter-defined ion implant features. Embodiments may include or be relevant to one of more of multiple patterning, pitch-halving, self-aligned double patterning, sputtering, tilted ion implantation.

Embodiments may be applicable for fin patterning, gate line patterning, or trench formation for BEOL layer fabrication. Artifacts of such processing may be the inclusion of argon, xenon, or krypton in or near such features or lattice defects associated with the inclusion of same.

Additional artifacts of such processing may include low concentrations of forward recoiled atoms of the masking or dielectric materials resultant from the sputter process. Embodiments may be extended and/or repeated for pitch quartering processing, etc. One or more embodiments is particularly suited for non-planar semiconductor device fabrication. In one such embodiment, a patterning approach described herein is particularly applicable to patterning silicon fins in a tri- gate transition patterning flow.

To provide context, the most common method for self-aligned double patterning (SADP) involves the use of a mask to define a set of patterns followed by a spacer process which defines additional features following the removal of the initial pattern. A more recent approach to SADP utilizes a tilted ion implant process to implant an impurity (commonly Argon) into a thin oxide film and then employ etch rate enhancement of Argon-doped oxide to preferentially remove the implanted oxide which allows a pattern to be created beneath. In contrast to known processes, one or more embodiments described herein involve the use of a thin (e.g., 2 nm-20nm) layer of a material with high etch selectivity relative to a wafer substrate or material to be patterned. A thicker hardmask or other etch resistant material is deposed and lithographically etched and patterned into a backbone arrangement on or above the thin layer of a material. The pitch of the backbone is ultimately halved by the use of two ion implant operations which are optimized for their sputtering potential (as described below) and tilted in two orientations such that two regions of the etch-resistant material are sputtered away leaving a central region of the un-sputtered etch-resistant layer. A subsequent etch is then applied to remove the now-exposed substrate material to a defined depth.

Embodiments described herein may be implemented to provide a process for self-aligned double patterning (SADP) or pitch-halving using ion implantation in a sputtering mode to define the additional features. An additional aspect of the present disclosure is possibility of enabling fin-pitch asymmetry upon the die which provides several advantages for engineering process strain in multi-fin devices or for easing later lithographic registration constraints. Processes described herein may be implemented to provide significant operation reduction versus standard SADP processing based on spacer-defined features. Advantages realized from implementing embodiments described herein may include substantial cost reduction and reduced processing time, as well as the opportunity to allow for a variable pitch patterning.

More particularly, in accordance with one or more embodiments of the present disclosure, tilted ion implantation of argon, xenon, or krypton is utilized to enhance an etch rate of an oxide film. In one embodiment, sputter definition of a patterning layer is abrupt and defined by the angle of a shadowed implant beam. In terms of processing operation cost, such embodiments when implemented utilize fewer operations than either an ion-implantation SADP process or a spacer-based SADP process, both of which are described in greater detail below for the purposes of comparison.

By contrast, state of the art patterning approaches rely upon etch-selectivity modulation of an oxide film. However, only 3-5 times etch selectivity enhancement has been experimentally demonstrated for such an effect. State of the art patterning may also rely upon a laterally-abrupt ion implantation profile to limit line-edge roughness. However, an ion implantation profile designed to introduce impurity through a 10 plus nanometer oxide layer introduces

approximately 5 plus nanometers of lightly doped oxide region adjacent to the highly-doped oxide region. The state of the art arrangement tends to exhibit varying degrees of etch rate enhancement yielding increased line-edge roughness and a significant remnant foot in the masking layer.

In an exemplary state of the art approach, SADP is performed utilizing formation of a spacer upon a lithographically-patterned backbone and the use of a lithographically-patterned backbone as a shadow mask for an argon implant designed to modulate the etch rate of an oxide layer on the wafer. The process begins as a hardmask region is lithographically patterned to form a backbone on an oxide layer. Positive and negative angle ion implantation is used to introduce argon ions into regions adjacent to the backbone, but argon is shadowed from being implanted into the central region of the oxide between the backbone features. A selective etch is utilized which removes the argon-doped oxide at a faster rate than the undoped oxide. A selective etch is used to etch the material beneath the oxide. The process is completed with the selective etch of the oxide layer. In another exemplary state of the art approach, a spacer- defined SADP process also begins with formation of a lithographically-patterned backbone. A spacer is formed on each side of the backbone features through use of deposition and dry etch of a material such as an oxide material. A selective etch is then used to remove the backbone features and a dry etch is then used to pattern the material beneath the spacer. The process concludes with an etch process to remove the spacer material.

The above state of the art approach utilizing tilted ion implantation is reliant upon an etch-rate modulation of an argon-doped oxide relative to an undoped oxide. In practice, however, such etch-rate enhancement is limited to approximately 2.8 times for common HF- based wet etch chemistry. Furthermore, an ion implantation profile is not typically laterally abrupt, but rather will be graded over several nanometers. Thus, such relatively modest etch-rate modulation tends to result in line edge roughness and significant footing upon the base of the patterned oxide layer. Others have reported report slightly higher etch rate enhancements than described above, however, they also exhibit stronger gradation between fully implanted and partially implanted regions.

As a result of the above described relatively modest etch-rate enhancement, practical implementations of the SADP process utilizing argon-implanted oxide layers produce a significant remnant foot in the oxide layer which results in significant non-uniformity in the shape of the created features/fins. The outcome is represents a significant limitation for this technique. The relative lack of selectivity can produces a feature (e.g., a first fin) which is significantly different from the features formed by the backbone (e.g., second on third fins on either side of the first fin, the second and third fins having substantially different shape and/or height than the first fin). A further limitation of such a state of the art approach is that it relies upon the etch rate modulation of a silicon dioxide layer, limiting possible variety in material selections.

In contrast to the above state of the art SADP approaches, and as an exemplary processing scheme representative of one or more embodiments of the present disclosure, Figures 1A-1D illustrate cross-sectional views of various operations in a method of fabricating semiconductor fins using a double patterning approach based on sputter defined ion implant features, in accordance with an embodiment of the present disclosure.

Referring to Figure 1 A, a starting structure 100 illustrates a substrate 102 having a non- patterned hardmask layer 104 formed thereon or there above. A dielectric backbone grating structure 106 is formed on or above the non-patterned hardmask layer 104.

In the exemplary embodiment shown, the substrate 102 is a bulk semiconductor substrate, such as a bulk monocrystalline silicon substrate. In an embodiment, the bulk semiconductor substrate 102 is a bulk single crystalline silicon substrate provided having fins 102 etched therein. In one embodiment, the bulk semiconductor substrate 102 is undoped or lightly doped at this stage. For example, in a particular embodiment, the bulk semiconductor substrate 102 has a concentration of less than approximately 1E17 atoms/cm³ of boron dopant impurity atoms.

In other embodiments, the "substrate" is a polycrystalline silicon layer used for forming dummy gate lines. In yet another embodiment, the "substrate" is an inter-layer dielectric (TLD) layer of a BEOL layer.

In an embodiment, the dielectric backbone grating structure 106 is formed using a lithographic process, e.g., a mask and etch process, exemplary lithographic nodes and materials for which are provided below. The dielectric backbone grating structure 106 includes features having a first pitch (PI). In one such embodiment, the number of features of the dielectric backbone grating structure 106 represents essentially half of the possibly number of fins ultimately formed in the substrate 102. That is, the first pitch (PI) is effectively relaxed to double the pitch of the final pattern of fins formed. In one embodiment, the dielectric backbone grating structure 106 is patterned directly using a lithographic process. However, in other embodiments, pitch division is first applied, e.g., pitch halving, and is used to provide dielectric backbone grating structure 106 with the first pitch (PI).

In an embodiment, the features of the dielectric backbone grating structure 106 are between 2 and 5 times taller than the pitch (PI) between adjacent backbone features. Such a ratio may to allow for optimal shadowing in the subsequent process operations described below. It is to be appreciated that the cross-sectional view of Figure 1 A effectively represents ends of relatively long lines that extend into the page.

In an embodiment, the non-patterned hardmask layer 104 is composed of a material selected for its etch selectivity relative to the material below the non-patterned hardmask layer 104 (e.g., relative to a bulk silicon substrate 102). The dielectric backbone grating structure 106 is formed from a material which is designed to provide maximal sputter resistance, as described below. In one embodiment, the non-patterned hardmask layer 104 is or includes a silicon dioxide layer, the substrate 102 is a silicon substrate, and the dielectric backbone grating structure 106 is or includes a silicon nitride layer. In another embodiment, the substrate 102 is a

GaAs or Ge substrate, and the non-patterned hardmask layer 104 includes a material with a highly selective etch characteristic relative to the substrate material.

Referring to Figure IB, a first sputtering implant process 120 is applied to the structure of

Figure 1 A from a first side 106A of the features of the dielectric backbone grating structure 106.

A second sputtering implant process 122 is applied from a second side 106B of the features of the dielectric backbone grating structure 106. A patterned hardmask layer 108 is formed from the non-patterned hardmask layer 104. The patterned hardmask layer 108 has first features 108 A exposed between features of the dielectric backbone grating structure 106, and second features 108B beneath the features of the dielectric backbone grating structure 106. The pitch (P2) between adjacent first 108A and second 108B is half of the pitch (PI).

In an embodiment, the first sputtering implant process 120 and the second sputtering implant process 122 are performed at using positive and negative tilt angles, respectively. The implants remove portions of the non-patterned hardmask layer 104 to provide the patterned hardmask layer 108, as depicted in Figure IB. In a particular embodiment, the region of the non- patterned hardmask layer 104 adjacent to the features of the dielectric backbone grating structure 106 are removed directly via the sputtering processes. In an alternative embodiment, a short duration wet etch follows the sputtering implant processes to remove any small remnant portions of the non-patterned hardmask layer 104 in locations targeted for removal.

It is to be appreciated that one of key differences between the approach described in association with Figure IB and a state of the art ion-implantation approach which modulates the etch rate of silicon dioxide is that the regions of the non-patterned hardmask layer 104 are physically removed by the sputter processes in the present case. In an embodiment, the direct sputter removal results in substantially more abrupt interfaces than modulating etch selectivity. It is to be appreciated, however, that in practice the sputter implants may slightly erode the features of the features of the dielectric backbone grating structure 106 as well as the desired regions of the non-patterned hardmask layer 104 at the inside corners of the features.

Accordingly, in an embodiment, an integrated approach involves use of a slightly larger implant angle magnitude for the second ion implantation operation 122 relative to the first ion

implantation operation 120.

In an embodiment, the ion implantation operations 120 and 122 involve sputtering with a noble gas species (e.g., argon (Ar), krypton (Kr), or xenon (Xe)). In one embodiment, sputtering is performed at an energy between 200eV and 1.5keV. In a specific embodiment, the resulting sputter beams produce a very abrupt patterned edge. In a specific embodiment, for a non- patterned hardmask layer 104 density of 2-5g/cc and a thickness of 10 nanometers, the doses of the ion implantations 120 and 122 are between 5el 5/cm2 to 5el6/cm2. It is to be appreciated that, as a structure result, there may be characteristic faceting of the corner surfaces from the sputter beam. Also, there may be detectable concentrations of the sputter ion (e.g., argon, krypton or xenon) or detectable concentrations of atoms which comprised the hardmask material 104 which were forward-recoiled by the sputter process as detectable by a SIMS measurement.

As an exemplary calculation for sputter beam parameter targeting, Figure 2 is a schematic showing a calculation of implant orientation for a representative structure, in accordance with an embodiment of the present disclosure.

Referring to Figure 2, two features of the dielectric backbone grating structure 106 along with a corresponding portion of the non-patterned hardmask layer 104. Upon performing the first 120 and second 122 sputter processes, regions 222 of the non-patterned hardmask layer 104 are removed to form the patterned layer 204 (corresponding to patterned layer 108 of Figure IB). The patterned layer 204 includes portions 220 of the non-patterned hardmask layer 104 preserved beneath the two features of the dielectric backbone grating structure 106. The patterned layer 204 includes a portion 224 of the non-patterned hardmask layer 104 that is in the shadow of the first 120 and second 122 sputter processes. The result is an effective pitch-halving of the pitch of the features of the dielectric backbone grating structure 106.

In an embodiment, the positive and negative implant angles (2, 1) are determined through the geometry relationship and width of a desired resultant patterned feature. In an exemplary embodiment, the selected parameters include a backbone pitch (PI) of 42 nanometers with a backbone feature width (W) of 10 nanometers and height (H) of 84 nanometers. A desired width of resultant features of 10 nanometers spaced equidistant between adjacent backbone features correlates with positive and negative implant angles calculated as +/- 14 degrees, as shown in Figure 2. It is to be appreciated that different geometries will require different tilt orientations.

In an embodiment, the above described process is illustrated as relying upon a single non- patterned hardmask layer 104. For the purposes of optimizing subsequent etch processing, however, a second non-patterned hardmask layer masking may be utilized beneath the non- patterned hardmask layer 104 to provide further etch resistance to later processing. Such a second non-patterned hardmask layer may also be patterned from the sputter pattern, e.g., in an etch process performed subsequent to the sputter processes. The use of such a second non- patterned hardmask layer could improve the etch resistance during a later etch used to pattern substrate 102.

Referring to Figure 1C, the pattern of the patterned hardmask layer 108 is etched into the substrate 102 to form fins 110 and remaining bulk substrate portion 102'. The fins 110 have first fins 110A exposed between features of the dielectric backbone grating structure 106, and second fins HOB beneath the features of the dielectric backbone grating structure 106. The pitch (P2) between adjacent first 110A and second HOB fins is half of the pitch PI (i.e., P2).

In an embodiment, the pattern of the patterned hardmask layer 108 is etched into the substrate 102 to form fins 110 prior to removal of the dielectric backbone grating structure 106, as is depicted in Figure 1C. In another embodiment, however, the pattern of the patterned hardmask layer 108 is etched into the substrate 102 to form fins 110 subsequent to removal of the dielectric backbone grating structure 106. In either case, following the removal of regions of the non-patterned hardmask layer 104 via the sputter process (and possibly an additional wet etch step), a dry etch process is performed to remove exposed portions of the substrate 102. In an embodiment, the dry etch is designed to be highly selective to the substrate 102 material over the material of the patterned hardmask layer 108. In a particular embodiment, such a dry etch is performed which is highly selective to the substrate 102 material relative and to the dielectric backbone grating structure 106. In one embodiment, the dry etch process involves use of a reactive ion etch, where the patterned hardmask layer 108 is sufficiently thick to provide protection of regions of the substrate directly beneath the features of the patterned hardmask layer 108 during the etching.

Referring to Figure ID, the patterned hardmask layer 108 and, if still present, the dielectric backbone grating structure 106 are removed from the structure of Figure 1C. In an embodiment, the patterned hardmask layer 108 and/or the dielectric backbone grating structure 106 are removing using one or more techniques, such as wet etching, chemical mechanical polishing, etc. The structure of Figure ID may then be subjected to further processing, such as formation of a shallow trench isolation (STI) layer, formation of gate structures, and formation of BEOL layers, exemplary embodiments for which are described below.

Referring again to Figure ID, in accordance with an embodiment of the present disclosure, an integrated circuit structure 150 includes a plurality of semiconductor fins 110 protruding from a substantially planar surface of a substrate 102'. In an embodiment, the substrate 102' is a monocrystalline bulk silicon substrate, and the plurality of semiconductor fins 110 is a plurality of silicon fins continuous with the monocrystalline bulk silicon substrate 102', as is depicted in Figure ID. In an embodiment, the plurality of semiconductor fins 110 has a grating pattern having a constant pitch (P2) between adjacent ones 1 lOA/110B of the plurality of semiconductor fins 110, as is also depicted in Figure ID.

As a result of the sputtering processing described above, in an embodiment, individual ones (1 lOA/110B) of the plurality of semiconductor fins 110 have argon (Ar), xenon (Xe) or krypton (Kr) atoms therein. In one such embodiment, a concentration of the Ar, Xe or Kr atoms along sidewalls 152 of the individual ones 110/110B of the plurality of semiconductor fins 110 is greater than a concentration of the Ar, Xe or Kr atoms in centers 154 of the individual ones

110/110B of the plurality of semiconductor fins 110. In one embodiment, a concentration of the Ar, Xe or Kr atoms in upper portions 156 of the plurality of semiconductor fins 110 is greater than a concentration of the Ar, Xe or Kr atoms in lower portions 158 of the plurality of semiconductor fins 110. In one specific embodiment, the argon (Ar), xenon (Xe) or krypton (Kr) atoms are Xe atoms. In another specific embodiment, the argon (Ar), xenon (Xe) or krypton

(Kr) atoms are Kr atoms. In another specific embodiment, the argon (Ar), xenon (Xe) or krypton (Kr) atoms are Ar atoms. In another specific embodiment, the argon (Ar), xenon (Xe) or krypton (Kr) atoms are a combination of two or more of Xe, Kr and Ar atoms (e.g. an implanted cluster). In an embodiment, with respect to utilizing an implant cluster, representative implant energies will be increased by a factor which is approximately equal to the number of atoms in the cluster, and the implanted dose will be reduced by the same factor. For example, a representative sputter process which requires 5el5/cm2 single-atom singly-ionized Ar ions at IkeV may be

approximately replaced with an ArlOO singly-ionized 100-atom Argon cluster implanted at lOOkeV with a dose of 5el3/cm2. That is, for a cluster implant, the previously representative doses of 5el5 to 5el6 and energies of 0.2 to 1.5keV can be reduced significantly and energy can increase significantly outside these ranges).

In an embodiment, as described in association with Figure 3 A, a trench isolation layer is between the plurality of semiconductor fins 110 and adjacent to the lower portions 158 of the plurality of semiconductor fins 110, but not adjacent to the upper portions 156 of the plurality of semiconductor fins 110. In an embodiment, since such a trench isolation layer is formed after forming performing the sputtering processes 120 and 122, such a trench isolation layer does not include the sputtering species therein. For example, in one embodiment, Xe atoms are used in the sputter processing 120 and 122, and the plurality of fins 110 includes Xe atoms therein, but the trench isolation layer does not include Xe atoms therein. In another embodiment, Kr atoms are used in the sputter processing 120 and 122, and the plurality of fins 110 includes Kr atoms therein, but the trench isolation layer does not include Kr atoms therein. In another embodiment, Ar atoms are used in the sputter processing 120 and 122, and the plurality of fins 110 includes Ar atoms therein, but the trench isolation layer does not include Ar atoms therein.

In an embodiment, the structure of Figure ID may subsequently be subjected to a "fin cut" process where one or more select fins are removed using an etch process. In one

embodiment, the select fins are removed to a level that leaves a protruding portion above the substantially planar surface of the substrate 102' . In another embodiment, the select fins are removed to a level approximately co-planar with the substantially planar surface of the substrate 102' . In another embodiment, the select fins are removed to a level that leaves a recess 148 below the substantially planar surface of the substrate 102'.

In an embodiment, as described in association with Figures 3 A and 3B, the integrated circuit structure 150 is further subjected to fabrication of one or more gate electrode stacks on top surfaces and sidewalls of the upper portions 156 of the plurality of semiconductor fins 110. Source and drain regions are on either side of the one or more gate electrode stacks.

It is to be appreciated that the structures resulting from the above exemplary processing schemes, e.g., structures from Figures IB or 5B (described below), may be used in a same or similar form for subsequent processing operations to complete device fabrication, such as PMOS and MOS device fabrication. As an example of a completed device, Figures 3 A and 3B illustrate a cross-sectional view and a plan view (taken along the a-a' axis of the cross-sectional view), respectively, of a non-planar integrated circuit structure, in accordance with an

embodiment of the present disclosure.

Referring to Figures 3A and 3B, a semiconductor structure or device 300 includes a non- planar active region (e.g., a fin structure including protruding fin portion 304 and sub-fin region 305) formed from substrate 302, and within isolation region 306. A gate line 308 is over the protruding portions 304 of the non-planar active region as well as over a portion of the isolation region 306. Although only one gate line 308 is depicted in Figure 3B, it is to be appreciated that, in accordance with an embodiment of the present disclosure, a plurality of such gate lines 308 is patterned using a sputter-based SADP process scheme as described above.

As shown, gate line 308 includes a gate electrode 350 and a gate dielectric layer 352. In one embodiment, gate line 308 may also include a dielectric cap layer 354. A gate contact 314, and overlying gate contact via 316 are also seen from this perspective, along with an overlying metal interconnect 360, all of which are in inter-layer dielectric stacks or layers 370. Also seen from the perspective of Figure 3 A, the gate contact 314 is, in one embodiment, over isolation region 306, but not over the non-planar active regions. Alternatively, in another embodiment, the gate contact 314 is over one or more of the non-planar active regions to provide a contact over active gate layout.

In an embodiment, the plurality of semiconductor fins 304 have xenon (Xe) or krypton

(Kr) atoms therein. In one such embodiment, a concentration of the Xe or Kr atoms along sidewalls of individual ones of the plurality of semiconductor fins 304 is greater than a concentration of the Xe or Kr atoms in centers of the individual ones of the plurality of semiconductor fins 304. In one embodiment, a concentration of the Xe or Kr atoms in upper portions 304 of the plurality of semiconductor fins is greater than a concentration of the Xe or Kr atoms in lower portions 305 of the plurality of semiconductor fins.

As is also depicted in Figure 3 A, in an embodiment, an interface 380 exists between a protruding fin portion 304 and sub-fin region 305. The interface 380 can be a transition region between a doped sub-fin region 305 and a lightly or undoped upper fin portion 304. In one such embodiment, each fin is approximately 10 nanometers wide or less, and sub-fin dopants are supplied from an adjacent solid state doping layer at the sub-fin location. It is to be appreciated that the lightly or undoped upper fin portion 304 is characterized as such with respect to N-type or P-type dopants. In some embodiments, the lightly or undoped upper fin portion 304 has a substantial amount of Ar, or Xe, or Kr as a result of the sputter-based patterning described above.

Referring to Figure 3B, the gate line 308 is shown as over the protruding fin portions

304. Source and drain regions 304A and 304B of the protruding fin portions 304 can be seen from this perspective. In one embodiment, the source and drain regions 304A and 304B are doped portions of original material of the protruding fin portions 304. In another embodiment, the material of the protruding fin portions 304 is removed and replaced with another

semiconductor material, e.g., by epitaxial deposition. In either case, the source and drain regions 304A and 304B may extend below the height of dielectric layer 306, i.e., into the sub-fin region

305. In accordance with an embodiment of the present disclosure, the more heavily doped sub- fin regions, i.e., the doped portions of the fins below interface 380, inhibits source to drain leakage through this portion of the bulk semiconductor fins.

In an embodiment, the semiconductor structure or device 300 is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines 308 surround at least a top surface and a pair of sidewalls of the three-dimensional body.

Substrate 302 may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, substrate 302 is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof, to form active region 304. In one embodiment, the concentration of silicon atoms in bulk substrate 302 is greater than 97%. In another embodiment, bulk substrate 302 is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. Bulk substrate 302 may alternatively be composed of a group III-V material. In an embodiment, bulk substrate 302 is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, bulk substrate 302 is composed of a III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium. In a particular embodiment, the substrate 302 is a monocrystalline bulk silicon substrate, and the plurality of semiconductor fins 304/305 is a plurality of silicon fins continuous with the monocrystalline bulk silicon substrate.

Isolation region 306 may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, the isolation region 306 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. In an embodiment, the upper fin portions 304 include Xe atoms, but the isolation region 306 does not include Xe atoms. In another embodiment, the upper fin portions 304 include Kr atoms, but the isolation region 306 does not include Kr atoms. In another embodiment, the upper fin portions 304 include Ar atoms, but the isolation region 306 does not include Ar atoms.

Gate line 308 may be composed of a gate electrode stack which includes a gate dielectric layer 352 and a gate electrode layer 350. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-K material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of the substrate 302. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.

In one embodiment, the gate electrode is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-workfunction- setting fill material formed above a metal workfunction-setting layer. The gate electrode layer may consist of a P-type workfunction metal or an N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

Spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

Gate contact 314 and overlying gate contact via 316 may be composed of a conductive material. In an embodiment, one or more of the contacts or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

In an embodiment (although not shown), providing structure 300 involves formation of a contact pattern which is essentially perfectly aligned to an existing gate pattern while eliminating the use of a lithographic operation with exceedingly tight registration budget. In one such embodiment, this approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts.

Furthermore, the gate stack structure 308 may be fabricated by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF₆. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous H4OH or

tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.

In an embodiment, one or more approaches described herein contemplate essentially a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at structure 300. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature anneal of at least a portion of the permanent gate stack. For example, in a specific such embodiment, an anneal of at least a portion of the permanent gate structures, e.g., after a gate dielectric layer is formed, is performed at a temperature greater than approximately 600 degrees Celsius. The anneal is performed prior to formation of the permanent contacts.

Referring again to Figure 3A, the arrangement of semiconductor structure or device 300 places the gate contact over isolation regions. Such an arrangement may be viewed as inefficient use of layout space. In another embodiment, however, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region. In general, prior to (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in a same layer as a trench contact via, one or more embodiments of the present disclosure include first using a gate aligned trench contact process. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, e.g., for integrated circuit fabrication. In an embodiment, a trench contact pattern is formed as aligned to an existing gate pattern. By contrast, conventional approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to an existing gate pattern in combination with selective contact etches. For example, a conventional process may include patterning of a poly (gate) grid with separate patterning of contact features.

It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. For example, in one embodiment, dummy gates need not ever be formed prior to fabricating gate contacts over active portions of the gate stacks. The gate stacks described above may actually be permanent gate stacks as initially formed. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a trigate device, an independently accessed double gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a 10 nanometer (10 nm) or smaller technology node.

In another aspect, information regarding the material properties of a masking layer, such as non-patterned hardmask layer 104 described above, allows for a sputtering yield to be determined for a given beam species and beam tilt in a sputter patterning process. An example using silicon dioxide as a non-patterned hardmask layer, Figure 4 is a plot 400 showing a sputtering yield simulation, in accordance with one or more embodiments of the present disclosure. The energetic distribution of sputtered atoms from an S1O2 masking layer for an incident xenon beam is shown in plot 400. The ions to the right of 3.4eV (e.g., the surface binding energy of the system) are removed from the surface by the ion beam. The integrated quantity of the ions reflects the sputtering yield.

In another aspect, an SADP process described herein allows for fabrication of an asymmetrical fin layout. In particular, features may be fabricated as offset from the midpoint of the backbone features. Such an approach permits several process variations, particularly as they apply to multiple-fin devices. Applications for stress enhancement and registration tolerance may also be enabled by such an asymmetric approach.

As an example of asymmetric patterning, Figures 5A and 5B illustrate cross-sectional views of various operations in another method of fabricating semiconductor fins using a double patterning approach based on sputter defined ion implant features, in accordance with another embodiment of the present disclosure.

Referring to Figure 5 A, the approach essentially begins using structure 100 of Figure 1 A. However, the sputtering angles of processes 120 and 122 are no longer complementary as was described in association with Figures IB and 2. Instead, one angle is substantially larger than the other. Such asymmetric sputtering situates newly created features offset from the midpoint of the back bone features.

Referring to Figure 5 A, first and second sputtering implant processes are performed to provide a patterned hardmask layer 508. The patterned hardmask layer 508 alternating features exposed between features of the dielectric backbone grating structure 106, and features beneath the features of the dielectric backbone grating structure 106.

Referring to Figure 5B, the pattern of the patterned hardmask layer 508 is etched into the substrate 102 to form fins 510 and remaining bulk substrate portion 502" . In an embodiment, the fins 510 protrude from a substantially planar surface of the substrate 102" to provide a grating pattern, as is depicted in Figure 5D. The grating pattern includes repeating pairs 51 OA of adj acent ones of the plurality of semiconductor fins 510. The grating pattern has a first pitch

(P3) for each pair 51 OA of adjacent ones of the plurality of semiconductor fins 510, and a second pitch (P4) between adjacent pairs 51 OA of the plurality of semiconductor fins 510. The second pitch (P4) is greater than the first pitch (P3).

In an embodiment, the structure of Figure 5B (referred to as an asymmetrical fin orientation) is fabricated on only a portion of a die or wafer (with regularly-spaced fins formed elsewhere on the same die or wafer through use of an additional lithographic operation). In another embodiment, the structure of Figure 5B is formed as such on an entirety of the die or wafer.

In another aspect, Figure 6 illustrates a cross-sectional view of a stack of metallization layers in an integrated circuit, in accordance with an embodiment of the present disclosure.

Referring to Figure 6, an integrated circuit structure 650 includes a plurality of metallization layers 652 above a substrate 602. Each of the metallization layers of the plurality of metallization layers 652 includes conductive lines and interlayer dielectric (ILD) layer(s). The metallization layers may be patterned in a grating-like pattern. In the specific example of Figure 6, the integrated circuit structure 650 includes lower eight matched metal layers 654, 656, 658, 660, 662, 664, 666 and 668. Thicker/wider metal lines 670 and 672 are fabricated on the lower eight matched metal layers 654, 656, 658, 660, 662, 664, 666 and 668. Via locations 674 are depicted as connecting the lower eight matched metal layers 654, 656, 658, 660, 662, 664, 666 and 668.

With reference again to Figure 6, in an embodiment, an integrated circuit structure 650 includes a plurality of trenches 698 in an inter-layer dielectric (ILD) layer 699 above a substrate 602. Regions 699A of the ILD layer 699 between individual ones of the plurality of trenches 698 have xenon (Xe) or krypton (Kr) atoms (or Ar atoms) therein. A concentration of the Xe or Kr (or Ar) atoms in upper portions of the regions 699A of the ILD layer 699 between individual ones of the plurality of trenches 698 is greater than a concentration of the Xe or Kr (or Ar) atoms in lower portions of the regions 699A of the ILD layer 699 between individual ones of the plurality of trenches 698. A plurality of conductive interconnects 654 is in corresponding ones of the plurality of trenches 698.

In an embodiment, the regions 699A of the ILD layer 699 between individual ones of the plurality of trenches 698 have atoms from a sputter patterning SADP process scheme therein, while the plurality of conductive interconnects 654 does not include the sputter atoms since they are formed in the trenches subsequent to patterning the trenches. In one embodiment, regions 699A of the ILD layer 699 between individual ones of the plurality of trenches 698 have Xe atoms therein, and the plurality of conductive interconnects 654 does not include Xe atoms therein. In one embodiment, regions 699A of the ILD layer 699 between individual ones of the plurality of trenches 698 have Kr atoms therein, and the plurality of conductive interconnects 654 does not include Kr atoms therein. In an embodiment, regions 699A of the ILD layer 699 between individual ones of the plurality of trenches 698 have Ar atoms therein, and the plurality of conductive interconnects 654 does not include Ar atoms therein.

In an embodiment, the plurality of trenches 698 has a grating pattern having a constant pitch (P5) between adjacent ones of the plurality of trenches 698, as is depicted in Figure 6. In another embodiment, now shown, the plurality of trenches has a grating pattern including repeating pairs of adjacent ones of the plurality of trenches, the grating pattern having a first pitch for each pair of adjacent ones of the plurality of trenches and a second pitch between adjacent pairs of the plurality of trenches, the second pitch greater than the first pitch, similar to the pattern described in association with Figure 5B.

It is to be appreciated that the layers and materials described in association with Figure 6 are typically formed on or above an underlying semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying

semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, although not depicted, the structure depicted in Figure 6 may be fabricated on underlying lower level back end of line (BEOL) interconnect layers.

In an embodiment, as used throughout the present description, interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (S1O2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In an embodiment, as is also used throughout the present description, metal lines or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect.

In an embodiment, as is also used throughout the present description, hardmask materials are composed of dielectric materials different from the interlayer dielectric material. In some embodiments, a hardmask layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a hardmask material includes a metal species. For example, a hardmask or other overlying material may include a layer of a nitride of titanium or another metal (e.g., titanium nitride). Potentially lesser amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hardmask layers known in the arts may be used depending upon the particular implementation. The hardmask layers maybe formed by CVD, PVD, or by other deposition methods. In an embodiment, as is also used throughout the present description, lithographic operations are performed using 193nm immersion litho (i 193), EUV and/or EBDW lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti- reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti -reflective coating layer is a silicon ARC layer.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

Figure 7 illustrates a computing device 700 in accordance with one implementation of an embodiment of the present disclosure. The computing device 700 houses a board 702. The board 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some implementations the at least one communication chip 706 is also physically and electrically coupled to the board 702. In further implementations, the communication chip 706 is part of the processor 704.

Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more integrated circuit structures, such as fins, gate lines, or interconnect trenches, built in accordance with double patterning implementations of embodiments of the disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In accordance with another implementation of the disclosure, the integrated circuit die of the communication chip includes one or more integrated circuit structures, such as fins, gate lines, or interconnect trenches, built in accordance with double patterning implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device 700 may contain an integrated circuit die that includes one or more integrated circuit structures, such as fins, gate lines, or interconnect trenches, built in accordance with double patterning implementations of embodiments of the disclosure.

In various embodiments, the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultramobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.

Figure 8 illustrates an interposer 800 that includes one or more embodiments of the present disclosure. The interposer 800 is an intervening substrate used to bridge a first substrate 802 to a second substrate 804. The first substrate 802 may be, for instance, an integrated circuit die. The second substrate 804 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 800 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 800 may couple an integrated circuit die to a ball grid array (BGA) 806 that can subsequently be coupled to the second substrate 804. In some embodiments, the first and second substrates 802/804 are attached to opposing sides of the interposer 800. In other embodiments, the first and second substrates 802/504 are attached to the same side of the interposer 800. And in further embodiments, three or more substrates are interconnected by way of the interposer 800.

In an embodiment, the first substrate 802 is an integrated circuit die including one or more integrated circuit structures, such as fins, gate lines, or interconnect trenches, built in accordance with double patterning implementations of embodiments of the disclosure. In an embodiment, the second substrate 804 is a memory module, a computer motherboard, or another integrated circuit die including one or more integrated circuit structures, such as fins, gate lines, or interconnect trenches, built in accordance with double patterning implementations of embodiments of the disclosure.

The interposer 800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 808 and vias 810, including but not limited to through-silicon vias (TSVs) 812. The interposer 800 may further include embedded devices 814, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 800. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer 800.

Thus, embodiments of the present disclosure include double patterning approaches based on sputter defined ion implant features, and integrated circuit structures resulting therefrom.

The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example embodiment 1 : An integrated circuit structure includes a plurality of semiconductor fins protruding from a substantially planar surface of a substrate. Individual ones of the plurality of semiconductor fins have xenon (Xe) or krypton (Kr) atoms therein. A concentration of the Xe or Kr atoms along sidewalls of the individual ones of the plurality of semiconductor fins is greater than a concentration of the Xe or Kr atoms in centers of the individual ones of the plurality of semiconductor fins. A concentration of the Xe or Kr atoms in upper portions of the plurality of semiconductor fins is greater than a concentration of the Xe or Kr atoms in lower portions of the plurality of semiconductor fins.

Example embodiment 2: The integrated circuit structure of example embodiment 1, further including a trench isolation layer between the plurality of semiconductor fins and adjacent to the lower portions of the plurality of semiconductor fins, but not adjacent to the upper portions of the plurality of semiconductor fins.

Example embodiment 3 : The integrated circuit structure of example embodiment 2, wherein the trench isolation layer does not include Xe atoms therein, and wherein the trench isolation layer does not include Kr atoms therein.

Example embodiment 4: The integrated circuit structure of example embodiment 1, 2 or 3, further including one or more gate electrode stacks on top surfaces and sidewalls of the upper portions of the plurality of semiconductor fins, and source and drain regions on either side of the one or more gate electrode stacks.

Example embodiment 5: The integrated circuit structure of example embodiment 1, 2, 3 or 4, wherein the plurality of semiconductor fins has a grating pattern having a constant pitch between adjacent ones of the plurality of semiconductor fins.

Example embodiment 6: The integrated circuit structure of example embodiment 1, 2, 3 or 4, wherein the plurality of semiconductor fins has a grating pattern including repeating pairs of adjacent ones of the plurality of semiconductor fins, the grating pattern having a first pitch for each pair of adjacent ones of the plurality of semiconductor fins and a second pitch between adjacent pairs of the plurality of semiconductor fins, the second pitch greater than the first pitch.

Example embodiment 7: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5 or 6, wherein the xenon (Xe) or krypton (Kr) atoms are Xe atoms.

Example embodiment 8: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6 or 7, wherein the xenon (Xe) or krypton (Kr) atoms are Kr atoms.

Example embodiment 9: The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7 or 8, wherein the substrate is a monocrystalline bulk silicon substrate, and wherein the plurality of semiconductor fins is a plurality of silicon fins continuous with the monocrystalline bulk silicon substrate.

Example embodiment 10: An integrated circuit structure includes a plurality of semiconductor fins protruding from a substantially planar surface of a substrate. The plurality of semiconductor fins has a grating pattern including repeating pairs of adjacent ones of the plurality of semiconductor fins. The grating pattern has a first pitch for each pair of adjacent ones of the plurality of semiconductor fins and a second pitch between adjacent pairs of the plurality of semiconductor fins. The second pitch is greater than the first pitch.

Example embodiment 11 : The integrated circuit structure of example embodiment 10, further including a trench isolation layer between the plurality of semiconductor fins and adj acent to lower portions of the plurality of semiconductor fins, but not adj acent to upper portions of the plurality of semiconductor fins. One or more gate electrode stacks are on top surfaces and sidewalls of the upper portions of the plurality of semiconductor fins and on portions of the trench isolation layer. Source and drain regions are on either side of the one or more gate electrode stacks.

Example embodiment 12: The integrated circuit structure of example embodiment 10 or

11, wherein the substrate is a monocrystalline bulk silicon substrate, and wherein the plurality of semiconductor fins is a plurality of silicon fins continuous with the monocrystalline bulk silicon substrate.

Example embodiment 13: An integrated circuit structure includes a plurality of trenches in an inter-layer dielectric (ILD) layer above a substrate. Regions of the ILD layer between individual ones of the plurality of trenches have xenon (Xe) or krypton (Kr) atoms therein. A concentration of the Xe or Kr atoms in upper portions of the regions of the ILD layer between individual ones of the plurality of trenches is greater than a concentration of the Xe or Kr atoms in lower portions of the regions of the ILD layer between individual ones of the plurality of trenches. A plurality of conductive interconnects is in corresponding ones of the plurality of trenches.

Example embodiment 14: The integrated circuit structure of example embodiment 13, wherein the plurality of conductive interconnects does not include Xe atoms therein, and wherein the plurality of conductive interconnects does not include Kr atoms therein.

Example embodiment 15: The integrated circuit structure of example embodiment 13 or

14, wherein the plurality of trenches has a grating pattern having a constant pitch between adjacent ones of the plurality of trenches.

Example embodiment 16: The integrated circuit structure of example embodiment 13 or 14, wherein the plurality of trenches has a grating pattern including repeating pairs of adjacent ones of the plurality of trenches, the grating pattern having a first pitch for each pair of adjacent ones of the plurality of trenches and a second pitch between adjacent pairs of the plurality of trenches, the second pitch greater than the first pitch.

Example embodiment 17: The integrated circuit structure of example embodiment 13, 14, 15 or 16, wherein the xenon (Xe) or krypton (Kr) atoms are Xe atoms.

Example embodiment 18: The integrated circuit structure of example embodiment 13,

14, 15, 16 or 17, wherein the xenon (Xe) or krypton (Kr) atoms are Kr atoms.

Example embodiment 19: A method of fabricating an integrated circuit structure includes forming a non-patterned hardmask layer above a substrate or layer for patterning. The method also includes forming a dielectric backbone grating structure on or above the non- patterned hardmask layer. The method also includes performing a first sputtering implant process at a first tilted angle from a first side of the features of the dielectric backbone grating structure. The method also includes performing a second sputtering implant process at a second tilted angle from a second side of the features of the dielectric backbone grating structure, the second side opposite the first side, wherein the first and second sputtering implant processes form a patterned hardmask layer from the non-patterned hardmask layer, the patterned hardmask layer having first features exposed between features of the dielectric backbone grating structure and second features beneath the features of the dielectric backbone grating structure. The method also includes using the patterned hardmask layer to pattern the underlying substrate or layer for patterning.

Example embodiment 20: The method of example embodiment 19, wherein the underlying substrate or layer for patterning is a bulk monocrystalline silicon substrate, and the patterning forms a plurality of fins.

Example embodiment 21 : The method of example embodiment 19, wherein the underlying substrate or layer for patterning is a polycrystalline silicon layer, and the patterning forms a plurality of dummy gate lines. Example embodiment 22: The method of example embodiment 19, wherein the underlying substrate or layer for patterning is back end of line (BEOL) inter-layer dielectric (ILD) layer, and the patterning forms a plurality of trenches for conductive interconnects.

Example embodiment 23: The method of example embodiment 19, 20, 21 or 22, wherein the first and second sputtering implant processes are based on xenon (Xe).

Example embodiment 24: The method of example embodiment 19, 20, 21 or 22, wherein the first and second sputtering implant processes are based on krypton (Kr).

Example embodiment 25: The method of example embodiment 19, 20, 21 or 22, wherein the first and second sputtering implant processes are based on argon (Ar).

Claims

CLAIMS What is claimed is:

1. An integrated circuit structure, comprising:

a plurality of semiconductor fins protruding from a substantially planar surface of a substrate, individual ones of the plurality of semiconductor fins having xenon (Xe) or krypton (Kr) atoms therein, wherein a concentration of the Xe or Kr atoms along sidewalls of the individual ones of the plurality of semiconductor fins is greater than a concentration of the Xe or Kr atoms in centers of the individual ones of the plurality of semiconductor fins, and wherein a concentration of the Xe or Kr atoms in the upper portions of the plurality of semiconductor fins is greater than a concentration of the Xe or Kr atoms in the lower portions of the plurality of semiconductor fins.

2. The integrated circuit structure of claim 1, further comprising:

a trench isolation layer between the plurality of semiconductor fins and adjacent to the lower portions of the plurality of semiconductor fins, but not adjacent to the upper portions of the plurality of semiconductor fins.

3. The integrated circuit structure of claim 2, wherein the trench isolation layer does not include Xe atoms therein, and wherein the trench isolation layer does not include Kr atoms therein.

4. The integrated circuit structure of claim 1, further comprising:

one or more gate electrode stacks on top surfaces and sidewalls of the upper portions of the plurality of semiconductor fins; and

source and drain regions on either side of the one or more gate electrode stacks.

5. The integrated circuit structure of claim 1, wherein the plurality of semiconductor fins has a grating pattern having a constant pitch between adjacent ones of the plurality of semiconductor fins.

6. The integrated circuit structure of claim 1, wherein the plurality of semiconductor fins has a grating pattern comprising repeating pairs of adjacent ones of the plurality of semiconductor fins, the grating pattern having a first pitch for each pair of adjacent ones of the plurality of semiconductor fins and a second pitch between adjacent pairs of the plurality of semiconductor fins, the second pitch greater than the first pitch.

7. The integrated circuit structure of claim 1, wherein the xenon (Xe) or krypton (Kr) atoms are Xe atoms.

8. The integrated circuit structure of claim 1, wherein the xenon (Xe) or krypton (Kr) atoms are Kr atoms.

9. The integrated circuit structure of claim 1, wherein the substrate is a monocrystalline bulk silicon substrate, and wherein the plurality of semiconductor fins is a plurality of silicon fins continuous with the monocrystalline bulk silicon substrate.

10. An integrated circuit structure, comprising:

a plurality of semiconductor fins protruding from a substantially planar surface of a substrate, wherein the plurality of semiconductor fins has a grating pattern comprising repeating pairs of adjacent ones of the plurality of semiconductor fins, the grating pattern having a first pitch for each pair of adjacent ones of the plurality of semiconductor fins and a second pitch between adjacent pairs of the plurality of semiconductor fins, the second pitch greater than the first pitch.

11. The integrated circuit structure of claim 10, further comprising:

a trench isolation layer between the plurality of semiconductor fins and adjacent to lower portions of the plurality of semiconductor fins, but not adjacent to upper portions of the plurality of semiconductor fins;

one or more gate electrode stacks on top surfaces and sidewalls of the upper portions of the plurality of semiconductor fins and on portions of the trench isolation layer; and source and drain regions on either side of the one or more gate electrode stacks.

12. The integrated circuit structure of claim 10, wherein the substrate is a monocrystalline bulk silicon substrate, and wherein the plurality of semiconductor fins is a plurality of silicon fins continuous with the monocrystalline bulk silicon substrate.

13. An integrated circuit structure, comprising:

a plurality of trenches in an inter-layer dielectric (ILD) layer above a substrate, wherein

regions of the ILD layer between individual ones of the plurality of trenches have xenon (Xe) or krypton (Kr) atoms therein, wherein a concentration of the Xe or Kr atoms in upper portions of the regions of the ILD layer between individual ones of the plurality of trenches is greater than a concentration of the Xe or Kr atoms in lower portions of the regions of the ILD layer between individual ones of the plurality of trenches; and a plurality of conductive interconnects in corresponding ones of the plurality of trenches.

14. The integrated circuit structure of claim 13, wherein the plurality of conductive

interconnects does not include Xe atoms therein, and wherein the plurality of conductive interconnects does not include Kr atoms therein.

15. The integrated circuit structure of claim 13, wherein the plurality of trenches has a grating pattern having a constant pitch between adjacent ones of the plurality of trenches.

16. The integrated circuit structure of claim 13, wherein the plurality of trenches has a grating pattern comprising repeating pairs of adjacent ones of the plurality of trenches, the grating pattern having a first pitch for each pair of adj acent ones of the plurality of trenches and a second pitch between adjacent pairs of the plurality of trenches, the second pitch greater than the first pitch.

17. The integrated circuit structure of claim 13, wherein the xenon (Xe) or krypton (Kr) atoms are Xe atoms.

18. The integrated circuit structure of claim 13, wherein the xenon (Xe) or krypton (Kr) atoms are Kr atoms.

19. A method of fabricating an integrated circuit structure, the method comprising:

forming a non-patterned hardmask layer above a substrate or layer for patterning;

forming a dielectric backbone grating structure on or above the non-patterned hardmask layer;

performing a first sputtering implant process at a first tilted angle from a first side of the features of the dielectric backbone grating structure;

performing a second sputtering implant process at a second tilted angle from a second side of the features of the dielectric backbone grating structure, the second side opposite the first side, wherein the first and second sputtering implant processes form a patterned hardmask layer from the non-patterned hardmask layer, the patterned hardmask layer having first features exposed between features of the dielectric backbone grating structure and second features beneath the features of the dielectric backbone grating structure; and using the patterned hardmask layer to pattern the underlying substrate or layer for patterning.

20. The method of claim 19, wherein the underlying substrate or layer for patterning is a bulk monocrystalline silicon substrate, and the patterning forms a plurality of fins.

21. The method of claim 19, wherein the underlying substrate or layer for patterning is a polycrystalline silicon layer, and the patterning forms a plurality of dummy gate lines.

22. The method of claim 19, wherein the underlying substrate or layer for patterning is back end of line (BEOL) inter-layer dielectric (TLD) layer, and the patterning forms a plurality of trenches for conductive interconnects.

23. The method of claim 19, wherein the first and second sputtering implant processes are based on xenon (Xe).

24. The method of claim 19, wherein the first and second sputtering implant processes are based on krypton (Kr).

25. The method of claim 19, wherein the first and second sputtering implant processes are based on argon (Ar).