WO2018233402A1 - 电流比较电路、显示装置及其驱动方法 - Google Patents

电流比较电路、显示装置及其驱动方法 Download PDF

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Publication number
WO2018233402A1
WO2018233402A1 PCT/CN2018/086807 CN2018086807W WO2018233402A1 WO 2018233402 A1 WO2018233402 A1 WO 2018233402A1 CN 2018086807 W CN2018086807 W CN 2018086807W WO 2018233402 A1 WO2018233402 A1 WO 2018233402A1
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WIPO (PCT)
Prior art keywords
inverting input
current
power supply
display device
comparator
Prior art date
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Ceased
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PCT/CN2018/086807
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English (en)
French (fr)
Inventor
王亚冉
张伟
孙继刚
孙伟
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Application filed by BOE Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/096,607 priority Critical patent/US10706759B2/en
Publication of WO2018233402A1 publication Critical patent/WO2018233402A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display technologies, and more particularly to a current circuit, a display device, and a driving method thereof.
  • Portable electronic devices such as mobile phones have become very common in everyday life. Standby duration is an area of concern for users of portable electronic devices. In a scene that is used violently (for example, playing a video), the power consumption of the portable electronic device increases, meaning that the standby time will be shortened. Display effects are another aspect of concern for users of portable electronic devices. When viewing video content, smooth picture presentation is what the user expects. This requires a larger refresh rate for the displayed picture to be refreshed.
  • a current comparison circuit for a display device is provided.
  • the display device is configured to be supplied with a plurality of power supply voltages for supplying power to the digital portion and the analog portion of the display device through respective power supply paths.
  • the current comparison circuit includes a plurality of comparator circuits, each comparator circuit being configured to compare currents on a respective one of the respective power supply paths with respective reference values and output respective comparison values. The combination of the respective comparison values output by the respective comparator circuits indicates the type of content being displayed by the display device.
  • the plurality of supply voltages includes a digital supply voltage for powering the digital portion of the display device, an analog supply positive voltage for powering the analog portion of the display device, And an analog power supply negative voltage for supplying power to the analog portion of the display device.
  • the plurality of comparator circuits includes: a first comparator circuit configured to compare a first current on the power supply path for the digital supply voltage with a first reference value; a second comparator circuit, Configuring to compare a second current on the power supply path for the analog power supply positive voltage with a second reference value; and a third comparator circuit configured to be used for the analog power supply negative voltage The third current on the power supply path is compared to a third reference value.
  • the first comparator circuit includes: a first comparator having a non-inverting input and an inverting input; and a first resistor coupled to the ground and the non-inverting input or the inverting Between one of the inputs for directing the first current to the ground.
  • the other of the non-inverting input or the inverting input is configured to receive a first reference voltage indicative of the first reference value.
  • the first comparator circuit further includes a second resistor coupled between the ground and the other of the non-inverting input or the inverting input for A reference current is directed to the ground to establish the first reference voltage at the other of the non-inverting input or the inverting input.
  • the first resistor and the second resistor have equal resistance values.
  • the second comparator circuit includes: a second comparator having a non-inverting input and an inverting input; and a third resistor coupled to the ground and the non-inverting input or the inverting Between one of the inputs for directing the second current to the ground.
  • the other of the non-inverting input or the inverting input is configured to receive a second reference voltage indicative of the second reference value.
  • the second comparator circuit further includes a fourth resistor coupled between the ground and the other of the non-inverting input or the inverting input for A second reference current is directed to the ground to establish the second reference voltage at the other of the non-inverting input or the inverting input.
  • the third resistor and the fourth resistor have equal resistance values.
  • the third comparator circuit includes: a third comparator having a non-inverting input and an inverting input; and a fifth resistor coupled to the ground and the non-inverting input or the inverting Between one of the inputs for directing the third current to the ground.
  • the other of the non-inverting input or the inverting input is configured to receive a third reference voltage indicative of the third reference value.
  • the third comparator circuit further includes a sixth resistor coupled between the ground and the other of the non-inverting input or the inverting input for A third reference current is directed to the ground to establish the third reference voltage at the other of the non-inverting input or the inverting input.
  • the fifth resistor and the sixth resistor have equal resistance values.
  • a display device including: a gate driver configured to sequentially output a plurality of scan signals; a data driver configured to output in synchronization with each of the scan signals a data signal; a power source configured to supply a plurality of power supply voltages for supplying power to the digital portion and the analog portion of the display device through respective power supply paths; a current comparison circuit as described above; and a timing controller configured to respond
  • the gate driver and the data driver are controlled to operate at different refresh frequencies at different combinations of respective comparison values output by the respective comparator circuits.
  • a method of driving a display device includes a gate driver, a data driver, a power source configured to supply power to the digital portion and the analog portion of the display device through respective power supply paths, a current comparison circuit, and a timing controller.
  • the method includes comparing, by the current comparison circuit, a current on each of the respective power supply paths with a corresponding reference value; in response to the comparing, outputting the plurality of comparison values by the current comparison circuit;
  • the gate driver and the data driver are controlled to operate at different refresh frequencies by the timing controller in response to different combinations of the comparison values.
  • FIG. 1 is a schematic block diagram of a display device in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic block diagram of a timing controller included in the display device shown in FIG. 1;
  • FIG. 3 is a schematic diagram of a current comparison circuit in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a schematic view showing transmission characteristics of the first comparator circuit shown in FIG. 3;
  • FIG. 5 is a flow chart of a method of driving a display device in accordance with an embodiment of the present disclosure.
  • FIG. 1 is a schematic block diagram of a display device 100 in accordance with an embodiment of the present disclosure.
  • the display device 100 includes a power source 110, a current comparison circuit 120, a gamma voltage generator 130, a display panel 140, a timing controller 150, a gate driver 160, and a data driver 170.
  • a power source 110 such as a DC/DC converter, generates a plurality of supply voltages from the input voltage VCC.
  • the supply voltage includes a digital supply voltage IOVCC, an analog supply positive voltage VSP, and an analog supply negative voltage VSN.
  • Digital supply voltage IOVCC is used to power the digital portion of display device 100, including, for example, timing controller 150, gate driver 160, a portion of data driver 170, and a portion of gamma voltage generator 130.
  • Both the analog power supply positive voltage VSP and the analog power supply negative voltage VSN are used to supply power to the analog portion of the display device 100, which includes, for example, another portion of the data driver 170 and another portion of the gamma voltage generator 130.
  • the power source 110 also supplies the gate turn-on voltage Von and the gate-off voltage Voff to the gate driver 160.
  • the power supply voltages listed above are exemplary, and depending on the type of display device 100, the power supply 110 can generate other supply voltages.
  • the analog power supply positive voltage VSP and the analog power supply negative voltage VSN may not be generated, and instead a single analog power supply voltage AVDD is generated.
  • the digital power supply voltage IOVCC, the analog power supply positive voltage VSP, and the analog power supply negative voltage VSN generated by the power source 110 are supplied to the gamma voltage generator 130, the timing controller via respective power supply paths (indicated by the arrowed lines in FIG. 1). 150.
  • the load of the power source 110 varies depending on the type of content being displayed by the display panel 140 such that the currents I IOVCC , I VSP , and I VSN on the respective power supply paths vary depending on the type of content being displayed. For example, when the display panel 140 is playing a dynamic picture, the power consumption of the data driver 170 is increased, resulting in increased currents I IOVCC , I VSP , and I VSN .
  • the power consumption of the data driver 170 is reduced, resulting in reduced currents I IOVCC , I VSP , and I VSN .
  • the magnitudes of the currents I IOVCC , I VSP , and I VSN may indicate the type of content being displayed.
  • the concept of the present disclosure has been proposed in which the refresh rate of the screen displayed by the display panel 140 is refreshed according to the magnitude of the current on each power supply path, so that the tuned refresh frequency is adapted to be displayed.
  • the type of content. Tuning of the refresh frequency would be advantageous as it allows for reduced power consumption while providing the desired display effect.
  • a current comparison circuit 120 is provided for comparing the current on each of the power supply paths with a corresponding reference value and outputting a plurality of comparison values, as shown in FIG.
  • current comparison circuit 120 outputs comparison values C1, C2, and C3 in response to a comparison between currents I IOVCC , I VSP , and I VSN and respective reference values.
  • comparison values C1, C2, and C3 may indicate different types of content being displayed. Details of the current comparison circuit 120 will be further described later.
  • the gamma voltage generator 130 generates a series of gamma voltages as a voltage reference for the data driver 170.
  • the gamma voltage generator 130 can be implemented by any known or future technology.
  • gamma voltage generator 130 may include a digital circuit portion powered by digital supply voltage IOVCC and an analog circuit portion powered by analog supply positive voltage VSP and analog supply negative voltage VSN.
  • the display panel 140 includes a plurality of gate lines GL extending in a first direction, a plurality of data lines DL extending in a second direction crossing the first direction, and a plurality of pixels PX arranged in a matrix. Each of the pixels PX is electrically connected to a corresponding one of the gate lines GL and a corresponding one of the data lines DL.
  • the timing controller 150 controls the operations of the display panel 140, the gate driver 160, and the data driver 170.
  • the timing controller 150 retrieves the input image data RGBD from a memory (not shown).
  • the input image data RGBD includes input pixel data for a plurality of pixels PX, each of the input pixel data may include red gradation data R, green gradation data G, or blue for a corresponding one of the plurality of pixels PX Grayscale data B.
  • the timing controller 150 also receives the main clock signal MCLK from a clock generator or a host controller (not shown), and receives the comparison values C1, C2, and C3 from the current comparison circuit 120.
  • the timing controller 150 generates output image data RGBD', a first control signal CONT1, and a second control signal CONT2 based on the input image data RGBD, the main clock signal MCLK, and the comparison values C1, C2, C3.
  • the output image data RGBD' is supplied to the data driver 170.
  • the output image data RGBD' may be substantially the same image data as the input image data RGBD.
  • the output image data RGBD' may be compensated image data generated by compensating the input image data RGBD.
  • the first control signal CONT1 is supplied to the gate driver 160, and the driving timing of the gate driver 160 can be controlled based on the first control signal CONT1.
  • the second control signal CONT2 is supplied to the data driver 170, and the driving timing of the data driver 170 can be controlled based on the second control signal CONT2.
  • the gate driver 160 receives the first control signal CONT1 from the timing controller 150.
  • the gate driver 160 is configured to sequentially output a plurality of scan signals to the gate lines GL based on the first control signal CONT1.
  • the gate driver 160 can be integrated in the display panel 140.
  • the gate driver 160 may be connected to the display panel 140 by, for example, a Tape Carrier Package (TCP).
  • TCP Tape Carrier Package
  • the data driver 170 receives the second control signal CONT2 and the output image data RGBD' from the timing controller 150.
  • the data driver 170 is configured to generate a plurality of data signals based on the second control signal CONT2 and the output image data RGBD'.
  • the data driver 170 is also configured to output the plurality of data signals to the data line DL in synchronization with each of the scan signals output by the gate driver 160.
  • data driver 170 may include a digital circuit portion powered by digital supply voltage IOVCC and an analog circuit portion powered by analog supply positive voltage VSP and analog supply negative voltage VSN.
  • data driver 170 can include a shift register, a latch, a digital to analog converter, and a buffer.
  • the shift register outputs a latch pulse to the latch.
  • the latch temporarily stores the output image data RGBD' and outputs the output image data RGBD' to the digital-to-analog converter.
  • the digital-to-analog converter generates an analog data signal based on the output image data RGBD' from the timing controller 150 and the gamma voltage from the gamma voltage generator 130, and outputs the analog data signal to the buffer.
  • the buffer outputs an analog data signal to the data line DL.
  • FIG. 2 is a schematic block diagram of a timing controller 150 included in the display device 100 illustrated in FIG. 1.
  • the timing controller 150 includes a data compensator 152, a mode selector 154, and a control signal generator 156.
  • the timing controller 150 is illustrated in FIG. 2 as being divided into three elements, although the timing controller 150 may not be physically divided.
  • the data compensator 152 receives the input image data RGBD, and can generate the output image data RGBD' by selectively compensating the input image data RGBD.
  • data compensator 152 can selectively perform image quality compensation, point compensation, adaptive color correction (ACC), and/or dynamic capacitance compensation (DCC) for input image data RGBD to generate output image data RGBD'.
  • data compensator 152 can include a single line memory that stores pixel data corresponding to a single row of pixels. Data compensator 152 can be optional.
  • the mode selector 154 receives the comparison values C1, C2, and C3 from the current comparison circuit 120. As described earlier, the combination of comparison values C1, C2, and C3 may indicate the type of content being displayed. In response to different combinations of comparison values C1, C2, and C3, mode selection module 154 determines different operating modes to adjust the refresh rate at which the display screen is refreshed. In particular, mode selection module 154 can select an appropriate clock frequency (eg, pixel clock frequency) and generate the required time parameters (eg, horizontal scan period, horizontal blanking duration, vertical blanking duration, etc.). In some embodiments, the adjustment of the refresh rate can be implemented using the mechanisms described in Chinese Patent Application Publication No. WO 106205460 A, the entire disclosure of which is incorporated herein by reference. In other embodiments, any other suitable mechanism can be used.
  • an appropriate clock frequency eg, pixel clock frequency
  • the required time parameters eg, horizontal scan period, horizontal blanking duration, vertical blanking duration, etc.
  • the control signal generator 156 generates a first control signal CONT1 for the gate driver 160 of FIG. 1 and for the data driver 170 of FIG. 1 based on the time parameter generated by the mode selector 154 and the received main clock signal MCLK.
  • the first control signal CONT1 may include a vertical enable signal, a gate clock signal, etc.
  • the second control signal CONT2 may include a horizontal enable signal, a data clock signal, a data load signal, a polarity control signal, and the like. It will be appreciated that the first and second control signals CONT1, CONT2 may take different forms depending on the type of display device 100.
  • the timing controller 150 can be implemented in a number of ways, such as with dedicated hardware, to perform the various functions discussed herein.
  • a "processor” is an example of a timing controller 150 that employs one or more microprocessors that can be programmed using software (eg, microcode) to perform the various functions discussed herein.
  • the timing controller 150 can be implemented with or without a processor, and can also be implemented as dedicated hardware that performs some functions and a processor that performs other functions (eg, one or more programmed microprocessors and associated The combination of circuits). Examples of controller components that may be employed in various embodiments of the present disclosure include, but are not limited to, conventional microprocessors, application specific integrated circuits (ASICs), and field programmable gate arrays (FPGAs).
  • ASICs application specific integrated circuits
  • FPGAs field programmable gate arrays
  • FIG. 3 shows the current comparison circuit 120 in more detail in accordance with an embodiment of the present disclosure.
  • the current comparison circuit 120 includes a plurality of comparator circuits 121, 122, 123. It will be understood that while three comparator circuits are shown in FIG. 3, in other embodiments, current comparison circuit 120 may include more or fewer comparator circuits.
  • the comparator circuits 121, 122, 123 are each configured to compare the current on a respective one of the respective power supply paths with a corresponding reference value and output a corresponding comparison value.
  • comparator circuits 121, 122, and 123 compare currents I VSP , I VSN , and I IOVCC with respective reference values, and comparator circuits 121, 122, and 123 output comparison values C1, C2, and C3, respectively.
  • the first comparator circuit 121 is configured to compare the first current I VSP with a first reference value and output a comparison value C1
  • the second comparator circuit 122 is configured to compare the second current I VSN with the second reference
  • the values are compared and a comparison value C2 is output
  • the third comparator circuit is configured to compare the third current I IOVCC with a third reference value and output a comparison value C3.
  • the particular combination of comparison values C1, C2, and C3 indicates the particular type of content being displayed. It will be appreciated that the first, second and third reference values may be suitably selected such that different combinations of comparison values C1, C2 and C3 are capable of indicating different typical types of content being displayed.
  • the first comparator circuit 121 includes a first comparator COMP1 and a first resistor R1.
  • the first comparator COMP1 has a non-inverting input indicated by “+” and an inverting input indicated by "-”.
  • the first resistor R1 is connected between the ground GND and the non-inverting input terminal "+” for guiding the first current I VSP to the ground GND. This establishes a voltage determined by the first current I VSP and the first resistor R1 at the non-inverting input "+”.
  • the inverting input "-" is configured to receive a first reference voltage V ref1 indicative of the first reference value. In the example shown in FIG.
  • the first comparator circuit 121 further includes a second resistor R2 connected between the ground GND and the inverting input "-" for using the first reference current.
  • I ref1 is directed to the ground GND to establish the first reference voltage V ref1 at the inverting input "-".
  • the first reference value to which the first current I VSP is compared is equal to the magnitude of the first reference current I ref1 .
  • I VSP >I ref1 the comparison value C1 output by the first comparator COMP1 is high
  • I VSP ⁇ I ref1 the comparison value C1 output by the first comparator COMP1 is low.
  • Such transmission characteristics of the first comparator circuit 121 are visually shown in FIG.
  • the first reference voltage V ref1 may be supplied by, for example, a separate voltage generator, and thus the first reference current I ref1 and the second resistor R2 are not necessary. It will also be understood that in some embodiments, the voltage established by the first current I VSP and the first resistor R1 may be applied to the inverting input "-" of the first comparator COMP1, and the first reference voltage V Ref1 can be applied to the non-inverting input "+” of the first comparator COMP1. This results in a transmission characteristic that is "flipped" compared to the transmission characteristics shown in FIG. That is, when I VSP >I ref1 , the comparison value C1 is low, and when I VSP ⁇ I ref1 , the comparison value C1 is high.
  • the second comparator circuit 122 includes a second comparator COMP2 and a third resistor R3.
  • the second comparator COMP2 has a non-inverting input indicated by "+” and an inverting input indicated by "-”.
  • the third resistor R3 is connected between the ground GND and the non-inverting input terminal "+” for guiding the second current I VSN to the ground GND. This establishes a voltage determined by the second current I VSN and the third resistor R3 at the non-inverting input "+”.
  • the inverting input "-" is configured to receive a second reference voltage V ref2 indicative of the second reference value. In the example shown in FIG.
  • the second comparator circuit 122 further includes a fourth resistor R4 connected between the ground GND and the inverting input "-" for using the second reference current.
  • I ref2 is directed to the ground GND to establish the second reference voltage V ref2 at the inverting input "-".
  • the second reference value to which the second current I VSN is compared is equal to the magnitude of the second reference current I ref2 .
  • the comparison value C2 outputted by the second comparator COMP2 is at a high level
  • I VSN ⁇ I ref2 the comparison value C2 output by the second comparator COMP2 is low. Level.
  • the second reference voltage V ref2 may be supplied by, for example, a separate voltage generator, and thus the second reference current I ref2 and the fourth resistor R4 are not necessary. It will also be understood that in some embodiments, the voltage established by the second current I VSN and the third resistor R3 may be applied to the inverting input "-" of the second comparator COMP2, and the second reference voltage V Ref2 can be applied to the non-inverting input "+" of the second comparator COMP2.
  • the third comparator circuit 123 includes a third comparator COMP3 and a fifth resistor R5.
  • the third comparator COMP3 has a non-inverting input indicated by “+” and an inverting input indicated by "-”.
  • the fifth resistor R5 is connected between the ground GND and the non-inverting input terminal "+” for guiding the third current I IOVCC to the ground GND. This establishes a voltage determined by the third current I IOVCC and the fifth resistor R5 at the non-inverting input "+”.
  • the inverting input "-" is configured to receive a third reference voltage V ref3 indicative of the third reference value. In the example shown in FIG.
  • the third comparator circuit 123 further includes a sixth resistor R6 connected between the ground GND and the inverting input "-" for using the third reference current.
  • I ref3 is directed to the ground GND to establish the third reference voltage V ref3 at the inverting input "-".
  • the third reference value to which the third current I IOVCC is compared is equal to the magnitude of the second reference current I ref3 .
  • the comparison value C3 outputted by the third comparator COMP3 is at a high level
  • I IOVCC ⁇ I ref3 the comparison value C3 output by the third comparator COMP3 is low. Level.
  • the third reference voltage V ref3 may be supplied by, for example, a separate voltage generator, and thus the third reference current I ref3 and the sixth resistor R6 are not necessary. It will also be understood that in some embodiments, the voltage established by the third current I IVOCC and the sixth resistor R6 may be applied to the inverting input "-" of the third comparator COMP3, and the third reference voltage V Ref3 can be applied to the non-inverting input "+" of the third comparator COMP3.
  • the comparison values C1, C2, and C3 may be provided to the timing controller 120 (FIG. 2) for adjusting the refresh frequency at which the display screen is refreshed.
  • These three comparison values have eight different combinations that can indicate eight different types of content being displayed. Different refresh frequencies can be used for different content types to reduce power consumption while providing the desired display. Specifically, a high refresh rate can be used for content that requires high display effects, and a low refresh rate can be used for content that requires low display effects.
  • Table 1 An example of the correspondence between the comparison value and the refresh frequency is shown in Table 1.
  • FIG. 5 is a flow chart of a method 500 of driving a display device in accordance with an embodiment of the present disclosure.
  • the display device may take the form of the display device 100 described above with respect to FIG. Specifically, the display device 100 includes a power source 110, a current comparison circuit 120, a timing controller 150, a gate driver 160, and a data driver 170.
  • the current comparison circuit 120 compares the current on each of the respective power supply paths to a corresponding reference value.
  • the current comparison circuit 120 outputs a plurality of comparison values in response to the comparison.
  • the timing controller 150 controls the gate driver 160 and the data driver 170 to operate at different refresh frequencies.
  • Method 500 can provide the same advantages as the display device embodiments described above, which are not repeated here.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种用于显示装置的电流比较电路。所述显示装置被配置成被供应用于通过相应的供电路径向该显示装置的数字部分和模拟部分供电的多个电源电压。所述电流比较电路包括多个比较器电路，每个比较器电路被配置成将各个供电路径中的一个相应供电路径上的电流与相应的基准值进行比较，并且输出相应的比较值。各个比较器电路所输出的相应比较值的组合指示所述显示装置正在显示的内容的类型。

Description

电流比较电路、显示装置及其驱动方法
相关申请的交叉引用
本申请要求2017年6月19日提交的中国专利申请No.201710463360.9的权益，其全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，尤指一种电流电路、显示装置及其驱动方法。
背景技术
诸如手机之类的便携式电子设备在日常生活中变得非常普遍。待机时长是便携式电子设备的用户关心的方面。在被剧烈使用的场景(例如，播放视频)下，便携式电子设备的功耗增大，意味着待机时长将会缩短。显示效果是便携式电子设备的用户关心的另一方面。在观看视频内容时，流畅的画面呈现是用户所期望的。这要求被显示的画面被刷新的更大刷新频率。
发明内容
根据本公开的一个方面，提供了一种用于显示装置的电流比较电路。所述显示装置被配置成被供应用于通过相应的供电路径向该显示装置的数字部分和模拟部分供电的多个电源电压。所述电流比较电路包括多个比较器电路，每个比较器电路被配置成将各个供电路径中的一个相应供电路径上的电流与相应的基准值进行比较，并且输出相应的比较值。各个比较器电路所输出的相应比较值的组合指示所述显示装置正在显示的内容的类型。
在一些实施例中，所述多个电源电压包括用于向所述显示装置的所述数字部分供电的数字电源电压、用于向所述显示装置的所述模拟部分供电的模拟电源正电压、以及用于向所述显示装置的所述模拟部分供电的模拟电源负电压。所述多个比较器电路包括：第一比较器电路，被配置成将用于所述数字电源电压的所述供电路径上的第一电流与第一基准值进行比较；第二比较器电路，被配置成将用于所述模拟 电源正电压的所述供电路径上的第二电流与第二基准值进行比较；以及第三比较器电路，被配置成将用于所述模拟电源负电压的所述供电路径上的第三电流与第三基准值进行比较。
在一些实施例中，所述第一比较器电路包括：第一比较器，具有同相输入端和反相输入端；以及第一电阻，连接于接地端与所述同相输入端或所述反相输入端之一之间，用于将所述第一电流引导到所述接地端。所述同相输入端或所述反相输入端中的另一个被配置成接收指示所述第一基准值的第一基准电压。在一些实施例中，所述第一比较器电路还包括第二电阻，其连接于所述接地端与所述同相输入端或所述反相输入端中的另一个之间，用于将第一基准电流引导到所述接地端以在所述同相输入端或所述反相输入端中的另一个处建立所述第一基准电压。在一些实施例中，所述第一电阻和所述第二电阻具有相等的阻值。
在一些实施例中，所述第二比较器电路包括：第二比较器，具有同相输入端和反相输入端；以及第三电阻，连接于接地端与所述同相输入端或所述反相输入端之一之间，用于将所述第二电流引导到所述接地端。所述同相输入端或所述反相输入端中的另一个被配置成接收指示所述第二基准值的第二基准电压。在一些实施例中，所述第二比较器电路还包括第四电阻，其连接于所述接地端与所述同相输入端或所述反相输入端中的另一个之间，用于将第二基准电流引导到所述接地端以在所述同相输入端或所述反相输入端中的另一个处建立所述第二基准电压。在一些实施例中，所述第三电阻和所述第四电阻具有相等的阻值。
在一些实施例中，所述第三比较器电路包括：第三比较器，具有同相输入端和反相输入端；以及第五电阻，连接于接地端与所述同相输入端或所述反相输入端之一之间，用于将所述第三电流引导到所述接地端。所述同相输入端或所述反相输入端中的另一个被配置成接收指示所述第三基准值的第三基准电压。在一些实施例中，所述第三比较器电路还包括第六电阻，其连接于所述接地端与所述同相输入端或所述反相输入端中的另一个之间，用于将第三基准电流引导到所述接地端以在所述同相输入端或所述反相输入端中的另一个处建立所述第三基准电压。在一些实施例中，所述第五电阻和所述第六电阻具有相 等的阻值。
根据本公开的另一方面，提供了一种显示装置，包括：栅极驱动器，被配置成顺序地输出多个扫描信号；数据驱动器，被配置成与所述扫描信号中的每一个同步地输出数据信号；电源，被配置成供应用于通过相应的供电路径向该显示装置的数字部分和模拟部分供电的多个电源电压；如上所述的电流比较电路；以及时序控制器，被配置成响应于各个比较器电路所输出的相应比较值的不同组合而控制所述栅极驱动器和所述数据驱动器在不同的刷新频率下操作。
根据本公开的又另一方面，提供了一种驱动显示装置的方法。所述显示装置包括栅极驱动器、数据驱动器、被配置成通过相应的供电路径向该显示装置的数字部分和模拟部分供电的电源、电流比较电路、以及时序控制器。所述方法包括：利用所述电流比较电路，将各个供电路径中的每一个上的电流与相应的基准值进行比较；响应于所述比较，由所述电流比较电路输出多个比较值；以及响应于所述比较值的不同组合，由所述时序控制器控制所述栅极驱动器和所述数据驱动器在不同的刷新频率下操作。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1为根据本公开实施例的显示装置的示意性框图；
图2为图1所示的显示装置包括的时序控制器的示意性框图；
图3为根据本公开实施例的电流比较电路的示意图；
图4为示出图3所示的第一比较器电路的传输特性的示意图；并且
图5为根据本公开实施例的驱动显示装置的方法的流程图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件和/或部分，但是这些元件、部件和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件或部分与另一个相区分。因此，下面讨论的第一元件、部件或部分可以被称为第二元 件、部件或部分而不偏离本公开的教导。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件被称为“连接到另一个元件”或“耦合到另一个元件”时，其可以直接连接到另一个元件或直接耦合到另一个元件，或者可以存在中间元件。相反，当元件被称为“直接连接到另一个元件”、“直接耦合到另一个元件”时，没有中间元件存在。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
下面将结合附图对本公开的实施例作进一步地详细描述。
图1为根据本公开实施例的显示装置100的示意性框图。显示装置100包括电源110、电流比较电路120、伽马电压生成器130、显示面板140、时序控制器150、栅极驱动器160和数据驱动器170。
电源110，例如DC/DC转换器，从输入电压VCC生成多个电源电压。在该示例中，所述电源电压包括数字电源电压IOVCC、模拟电源正电压VSP和模拟电源负电压VSN。数字电源电压IOVCC用于向显示装置100的数字部分供电，所述数字部分包括例如时序控制器150、栅极驱动器160、数据驱动器170的一部分、以及伽马电压生成器130的一部分。模拟电源正电压VSP和模拟电源负电压VSN两者用于向显示装置100的模拟部分供电，所述模拟部分包括例如数据驱动器170的另一部分以及伽马电压生成器130的另一部分。在该示例中，电源 110还向栅极驱动器160供应栅极开启电压Von和栅极关闭电压Voff。将理解的是，上面列出的这些电源电压是示例性的，并且取决于显示装置100的类型，电源110可以生成其他电源电压。例如，模拟电源正电压VSP和模拟电源负电压VSN可以不被生成，并且替代地单个模拟电源电压AVDD被生成。
电源110生成的数字电源电压IOVCC、模拟电源正电压VSP和模拟电源负电压VSN经由各自的供电路径(在图1中由带箭头的线条指示)被供应给伽马电压生成器130、时序控制器150、栅极驱动器160和数据驱动器170。电源110的负载随显示面板140正在显示的内容的类型不同而变化，使得各个供电路径上的电流I IOVCC、I VSP和I VSN随正被显示的内容的类型不同而变化。例如，当显示面板140正在播放动态画面时，数据驱动器170的功耗增大，导致增大的电流I IOVCC、I VSP和I VSN。当显示面板140正在播放静态画面时，数据驱动器170的功耗减小，导致减小的电流I IOVCC、I VSP和I VSN。因此，电流I IOVCC、I VSP和I VSN的量值可以指示正被显示的内容的类型。基于这一认识，提出了本公开的构思，其中根据各个供电路径上的电流的量值来调谐显示面板140所显示的画面被刷新的刷新频率，使得经调谐的刷新频率适配于正被显示的内容的类型。刷新频率的调谐将是有利的，因为其允许在提供期望的显示效果的同时降低功耗。
电流比较电路120被提供用于将各个供电路径上的电流与相应的基准值进行比较并且输出多个比较值，如图1所示。在该示例中，响应于电流I IOVCC、I VSP和I VSN与各自的基准值之间的比较，电流比较电路120输出比较值C1、C2和C3。如上解释的，比较值C1、C2和C3的不同组合可以指示正被显示的内容的不同类型。电流比较电路120的详情将在稍后进一步描述。
伽马电压生成器130生成一系列伽马电压作为数据驱动器170的电压基准。伽马电压生成器130可以由任何已知或将来的技术实现。在图1所示的示例中，伽马电压生成器130可以包括由数字电源电压IOVCC供电的数字电路部分和由模拟电源正电压VSP和模拟电源负电压VSN供电的模拟电路部分。
显示面板140包括在第一方向上延伸的多个栅极线GL、在与第一方向交叉的第二方向上延伸的多个数据线DL、以及排列在矩阵中的多 个像素PX。像素PX中的每一个电连接至栅极线GL中的对应一个栅极线和数据线DL中的对应一个数据线。
时序控制器150控制显示面板140、栅极驱动器160和数据驱动器170的操作。时序控制器150从存储器(未示出)取回输入图像数据RGBD。输入图像数据RGBD包括用于多个像素PX的输入像素数据，输入像素数据中的每一个可包括用于多个像素PX中的对应一个的红色灰度数据R、绿色灰度数据G或蓝色灰度数据B。时序控制器150还从时钟发生器或主机控制器(未示出)接收主时钟信号MCLK，并且从电流比较电路120接收比较值C1、C2和C3。时序控制器150基于输入图像数据RGBD、主时钟信号MCLK和比较值C1、C2、C3生成输出图像数据RGBD’、第一控制信号CONT1和第二控制信号CONT2。输出图像数据RGBD’被提供给数据驱动器170。在一些实施例中，输出图像数据RGBD’可以是与输入图像数据RGBD基本相同的图像数据。在一些实施例中，输出图像数据RGBD’可以是通过补偿输入图像数据RGBD生成的补偿图像数据。第一控制信号CONT1被提供给栅极驱动器160，并且栅极驱动器160的驱动时序可基于第一控制信号CONT1被控制。第二控制信号CONT2被提供给数据驱动器170，并且数据驱动器170的驱动时序可基于第二控制信号CONT2被控制。
栅极驱动器160从时序控制器150接收第一控制信号CONT1。栅极驱动器160被配置成基于第一控制信号CONT1向栅极线GL顺序地输出多个扫描信号。在一些实施例中，栅极驱动器160可被集成在显示面板140中。替换地，栅极驱动器160可以通过例如带式载体封装(Tape Carrier Package，TCP)连接至显示面板140。
数据驱动器170从时序控制器150接收第二控制信号CONT2和输出图像数据RGBD’。数据驱动器170被配置成基于第二控制信号CONT2和输出图像数据RGBD’生成多个数据信号。数据驱动器170还被配置成与栅极驱动器160输出的扫描信号中的每一个同步地将所述多个数据信号输出至数据线DL。在图1所示的示例中，数据驱动器170可以包括由数字电源电压IOVCC供电的数字电路部分和由模拟电源正电压VSP和模拟电源负电压VSN供电的模拟电路部分。例如，数据驱动器170可包括移位寄存器、锁存器、数模转换器和缓冲器。移位寄存器向锁存器输出锁存脉冲。锁存器暂时存储输出图像数据 RGBD’，并且将输出图像数据RGBD’输出至数模转换器。数模转换器基于来自时序控制器150的输出图像数据RGBD’和来自伽马电压生成器130的伽马电压生成模拟数据信号，并且将模拟数据信号输出至缓冲器。缓冲器将模拟数据信号输出至数据线DL。
图2为图1所示的显示装置100包括的时序控制器150的示意性框图。参考图2，时序控制器150包括数据补偿器152、模式选择器154和控制信号生成器156。为了方便描述，时序控制器150在图2中被示出为划分成三个元件，尽管时序控制器150可不被物理划分。
数据补偿器152接收输入图像数据RGBD，并且可通过选择性地补偿输入图像数据RGBD而生成输出图像数据RGBD’。例如，数据补偿器152可选择性地为输入图像数据RGBD执行图像质量补偿、点补偿、适应性颜色校正(ACC)、和/或动态电容补偿(DCC)以生成输出图像数据RGBD’。在一些实施例中，数据补偿器152可包括单线存储器，该单线存储器存储与单个像素行对应的像素数据。数据补偿器152可以是可选的。
模式选择器154接收来自电流比较电路120的比较值C1、C2和C3。如较早前所述的，比较值C1、C2和C3的组合可以指示正被显示的内容的类型。响应于比较值C1、C2和C3的不同组合，模式选择模块154确定不同工作模式以调整显示画面被刷新的刷新频率。具体地，模式选择模块154可以选择合适的时钟频率(例如，像素时钟频率)并产生所需的时间参数(例如，水平扫描周期、水平消隐时长、垂直消隐时长等)。在一些实施例中，刷新频率的调整可以采用中国专利申请公开CN 106205460 A中描述的机制来实现，其全部公开内容通过引用并入本文。在其他实施例中，任何其他适当的机制可以被使用。
控制信号生成器156基于模式选择器154所产生的时间参数和接收的主时钟信号MCLK，生成用于图1中的栅极驱动器160的第一控制信号CONT1和用于图1中的数据驱动器170的第二控制信号CONT2。在一些实施例中，第一控制信号CONT1可包括垂直启动信号、栅极时钟信号等，并且第二控制信号CONT2可包括水平启动信号、数据时钟信号、数据负载信号、极性控制信号等。将理解的是，取决于显示装置100的类型，第一和第二控制信号CONT1、CONT2可以采取不同的形式。
时序控制器150可以以许多方式(诸如用专用硬件)实现，以执行本文所讨论的各种功能。“处理器”是时序控制器150的一个示例，其采用可以使用软件(例如微代码)编程以执行本文所讨论的各种功能的一个或多个微处理器。时序控制器150可以在采用或不采用处理器的情况下来实现，并且也可以实现为执行一些功能的专用硬件和执行其它功能的处理器(例如，一个或多个编程的微处理器和相关联的电路)的组合。在本公开的各种实施例中可以采用的控制器组件的示例包含但不限于常规的微处理器、专用集成电路(ASIC)和现场可编程门阵列(FPGA)。
图3更详细地示出了根据本公开实施例的电流比较电路120。参考图3，电流比较电路120包括多个比较器电路121、122、123。将理解的是，虽然三个比较器电路在图3中被示出，但是在其他实施例中，电流比较电路120可以包括更多或更少的比较器电路。
比较器电路121、122、123每一个都被配置成将各个供电路径中的一个相应供电路径上的电流与相应的基准值进行比较，并且输出相应的比较值。在该示例中，比较器电路121、122和123分别将电流I VSP、I VSN和I IOVCC与各自的基准值进行比较，并且比较器电路121、122和123分别输出比较值C1、C2和C3。具体地，第一比较器电路121被配置成将第一电流I VSP与第一基准值进行比较并且输出比较值C1，第二比较器电路122被配置成将第二电流I VSN与第二基准值进行比较并且输出比较值C2，并且第三比较器电路被配置成将第三电流I IOVCC与第三基准值进行比较并且输出比较值C3。如前所述，比较值C1、C2和C3的特定组合指示正被显示的内容的特定类型。将理解的是，第一、第二和第三基准值可以被适当地选择使得比较值C1、C2和C3的不同组合能够指示正被显示的内容的不同典型类型。
第一比较器电路121包括第一比较器COMP1和第一电阻R1。第一比较器COMP1具有由“+”指示的同相输入端和由“-”指示的反相输入端。第一电阻R1连接于接地端GND与所述同相输入端“+”之间，用于将所述第一电流I VSP引导到所述接地端GND。这在所述同相输入端“+”处建立由第一电流I VSP和第一电阻R1决定的电压。所述反相输入端“-”被配置成接收指示所述第一基准值的第一基准电压V ref1。在图3所示的示例中，第一比较器电路121还包括第二电阻R2，其连 接于所述接地端GND与所述反相输入端“-”之间，用于将第一基准电流I ref1引导到所述接地端GND以在所述反相输入端“-”处建立所述第一基准电压V ref1。在第一电阻R1和第二电阻R2具有相等阻值的情况下，第一电流I VSP与之相比较的所述第一基准值等于第一基准电流I ref1的量值。在这种情况下，当I VSP＞I ref1时，第一比较器COMP1输出的比较值C1为高电平，并且当I VSP＜I ref1时，第一比较器COMP1输出的比较值C1为低电平。第一比较器电路121的这样的传输特性在图4中被直观地示出。
在一些实施例中，所述第一基准电压V ref1可以由例如单独的电压生成器供应，并且因此第一基准电流I ref1和第二电阻R2不是必须的。还将理解的是，在一些实施例中，由第一电流I VSP与第一电阻R1建立的电压可以被施加到第一比较器COMP1的反相输入端“-”，并且第一基准电压V ref1可以被施加到第一比较器COMP1的同相输入端“+”。这导致与图4中所示的传输特性相比被“翻转”的传输特性。即，当I VSP＞I ref1时，比较值C1为低，并且当I VSP＜I ref1时，比较值C1为高。
类似地，第二比较器电路122包括第二比较器COMP2和第三电阻R3。第二比较器COMP2具有由“+”指示的同相输入端和由“-”指示的反相输入端。第三电阻R3连接于接地端GND与所述同相输入端“+”之间，用于将所述第二电流I VSN引导到所述接地端GND。这在所述同相输入端“+”处建立由第二电流I VSN和第三电阻R3决定的电压。所述反相输入端“-”被配置成接收指示所述第二基准值的第二基准电压V ref2。在图3所示的示例中，第二比较器电路122还包括第四电阻R4，其连接于所述接地端GND与所述反相输入端“-”之间，用于将第二基准电流I ref2引导到所述接地端GND以在所述反相输入端“-”处建立所述第二基准电压V ref2。在第三电阻R3和第四电阻R4具有相等阻值的情况下，第二电流I VSN与之相比较的所述第二基准值等于第二基准电流I ref2的量值。在这种情况下，当I VSN＞I ref2时，第二比较器COMP2输出的比较值C2为高电平，并且当I VSN＜I ref2时，第二比较器COMP2输出的比较值C2为低电平。
在一些实施例中，所述第二基准电压V ref2可以由例如单独的电压生成器供应，并且因此第二基准电流I ref2和第四电阻R4不是必须的。还将理解的是，在一些实施例中，由第二电流I VSN与第三电阻R3建立 的电压可以被施加到第二比较器COMP2的反相输入端“-”，并且第二基准电压V ref2可以被施加到第二比较器COMP2的同相输入端“+”。
类似地，第三比较器电路123包括第三比较器COMP3和第五电阻R5。第三比较器COMP3具有由“+”指示的同相输入端和由“-”指示的反相输入端。第五电阻R5连接于接地端GND与所述同相输入端“+”之间，用于将所述第三电流I IOVCC引导到所述接地端GND。这在所述同相输入端“+”处建立由第三电流I IOVCC和第五电阻R5决定的电压。所述反相输入端“-”被配置成接收指示所述第三基准值的第三基准电压V ref3。在图3所示的示例中，第三比较器电路123还包括第六电阻R6，其连接于所述接地端GND与所述反相输入端“-”之间，用于将第三基准电流I ref3引导到所述接地端GND以在所述反相输入端“-”处建立所述第三基准电压V ref3。在第五电阻R5和第六电阻R6具有相等阻值的情况下，第三电流I IOVCC与之相比较的所述第三基准值等于第二基准电流I ref3的量值。在这种情况下，当I IOVCC＞I ref3时，第三比较器COMP3输出的比较值C3为高电平，并且当I IOVCC＜I ref3时，第三比较器COMP3输出的比较值C3为低电平。
在一些实施例中，所述第三基准电压V ref3可以由例如单独的电压生成器供应，并且因此第三基准电流I ref3和第六电阻R6不是必须的。还将理解的是，在一些实施例中，由第三电流I IOVCC与第六电阻R6建立的电压可以被施加到第三比较器COMP3的反相输入端“-”，并且第三基准电压V ref3可以被施加到第三比较器COMP3的同相输入端“+”。
继续图3的示例，比较值C1、C2和C3可以被提供给时序控制器120(图2)以用于调整显示画面被刷新的刷新频率。这三个比较值具有八种不同的组合，其可以指示正被显示的内容的八种不同类型。针对不同的内容类型可以采用不同的刷新频率，从而在提供期望的显示效果的同时降低功耗。具体地，对于显示效果要求高的内容可以采用高的刷新频率，并且对于显示效果要求低的内容可以采用低的刷新频率。比较值与刷新频率的对应关系的一个示例如表1所示。
表1
Figure PCTCN2018086807-appb-000001
图5为根据本公开实施例的驱动显示装置的方法500的流程图。所述显示装置可以采取上面关于图1描述的显示装置100的形式。具体地，显示装置100包括电源110、电流比较电路120、时序控制器150、栅极驱动器160、以及数据驱动器170。
在步骤501处，所述电流比较电120将各个供电路径中的每一个上的电流与相应的基准值进行比较。在步骤502处，响应于所述比较，所述电流比较电路120输出多个比较值。在步骤503处，响应于所述比较值的不同组合，所述时序控制器150控制所述栅极驱动器160和所述数据驱动器170在不同的刷新频率下操作。
方法500可以提供与上面描述的显示装置实施例相同的优点，其在此不再重复。
本领域的技术人员可以对公开的实施例进行各种改动和变型而不脱离本公开的范围。这样，倘若这些修改和变型属于所附权利要求及其等同范围之内，则本公开也意图包含这些改动和变型在内。

Claims (13)

  1. 一种用于显示装置的电流比较电路，所述显示装置被配置成被供应用于通过相应的供电路径向该显示装置的数字部分和模拟部分供电的多个电源电压，所述电流比较电路包括：
    多个比较器电路，每个比较器电路被配置成将各个供电路径中的一个相应供电路径上的电流与相应的基准值进行比较，并且输出相应的比较值，其中各个比较器电路所输出的相应比较值的组合指示所述显示装置正在显示的内容的类型。
  2. 如权利要求1所述的电流比较电路，其中所述多个电源电压包括用于向所述显示装置的所述数字部分供电的数字电源电压、用于向所述显示装置的所述模拟部分供电的模拟电源正电压、以及用于向所述显示装置的所述模拟部分供电的模拟电源负电压，并且其中所述多个比较器电路包括：
    第一比较器电路，被配置成将用于所述数字电源电压的所述供电路径上的第一电流与第一基准值进行比较；
    第二比较器电路，被配置成将用于所述模拟电源正电压的所述供电路径上的第二电流与第二基准值进行比较；以及
    第三比较器电路，被配置成将用于所述模拟电源负电压的所述供电路径上的第三电流与第三基准值进行比较。
  3. 如权利要求2所述的电流比较电路，其中所述第一比较器电路包括：
    第一比较器，具有同相输入端和反相输入端；以及
    第一电阻，连接于接地端与所述同相输入端或所述反相输入端之一之间，用于将所述第一电流引导到所述接地端，并且
    其中所述同相输入端或所述反相输入端中的另一个被配置成接收指示所述第一基准值的第一基准电压。
  4. 如权利要求3所述的电流比较电路，其中所述第一比较器电路还包括第二电阻，其连接于所述接地端与所述同相输入端或所述反相输入端中的另一个之间，用于将第一基准电流引导到所述接地端以在所述同相输入端或所述反相输入端中的另一个处建立所述第一基准电压。
  5. 如权利要求4所述的电流比较电路，其中所述第一电阻和所述第二电阻具有相等的阻值。
  6. 如权利要求2所述的电流比较电路，其中所述第二比较器电路包括：
    第二比较器，具有同相输入端和反相输入端；以及
    第三电阻，连接于接地端与所述同相输入端或所述反相输入端之一之间，用于将所述第二电流引导到所述接地端，并且
    其中所述同相输入端或所述反相输入端中的另一个被配置成接收指示所述第二基准值的第二基准电压。
  7. 如权利要求6所述的电流比较电路，其中所述第二比较器电路还包括第四电阻，其连接于所述接地端与所述同相输入端或所述反相输入端中的另一个之间，用于将第二基准电流引导到所述接地端以在所述同相输入端或所述反相输入端中的另一个处建立所述第二基准电压。
  8. 如权利要求7所述的电流比较电路，其中所述第三电阻和所述第四电阻具有相等的阻值。
  9. 如权利要求2所述的电流比较电路，其中所述第三比较器电路包括：
    第三比较器，具有同相输入端和反相输入端；以及
    第五电阻，连接于接地端与所述同相输入端或所述反相输入端之一之间，用于将所述第三电流引导到所述接地端，并且
    其中所述同相输入端或所述反相输入端中的另一个被配置成接收指示所述第三基准值的第三基准电压。
  10. 如权利要求9所述的电流比较电路，其中所述第三比较器电路还包括第六电阻，其连接于所述接地端与所述同相输入端或所述反相输入端中的另一个之间，用于将第三基准电流引导到所述接地端以在所述同相输入端或所述反相输入端中的另一个处建立所述第三基准电压。
  11. 如权利要求10所述的电流比较电路，其中所述第五电阻和所述第六电阻具有相等的阻值。
  12. 一种显示装置，包括：
    栅极驱动器，被配置成顺序地输出多个扫描信号；
    数据驱动器，被配置成与所述扫描信号中的每一个同步地输出数据信号；
    电源，被配置成供应用于通过相应的供电路径向该显示装置的数字部分和模拟部分供电的多个电源电压；
    如权利要求1-11中任一项所述的电流比较电路；以及
    时序控制器，被配置成响应于各个比较器电路所输出的相应比较值的不同组合而控制所述栅极驱动器和所述数据驱动器在不同的刷新频率下操作。
  13. 一种驱动显示装置的方法，所述显示装置包括栅极驱动器、数据驱动器、被配置成通过相应的供电路径向该显示装置的数字部分和模拟部分供电的电源、电流比较电路、以及时序控制器，所述方法包括：
    利用所述电流比较电路，将各个供电路径中的每一个上的电流与相应的基准值进行比较；
    响应于所述比较，由所述电流比较电路输出多个比较值；以及
    响应于所述比较值的不同组合，由所述时序控制器控制所述栅极驱动器和所述数据驱动器在不同的刷新频率下操作。
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CN102110409A (zh) * 2009-12-29 2011-06-29 乐金显示有限公司 有机发光显示设备及其驱动方法
CN104282271A (zh) * 2014-10-24 2015-01-14 京东方科技集团股份有限公司 一种有源有机发光二极管显示系统的补偿电路设计
CN105405425A (zh) * 2015-12-24 2016-03-16 昆山龙腾光电有限公司 一种驱动电流切换控制电路及显示装置
CN105469768A (zh) * 2016-01-15 2016-04-06 京东方科技集团股份有限公司 显示模组的控制装置及控制方法、显示装置
CN107038988A (zh) * 2017-06-19 2017-08-11 京东方科技集团股份有限公司 控制电路、显示屏、显示屏的驱动方法及显示装置

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