WO2018233118A1 - 一种通信控制方法及电子设备 - Google Patents

一种通信控制方法及电子设备 Download PDF

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WO2018233118A1
WO2018233118A1 PCT/CN2017/103665 CN2017103665W WO2018233118A1 WO 2018233118 A1 WO2018233118 A1 WO 2018233118A1 CN 2017103665 W CN2017103665 W CN 2017103665W WO 2018233118 A1 WO2018233118 A1 WO 2018233118A1
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bmc
status information
register
cpu
status
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French (fr)
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何海洋
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Lenovo Beijing Ltd
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Lenovo Beijing Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

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  • the present disclosure relates to the field of computer technologies, and in particular, to a communication control method and an electronic device.
  • the operating system is the intelligent platform management interface (IPMI) between the central processing unit (CPU) and the baseboard management controller (BMC). Protocol transmission is generally done through the kernel to the Kernel Cache System (KCS) interface.
  • IPMI intelligent platform management interface
  • KCS Kernel Cache System
  • the characteristic of the IPMI protocol is that the read and write operations are initiated by the CPU, and the BMC can only passively wait for the read and write response of the CPU, and cannot initiate communication to the CPU actively.
  • the BMC exception cannot be obtained by the CPU when the KMC interface fails to complete the subsequent protocol interaction.
  • the CPU will continue to send read and write communication requests to the BMC, resulting in waste of resources. It brings great inconvenience to system management and maintenance.
  • an object of the present disclosure is to provide a communication control method and an electronic device, which are used to solve the technical problem of waste of resources caused by an abnormality of a BMC in the prior art that cannot be acquired by a CPU.
  • the present disclosure provides a communication control method, the method comprising:
  • Reading BMC status information stored in a status register the status register being a register of a KCS interface between the CPU and the BMC;
  • the BMC Based on the BMC status information, the BMC communicates with the BMC in a communication manner corresponding to the BMC status information.
  • reading the BMC state information stored in the status register includes:
  • OEM Original Equipment Manufacturer
  • the identifying the BMC status information corresponding to the bytecode includes:
  • the BMC status information indicates that the BMC is in a normal state
  • the BMC status information indicates that the BMC is in an abnormal state.
  • the communicating with the BMC in a communication manner corresponding to the BMC state information based on the BMC state information including:
  • the BMC status information indicates that the BMC is in a normal state, communicate with the BMC in a first communication manner;
  • the BMC status information indicates that the BMC is in an abnormal state, communicate with the BMC in a second communication manner.
  • the foregoing method optionally, communicating with the BMC in the first communication manner, includes:
  • the first target data is written to the write register of the KCS interface.
  • the foregoing method optionally, communicating with the BMC in the second communication manner, includes:
  • the second target data in the read register of the KCS interface is read, the second target data is data written when the BMC is abnormal, and the second target data indicates abnormal type information of the BMC.
  • the above method optionally, further includes:
  • An exception handling process is initiated based on the second target data.
  • the present disclosure also provides another communication control method, including:
  • the BMC writes the BMC status information into a status register, which is a register of the KCS interface between the CPU and the BMC, such that the CPU reads the BMC status information to communicate with the BMC status information.
  • BMC communicates;
  • the above method optionally, further includes:
  • the BMC writes the second target data into a read register of the KCS interface, the second target data indicating that the BMC has abnormal exception type information, such that the CPU reads the second target data and based on the second The target data starts the exception handling process.
  • the present disclosure also provides an electronic device, including: a CPU; a BMC; and a KCS interface connected between the CPU and the BMC, the KCS interface having a status register;
  • the BMC writes the BMC status information into the status register, and the CPU communicates with the BMC in a communication manner corresponding to the BMC status information by reading the BMC status information stored in the status register.
  • the communication control method and the electronic device provided by the present disclosure read the stored BMC state information in the status register of the KCS interface on the CPU side, and then perform corresponding communication based on the BMC state information.
  • the mode communicates with the BMC, so that the CPU can know the state of the BMC in time by reading the BMC state information, and can communicate according to the real-time state of the BMC in a corresponding communication manner, so as to avoid the CPU still sending the BMC to the BMC when an abnormality occurs in the BMC.
  • the waste of resources caused by communication requests such as reading and writing is inconvenient for system management and maintenance. Public purpose.
  • FIG. 1 is a flowchart of implementing a communication control method according to an embodiment of the present disclosure
  • FIG. 2 is a diagram showing an example of application of an embodiment of the present disclosure
  • FIG. 3 is a partial flowchart of a communication control method according to an embodiment of the present disclosure
  • FIG. 4 is a flowchart of implementing a communication control method according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a bit structure of a register of a KCS interface according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
  • the techniques of this disclosure may be implemented in the form of hardware and/or software (including firmware, microcode, etc.). Additionally, the techniques of this disclosure may take the form of a computer program product on a computer readable medium storing instructions for use by or in connection with an instruction execution system.
  • a computer readable medium can be any medium that can contain, store, communicate, propagate or transport the instructions.
  • a computer readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium.
  • the computer readable medium include: a magnetic storage device such as a magnetic tape or a hard disk (HDD); an optical storage device such as a compact disk (CD-ROM); a memory such as a random access memory (RAM) or a flash memory; and/or a wired /Wireless communication link.
  • a magnetic storage device such as a magnetic tape or a hard disk (HDD)
  • an optical storage device such as a compact disk (CD-ROM)
  • a memory such as a random access memory (RAM) or a flash memory
  • RAM random access memory
  • FIG. 1 a flowchart of an implementation of a communication control method according to an embodiment of the present disclosure is applied to a CPU, and in order to enable timely communication to learn the status of the BMC, the CPU may perform the following steps:
  • Step 101 Read the BMC state stored in the status register.
  • the status register is a register of the KCS interface between the CPU and the BMC, as shown in FIG.
  • the BMC updates its BMC status information to the relevant bits in the status register in real time. Therefore, the CPU can read the BMC status information stored in the status register of the KCS interface, and then know the current status of the BMC in time. If the BMC is in a normal state or an abnormal state, or whether the BMC is in a normal state or an abnormal state caused by some reason.
  • Step 102 Based on the BMC status information, communicate with the BMC in a communication manner corresponding to the BMC status information.
  • the CPU after reading the BMC state information capable of characterizing the current state of the BMC, the CPU communicates with the BMC in different manners according to the current state of the BMC, instead of the prior art, regardless of the terminal of the BMC.
  • the CPU initiates a communication operation such as reading to the BMC. Therefore, in the present disclosure, there is no waste of resources and inconvenience in system management and maintenance due to the communication mode of the CPU.
  • a communication control method reads the stored BMC state information in the status register of the KCS interface on the CPU side, and then uses the corresponding communication mode based on the BMC state information.
  • the CPU communicates with the BMC, so that the CPU can know the status of the BMC in time by reading the BMC status information, and can communicate according to the real-time status of the BMC in a corresponding communication manner, so as to prevent the CPU from issuing a read to the BMC when an abnormality occurs in the BMC.
  • the purpose of this embodiment is achieved by writing a communication request and causing waste of resources to cause inconvenience to system management and maintenance.
  • the CPU when the CPU reads the BMC state information stored in the status register, the CPU may be implemented by the following steps, as shown in FIG. 3:
  • Step 301 Read the bytecode in the OEM bit in the status register.
  • the BMC will write the BMC status information that can characterize its current status to the OEM bit in the status register of the KCS interface in real time, since the OEM (Original Equipment Manufacturer) is reserved for the device manufacturer. The bit is not used.
  • the CPU can accurately read the byte code representing the BMC status information written by the BMC in the OEM bit from the OEM bit in the status register of the KCS interface.
  • Step 302 Identify BMC status information corresponding to the byte code.
  • the OEM bit generally has two bits in the status register of the KCS interface, such as OEM1 and OEM2.
  • the BMC writes bytecodes in OEM1 and OEM2 to represent the current state of the BMC, such as normal state or abnormal state.
  • the CPU first reads the bytecode when it needs to communicate with the BMC, and determines the BMC state information corresponding to the bytecode by the corresponding relationship between the preset code and the state information, and the bytecodes of different values may be different.
  • the BMC status information corresponds to indicate that the BMC is in a different state.
  • the correspondence between the code and the status information may be set by the manufacturer in advance or jointly agreed by the manufacturer.
  • correspondence between the bytecode and the state information may include two correspondences, for example:
  • the byte code is the first value, and the BMC status information indicates that the BMC is in a normal state; the byte code is the second value, and the BMC status information indicates that the BMC is in an abnormal state.
  • the above determines whether the BMC is normal or in an abnormal state by setting two values in advance for the bytecode.
  • the correspondence between the bytecode and the status information may include more correspondences, for example:
  • the byte code is the first value, and the BMC status information indicates that the BMC is in a normal state; the byte code is the second value, and the BMC status information indicates that the BMC is in the first type of abnormal state; the byte code is the third value. Corresponding to the BMC status information indicates that the BMC is in the second type of abnormal state; and so on.
  • the above indicates whether the BMC is in a normal state or in which type of abnormal state, such as an abnormality information of a BMC chip crash type or an abnormal state of an OEM accidental restart type, by setting a plurality of values in advance for the bytecode.
  • the CPU can determine whether the BMC is in a normal state or an abnormal state by the value of the bytecode
  • the CPU can determine whether the BMC is in a normal state or an abnormal state by the value of the bytecode. Further, when the BMC is in an abnormal state, the CPU can determine the type of abnormal state of the BMC by the value of the bytecode.
  • the CPU when the CPU reads the BMC status information and communicates with the BMC in a communication manner corresponding to the BMC status information, the CPU may perform communication by using a preset different communication manner, for example:
  • the BMC status information indicates that the BMC is in a normal state, communicate with the BMC in a first communication manner, such as writing first target data to a write register of the KCS interface;
  • the BMC status information indicates that the BMC is in an abnormal state or a certain type of abnormal state
  • communication is performed in a second communication manner different from the first communication mode, such as reading the second target data in the read register of the KCS interface, and second.
  • the target data is the data written when the BMC is abnormal, and can indicate the abnormal type information of the BMC.
  • the first communication mode may be a communication manner implemented by the KCS interface based on the normal IPMI protocol between the CPU and the BMC.
  • the CPU determines that the BMC status information indicates that the BMC is in a normal state by reading the bytecode in the OEM bit
  • the CPU writes the first target data into the write register of the KCS interface, and then the BMC sends the first target data to the KCS.
  • the reply data is written in the read register of the interface, and the CPU can read the reply data written by the BMC from the read register of the KCS interface to complete the communication.
  • the second communication mode may be a communication mode in which the CPU only reads.
  • the CPU determines that the BMC status information indicates that the BMC is in an abnormal state by reading the bytecode in the OEM bit
  • the CPU reads the second target data data written by the BMC from the read register of the KCS interface, and completes the communication.
  • the second target data written by the BMC to the read register of the KCS interface when the abnormality is abnormal can indicate abnormal type information of the BMC, such as the cause of the abnormality of the BMC or the BMC. Which type of correspondence should be used for exceptions that occur, and so on. Therefore, after the CPU reads the second target data, the exception handling process can be started to perform exception processing, and the BMC abnormality can be dealt with as soon as possible, thereby avoiding unnecessary loss or even CPU crash.
  • a flowchart of implementing a communication control method according to an embodiment of the present disclosure is applicable to a BMC, and the following steps are:
  • Step 401 Monitor the status of the BMC to obtain BMC status information.
  • Step 402 Write BMC status information into the status register for reading to the CPU.
  • the status register is a register of the KCS interface between the BMC and the CPU. Therefore, the BMC writes information indicating the current state of the BMC to the status register. When the CPU needs to perform communication such as reading and writing, the status can be read.
  • the BMC status information in the register determines the current state of the BMC and communicates with the BMC in a corresponding communication manner.
  • the CPU can know the state of the BMC in time by reading the BMC state information, and can communicate according to the real-time state of the BMC in a corresponding communication manner, so as to prevent the CPU from issuing a read/write request and the like to the BMC when the BMC is abnormal.
  • the waste of resources causes inconvenience to system management and maintenance, and achieves the purpose of the embodiment.
  • the BMC writes its BMC state information to the OEM bit in the status register, and indicates whether the BMC is in a normal state or an abnormal state, or in which type, by the value indicated by the bytecode in the OEM bit. The abnormal state of the type, etc.
  • the BMC may write the second target data of the abnormal type information indicating the abnormality of the BMC to the read register of the KCS interface when the abnormality occurs, and further, the CPU is in the read OEM bit.
  • the second target data can be read from the read register of the KCS interface, and based on this, the abnormal type information of the BMC is abnormal, such as the BMC abnormality caused by the cause, and the like.
  • the CPU can start the exception processing process based on the second target data, thereby performing exception processing, so as to avoid loss as soon as possible or return to normal as soon as possible.
  • the bit structure of the register of the KCS interface can be referred to as shown in FIG. 5, and 8 bits in the register can be used for information writing by the CPU and the BMC in a bit sharing manner, such as a status register, a write register, and a read register: 0-7
  • the write register is used by the CPU for writing the first target data
  • the read register is used for the BMC to perform the reply data or the BMC abnormal type information, that is, the writing of the second target data
  • the OEM bit in the status register is used for the BMC state.
  • the writing of information implements the above scheme based on the bit structure in this register.
  • FIG. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
  • the electronic device may include:
  • the BMC 602 writes the BMC status information into the status register 604, and the CPU 601 communicates with the BMC 602 in a communication manner corresponding to the BMC status information by reading the BMC status information stored in the status register 604.
  • the CPU 601 can know the state of the BMC 602 in time by reading the status information of the BMC 602, and can communicate according to the real-time status of the BMC 602 in a corresponding communication manner, so that when the BMC 602 is abnormal, the CPU 601 still
  • the BMC 602 issues a communication request such as reading and writing, which causes waste of resources, which causes inconvenience to system management and maintenance, and achieves the purpose of the present disclosure.

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Abstract

一种通信控制方法及电子设备，该方法包括：读取状态寄存器中所存储的BMC状态信息（101），所述状态寄存器为CPU与BMC之间的KCS接口的寄存器；基于所述BMC状态信息，以与所述BMC状态信息相对应的通信方式与BMC进行通信（102）。由此，CPU通过读取BMC状态信息来及时获知BMC的状态，能够基于BMC的实时状态来以相应的通信方式进行通信，避免在BMC出现异常时，CPU仍然向BMC发出读写等通信请求造成资源浪费为系统管理和维护造成不便的情况。

Description

一种通信控制方法及电子设备 技术领域
本公开涉及计算机技术领域，特别涉及一种通信控制方法及电子设备。
背景技术
在计算机中，操作系统(Operating System，OS)也就是中央处理器(Central Processing Unit，CPU)和基板管理控制器(Baseboard Management Controller，BMC)之间的智能平台管理接口(Intelligent Platform Management Interface，IPMI)协议传输，一般是通过内核换成系统(Kernel Cache System，KCS)接口来完成的。IPMI协议的特点是：读写操作由CPU发起，BMC只能被动等待CPU的读写响应，而无法主动向CPU发起通信。
正是由于IPMI协议的特点，使得一旦BMC出现异常而导致KCS接口无法完成后续的协议交互时，BMC的异常无法被CPU所获取，CPU会仍然继续向BMC发出读写等通信要求，造成资源浪费，为系统管理及维护带来很大不便。
发明内容
有鉴于此，本公开的目的是提供一种通信控制方法及电子设备，用以解决现有技术中BMC的异常无法被CPU所获取所造成的资源浪费的技术问题。
本公开提供了一种通信控制方法，该方法包括：
读取状态寄存器中所存储的BMC状态信息，所述状态寄存器为CPU与BMC之间的KCS接口的寄存器；
基于所述BMC状态信息，以与所述BMC状态信息相对应的通信方式与BMC进行通信。
上述方法，可选地，读取状态寄存器中所存储的BMC状态信息，包括：
读取所述状态寄存器中原始设备制造商(Original Equipment Manufacturer，OEM)位中的字节码；
识别所述字节码所对应的BMC状态信息。
上述方法，可选地，所述识别所述字节码所对应的BMC状态信息，包括：
基于预设的码与状态信息的对应关系，确定所述字节码对应的BMC状态信息；
其中，如果所述字节码为第一数值，所述BMC状态信息表明所述BMC处于正常状态；
如果所述字节码为第二数值，所述BMC状态信息表明所述BMC处于异常状态。
上述方法，可选地，所述基于所述BMC状态信息，以与所述BMC状态信息相对应的通信方式与BMC进行通信，包括：
如果所述BMC状态信息表明所述BMC处于正常状态，以第一通信方式与BMC进行通信；
如果所述BMC状态信息表明所述BMC处于异常状态，以第二通信方式与BMC进行通信。
上述方法，可选地，以第一通信方式与BMC进行通信，包括：
向KCS接口的写寄存器中写入第一目标数据。
上述方法，可选地，以第二通信方式与BMC进行通信，包括：
读取KCS接口的读寄存器中的第二目标数据，所述第二目标数据为BMC出现异常时所写入的数据，所述第二目标数据表明所述BMC出现异常的异常类型信息。
上述方法，可选地，还包括：
基于所述第二目标数据，启动异常处理进程。
本公开还提供了另一种通信控制方法，包括：
BMC将BMC状态信息写入状态寄存器中，所述状态寄存器为CPU与BMC之间的KCS接口的寄存器，使得CPU通过读取所述BMC状态信息以与所述BMC状态信息相对应的通信方式与BMC进行通信；
上述方法，可选地，还包括：
BMC将第二目标数据写入到KCS接口的读寄存器中，所述第二目标数据表明所述BMC出现异常的异常类型信息，使得CPU通过读取所述第二目标数据并基于所述第二目标数据启动异常处理进程。
本公开还提供了一种电子设备，包括：CPU；BMC；以及连接在CPU与BMC之间的KCS接口，所述KCS接口具有状态寄存器；
其中：
BMC将BMC状态信息写入状态寄存器中，CPU通过读取所述状态寄存器中所存储的BMC状态信息，以与所述BMC状态信息相对应的通信方式与BMC进行通信。
由上述方案可知，本公开提供的一种通信控制方法及电子设备，在CPU端通过在KCS接口的状态寄存器中读取所存储的BMC状态信息，从而再基于这一BMC状态信息以相应的通信方式与BMC进行通信，由此，CPU通过读取BMC状态信息来及时获知BMC的状态，能够基于BMC的实时状态来以相应的通信方式进行通信，避免在BMC出现异常时，CPU仍然向BMC发出读写等通信请求造成资源浪费为系统管理和维护造成不便的情况，实现本 公开目的。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种通信控制方法的实现流程图；
图2为本公开实施例的应用示例图；
图3为本公开实施例提供的一种通信控制方法的部分流程图；
图4为本公开实施例提供的一种通信控制方法的实现流程图；
图5为本公开实施例提供的KCS接口的寄存器的位结构示意图；以及
图6为本公开实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在此使用的术语仅仅是为了描述具体实施例，而并非意在限制本公开。在此使用的术语“包括”、“包含”等表明了所述特征、步骤、操作和/或部件的存在，但是并不排除存在或添加一个或多个其他特征、步骤、操作或部件。
在此使用的所有术语(包括技术和科学术语)具有本领域技术人员通常所理解的含义，除非另外定义。应注意，这里使用的术语应解释为具有与本说明书的上下文相一致的含义，而不应以理想化或过于刻板的方式来解释。
在使用类似于“A、B和C等中至少一个”这样的表述的情况下，一般来说应该按照本领域技术人员通常理解该表述的含义来予以解释(例如，“具有A、B和C中至少一个的系统”应包括但不限于单独具有A、单独具有B、单独具有C、具有A和B、具有A和C、具有B和C、和/或具有A、B、C的系统等)。在使用类似于“A、B或C等中至少一个”这样的表述的情况下，一般来说应该按照本领域技术人员通常理解该表述的含义来予以解释(例如， “具有A、B或C中至少一个的系统”应包括但不限于单独具有A、单独具有B、单独具有C、具有A和B、具有A和C、具有B和C、和/或具有A、B、C的系统等)。本领域技术人员还应理解，实质上任意表示两个或更多可选项目的转折连词和/或短语，无论是在说明书、权利要求书还是附图中，都应被理解为给出了包括这些项目之一、这些项目任一方、或两个项目的可能性。例如，短语“A或B”应当被理解为包括“A”或“B”、或“A和B”的可能性。
附图中示出了一些方框图和/或流程图。应理解，方框图和/或流程图中的一些方框或其组合可以由计算机程序指令来实现。这些计算机程序指令可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器，从而这些指令在由该处理器执行时可以创建用于实现这些方框图和/或流程图中所说明的功能/操作的装置。
因此，本公开的技术可以硬件和/或软件(包括固件、微代码等)的形式来实现。另外，本公开的技术可以采取存储有指令的计算机可读介质上的计算机程序产品的形式，该计算机程序产品可供指令执行系统使用或者结合指令执行系统使用。在本公开的上下文中，计算机可读介质可以是能够包含、存储、传送、传播或传输指令的任意介质。例如，计算机可读介质可以包括但不限于电、磁、光、电磁、红外或半导体系统、装置、器件或传播介质。计算机可读介质的具体示例包括：磁存储装置，如磁带或硬盘(HDD)；光存储装置，如光盘(CD-ROM)；存储器，如随机存取存储器(RAM)或闪存；和/或有线/无线通信链路。
参考图1，为本公开实施例提供的一种通信控制方法的实现流程图，应用于CPU中，为了能够及时得知BMC的状态而进行相应的通信，CPU可以通过执行以下步骤实现：
步骤101：读取状态寄存器中所存储的BMC状态。
其中，状态寄存器为CPU与BMC之间的KCS接口的寄存器，如图2中所示。
其中，BMC会实时更新其BMC状态信息到该状态寄存器中的相关位中，由此，CPU能够通过对KCS接口的状态寄存器中存储的BMC状态信息进行读取，进而及时了解到BMC当前的状态，如BMC处于正常状态还是异常状态，或者BMC处于正常状态还是某种原因导致的异常状态。
步骤102：基于BMC状态信息，以与BMC状态信息相对应的通信方式与BMC进行通信。
也就是说，CPU在读取到能够表征BMC当前状态的BMC状态信息之后，会根据BMC当前的状态，以不同的方式与BMC进行通信，而不是现有技术中不论BMC出于何种终端，CPU均会向BMC发起读取等通信操作，由此，本公开中不会由于CPU无变通的通信方式而出现资源浪费及系统管理及维护不便的情况。
由上述方案可知，本公开实施例提供的一种通信控制方法，在CPU端通过在KCS接口的状态寄存器中读取所存储的BMC状态信息，从而再基于这一BMC状态信息以相应的通信方式与BMC进行通信，由此，CPU通过读取BMC状态信息来及时获知BMC的状态，能够基于BMC的实时状态来以相应的通信方式进行通信，避免在BMC出现异常时，CPU仍然向BMC发出读写等通信请求造成资源浪费为系统管理和维护造成不便的情况，实现本实施例目的。
在一种实现方式中，CPU在读取状态寄存器中所存储的BMC状态信息时，可以通过以下步骤实现，如图3中所示：
步骤301：读取状态寄存器中OEM位中的字节码。
也就是说，BMC会实时将能够表征其当前状态的BMC状态信息写入到KCS接口的状态寄存器中的OEM位，由于OEM(Original Equipment Manufacturer，原始设备制造商)为是设备制造商预留的位，并没有被使用，由此，本实施例中CPU可以从KCS接口的状态寄存器中的OEM位中准确读取到BMC在OEM位所写入的代表BMC状态信息的字节码。
步骤302：识别字节码所对应的BMC状态信息。
其中，OEM位在KCS接口的状态寄存器中一般有两位，如OEM1和OEM2，BMC在OEM1和OEM2中写入字节码，来表征BMC当前所处的状态，如正常状态或者异常状态等，之后，CPU在需要与BMC进行通信时首先读取该字节码，并通过预设的码与状态信息的对应关系来确定字节码对应的BMC状态信息，不同数值的字节码可以与不同的BMC状态信息相对应，用于表示BMC处于不同的状态。
其中，码与状态信息的对应关系可以预先由厂商自行设置，或者由厂商之间共同约定。
需要说明的是，在字节码与状态信息的对应关系中可以包括有两个对应关系，例如：
字节码为第一数值，对应于BMC状态信息表明BMC处于正常状态；字节码为第二数值，对应于BMC状态信息表明BMC处于异常状态。
以上通过预先对字节码设置两个数值来表征BMC处于正常还是处于异常状态。
或者，字节码与状态信息的对应关系中可以包括更多个对应关系，例如：
字节码为第一数值，对应于BMC状态信息表明BMC处于正常状态；字节码为第二数值，对应于BMC状态信息表明BMC处于第一类型的异常状态；字节码为第三数值，对应于BMC状态信息表明BMC处于第二类型的异常状态；等等。
以上通过预先对字节码设置多个数值来分别表明BMC处于正常状态还是处于哪种类型的异常状态，如BMC芯片崩溃类型的异常信息或OEM意外重启类型的异常状态等。
由此，CPU在基于预设的码与状态信息的对应关系确定字节码对应的BMC状态信息时，有以下两种情况：
一种：CPU可以通过字节码的数值确定出BMC处于正常状态还是异常状态；
一种：CPU可以通过字节码的数值确定出BMC处于正常状态还是异常状态，进一步的在BMC处于异常状态时，CPU通过字节码的数值还可以确定出BMC处于哪种类型的异常状态。
在一种实现方式中，CPU在读取到BMC状态信息，并以与BMC状态信息相对应的通信方式与BMC进行通信时，可以通过预设的不同的通信方式进行通信，例如：
如果BMC状态信息表明BMC处于正常状态，则以第一通信方式与BMC进行通信，如向KCS接口的写寄存器中写入第一目标数据等；
如果BMC状态信息表明BMC处于异常状态或者某种类型的异常状态，则以不同于第一通信方式的第二通信方式进行通信，如读取KCS接口的读寄存器中的第二目标数据，第二目标数据为BMC出现异常时所写入的数据，能够表明BMC出现异常的异常类型信息。
也就是说，在BMC状态信息表明BMC处于正常状态时，第一通信方式可以为CPU与BMC之间正常的基于IPMI协议通过KCS接口所实现的通信方式。
例如：CPU通过读取OEM位中的字节码判断出BMC状态信息表明BMC处于正常状态时，CPU向KCS接口的写寄存器中写入第一目标数据，之后，BMC基于第一目标数据向KCS接口的读寄存器中写入回复数据，CPU能够从KCS接口的读寄存器中读取到BMC写入的回复数据，完成通信。
在BMC状态信息表明BMC处于异常状态时，第二通信方式可以为CPU只读取的通信方式。
例如，CPU通过读取OEM位中的字节码判断出BMC状态信息表明BMC处于异常状态时，CPU从KCS接口的读寄存器中读取到BMC写入的第二目标数据数据，完成通信。
在一种实现方式中，BMC在异常时写入到KCS接口的读寄存器中的第二目标数据能够表明BMC出现异常的异常类型信息，如BMC所出现的异常是哪种原因导致的或者BMC所出现的异常该用哪种类型的对应方式等等。由此，在CPU读取到该第二目标数据之后，可以通过启动异常处理进程来进行异常处理，尽快对BMC出现异常做出应对措施，尽量避免不必要的损失甚至CPU崩溃的情况。
参考图4，为本公开实施例提供的一种通信控制方法的实现流程图，适用于BMC中，可以以下步骤：
步骤401：监测BMC的状态，以获得BMC状态信息。
步骤402：将BMC状态信息写入状态寄存器中，以提供给CPU读取。
其中，状态寄存器为BMC与CPU之间的KCS接口的寄存器，由此，BMC将能够表征BMC当前状态的信息写入到状态寄存器中，当CPU需要进行读写等通信时，可以通过读取状态寄存器中的BMC状态信息来确定BMC当前的状态，并以相应的通信方式与BMC进行通信。
由此，CPU通过读取BMC状态信息来及时获知BMC的状态，能够基于BMC的实时状态来以相应的通信方式进行通信，避免在BMC出现异常时，CPU仍然向BMC发出读写等通信请求造成资源浪费为系统管理和维护造成不便的情况，实现本实施例目的。
在一种实现方式中，BMC将其BMC状态信息写入到状态寄存器中的OEM位中，通过OEM位中字节码所指代的数值来表征BMC处于正常状态还是异常状态，或者处于哪种类型的异常状态等。
在一种实现方式中，BMC在其出现异常时可以将能够表明BMC出现异常的异常类型信息的第二目标数据写入到KCS接口的读寄存器中，进而，CPU在通过读取OEM位中的字节码发现BMC已经处于异常状态时，可以从KCS接口的读寄存器中读取到第二目标数据，并基于此来知道BMC出现异常的异常类型信息，如什么原因造成的BMC异常等，之后，CPU可以基于该第二目标数据启动异常处理进程，从而进行异常处理，以便尽快避免损失或尽快恢复正常。
其中，KCS接口的寄存器的位结构可以参考图5中所示，寄存器中的8位可以通过位共享的方式供CPU和BMC进行信息写入，如状态寄存器、写寄存器及读寄存器：0-7，其中，写寄存器用于CPU进行第一目标数据的写入，读寄存器用于BMC进行回复数据或者BMC异常类型信息即第二目标数据的写入，而状态寄存器中的OEM位用于BMC状态信息的写入。基于该寄存器中的位结构，本公开实现以上方案。
参考图6，为本公开实施例提供的一种电子设备的结构示意图，该电子设备中可以包括有：
CPU601；BMC602；以及连接在CPU601与BMC602之间的KCS接口603，而KCS接口603具有状态寄存器604；
其中：
BMC602将BMC状态信息写入状态寄存器604中，CPU601通过读取状态寄存器604中所存储的BMC状态信息，以与BMC状态信息相对应的通信方式与BMC602进行通信。
由此，本实施例的电子设备中，CPU601通过读取BMC602状态信息来及时获知BMC602的状态，能够基于BMC602的实时状态来以相应的通信方式进行通信，避免在BMC602出现异常时，CPU601仍然向BMC602发出读写等通信请求造成资源浪费为系统管理和维护造成不便的情况，实现本公开目的。
需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
本领域技术人员可以理解，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合或/或结合，即使这样的组合或结合没有明确记载于本公开中。特别地，在不脱离本公开精神和教导的情况下，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合和/或结合。所有这些组合和/或结合均落入本公开的范围。
以上对本发明所提供的一种通信控制方法及电子设备进行了详细介绍，对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种通信控制方法，包括：
    读取状态寄存器中所存储的BMC状态信息，所述状态寄存器为CPU与BMC之间的KCS接口的寄存器；
    基于所述BMC状态信息，以与所述BMC状态信息相对应的通信方式与所述BMC进行通信。
  2. 根据权利要求1所述的方法，其中，读取状态寄存器中所存储的BMC状态信息，包括：
    读取所述状态寄存器中原始设备制造商位中的字节码；
    识别所述字节码所对应的BMC状态信息。
  3. 根据权利要求2所述的方法，其中，所述识别所述字节码所对应的BMC状态信息，包括：
    基于预设的码与状态信息的对应关系，确定所述字节码对应的BMC状态信息；
    其中，如果所述字节码为第一数值，所述BMC状态信息表明所述BMC处于正常状态；
    如果所述字节码为第二数值，所述BMC状态信息表明所述BMC处于异常状态。
  4. 根据权利要求1所述的方法，其中，所述基于所述BMC状态信息，以与所述BMC状态信息相对应的通信方式与所述BMC进行通信，包括：
    如果所述BMC状态信息表明所述BMC处于正常状态，以第一通信方式与所述BMC进行通信；
    如果所述BMC状态信息表明所述BMC处于异常状态，以第二通信方式与所述BMC进行通信。
  5. 根据权利要求4所述的方法，其中，以第一通信方式与所述BMC进行通信，包括：
    向所述KCS接口的写寄存器中写入第一目标数据。
  6. 根据权利要求4所述的方法，其中，以第二通信方式与所述BMC进行通信，包括：
    读取所述KCS接口的读寄存器中的第二目标数据，所述第二目标数据为所述BMC出现异常时所写入的数据，所述第二目标数据表明所述BMC出现异常的异常类型信息。
  7. 根据权利要求6所述的方法，其中，还包括：
    基于所述第二目标数据，启动异常处理进程。
  8. 一种通信控制方法，包括：
    BMC将BMC状态信息写入状态寄存器中，所述状态寄存器为CPU与所述BMC之间的 KCS接口的寄存器，使得所述CPU在读取所述BMC状态信息之后，以与所述BMC状态信息相对应的通信方式与所述BMC进行通信；
  9. 根据权利要求8所述的方法，其中，还包括：
    所述BMC将第二目标数据写入到所述KCS接口的读寄存器中，所述第二目标数据表明所述BMC出现异常的异常类型信息，使得所述CPU在读取所述第二目标数据之后，并基于所述第二目标数据启动异常处理进程。
  10. 一种电子设备，包括：CPU；BMC；以及连接在所述CPU与所述BMC之间的KCS接口，所述KCS接口具有状态寄存器；
    其中：
    所述BMC将BMC状态信息写入状态寄存器中，所述CPU通过读取所述状态寄存器中所存储的BMC状态信息，以与所述BMC状态信息相对应的通信方式与所述BMC进行通信。
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CN106020804A (zh) * 2016-05-12 2016-10-12 浪潮电子信息产业股份有限公司 一种自动更新dmi电源信息的方法

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