WO2018231212A1

WO2018231212A1 - Quantum computing package structures

Info

Publication number: WO2018231212A1
Application number: PCT/US2017/037378
Authority: WO
Inventors: Shawna LIFF; Adel A. ELSHERBINI; Johanna M. Swan; Javier A. FALCON; Ye Seul Nam; James S. Clarke; Jeanette M. Roberts; Roman CAUDILLO
Original assignee: Intel Corporation
Priority date: 2017-06-14
Filing date: 2017-06-14
Publication date: 2018-12-20

Abstract

Disclosed herein are quantum computing (QC) package structures, as well as related methods and devices. In some embodiments, a QC package may include: a package substrate; a quantum processing die coupled to the package substrate; and a lid above the quantum processing die such that the quantum processing die is between the package substrate and a top portion of the lid, wherein the lid is electrically coupled to the quantum processing die and to the package substrate. In some embodiments, a QC package may include: a package substrate; and a quantum processing die coupled to the package substrate; wherein the quantum processing die includes at least one first stop element, the package substrate includes at least one second stop element, and the first stop elements are aligned with the second stop elements to provide a mechanical stop structure between the quantum processing die and the package substrate

Description

QUANTUM COMPUTING PACKAGE STRUCTURES

Background

[0001] Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

Brief Description of the Drawings

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0003] FIGS. 1-7 are side cross-sectional views of example quantum computing (QC) packages, in accordance with various embodiments.

[0004] FIGS. 8-12 are perspective views of various mechanical stop structures that may be included in a QC package, in accordance with various embodiments.

[0005] FIG. 13 is a block diagram of an example superconducting qubit-type quantum device, in accordance with various embodiments.

[0006] FIGS. 14 and 15 illustrate example physical layouts of superconducting qubit-type quantum devices, in accordance with various embodiments.

[0007] FIGS. 16A-C are cross-sectional views of a spin qubit-type quantum device, in accordance with various embodiments.

[0008] FIGS. 17A-C are cross-sectional views of various examples of quantum well stacks that may be used in a spin qubit-type quantum device, in accordance with various embodiments.

[0009] FIG. 18 is a top view of a wafer and dies that may be included in any of the QC packages disclosed herein.

[0010] FIG. 19 is a cross-sectional side view of a device assembly that may include any of the QC packages disclosed herein.

[0011] FIG. 20 is a block diagram of an example quantum computing device that may include any of the QC packages disclosed herein, in accordance with various embodiments.

Detailed Description

[0012] Disclosed herein are quantum computing (QC) package structures, as well as related methods and devices. In some embodiments, a QC package may include: a package substrate; a quantum processing die coupled to the package substrate; and a lid above the quantum processing die such that the quantum processing die is between the package substrate and a top portion of the lid, wherein the lid is electrically coupled to the quantum processing die and to the package substrate. In some embodiments, a QC package may include: a package substrate; and a quantum processing die coupled to the package substrate; wherein the quantum processing die includes at least one first stop element, the package substrate includes at least one second stop element, and the first stop elements are aligned with the second stop elements to provide a mechanical stop structure between the quantum processing die and the package substrate.

[0013] Some conventional integrated circuit (IC) packages may include a thermal lid to conduct heat away from a die. Conventional thermal lids may be formed of copper (e.g., in high-end applications) and may be coupled to the die with an adhesive thermal interface material (TIM). Typically, a conventional lid is "bottomed out" on the die, squeezing a TIM therebetween and forming a thin, non-conductive bond-line with low thermal resistance. The lid may then be anchored in the package using an electrically insulating sealant.

[0014] Such conventional lids may cause significant performance degradation in quantum computing packages. As an initial matter, in a quantum computing package that includes superconducting qubit-type quantum devices, the presence of a conventional thermal lid may negatively impact the package's radio frequency ( F) performance by introducing spurious resonant modes within the package. Additionally, the thermal compression bonding operations that may be used to secure the conventional thermal lid in the package may disrupt the interconnects between the die and the package substrate (e.g., by causing bridging or other solder joint problems).

[0015] The QC package structures disclosed herein may address one or more of these issues, providing improved thermal and electrical performance relative to conventional approaches.

Additionally, although the lid and mechanical stop structures disclosed herein may be particularly advantageous in the quantum computing setting, all of the lid and mechanical stop structures disclosed herein may be used for non-quantum packages (e.g., when the packaged die is not a quantum processing die), solely or in combination.

[0016] In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. [0017] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment.

Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0018] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

[0019] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. When used to describe a range of dimensions, the phrase "between X and Y" represents a range that includes X and Y. As used herein, the terms "conductive" and "electrically conductive" are synonymous unless otherwise indicated. Although various ones of the drawings illustrate certain features in combination (e.g., a QC package that includes a lid and a mechanical stop structure), the embodiments disclosed herein may include any of these features alone (e.g., a QC package that includes a lid and no mechanical stop structure, or a QC package that includes a mechanical stop structure and not lid) or in any other combination.

[0020] As used herein, terms indicating what may be considered an idealized behavior, such as "superconducting" or "lossless," are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss, either in terms of nonzero electrical resistance or a nonzero amount of spurious two-level systems may be acceptable, and thus the resulting materials and structures may still be referred to by these

"idealized" terms. Specific values associated with an acceptable level of loss are expected to change over time as fabrication precision improves and as fault-tolerant schemes become more tolerant of higher losses, all of which are within the scope of the present disclosure.

[0021] As used herein, a "magnet line" refers to a magnetic field-generating structure to influence (e.g., change, reset, scramble, or set) the spin states of quantum dots. One example of a magnet line, as discussed herein, is a conductive pathway that is proximate to an area of quantum dot formation and selectively conductive of a current pulse that generates a magnetic field to influence a spin state of a quantum dot in the area.

[0022] FIGS. 1-7 are side cross-sectional views of example QC packages 100, in accordance with various embodiments. Beginning with FIG. 1, the QC package 100 may include a package substrate 102 and a quantum processing (QP) die 104 coupled to the package substrate 102. In particular, conductive contacts 130 at a top face 126 of the package substrate 102 may be electrically coupled to conductive contacts 122 at a bottom face 118 of the QP die 104 by first level interconnects (FLI) 132. The FLI 132 may include solder bumps or balls; for example, the FLI 132 may be flip chip (or controlled collapse chip connection, C4) bumps disposed initially on the QP die 104 or on the package substrate 102. In some embodiments, the FLI 132 may include an indium-based solder (e.g., a solder including indium or an indium alloy). Indium-based solders may be advantageous for quantum computing applications because they are superconducting and ductile at cryogenic temperatures. The package substrate 102 may include conductive contacts 110 disposed at a bottom face 128 of the package substrate 102. Second level interconnects (SLI) 109 (e.g., solder balls or other types of interconnects) may be disposed on the conductive contacts 110. In some embodiments, the bottom face 128 of the package substrate 102 may not include solder balls, but may instead include a series of connectors (e.g., coaxial or twinaxial connectors); solder may be used to secure the connectors to the bottom face 128. The QP die 104 and the package substrate 102 may have an x-y footprint with side dimensions between 2 millimeters and 100 millimeters. In some embodiments, a thickness of the QP die 104 may be between 100 microns and 800 microns. The QP die 104 may include circuitry for performing quantum computations; a number of embodiments of such circuitry are discussed below.

[0023] The conductive contacts disclosed herein may be formed of any suitable conductive material (e.g., a superconducting material). Various ones of the conductive contacts illustrated in the drawings may take form of solder bond pads, but other structures may be used (e.g., conductive epoxies, anisotropic conductive films, metal-to-metal bonding posts, etc.) to route electrical signals to/from the QP die 104 and the package substrate 102, as discussed below. The QP die 104 and the package substrate 102 may include conductive pathways therein (not shown) for routing electrical signals. For example, conductive pathways may extend through an insulating material of the package substrate 102 between the bottom face 128 and the top face 126 of the package substrate 102, electrically coupling various ones of the conductive contacts 130 to various ones of the conductive contacts 110, in any desired manner. Similarly, conductive pathways may extend through an insulating material of the QP die 104 between the bottom face 118 and the top face 120 of the QP die 104, electrically coupling various ones of the conductive contacts 122 to various ones of the conductive contacts 124, in any desired manner. The insulating material may be a dielectric material (e.g., an interlayer dielectric), such as silicon oxide, silicon nitride, aluminum oxide, carbon- doped oxide, and/or silicon oxynitride. The conductive pathways may include one or more conductive vias, one or more conductive lines, or a combination of conductive vias and conductive lines, for example. During operation of the QC package 100, electrical signals (such as power, input/output (I/O) signals, various control signals, etc.) may be routed to and/or from the QP die 104 through the package substrate 102. In some embodiments, the conductive elements in the QC package 100 (e.g., the conductive contacts, lines, vias, etc.) may include a superconducting material, such as aluminum, niobium, tin, titanium, osmium, zinc, molybdenum, tantalum, vanadium, or composites of such materials (e.g., niobium titanium, niobium-aluminum, titanium nitride, or niobium tin).

[0024] The conductive contacts 110, 122, 130, and/or 124 may include multiple layers of material that may be selected to serve different purposes. In some embodiments, the conductive contacts may be formed of aluminum, and may include a layer of gold (e.g., with a thickness of less than 1 micron) between the aluminum and the adjacent interconnect to limit the oxidation of the surface of the contacts and improve the adhesion with adjacent solder. Alternate materials for the surface finish include palladium, platinum, silver and tin. In some embodiments, the conductive contacts may be formed of aluminum, and may include a layer of a barrier metal such as nickel or cobalt, as well as a layer of gold, or other appropriate material, wherein the layer of barrier metal is disposed between the aluminum and the layer of gold, and the layer of gold is disposed between the barrier metal and the adjacent interconnect. In such embodiments, the gold, or other surface finish, may protect the barrier metal surface from oxidation before assembly, and the barrier metal may limit the diffusion of solder from the adjacent interconnects into the aluminum.

[0025] Limiting differential expansion and contraction may help preserve the mechanical and electrical integrity of the QC package 100 as the QC package 100 is fabricated (and exposed to higher temperatures) and used in a cooled environment (and exposed to lower, cryogenic temperatures). In some embodiments, thermal expansion and contraction in the package substrate 102 and/or QP die 104 may be managed by maintaining an approximately uniform density of the conductive material in these elements (so that different portions of these elements expand and contract uniformly), using reinforced dielectric materials as the insulating material (e.g., dielectric materials with silicon dioxide fillers), or utilizing stiffer materials as the insulating material (e.g., a prepreg material including glass cloth fibers). [0026] In some embodiments, the QC package 100 may include a lid 106. The lid 106 may have a top portion 112 and a footer portion 114; the QP die 104 may be between the package substrate 102 and the top portion 112 of the lid 106, and the footer portion 114 may extend down laterally around the QP die 104 to mechanically couple with the package substrate 102. The lid 106 may act as a thermal spreader and sink, conducting heat away from the QP die 104. At the cryogenic temperatures at which the QC package 100 may operate, the heat capacities of most materials are low, and thus significant heat must be drawn away from the QP die 104 for successful operation. An interface material 108 may be disposed between the QP die 104 and the top portion 112 of the lid 106. In some embodiments, the interface material 108 may be a TIM, such as a thermal paste. A thickness of the interface material 108 between the top face 120 of the QP die 104 and the lid 106 may take any suitable value (e.g., between 20 microns and 500 microns, or between 100 microns and 300 microns). Although the lid 106 is illustrated as a single, monolithic structure, the lid 106 may be formed and assembled in two or more sections, as desired (e.g., a section for the top portion 112 and a section for the footer portion 114).

[0027] The lid 106 may include any suitable materials. For example, in some embodiments, the lid 106 may include a superconducting material, such as aluminum or any of the other superconducting materials disclosed herein. A lid 106 including aluminum (e.g., pure aluminum or an aluminum alloy) may be advantageous over a lid 106 including copper because the coefficient of thermal expansion (CTE) of copper is larger than that of aluminum (which may result in CTE mismatch with surrounding materials, and thus delamination or cracking). Further, when the lid 106 is to be conductively coupled to the QP die 104 and the package substrate (and may conduct electrical signals), aluminum may be advantageous over copper because aluminum is a superconductor below 1.2 Kelvin (while copper is not).

[0028] The lid 106 may have any suitable dimensions. For example, a thickness of a top portion of the lid 106 may be between 0.0.05 millimeters and 5 millimeters, in some embodiments. Other dimensions of a lid 106, such as the depths of any recesses included in the top portion 112 of the lid 106, or the spacing between the footer portion 114 of the lid 106 and the side faces of the QP die 104, may be selected to achieve particular performance requirements (e.g., to tune resonances), as discussed below.

[0029] In some embodiments, the lid 106 may be conductively coupled to the QP die 104. For example, the QP die 104 may include one or more conductive contacts 124 at the top face 120 of the QP die 104 (as illustrated in FIG. 1), the lid 106 and the interface material 108 may be conductive, and those conductive contacts 124 may be conductively coupled to the lid 106 via the conductive interface material 108. Examples of conductive interface material 108 may include a conductive polymer compound (e.g., a visco-elastic polymer having conductive particles suspended therein), aluminum, tin, gold, zinc, cobalt, indium (e.g., bulk indium or a binary or tertiary indium alloy), or nickel. In some embodiments, the conductive contacts 124 and/or the bottom face of the top portion 112 of the lid 106 may include gold or aluminum with gold plating (e.g., to promote wetting and/or adhesion with a conductive interface material 108 including indium or an indium alloy). In some embodiments, the conductive contacts 124 and/or the bottom face of the top portion 112 of the lid 106 may include a layer of tin zinc, zinc aluminum, cobalt, or nickel (e.g., to enable robust interconnects). In some embodiments, the lid 106 and the conductive contacts 124 may be bonded together using a metal-to-metal weld (e.g., an aluminum-to-aluminum weld), and thus no additional interface material 108 may be present.

[0030] In other embodiments, the lid 106 may not be conductively coupled to the QP die 104 but instead capacitively coupled to the QP die 104.; in some such embodiments, the interface material 108 may be a thin layer of an electrical insulator, such as non-conductive cryogenic thermal grease (e.g., a hydrocarbon high vacuum grease, such as Apezion). In other embodiments, the lid 106 may not be conductively or capacitively coupled to the QP die 104.

[0031] In some embodiments, the lid 106 may be conductively coupled to the package substrate 102. For example, the lid 106 may be conductive, and a conductive interface material 108 (e.g., in accordance with any of the material compositions discussed above) may be disposed between the lid 106 and one or more conductive contacts 130 (e.g., in accordance with any of the material compositions discussed above for the conductive contacts 124) at the top face 126 of the package substrate 102 (e.g., as illustrated in FIG. 1). Similarly, the portion of the footer portion 114 in contact with the conductive interface material 108 may take any of the forms discussed above with reference to the bottom face of the top portion 112. In other embodiments, the lid 106 may not be conductively coupled to the package substrate 102 (e.g., the package substrate 102 may not include any conductive contacts 130 aligned with the footer portion 114, and/or any interface material 108 between the footer portion 114 and the top face 126 of the package substrate 102 may be an electrical insulator), or the lid 106 may be capacitively coupled to the package substrate 102 (as discussed above). When the interface material 108 is present between the footer portion 114 of the lid 106 and the top face 126 of the package substrate 102 (e.g., as shown in FIG. 1), a thickness of the interface material 108 between the top face 126 of the package substrate 102 and the lid 106 may take any suitable value (e.g., between 20microns and 500microns). Note that the material composition of the interface material 108 at the footer portion 114 may be different than the interface material 108 at the top portion 112. In some embodiments, the footer portion 114 may be conductively coupled to the package substrate 102 via a metal-to-metal bond, as discussed above. [0032] In some embodiments, the lid 106 may be conductively coupled to both the package substrate 102 and the QP die 104. Having the lid 106 be electrically connected to both the QP die 104 and the package substrate 102 may suppress spurious modes in QP dies 104 that include resonators (as discussed below), and may help with confinement and/or uniformity. In some embodiments, the QP die 104 may include conductive pathways that conductively couple the resonators (discussed below) to the lid 106 and the package substrate 102.

[0033] In some embodiments, a single lid 106 may be disposed over multiple QP dies 104 or other dies; an example of such an embodiment is discussed below with reference to FIG. 6. In some embodiments, the QC package 100 may include multiple lids 106 (e.g., each disposed over one or more QP dies 104 or other dies). A number of examples of lids 106 are discussed below with reference to FIGS. 3-6. In some embodiments, the QC package 100 may not include a lid 106.

[0034] In some embodiments, the QC package 100 may include one or more mechanical stop structures 138. A mechanical stop structure 138 may include an arrangement of structures on the QP die 104 and the package substrate 102 that limits the relative movement of the QP die 104 and the package substrate 102 when the QP die 104 and the package substrate 102 are compressed. For example, during manufacture of the QC package 100, the QP die 104 may be brought in contact with the package substrate 102 using a pick-and-place apparatus, for example, and a reflow or thermal compression bonding operation may be used to couple the QP die 104 to the package substrate 102 via the FLI 132. In particular, a mechanical stop structure 138 between the QP die 104 and the package substrate 102 may limit or prevent the FLI 132 from being compressed and deformed during handling or processing (e.g., during thermal compression bonding of the lid 106), mitigating the risk of solder bridging. A mechanical stop structure 138 may be particularly valuable when the FLI 132 include a solder that is soft at room temperature (or other processing temperatures), such as indium-based solders; such FLI 132 may be easily bridged during thermal compression bonding (e.g., during attachment of a lid 106) or other normal handling, in the absence of a mechanical stop structure 138.

[0035] A mechanical stop structure 138 may take any suitable form. In some embodiments, a mechanical stop structure 138 may include one or more first stop elements 140 on the bottom face 118 of the QP die 104, and one or more second associated stop elements 142 on the top face 126 of the package substrate 102. The first stop element(s) 140 and the associated second stop element(s) 142 may mate or otherwise contact each other to provide a mechanical stop structure 138 that limits the relative motion of the QP die 104 and the package substrate 102 when compressed. For example, FIG. 1 illustrates a mechanical stop structure 138 in which the first stop elements 140 are portions of spheres on the bottom face 118 of the QP die 104, and the second stop elements 142 are recesses (e.g., faceted recesses) in the top face 126 of the package substrate 102 that at least partially receive the first stop elements 140. This particular mechanical stop structure 138 is simply illustrative, and any mechanical stop structure 138 may be used, such as a kinematic coupling, a Maxwell coupling, a Kelvin coupling, an elastic averaging coupling, a quasi-kinematic coupling, or any combination of desired couplings. A number of examples of mechanical stop structures 138 are discussed below with reference to FIGS. 7-12.

[0036] The type and strength of a mechanical stop structure 138 in a QC package 100 may be selected based on, e.g., the forces expected to impinge on the QC package 100 during manufacturing and handling. In some embodiments, the mechanical stop structure 138 may be configured to limit bridging of the FLI 132 under a thermal compression bonding operation that exerts a compressive force of up to 100s of Newtons (e.g., up to 100 Newtons).

[0037] For any of the mechanical stop structures 138 discussed herein, the structures of the first stop element 140 and the second stop element 142 may be reversed; for example, a variant on the embodiment of FIG. 1 may include a first stop element 140 that is a recess in the bottom face 118 of the QP die 104 and a second stop element 142 that is a portion of a sphere on the top face 126 of the package substrate 102. A stop element in a mechanical stop structure 138 need not include a projection (e.g., the partial sphere of the first stop element 140 of FIG. 1) or a recess; in some embodiments, a flat surface (e.g., of the package substrate 102) may abut a projection (e.g., the partial sphere of the first stop element 140 of FIG. 1) to provide a mechanical stop structure 138. The structures included in a mechanical stop structure 138 may be formed on or in the bottom face 118 of the QP die 104 and the top face 126 of the package substrate 102 in any suitable manner. For example, the stop elements 140/142 may be formed from a dielectric material (e.g., a solder resist or a polyimide), or a conductive material (e.g., a metal) (e.g., using a grayscale technique and plating up). In some embodiments, the first stop elements 140 may be a dielectric material and the second stop elements 142 may be a conductive material (or vice versa). In some embodiments, the first stop element 140 and/or the second stop element 142 may include a hemisphere or other partial sphere provided by a solder ball (e.g., a copper core solder ball, a polymer core solder ball, or a high temperature solder ball) on a conductive contact (e.g., a conductive contact 122 or 130).

[0038] In some embodiments, a QC package 100 that includes a lid 106 may also include a mechanical stop structure 138 between the lid 106 and the package substrate 102; an example of such an embodiment is illustrated in FIG. 2. In particular, FIG. 2 illustrates a mechanical stop structure 138-1 between the QP die 104 and the package substrate 102, and a mechanical stop structure 138-2 between the lid 106 and the package substrate 102. The other elements of the QC package 100 of FIG. 2 (and other figures herein) may take any of the forms disclosed herein, and thus are not discussed further. In some embodiments, a QC package 100 may include a mechanical stop structure 138 between the lid 106 and the package substrate 102, and may not include a mechanical stop structure 138 between the QP die 104 and the package substrate 102. In some embodiments, a QC package 100 may not include any mechanical stop structures 138.

[0039] Any one or more QP dies 104 (and optionally other dies) may be included in a QC package 100. In some embodiments, a QP die 104 may include one or more resonators 116. Resonators 116 may be particularly useful in a superconducting qubit-type QP die 104, as discussed in further detail below with reference to FIGS. 13-15; in particular, the resonators 116 may include the resonators 316 and 318, discussed below. The resonators 116 may be disposed at the bottom face 118 of the QP die 104 (e.g., in areas between the conductive contacts 122) or at the top face 120 of the QP die 104.

[0040] For example, FIG. 3 depicts a QC package 100 including multiple resonators 116 at the bottom face 118 of the QP die 104. Since the electromagnetic fields from the resonators 116 may extend a non-negligible distance from the surface of the QP die 104, the material of the package substrate 102 may advantageously be extremely low loss and/or sufficiently far away from the QP die 104 to reduce the negative effects of these fields on the quality factor of the resonators 116 (and, thus, on the coherence times of the superconducting qubits, discussed in detail below with reference to FIGS. 13-15). In some embodiments, the QP die 104 and the package substrate 102 may be formed on a same substrate material (e.g., a silicon wafer, a germanium, wafer, a lll-V material, etc.).

[0041] FIG. 4 depicts a QC package 100 including multiple resonators 116 disposed at the top face 120 of the QP die 104. In FIG. 4, the interface material 108 between the top face 120 and the lid 106 may be patterned to create cavities 134 around the resonators 116. The dimensions of these cavities (e.g., in the x-, y-, and z-directions) may be selected to achieve desired resonances so as not to introduce spurious modes during operation, as discussed below.

[0042] In some embodiments, a top portion 112 of the lid 106 may include one or more recesses 136. In some embodiments, the dimensions and positions of the recesses 136 may be selected to achieve desired dimensions for cavities 134 around resonators 116 on the top face 120 of a QP die 104. For example, FIG. 5 depicts a QC package 100 having a lid 106 whose top portion 112 includes recesses 136-1 and 136-2 having different depths 146-1 and 146-2, respectively, aligned with different ones of the resonators 116. Recesses 136 may be formed in the lid 106 by molding, stamping, machining or any other suitable technique. Recesses 136 may also be present in the lid 106 to form cavities 134 to accommodate resonators 116 on the bottom face 118 of the QP die 104 (e.g., when the QP die 104 is thin). [0043] In some embodiments, a top portion 112 of the lid 106 may include multiple recesses 136 to accommodate multiple different dies under the lid 106. For example, FIG. 6 illustrates a QC package 100 that includes recesses 136-1 and 136-2 having different depths and other dimensions, selected to accommodate a QP die 104 and another die 105. The die 105 may be a QP die, or may be a die that performs non-quantum processing or control operations (and is in contact with the QP die via the package substrate 102). Although two dies are illustrated in FIG. 6, any desired number of dies may be included in a QC package 100, and a lid 106 may extend over any suitable number of dies.

[0044] In some embodiments, the die 105 may include one or more non-quantum circuits, e.g. the die 105 may include control logic for controlling the operation of the QP die 104. In some embodiments, the control logic may provide peripheral logic to support the operation of the QP die 104. For example, the control logic may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The control logic may also perform conventional computing functions to supplement the computing functions which may be provided by the QP die 104. For example, the control logic may interface with one or more of the other components of a quantum computing device, such as the quantum computing device discussed below with reference to FIG. 20, in a conventional manner, and may serve as an interface between the QP die 104 and conventional components. In some embodiments, the control logic may be implemented in or may be used to implement the non-quantum processing device 2028 described below with reference to FIG. 20.

[0045] The control that the control logic may exercise over the operation of the QP die 104 may depend on the type of qubits implemented by the QP die 104. For example, if the QP die 104 implements superconducting qubits (discussed below with reference to FIGS. 13-15), the control logic may provide and/or detect appropriate currents in any of flux bias lines, microwave lines, and/or drive lines to initialize and manipulate the superconducting dots. In some embodiments, the die 105 may further include circuits performing additional or different functionality than the control logic described above. For example, the die 105 may include components of a communication device to enable communication between the QP die 104 and various external devices.

[0046] As noted above, some embodiments of the QC packages 100 disclosed herein may include one or more mechanical stop structures 138 (e.g., between a QP die 104 and a package substrate 102, and/or between a lid 106 and a package substrate 102). FIGS. 7-12 illustrate various examples of mechanical stop structures 138 that may be included in a QC package 100; these examples are simply illustrative, and are not limiting of the scope of mechanical stop structures 138 that maybe included in a QC package 100. For example, other mechanical stop structures 138, such as pinned joints or flexural kinematic couplings, may be used as desired. [0047] When a stop element 140/142 includes a recess, that recess may be located in a prevailing substantially flat portion of a face, or may be located in a projection extending out from a prevailing portion of a face. For example, FIG. 7 is a side view of a QC package 100 including a mechanical stop structure 138 similar to those of FIG. 1, but in which the second stop elements 142 include a recess within a projection extending away from the top face 126 of the package substrate 102 (instead of a recess within a prevailing flat portion of the face 126, as illustrated in FIG. 1). This may be true for all the mechanical stop structures 138 disclosed herein; the structures included in the stop elements 140/142 may be recessed or projected from a prevailing flat face as desired.

[0048] FIGS. 8-12 are perspective views of various mechanical stop structures 138 in a QC package 100. The arrangements of stop elements 140/142 may be included in a QC package in any desired manner (e.g., distributed in the shadow of a QP die 104 or in the shadow of a lid 106).

[0049] In some embodiments, a mechanical stop structure 138 may be a kinematic coupling. A kinematic coupling is a mechanical coupling designed to exactly constrain a part in the six spatial degrees of freedom. One example of a kinematic coupling is a Maxwell coupling. In a Maxwell coupling, one part has three v-shaped grooves that are arranged and oriented towards a center of the part, and the other part has three curved elements that mate with the three v-shaped grooves, forming two-point contacts at each element. FIG. 8 illustrates a particular example of a Maxwell coupling, including three hemispherical first stop elements 140-1, 140-2, and 140-3, respectively, and three corresponding v-shaped grooves as the second stop elements 142-1, 142-2, and 142-3, respectively.

[0050] Another example of a kinematic coupling is a Kelvin coupling. In a Kelvin coupling, a first part includes a concave tetrahedron, a v-shaped groove, and a flat plate, and the second part has three hemispheres that mate with the elements of the first part, fixing the relative position with three, two, and one point contacts, respectively. FIG. 9 illustrates a particular example of a Kelvin coupling, including three hemispherical first stop elements 140-1, 140-2, and 140-3, respectively, and three corresponding second stop elements 142-1 (the concave tetrahedron), 142-2 (the flat plate), and 142-3 (the v-shaped groove), respectively.

[0051] In some embodiments, a mechanical stop structure 138 may be a quasi-kinematic coupling. FIG. 10 illustrates a particular example of a quasi-kinematic coupling, including three hemispherical first stop elements 140, and three corresponding second stop elements 142, each taking the form of a spherical recess having side reliefs.

[0052] In some embodiments, a mechanical stop structure 138 may be an elastic averaging coupling. In an elastic averaging coupling, each part includes a large number of features that are spread out over an area, and that elastically deform when mated. FIG. 11 illustrates a Hirth coupling, a particular example of an elastic averaging coupling, including a first stop element 140 with radial teeth and a mating second stop element 142 with radial teeth. One or more of the stop elements 140/142 of FIG. 11 may be included in a QC package 100.

[0053] In some embodiments, a mechanical stop structure 138 may include any suitable arrangement of mating first stop elements 140 and second stop elements 142. FIG. 12 illustrates a mechanical stop structure 138 including four first stop elements 140 that take the form of posts or pillars, and four corresponding second stop elements 142 that take the form of complementary holes or receptacles. Variants on the mechanical stop structure 138 of FIG. 12 may include more or fewer posts and larger, shallower receptacles.

[0054] The QP die(s) 104 included in a QC package 100 may take any form. For example, in some embodiments, the QP die 104 may be superconducting qubit-type quantum device or a spin qubit- type quantum device. FIGS. 13-15 discuss example embodiments in which the QP die 104 is a superconducting qubit-type quantum device, and FIGS. 16-17 discuss example embodiments in which the QP die 104 is a spin qubit-type quantum device.

[0055] The operation of superconducting qubit-type quantum devices may be based on the Josephson effect, a macroscopic quantum phenomenon in which a supercurrent (a current that, due to zero electrical resistance, flows for indefinitely long without any voltage applied) flows across a device known as a Josephson junction. Examples of superconducting qubit-type quantum devices may include charge qubits, flux qubits, and phase qubits. Transmons, a type of charge qubit with the name being an abbreviation of "transmission line shunted plasma oscillation qubits,", may exhibit reduced sensitivity to charge noise, and thus may be particularly advantageous. Transmon-type quantum devices include inductors, capacitors, and at least one nonlinear element (e.g., a Josephson junction) are used to achieve an effective two-level quantum state system.

[0056] Josephson junctions may provide the central circuit elements of a superconducting qubit- type quantum device. A Josephson junction may include two superconductors connected by a weak link. For example, a Josephson junction may be implemented as a thin layer of an insulating material, referred to as a barrier or a tunnel barrier and serving as the "weak link" of the junction, sandwiched between two layers of superconductor. Josephson junctions may act as

superconducting tunnel junctions. Cooper pairs may tunnel across the barrier from one

superconducting layer to the other. The electrical characteristics of this tunneling are governed by the Josephson relations. Because the inductance of a Josephson junction is nonlinear, when used in an LC circuit in a transmon-type quantum device, the resulting circuit has uneven spacing between its energy states. In other classes of superconducting qubit-type quantum devices, Josephson junctions combined with other circuit elements may similarly provide the non-linearity necessary for forming an effective two-level quantum state to act as a qubit.

[0057] FIG. 13 is a block diagram of an example superconducting quantum circuit 300 that may be included in a QP die 104. As shown in FIG. 13, a superconducting quantum circuit 300 includes two or more qubits, 302-1 and 302-2. Qubits 302-1 and 302-2 may be identical and thus the discussion of FIG. 13 may refer generally to the "qubit 302"; the same applies to Josephson junctions 304-1 and 304-2, which may generally be referred to as "Josephson junctions 304," and to circuit elements 306-1 and 306-2, which may generally be referred to as "circuit elements 306." As shown in FIG. 13, each of the superconducting qubits 302 may include one or more Josephson junctions 304 connected to one or more other circuit elements 306, which, in combination with the Josephson junction(s) 304, may form a nonlinear circuit providing a unique two-level quantum state for the qubit. The circuit elements 306 could be, for example, capacitors in transmons or superconducting loops in flux qubits.

[0058] A superconducting quantum circuit 300 may include circuitry 308 for providing external control of qubits 302 and circuitry 310 for providing internal control of qubits 302. In this context, "external control" refers to controlling the qubits 302 from outside of the QP die 104 that includes the qubits 302, including control by a user of a quantum computer, while "internal control" refers to controlling the qubits 302 within QP die 104. For example, if qubits 302 are transmon qubits, external control may be implemented by means of flux bias lines (also known as "flux lines" and "flux coil lines") and by means of readout and drive lines (also known as "microwave lines" since qubits are typically designed to operate with microwave signals), described in greater detail below. On the other hand, internal control lines for such qubits may be implemented by means of resonators, e.g., coupling and readout resonators, also described in greater detail below.

[0059] FIG. 14 illustrates an example of a physical layout 311 of a superconducting quantum circuit where qubits are implemented as transmons. Similarly to FIG. 13, FIG. 14 illustrates two qubits 302. In addition, FIG. 14 illustrates flux bias lines 312, microwave lines 314, a coupling resonator 316, a readout resonator 318, and conductive contacts 320 and 322. The flux bias lines 312 and the microwave lines 314 may be viewed as examples of the external control circuitry 308 shown in FIG. 13. The coupling resonator 316 and the readout resonator 318 may be viewed as examples of the internal control circuitry 310 shown in FIG. 1.

[0060] Running a current through the flux bias lines 312, provided from the conductive contacts 320, enables the tuning of the frequency of the corresponding qubits 302 to which each line 312 is connected. For example, a magnetic field is created by running the current in a particular flux bias line 312. If such a magnetic field is in sufficient proximity to the qubit 302, the magnetic field couples to the qubit 302, thereby changing the spacing between the energy levels of the qubit 302. This, in turn, changes the frequency of the qubit 302 since the frequency is related to the spacing between the energy levels via Planck's equation. Provided there is sufficient multiplexing, different currents can be sent down each of the flux lines 312, allowing for independent tuning of the various qubits 302.

[0061] Typically, the qubit frequency may be controlled to bring the frequency either closer to or further away from another resonant element, such as a coupling resonator 316 as shown in FIG. 14 that connects two or more qubits 302 together. For example, if it is desired that a first qubit 302 (e.g. the qubit 302 shown on the left side of FIG. 14) and a second qubit 302 (e.g. the qubit 302 shown on the right side of FIG. 14) interact, via the coupling resonator 316 connecting these qubits, then both qubits 302 may be tuned at nearly the same frequency. In other scenarios, two qubits 302 could interact via a coupling resonator 316 at specific frequencies, but these three elements do not have to be tuned to be at nearly the same frequency with one another. Interactions between the qubits 302 can similarly be reduced or prevented by controlling the current in the appropriate flux bias lines. The state(s) of each qubit 302 may be read by way of its corresponding readout resonator 318. As discussed below, the qubit 302 may induce a resonant frequency in the readout resonator 318. This resonant frequency is then passed to the microwave lines 314 and communicated to the conductive contacts 322.

[0062] A readout resonator 318 may be provided for each qubit. The readout resonator 318 may be a transmission line that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side (for a quarter-wavelength resonator) or has a capacitive connection to ground (for a half-wavelength resonator), which results in oscillations within the transmission line (resonance). The resonant frequency of the oscillations may be close to the frequency of the qubit 302. The readout resonator 318 may be coupled to the qubit 302 by being in sufficient proximity to the qubit 302 (e.g., through capacitive or inductive coupling). Due to the coupling between the readout resonator 318 and the qubit 302, changes in the state of the qubit 302 may result in changes of the resonant frequency of the readout resonator 318. In turn, because the readout resonator 318 is in sufficient proximity to the microwave line 314, changes in the resonant frequency of the readout resonator 318 may induce changes in the current in the microwave line 314, and that current can be read externally via the conductive contacts 322.

[0063] The coupling resonator 316 may be used to couple different qubits together to realize quantum logic gates. The coupling resonator 316 may be similar to the readout resonator 318 in that it is a transmission line that may include capacitive connections to ground on both sides (for a half-wavelength resonator), which may result in oscillations within the coupling resonator 316. Each side of the coupling resonator 316 may be coupled (again, either capacitively or inductively) to a respective qubit 302 by being in sufficient proximity to the qubit 302. Because each side of the coupling resonator 316 couples with a respective different qubit 302, the two qubits 302 may be coupled together through the coupling resonator 316. In this manner, a state of one qubit 302 may depend on the state of the other qubit 302, and the vice versa. Thus, coupling resonators 316 may be employed to use a state of one qubit 302 to control a state of another qubit 302.

[0064] In some implementations, the microwave line 314 may be used to not only readout the state of the qubits 302 as described above, but also to control the state of the qubits 302. When a single microwave line 314 is used for this purpose, the line 314 may operate in a half-duplex mode in which, at some times, it is configured to readout the state of the qubits 302, and, at other times, it is configured to control the state of the qubits 302. In other implementations, microwave lines such as the line 314 shown in FIG. 14 may be used to only readout the state of the qubits as described above, while separate drive lines (such as the drive lines 324 shown in FIG. 14) may be used to control the state of the qubits 302. In such implementations, the microwave lines used for readout may be referred to as readout lines (e.g., the readout line 314), while microwave lines used for controlling the state of the qubits may be referred to as drive lines (e.g., the drive lines 324). The drive lines 324 may control the state of their respective qubits 302 by providing (e.g., using conductive contacts 326 as shown in FIG. 14) a microwave pulse at the qubit frequency, which in turn stimulates a transition between the states of the qubit 302. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the states of the qubit 302.

[0065] Flux bias lines, microwave lines, coupling resonators, drive lines, and readout resonators, such as those described above, together form interconnects for supporting propagation of microwave signals. Further, any other connections for providing direct electrical interconnection between different quantum circuit elements and components, such as connections from electrodes of Josephson junctions to plates of the capacitors or to superconducting loops of superconducting quantum interference devices (SQUIDS) or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, are also referred to herein as interconnects. Still further, the term "interconnect" may also be used to refer to elements providing electrical interconnections between quantum circuit elements and components and non- quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit. Examples of non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog-to-digital converters, mixers, multiplexers, amplifiers, etc. [0066] Coupling resonators and readout resonators may be configured for capacitive coupling to other circuit elements at one or both ends to have resonant oscillations, whereas flux bias lines and microwave lines may be similar to conventional microwave transmission lines because there is no resonance in these lines. Each one of these interconnects may be implemented as any suitable architecture of a microwave transmission line, such as a coplanar waveguide, a stripline, a microstrip line, or an inverted microstrip line. Typical materials to make the interconnects include aluminum, niobium, niobium nitride, titanium nitride, molybdenum rhenium, and niobium titanium nitride, all of which are particular types of superconductors. However, in various embodiments, other suitable superconductors and alloys of superconductors may be used as well.

[0067] In various embodiments, the interconnects as shown in FIG. 14 could have different shapes and layouts. For example, some interconnects may comprise more curves and turns while other interconnects may comprise fewer curves and turns, and some interconnects may comprise substantially straight lines. In some embodiments, various interconnects may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using a bridge to bridge one interconnect over the other, for example.

[0068] In addition, FIG. 14 further illustrates ground contacts 328, connecting to the ground plane. Such ground contacts 328 may be used when a QP die 104 supports propagation of microwave signals to suppress microwave parallel plate modes, cross-coupling between circuit blocks, and/or substrate resonant modes. In general, providing ground pathways may improve signal quality, enable fast pulse excitation and improve the isolation between the different lines.

[0069] Only two ground contacts are labeled in FIG. 14 with the reference numeral 328, but all white circles shown throughout FIG. 14 may illustrate exemplary locations of ground conductive contacts. The illustration of the location and the number of the ground contacts 328 in FIG. 14 is purely illustrative and, in various embodiments, ground contacts 328 may be provided at different places, as known in microwave engineering. More generally, any number of qubits 302, flux bias lines 312, microwave lines 314, coupling resonators 316, readout resonators 318, drive lines 324, contacts 320, 322, 326, and 328, and other components discussed herein with reference to the superconducting quantum circuit 300 may be included in a QP die 104.

[0070] While FIGS. 13 and 14 illustrate examples of quantum circuits comprising only two qubits 302, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure. Furthermore, while FIGS. 13 and 14 may illustrate various features specific to transmon-type quantum devices, the QP dies 104 may include quantum circuits implementing other types of superconducting qubits. [0071] In some embodiments, the bottom face 118 of the QP die 104 around the conductive contacts 122, and the top face 126 of the package substrate 102 around the conductive contacts 130 may be coated with a solder resist material (not shown). The solder resist may include silicon nitride, aluminum oxide, or silicon oxide, for example. Because the solder resist material may be lossy, it may be advantageous to avoid using solder resist material proximate to or around the conductive contacts 122 and 130 in some embodiments in which one or more resonators 116 is disposed at the bottom face 118 of the QP die 104 (e.g., as shown in FIG. 3). FIG. 15 illustrates the superconducting qubit-type quantum device 300 of FIG. 14 with an example area 382 around the resonator 316 in which no solder resist is provided. As discussed below, positioning a lossy material close to the resonators 116 may create spurious two-level systems that may compromise performance of the QP die 104 (e.g., by leading to qubit decoherence).

[0072] As noted above, in some embodiments, the QP die 104 may include spin qubit-type quantum devices. FIG. 16 depicts cross-sectional views of an example spin qubit-type quantum device 700, in accordance with various embodiments. In particular, FIG. 16B illustrates the spin qubit-type quantum device 700 taken along the section A-A of FIG. 16A (while FIG. 16A illustrates the spin qubit-type quantum device 700 taken along the section C-C of FIG. 16B), and FIG. 16C illustrates the spin qubit-type quantum device 700 taken along the section B-B of FIG. 16A with a number of components not shown to more readily illustrate how the gates 706/708 and the magnet line 721 may be patterned (while FIG. 16A illustrates a spin qubit-type quantum device 700 taken along the section D-D of FIG. 16C). Although FIG. 16A indicates that the cross-section illustrated in FIG. 16B is taken through the fin 704-1, an analogous cross-section taken through the fin 704-2 may be identical, and thus the discussion of FIG. 16B refers generally to the "fin 704." The spin qubit- type quantum device 700 is simply illustrative, and other spin qubit-type quantum devices may be included in a QP die 104.

[0073] The spin qubit-type quantum device 700 may include a base 702 and multiple fins 704 extending away from the base 702. The base 702 and the fins 704 may include a substrate and a quantum well stack (not shown in FIG. 16, but discussed below with reference to the substrate 744 and the quantum well stack 746), distributed in any of a number of ways between the base 702 and the fins 704. The base 702 may include at least some of the substrate, and the fins 704 may each include a quantum well layer of the quantum well stack (discussed below with reference to the quantum well layer 752).

[0074] Although only two fins, 704-1 and 704-2, are shown in FIG. 16, this is simply for ease of illustration, and more than two fins 704 may be included in the spin qubit-type quantum device 700. In some embodiments, the total number of fins 704 included in the spin qubit-type quantum device 700 is an even number, with the fins 704 organized into pairs including one active fin 704 and one read fin 704, as discussed in detail below. When the spin qubit-type quantum device 700 includes more than two fins 704, the fins 704 may be arranged in pairs in a line (e.g., 2N fins total may be arranged in a lx2N line, or a 2xN line) or in pairs in a larger array (e.g., 2N fins total may be arranged as a 4xN/2 array, a 6xN/3 array, etc.). The discussion herein will largely focus on a single pair of fins 704 for ease of illustration, but all the teachings of the present disclosure apply to spin qubit-type quantum devices 700 with more fins 704.

[0075] As noted above, each of the fins 704 may include a quantum well layer (not shown in FIG. 16, but discussed below with reference to the quantum well layer 752). The quantum well layer included in the fins 704 may be arranged normal to the z-direction, and may provide a layer in which a two-dimensional electron gas (2DEG) may form to enable the generation of a quantum dot during operation of the spin qubit-type quantum device 700, as discussed in further detail below. The quantum well layer itself may provide a geometric constraint on the z-location of quantum dots in the fins 704, and the limited extent of the fins 704 (and therefore the quantum well layer) in the y- direction may provide a geometric constraint on the y-location of quantum dots in the fins 704. To control the x-location of quantum dots in the fins 704, voltages may be applied to gates disposed on the fins 704 to adjust the energy profile along the fins 704 in the x-direction and thereby constrain the x-location of quantum dots within quantum wells (discussed in detail below with reference to the gates 706/708). The dimensions of the fins 704 may take any suitable values. For example, in some embodiments, the fins 704 may each have a width 762 between 10 and 30 nanometers. In some embodiments, the fins 704 may each have a height 764 between 200 and 400 nanometers (e.g., between 250 and 350 nanometers, or equal to 300 nanometers).

[0076] The fins 704 may be arranged in parallel, as illustrated in FIGS. 16A and 16C, and may be spaced apart by an insulating material 728, which may be disposed on opposite faces of the fins 704. The insulating material 728 may be a dielectric material, such as silicon oxide. For example, in some embodiments, the fins 704 may be spaced apart by a distance 760 between 100 and 250 nanometers.

[0077] Multiple gates may be disposed on each of the fins 704. In the embodiment illustrated in FIG. 16B, three gates 706 and two gates 708 are shown as distributed on the top of the fin 704. This particular number of gates is simply illustrative, and any suitable number of gates may be used.

[0078] As shown in FIG. 16B, the gate 708-1 may be disposed between the gates 706-1 and 706-2, and the gate 708-2 may be disposed between the gates 706-2 and 706-3. Each of the gates 706/708 may include a gate dielectric 714; in the embodiment illustrated in FIG. 16B, the gate dielectric 714 for all of the gates 706/708 is provided by a common layer of gate dielectric material. In other embodiments, the gate dielectric 714 for each of the gates 706/708 may be provided by separate portions of gate dielectric 714. In some embodiments, the gate dielectric 714 may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the fin 704 and the corresponding gate metal). The gate dielectric 714 may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric 714 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that may be used in the gate dielectric 714 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric 714 to improve the quality of the gate dielectric 714.

[0079] Each of the gates 706 may include a gate metal 710 and a hardmask 716. The hardmask 716 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 710 may be disposed between the hardmask 716 and the gate dielectric 714, and the gate dielectric 714 may be disposed between the gate metal 710 and the fin 704. Only one portion of the hardmask 716 is labeled in FIG. 16B for ease of illustration. In some embodiments, the gate metal 710 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride. In some embodiments, the hardmask 716 may not be present in the spin qubit-type quantum device 700 (e.g., a hardmask like the hardmask 716 may be removed during processing, as discussed below). The sides of the gate metal 710 may be substantially parallel, as shown in FIG. 16B, and insulating spacers 734 may be disposed on the sides of the gate metal 710 and the hardmask 716. As illustrated in FIG. 16B, the spacers 734 may be thicker closer to the fin 704 and thinner farther away from the fin 704. In some embodiments, the spacers 734 may have a convex shape. The spacers 734 may be formed of any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride). The gate metal 710 may be any suitable metal, such as titanium nitride.

[0080] Each of the gates 708 may include a gate metal 712 and a hardmask 718. The hardmask 718 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 712 may be disposed between the hardmask 718 and the gate dielectric 714, and the gate dielectric 714 may be disposed between the gate metal 712 and the fin 704. In the embodiment illustrated in FIG. 16B, the hardmask 718 may extend over the hardmask 716 (and over the gate metal 710 of the gates 706), while in other embodiments, the hardmask 718 may not extend over the gate metal 710. In some embodiments, the gate metal 712 may be a different metal from the gate metal 710; in other embodiments, the gate metal 712 and the gate metal 710 may have the same material composition. In some embodiments, the gate metal 712 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride. In some embodiments, the hardmask 718 may not be present in the spin qubit-type quantum device 700 (e.g., a hardmask like the hardmask 718 may be removed during processing, as discussed below).

[0081] The gate 708-1 may extend between the proximate spacers 734 on the sides of the gate 706- 1 and the gate 706-2, as shown in FIG. 16B. In some embodiments, the gate metal 712 of the gate 708-1 may extend between the spacers 734 on the sides of the gate 706-1 and the gate 706-2. Thus, the gate metal 712 of the gate 708-1 may have a shape that is substantially complementary to the shape of the spacers 734, as shown. Similarly, the gate 708-2 may extend between the proximate spacers 734 on the sides of the gate 706-2 and the gate 706-3. In some embodiments in which the gate dielectric 714 is not a layer shared commonly between the gates 708 and 706, but instead is separately deposited on the fin 704 between the spacers 734, the gate dielectric 714 may extend at least partially up the sides of the spacers 734, and the gate metal 712 may extend between the portions of gate dielectric 714 on the spacers 734. The gate metal 712, like the gate metal 710, may be any suitable metal, such as titanium nitride.

[0082] The dimensions of the gates 706/708 may take any suitable values. For example, in some embodiments, the z-height 766 of the gate metal 710 may be between 40 and 75 nanometers (e.g., approximately 50 nanometers); the z-height of the gate metal 712 may be in the same range. In embodiments like the ones illustrated in FIG. 16B, the z-height of the gate metal 712 may be greater than the z-height of the gate metal 710. In some embodiments, the length 768 of the gate metal 710 (i.e., in the x-direction) may be between 20 and 40 nanometers (e.g., 30 nanometers). In some embodiments, the distance 770 between adjacent ones of the gates 706 (e.g., as measured from the gate metal 710 of one gate 706 to the gate metal 710 of an adjacent gate 706 in the x-direction, as illustrated in FIG. 16B) may be between 40 and 60 nanometers (e.g., 50 nanometers). In some embodiments, the thickness 772 of the spacers 734 may be between 1 and 10 nanometers (e.g., between 3 and 5 nanometers, between 4 and 6 nanometers, or between 4 and 7 nanometers). The length of the gate metal 712 (i.e., in the x-direction) may depend on the dimensions of the gates 706 and the spacers 734, as illustrated in FIG. 16B. As indicated in FIG. 16A, the gates 706/708 on one fin 704 may extend over the insulating material 728 beyond their respective fins 704 and towards the other fin 704, but may be isolated from their counterpart gates by the intervening insulating material 730 and spacers 734.

[0083] Although all the gates 706 are illustrated in the accompanying drawings as having the same length 768 of the gate metal 710, in some embodiments, the "outermost" gates 706 (e.g., the gates 706-1 and 706-3 of the embodiment illustrated in FIG. 16B) may have a greater length 768 than the "inner" gates 706 (e.g., the gate 706-2 in the embodiment illustrated in FIG. 16B). Such longer "outside" gates 706 may provide spatial separation between the doped regions 740 and the areas under the gates 708 and the inner gates 706 in which quantum dots 742 may form, and thus may reduce the perturbations to the potential energy landscape under the gates 708 and the inner gates 706 caused by the doped regions 740.

[0084] As shown in FIG. 16B, the gates 706 and 708 may be alternatingly arranged along the fin 704 in the x-direction. During operation of the spin qubit-type quantum device 700, voltages may be applied to the gates 706/708 to adjust the potential energy in the quantum well layer (not shown) in the fin 704 to create quantum wells of varying depths in which quantum dots 742 may form. Only one quantum dot 742 is labeled with a reference numeral in FIGS. 16B and 16C for ease of illustration, but five are indicated as dotted circles in each fin 704. The location of the quantum dots 742 in FIG. 16B is not intended to indicate a particular geometric positioning of the quantum dots 742. The spacers 734 may themselves provide "passive" barriers between quantum wells under the gates 706/708 in the quantum well layer, and the voltages applied to different ones of the gates 706/708 may adjust the potential energy under the gates 706/708 in the quantum well layer;

decreasing the potential energy may form quantum wells, while increasing the potential energy may form quantum barriers.

[0085] The fins 704 may include doped regions 740 that may serve as a reservoir of charge carriers for the spin qubit-type quantum device 700. For example, an n-type doped region 740 may supply electrons for electron-type quantum dots 742, and a p-type doped region 740 may supply holes for hole-type quantum dots 742. In some embodiments, an interface material 741 may be disposed at a surface of a doped region 740, as shown. The interface material 741 may facilitate electrical coupling between a conductive contact (e.g., a conductive via 736, as discussed below) and the doped region 740. The interface material 741 may be any suitable metal-semiconductor ohmic contact material; for example, in embodiments in which the doped region 740 includes silicon, the interface material 741 may include nickel silicide, aluminum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tungsten silicide, or platinum silicide. In some embodiments, the interface material 741 may be a non-silicide compound, such as titanium nitride. In some embodiments, the interface material 741 may be a metal (e.g., aluminum, tungsten, or indium). [0086] The spin qubit-type quantum devices 700 disclosed herein may be used to form electron- type or hole-type quantum dots 742. Note that the polarity of the voltages applied to the gates 706/708 to form quantum wells/barriers depend on the charge carriers used in the spin qubit-type quantum device 700. In embodiments in which the charge carriers are electrons (and thus the quantum dots 742 are electron-type quantum dots), amply negative voltages applied to a gate 706/708 may increase the potential barrier under the gate 706/708, and amply positive voltages applied to a gate 706/708 may decrease the potential barrier under the gate 706/708 (thereby forming a potential well in which an electron-type quantum dot 742 may form). In embodiments in which the charge carriers are holes (and thus the quantum dots 742 are hole-type quantum dots), amply positive voltages applied to a gate 706/708 may increase the potential barrier under the gate 706/708, and amply negative voltages applied to a gate 706 and 708 may decrease the potential barrier under the gate 706/708 (thereby forming a potential well in which a hole-type quantum dot 742 may form). The spin qubit-type quantum devices 700 disclosed herein may be used to form electron-type or hole-type quantum dots.

[0087] Voltages may be applied to each of the gates 706 and 708 separately to adjust the potential energy in the quantum well layer under the gates 706 and 708, and thereby control the formation of quantum dots 742 under each of the gates 706 and 708. Additionally, the relative potential energy profiles under different ones of the gates 706 and 708 allow the spin qubit-type quantum device 700 to tune the potential interaction between quantum dots 742 under adjacent gates. For example, if two adjacent quantum dots 742 (e.g., one quantum dot 742 under a gate 706 and another quantum dot 742 under a gate 708) are separated by only a short potential barrier, the two quantum dots 742 may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each gate 706/708 may be adjusted by adjusting the voltages on the respective gates 706/708, the differences in potential between adjacent gates 706/708 may be adjusted, and thus the interaction tuned.

[0088] In some applications, the gates 708 may be used as plunger gates to enable the formation of quantum dots 742 under the gates 708, while the gates 706 may be used as barrier gates to adjust the potential barrier between quantum dots 742 formed under adjacent gates 708. In other applications, the gates 708 may be used as barrier gates, while the gates 706 are used as plunger gates. In other applications, quantum dots 742 may be formed under all the gates 706 and 708, or under any desired subset of the gates 706 and 708.

[0089] Conductive vias and lines may contact the gates 706/708, and to the doped regions 740, to enable electrical connection to the gates 706/708 and the doped regions 740 to be made in desired locations. As shown in FIG. 16, the gates 706 may extend away from the fins 704, and conductive vias 720 may contact the gates 706 (and are drawn in dashed lines in FIG. 16B to indicate their location behind the plane of the drawing). The conductive vias 720 may extend through the hardmask 716 and the hardmask 718 to contact the gate metal 710 of the gates 706. The gates 708 may extend away from the fins 704, and conductive vias 722 may contact the gates 708 (also drawn in dashed lines in FIG. 16B to indicate their location behind the plane of the drawing). The conductive vias 722 may extend through the hardmask 718 to contact the gate metal 712 of the gates 708. Conductive vias 736 may contact the interface material 741 and may thereby make electrical contact with the doped regions 740. The spin qubit-type quantum device 700 may include further conductive vias and/or lines (not shown) to make electrical contact to the gates 706/708 and/or the doped regions 740, as desired. The conductive vias and lines included in a spin qubit- type quantum device 700 may include any suitable materials, such as copper, tungsten (deposited, e.g., by CVD), or a superconductor (e.g., aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium).

[0090] During operation, a bias voltage may be applied to the doped regions 740 (e.g., via the conductive vias 736 and the interface material 741) to cause current to flow through the doped regions 740. When the doped regions 740 are doped with an n-type material, this voltage may be positive; when the doped regions 740 are doped with a p-type material, this voltage may be negative. The magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts).

[0091] The spin qubit-type quantum device 700 may include one or more magnet lines 721. For example, a single magnet line 721 is illustrated in FIG. 16 proximate to the fin 704-1. The magnet line 721 may be formed of a conductive material, and may be used to conduct current pulses that generate magnetic fields to influence the spin states of one or more of the quantum dots 742 that may form in the fins 704. In some embodiments, the magnet line 721 may conduct a pulse to reset (or "scramble") nuclear and/or quantum dot spins. In some embodiments, the magnet line 721 may conduct a pulse to initialize an electron in a quantum dot in a particular spin state. In some embodiments, the magnet line 721 may conduct current to provide a continuous, oscillating magnet field to which the spin of a qubit may couple. The magnet line 721 may provide any suitable combination of these embodiments, or any other appropriate functionality.

[0092] In some embodiments, the magnet line 721 may be formed of copper. In some

embodiments, the magnet line 721 may be formed of a superconductor, such as aluminum. The magnet line 721 illustrated in FIG. 16 is non-coplanar with the fins 704, and is also non-coplanar with the gates 706/708. In some embodiments, the magnet line 721 may be spaced apart from the gates 706/708 by a distance 767. The distance 767 may take any suitable value (e.g., based on the desired strength of magnetic field interaction with the quantum dots 742); in some embodiments, the distance 767 may be between 25 nanometers and 1 micron (e.g., between 50 nanometers and 200 nanometers).

[0093] In some embodiments, the magnet line 721 may be formed of a magnetic material. For example, a magnetic material (such as cobalt) may be deposited in a trench in the insulating material 730 to provide a permanent magnetic field in the spin qubit-type quantum device 700.

[0094] The magnet line 721 may have any suitable dimensions. For example, the magnet line 721 may have a thickness 769 between 25 and 100 nanometers. The magnet line 721 may have a width 771 between 25 and 100 nanometers. In some embodiments, the width 771 and thickness 769 of a magnet line 721 may be equal to the width and thickness, respectively, of other conductive lines in the spin qubit-type quantum device 700 (not shown) used to provide electrical interconnects, as known in the art. The magnet line 721 may have a length 773 that may depend on the number and dimensions of the gates 706/708 that are to form quantum dots 742 with which the magnet line 721 is to interact. The magnet line 721 illustrated in FIG. 16 is substantially linear, but this need not be the case; the magnet lines 721 disclosed herein may take any suitable shape. Conductive vias 723 may contact the magnet line 721.

[0095] The conductive vias 720, 722, 736, and 723 may be electrically isolated from each other by an insulating material 730. The insulating material 730 may be any suitable material, such as an interlayer dielectric (ILD). Examples of the insulating material 730 may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride. As known in the art of IC manufacturing, conductive vias and lines may be formed in an iterative process in which layers of structures are formed on top of each other. In some embodiments, the conductive vias

720/722/736/723 may have a width that is 20 nanometers or greater at their widest point (e.g., 30 nanometers), and a pitch of 80 nanometers or greater (e.g., 100 nanometers). In some

embodiments, conductive lines (not shown) included in the spin qubit-type quantum device 700 may have a width that is 100 nanometers or greater, and a pitch of 100 nanometers or greater. The particular arrangement of conductive vias shown in FIG. 16 is simply illustrative, and any electrical routing arrangement may be implemented.

[0096] As discussed above, the structure of the fin 704-1 may be the same as the structure of the fin 704-2; similarly, the construction of gates 706/708 on the fin 704-1 may be the same as the construction of gates 706/708 on the fin 704-2. The gates 706/708 on the fin 704-1 may be mirrored by corresponding gates 706/708 on the parallel fin 704-2, and the insulating material 730 may separate the gates 706/708 on the different fins 704-1 and 704-2. In particular, quantum dots 742 formed in the fin 704-1 (under the gates 706/708) may have counterpart quantum dots 742 in the fin 704-2 (under the corresponding gates 706/708). In some embodiments, the quantum dots 742 in the fin 704-1 may be used as "active" quantum dots in the sense that these quantum dots 742 act as qubits and are controlled (e.g., by voltages applied to the gates 706/708 of the fin 704-1) to perform quantum computations. The quantum dots 742 in the fin 704-2 may be used as "read" quantum dots in the sense that these quantum dots 742 may sense the quantum state of the quantum dots 742 in the fin 704-1 by detecting the electric field generated by the charge in the quantum dots 742 in the fin 704-1, and may convert the quantum state of the quantum dots 742 in the fin 704-1 into electrical signals that may be detected by the gates 706/708 on the fin 704-2. Each quantum dot 742 in the fin 704-1 may be read by its corresponding quantum dot 742 in the fin 704-2. Thus, the spin qubit-type quantum device 700 enables both quantum computation and the ability to read the results of a quantum computation.

[0097] As discussed above, the base 702 and the fin 704 of a spin qubit-type quantum device 700 may be formed from a substrate 744 and a quantum well stack 746 disposed on the substrate 744. The quantum well stack 746 may include a quantum well layer in which a 2DEG may form during operation of the spin qubit-type quantum device 700. The quantum well stack 746 may take any of a number of forms, several of which are illustrated in FIG. 17. The various layers in the quantum well stacks 746 discussed below may be grown on the substrate 744 (e.g., using epitaxial processes).

[0098] FIG. 17A is a cross-sectional view of a quantum well stack 746 including only a quantum well layer 752. The quantum well layer 752 may be disposed on the substrate 744, and may be formed of a material such that, during operation of the spin qubit-type quantum device 700, a 2DEG may form in the quantum well layer 752 proximate to the upper surface of the quantum well layer 752. The gate dielectric 714 of the gates 706/708 may be disposed on the upper surface of the quantum well layer 752. In some embodiments, the quantum well layer 752 of FIG. 17A may be formed of intrinsic silicon, and the gate dielectric 714 may be formed of silicon oxide; in such an arrangement, during use of the spin qubit-type quantum device 700, a 2DEG may form in the intrinsic silicon at the interface between the intrinsic silicon and the silicon oxide. Embodiments in which the quantum well layer 752 of FIG. 17A is formed of intrinsic silicon may be particularly advantageous for electron- type spin qubit-type quantum devices 700. In some embodiments, the quantum well layer 752 of FIG. 17A may be formed of intrinsic germanium, and the gate dielectric 714 may be formed of germanium oxide; in such an arrangement, during use of the spin qubit-type quantum device 700, a 2DEG may form in the intrinsic germanium at the interface between the intrinsic germanium and the germanium oxide. Such embodiments may be particularly advantageous for hole-type spin qubit- type quantum devices 700. In some embodiments, the quantum well layer 752 may be strained, while in other embodiments, the quantum well layer 752 may not be strained. The thicknesses (i.e., z-heights) of the layers in the quantum well stack 746 of FIG. 17A may take any suitable values. For example, in some embodiments, the thickness of the quantum well layer 752 (e.g., intrinsic silicon or germanium) may be between 0.8 and 1.2 microns.

[0099] FIG. 17B is a cross-sectional view of a quantum well stack 746 including a quantum well layer 752 and a barrier layer 754. The quantum well stack 746 may be disposed on a substrate 744 such that the barrier layer 754 is disposed between the quantum well layer 752 and the substrate 744. The barrier layer 754 may provide a potential barrier between the quantum well layer 752 and the substrate 744. As discussed above, the quantum well layer 752 of FIG. 17B may be formed of a material such that, during operation of the spin qubit-type quantum device 700, a 2DEG may form in the quantum well layer 752 proximate to the upper surface of the quantum well layer 752. For example, in some embodiments in which the substrate 744 is formed of silicon, the quantum well layer 752 of FIG. 17B may be formed of silicon, and the barrier layer 754 may be formed of silicon germanium. The germanium content of this silicon germanium may be 20-80% (e.g., 30%). In some embodiments in which the quantum well layer 752 is formed of germanium, the barrier layer 754 may be formed of silicon germanium (with a germanium content of 20-80% (e.g., 70%)). The thicknesses (i.e., z-heights) of the layers in the quantum well stack 746 of FIG. 17B may take any suitable values. For example, in some embodiments, the thickness of the barrier layer 754 (e.g., silicon germanium) may be between 0 and 400 nanometers. In some embodiments, the thickness of the quantum well layer 752 (e.g., silicon or germanium) may be between 5 and 30 nanometers.

[0100] FIG. 17C is a cross-sectional view of a quantum well stack 746 including a quantum well layer 752 and a barrier layer 754-1, as well as a buffer layer 776 and an additional barrier layer 754-2. The quantum well stack 746 may be disposed on the substrate 744 such that the buffer layer 776 is disposed between the barrier layer 754-1 and the substrate 744. The buffer layer 776 may be formed of the same material as the barrier layer 754, and may be present to trap defects that form in this material as it is grown on the substrate 744. In some embodiments, the buffer layer 776 may be grown under different conditions (e.g., deposition temperature or growth rate) from the barrier layer 754-1. In particular, the barrier layer 754-1 may be grown under conditions that achieve fewer defects than the buffer layer 776. In some embodiments in which the buffer layer 776 includes silicon germanium, the silicon germanium of the buffer layer 776 may have a germanium content that varies from the substrate 744 to the barrier layer 754-1; for example, the silicon germanium of the buffer layer 776 may have a germanium content that varies from zero percent at the silicon substrate 744 to a nonzero percent (e.g., 30%) at the barrier layer 754-1. The thicknesses (i.e., z- heights) of the layers in the quantum well stack 746 of FIG. 17C may take any suitable values. For example, in some embodiments, the thickness of the buffer layer 776 (e.g., silicon germanium) may be between 0.3 and 4 microns (e.g., 0.3-2 microns, or 0.5 microns). In some embodiments, the thickness of the barrier layer 754-1 (e.g., silicon germanium) may be between 0 and 400

nanometers. In some embodiments, the thickness of the quantum well layer 752 (e.g., silicon or germanium) may be between 5 and 30 nanometers (e.g., 10 nanometers). The barrier layer 754-2, like the barrier layer 754-1, may provide a potential energy barrier around the quantum well layer 752, and may take the form of any of the embodiments of the barrier layer 754-1. In some embodiments, the thickness of the barrier layer 754-2 (e.g., silicon germanium) may be between 25 and 75 nanometers (e.g., 32 nanometers).

[0101] As discussed above with reference to FIG. 17B, the quantum well layer 752 of FIG. 17C may be formed of a material such that, during operation of the spin qubit-type quantum device 700, a 2DEG may form in the quantum well layer 752 proximate to the upper surface of the quantum well layer 752. For example, in some embodiments in which the substrate 744 is formed of silicon, the quantum well layer 752 of FIG. 17C may be formed of silicon, and the barrier layer 754-1 and the buffer layer 776 may be formed of silicon germanium. In some such embodiments, the silicon germanium of the buffer layer 776 may have a germanium content that varies from the substrate 744 to the barrier layer 754-1; for example, the silicon germanium of the buffer layer 776 may have a germanium content that varies from zero percent at the silicon substrate 744 to a nonzero percent (e.g., 30%) at the barrier layer 754-1. In other embodiments, the buffer layer 776 may have a germanium content equal to the germanium content of the barrier layer 754-1 but may be thicker than the barrier layer 754-1 to absorb the defects that arise during growth.

[0102] In some embodiments, the quantum well layer 752 of FIG. 17C may be formed of germanium, and the buffer layer 776 and the barrier layer 754-1 may be formed of silicon germanium. In some such embodiments, the silicon germanium of the buffer layer 776 may have a germanium content that varies from the substrate 744 to the barrier layer 754-1; for example, the silicon germanium of the buffer layer 776 may have a germanium content that varies from zero percent at the substrate 744 to a nonzero percent (e.g., 70%) at the barrier layer 754-1. The barrier layer 754-1 may in turn have a germanium content equal to the nonzero percent. In other embodiments, the buffer layer 776 may have a germanium content equal to the germanium content of the barrier layer 754-1 but may be thicker than the barrier layer 754-1 to absorb the defects that arise during growth. In some embodiments of the quantum well stack 746 of FIG. 17C, the buffer layer 776 and/or the barrier layer 754-2 may be omitted.

[0103] FIG. 18 is a top view of a wafer 450 and dies 452 that may be formed from the wafer 450; the dies 452 may be the QP dies 104 discussed herein. The wafer 450 may include semiconductor material and may include one or more dies 452 having conventional and/or quantum computing device elements formed on a surface of the wafer 450. Each of the dies 452 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum computing device. After the fabrication of the semiconductor product is complete, the wafer 450 may undergo a singulation process in which each of the dies 452 is separated from one another to provide discrete "chips" of the semiconductor product. A die 452 may include one or more quantum computing devices (e.g., the devices discussed above with reference to FIGS. 13-17) and/or supporting circuitry to route electrical signals to the quantum computing devices (e.g., interconnects including conductive vias and lines, or control circuitry), as well as any other IC components. In some embodiments, the wafer 450 or the die 452 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AN D, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 452. For example, a memory array formed by multiple memory devices may be formed on a same die 452 as a processing device (e.g., the processing device 2002 of FIG. 20) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0104] FIG. 19 is a cross-sectional side view of a device assembly 400 that may include any of the QC packages 100 disclosed herein. The device assembly 400 includes a number of components disposed on a circuit board 402. The device assembly 400 may include components disposed on a first face 440 of the circuit board 402 and an opposing second face 442 of the circuit board 402; generally, components may be disposed on one or both faces 440 and 442.

[0105] In some embodiments, the circuit board 402 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 402. In other embodiments, the circuit board 402 may be a package substrate or flexible board.

[0106] The device assembly 400 illustrated in FIG. 19 includes a package-on-interposer structure 436 coupled to the first face 440 of the circuit board 402 by coupling components 416. The coupling components 416 may electrically and mechanically couple the package-on-interposer structure 436 to the circuit board 402, and may include solder balls (as shown in FIG. 19), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0107] The package-on-interposer structure 436 may include a package 420 coupled to an interposer 404 by coupling components 418. The coupling components 418 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 416. Although a single package 420 is shown in FIG. 19, multiple packages may be coupled to the interposer 404; indeed, additional interposers may be coupled to the interposer 404. The interposer 404 may provide an intervening substrate used to bridge the circuit board 402 and the package 420. The package 420 may be a QC package 100 or may be a conventional IC package, for example. Generally, the interposer 404 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 404 may couple the package 420 (e.g., a die) to a ball grid array (BGA) of the coupling components 416 for coupling to the circuit board 402. In the embodiment illustrated in FIG. 19, the package 420 and the circuit board 402 are attached to opposing sides of the interposer 404; in other embodiments, the package 420 and the circuit board 402 may be attached to a same side of the interposer 404. In some embodiments, three or more components may be interconnected by way of the interposer 404.

[0108] The interposer 404 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 404 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 404 may include metal interconnects 408 and vias 410, including but not limited to through-silicon vias (TSVs) 406. The interposer 404 may further include embedded devices 414, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as F devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 404. The package-on-interposer structure 436 may take the form of any of the package-on-interposer structures known in the art.

[0109] The device assembly 400 may include a package 424 coupled to the first face 440 of the circuit board 402 by coupling components 422. The coupling components 422 may take the form of any of the embodiments discussed above with reference to the coupling components 416, and the package 424 may take the form of any of the embodiments discussed above with reference to the package 420. The package 424 may be a QC package 100 or may be a conventional IC package, for example.

[0110] The device assembly 400 illustrated in FIG. 19 includes a package-on-package structure 434 coupled to the second face 442 of the circuit board 402 by coupling components 428. The package- on-package structure 434 may include a package 426 and a package 432 coupled together by coupling components 430 such that the package 426 is disposed between the circuit board 402 and the package 432. The coupling components 428 and 430 may take the form of any of the embodiments of the coupling components 416 discussed above, and the packages 426 and 432 may take the form of any of the embodiments of the package 420 discussed above. Each of the packages 426 and 432 may be a QC package 100 or may be a conventional IC package, for example.

[0111] FIG. 20 is a block diagram of an example quantum computing device 2000 that may include any of the QC packages 100 disclosed herein. As noted above, the lids and mechanical stops disclosed herein may also be used in non-quantum packages (e.g., to package non-quantum processing dies, memory devices, any other dies, etc.); in such embodiments, the computing device 2000 may not include a quantum processing device 2026 (and thus may not be a quantum computing device). A number of components are illustrated in FIG. 20 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all the components included in the quantum computing device 2000 may be attached to one or more PCBs (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single system-on- a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 20, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the quantum computing device 2000 may not include an audio input device 2024 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2024 or audio output device 2008 may be coupled.

[0112] The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include one or more of the QP dies 104 disclosed herein, and may perform data processing by performing operations on the qubits that may be generated in the QP dies 104, and monitoring the result of those operations. For example, as discussed above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of qubits may be read. The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.

[0113] As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, control the performance of any of the operations discussed herein, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the

communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute

cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[0114] The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0115] The quantum computing device 2000 may include a cooling apparatus 2030. The cooling apparatus 2030 may maintain the quantum processing device 2026 at a predetermined low temperature during operation to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some

embodiments, the temperature may be 5 Kelvin or less. In some embodiments, the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature. The cooling apparatus 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.

[0116] In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0117] The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for

Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0118] In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.

[0119] The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).

[0120] The quantum computing device 2000 may incl ude a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0121] The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0122] The quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above). The audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (M I DI) output).

[0123] The quantum computing device 2000 may include a GPS device 2018 (or corresponding interface circuitry, as discussed above). The GPS device 2018 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.

[0124] The quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. [0125] The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0126] The following paragraphs provide various examples of the embodiments disclosed herein.

[0127] Example 1 is a quantum computing (QC) package, including: a package substrate; a quantum processing die coupled to the package substrate; and a lid above the quantum processing die such that the quantum processing die is between the package substrate and a top portion of the lid, wherein the lid is mechanically secured to the package substrate, and the lid is electrically coupled to the quantum processing die and to the package substrate.

[0128] Example 2 may include the subject matter of Example 1, and may further specify that the lid includes a superconducting material.

[0129] Example 3 may include the subject matter of Example 2, and may further specify that the lid includes aluminum.

[0130] Example 4 may include the subject matter of any of Examples 1-3, and may further include a conductive interface material between the quantum processing die and the top portion of the lid.

[0131] Example 5 may include the subject matter of Example 4, and may further specify that the conductive interface material includes a polymer.

[0132] Example 6 may include the subject matter of any of Examples 4-5, and may further specify that the conductive interface material includes indium.

[0133] Example 7 may include the subject matter of any of Examples 4-6, and may further specify that a top surface of the quantum processing die includes a conductive contact that is in contact with the conductive interface material.

[0134] Example 8 may include the subject matter of Example 7, and may further specify that the conductive contact includes tin, zinc, cobalt, nickel, aluminum, or gold.

[0135] Example 9 may include the subject matter of any of Examples 4-8, and may further specify that a thickness of the conductive interface material is between 20 microns and 500 microns.

[0136] Example 10 may include the subject matter of any of Examples 1-9, and may further specify that a top surface of the quantum processing die includes a conductive contact that is bonded to the lid with a metal-to-metal bond.

[0137] Example 11 may include the subject matter of any of Examples 1-10, and may further include conductive interface material between a footer portion of the lid and the package substrate. [0138] Example 12 may include the subject matter of Example 11, and may further specify that the conductive interface material includes a polymer.

[0139] Example 13 may include the subject matter of any of Examples 11-12, and may further specify that the conductive interface material includes indium.

[0140] Example 14 may include the subject matter of any of Examples 11-13, and may further specify that a top surface of the package substrate includes a conductive contact that is in contact with the conductive interface material.

[0141] Example 15 may include the subject matter of Example 14, and may further specify that the conductive contact includes tin, zinc, cobalt, nickel, aluminum, or gold.

[0142] Example 16 may include the subject matter of any of Examples 1-15, and may further specify that a top surface of the package substrate includes a conductive contact that is bonded to the footer portion of the lid with a metal-to-metal bond.

[0143] Example 17 may include the subject matter of any of Examples 1-16, and may further specify that the top portion of the lid includes one or more recesses.

[0144] Example 18 may include the subject matter of Example 17, and may further specify that at least one of the recesses is aligned with a resonator on a top or bottom surface of the quantum processing die.

[0145] Example 19 may include the subject matter of any of Examples 17-18, and may further specify that multiple recesses in the lid are aligned with respective ones of multiple resonators on the quantum processing die.

[0146] Example 20 may include the subject matter of any of Examples 17-19, and may further specify that the top portion of the lid includes multiple recesses, and at least one recess has a different depth than at least one other recess.

[0147] Example 21 may include the subject matter of any of Examples 1-20, and may further specify that the quantum processing die includes one or more resonators on a bottom surface of the quantum processing die.

[0148] Example 22 may include the subject matter of Example 21, and may further specify that the quantum processing die includes one or more conductive pathways through the quantum processing die between the one or more resonators and a top surface of the quantum processing die.

[0149] Example 23 may include the subject matter of any of Examples 1-22, and may further specify that a thickness of a top portion of the lid is between 0.0.05 millimeters and 5 millimeters.

[0150] Example 24 may include the subject matter of any of Examples 1-23, and may further specify that the quantum processing die includes one or more first stop elements, the package substrate includes one or more second stop elements, and the first stop elements are aligned with the second stop elements to provide a mechanical stop structure between the quantum processing die and the package substrate restricting further collapse in z.

[0151] Example 25 may include the subject matter of Example 24, and may further specify that the quantum processing die is electrically coupled to the package substrate with a solder, and the solder includes indium or indium alloy.

[0152] Example 26 may include the subject matter of any of Examples 24-25, and may further specify that the mechanical stop structure includes a kinematic coupling.

[0153] Example 27 may include the subject matter of Example 26, and may further specify that the mechanical stop structure includes a Maxwell coupling.

[0154] Example 28 may include the subject matter of any of Examples 26-27, and may further specify that the mechanical stop structure includes a Kelvin coupling.

[0155] Example 29 may include the subject matter of any of Examples 24-28, and may further specify that the mechanical stop structure includes an elastic averaging coupling.

[0156] Example 30 may include the subject matter of any of Examples 24-29, and may further specify that the mechanical stop structure includes a quasi-kinematic coupling.

[0157] Example 31 may include the subject matter of any of Examples 24-30, and may further specify that the mechanical stop structure is not significantly deformed under a compression force less than 100 Newtons.

[0158] Example 32 may include the subject matter of any of Examples 24-31, and may further specify that the one or more first stop elements include a dielectric material.

[0159] Example 33 may include the subject matter of any of Examples 24-32, and may further specify that the one or more first stop elements include a metal.

[0160] Example 34 may include the subject matter of any of Examples 1-33, and may further specify that the lid includes one or more first stop elements, the package substrate includes one or more second stop elements, and the first stop elements are aligned with the second stop elements to provide a mechanical stop structure between the lid and the package substrate.

[0161] Example 35 may include the subject matter of Example 34, and may further specify that the mechanical stop structure includes a kinematic coupling.

[0162] Example 36 may include the subject matter of Example 35, and may further specify that the mechanical stop structure includes a Maxwell coupling.

[0163] Example 37 may include the subject matter of any of Examples 35-36, and may further specify that the mechanical stop structure includes a Kelvin coupling.

[0164] Example 38 may include the subject matter of any of Examples 34-37, and may further specify that the mechanical stop structure includes an elastic averaging coupling. [0165] Example 39 may include the subject matter of any of Examples 34-38, and may further specify that the mechanical stop structure includes a quasi-kinematic coupling.

[0166] Example 40 may include the subject matter of any of Examples 34-39, and may further specify that the mechanical stop structure is not deformed under a compression force less than 100

Newtons.

[0167] Example 41 may include the subject matter of any of Examples 34-40, and may further specify that the one or more first stop elements include a dielectric material.

[0168] Example 42 may include the subject matter of any of Examples 34-41, and may further specify that the one or more first stop elements include a metal.

[0169] Example 43 may include the subject matter of any of Examples 1-42, and may further specify that the quantum processing die includes one or more Josephson junctions.

[0170] Example 44 may include the subject matter of any of Examples 1-43, and may further specify that the quantum processing die includes a quantum well stack.

[0171] Example 45 is a quantum computing (QC) package, including: a package substrate; and a quantum processing die coupled to the package substrate; wherein the quantum processing die includes one or more first stop elements, the package substrate includes one or more second stop elements, and the first stop elements are aligned with the second stop elements as part of a mechanical stop structure between the quantum processing die and the package substrate.

[0172] Example 46 may include the subject matter of Example 45, and may further specify that the quantum processing die is electrically coupled to the package substrate with a solder, and the solder includes indium.

[0173] Example 47 may include the subject matter of any of Examples 45-46, and may further specify that the mechanical stop structure includes a kinematic coupling.

[0174] Example 48 may include the subject matter of Example 47, and may further specify that the mechanical stop structure includes a Maxwell coupling.

[0175] Example 49 may include the subject matter of any of Examples 47-48, and may further specify that the mechanical stop structure includes a Kelvin coupling.

[0176] Example 50 may include the subject matter of any of Examples 45-49, and may further specify that the mechanical stop structure includes an elastic averaging coupling.

[0177] Example 51 may include the subject matter of any of Examples 45-50, and may further specify that the mechanical stop structure includes a quasi-kinematic coupling.

[0178] Example 52 may include the subject matter of any of Examples 45-51, and may further specify that the mechanical stop structure is not deformed under a compression force less than 100

Newtons. [0179] Example 53 may include the subject matter of any of Examples 45-52, and may further specify that the one or more first stop elements include a dielectric material.

[0180] Example 54 may include the subject matter of any of Examples 45-53, and may further specify that the one or more first stop elements include a metal.

[0181] Example 55 may include the subject matter of any of Examples 45-54, and may further specify that the one or more first stop elements and the one or more second stop elements are in a shadow of the quantum processing die.

[0182] Example 56 may include the subject matter of any of Examples 45-55, and may further include a lid above the quantum processing die such that the quantum processing die is between the package substrate and a top portion of the lid.

[0183] Example 57 may include the subject matter of Example 56, and may further specify that the lid includes a superconducting material.

[0184] Example 58 may include the subject matter of Example 57, and may further specify that the lid includes aluminum.

[0185] Example 59 may include the subject matter of any of Examples 56-57, and may further include a conductive interface material between the quantum processing die and a top portion of the lid.

[0186] Example 60 may include the subject matter of Example 59, and may further specify that the conductive interface material includes a polymer.

[0187] Example 61 may include the subject matter of any of Examples 59-60, and may further specify that the conductive interface material includes indium.

[0188] Example 62 may include the subject matter of any of Examples 59-61, and may further specify that a top surface of the quantum processing die includes a conductive contact that is in contact with the conductive interface material.

[0189] Example 63 may include the subject matter of any of Examples 59-62, and may further specify that a thickness of the conductive interface material is between 20 microns and 500 microns.

[0190] Example 64 may include the subject matter of any of Examples 56-63, and may further specify that the top portion of the lid includes tin, zinc, cobalt, nickel, aluminum, or gold.

[0191] Example 65 may include the subject matter of any of Examples 56-64, and may further specify that a top surface of the package substrate includes a conductive contact that is bonded to the top portion of the lid with a metal-to-metal bond.

[0192] Example 66 may include the subject matter of any of Examples 56-65, and may further include conductive interface material between a footer portion of the lid and the package substrate. [0193] Example 67 may include the subject matter of Example 66, and may further specify that the conductive interface material includes a polymer.

[0194] Example 68 may include the subject matter of any of Examples 66-67, and may further specify that the conductive interface material includes indium.

[0195] Example 69 may include the subject matter of any of Examples 66-68, and may further specify that a top surface of the package substrate includes a conductive contact that is in contact with the conductive interface material.

[0196] Example 70 may include the subject matter of any of Examples 56-69, and may further specify that the footer portion of the lid includes tin, zinc, cobalt, nickel, aluminum, or gold.

[0197] Example 71 may include the subject matter of any of Examples 56-70, and may further specify that a top surface of the package substrate includes a conductive contact that is bonded to a footer portion of the lid with a metal-to-metal bond.

[0198] Example 72 may include the subject matter of any of Examples 56-71, and may further specify that the top portion of the lid includes one or more recesses.

[0199] Example 73 may include the subject matter of Example 72, and may further specify that at least one of the recesses is aligned with a resonator on a top surface of the quantum processing die.

[0200] Example 74 may include the subject matter of any of Examples 72-73, and may further specify that multiple recesses in the lid are aligned with respective ones of multiple resonators on a top surface of the quantum processing die.

[0201] Example 75 may include the subject matter of any of Examples 72-74, and may further specify that the top portion of the lid includes multiple recesses, and at least one recess has a different depth than at least one other recess.

[0202] Example 76 may include the subject matter of any of Examples 56-75, and may further specify that the quantum processing die includes one or more resonators on a bottom surface of the quantum processing die.

[0203] Example 77 may include the subject matter of Example 76, and may further specify that the quantum processing die includes one or more conductive pathways through the quantum processing die between the one or more resonators and a top surface of the quantum processing die.

[0204] Example 78 may include the subject matter of any of Examples 56-77, and may further specify that a thickness of a top portion of the lid is between 0.05 millimeters and 5 millimeters.

[0205] Example 79 may include the subject matter of any of Examples 56-78, and may further specify that the mechanical stop structure is a first mechanical stop structure, the lid includes one or more third stop elements, the package substrate includes one or more fourth stop elements, and the third stop elements are aligned with the fourth stop elements to provide a second mechanical stop structure between the lid and the package substrate.

[0206] Example 80 may include the subject matter of Example 79, and may further specify that the second mechanical stop structure includes a kinematic coupling.

[0207] Example 81 may include the subject matter of Example 80, and may further specify that the second mechanical stop structure includes a Maxwell coupling.

[0208] Example 82 may include the subject matter of any of Examples 80-81, and may further specify that the second mechanical stop structure includes a Kelvin coupling.

[0209] Example 83 may include the subject matter of any of Examples 79-82, and may further specify that the second mechanical stop structure includes an elastic averaging coupling.

[0210] Example 84 may include the subject matter of any of Examples 79-83, and may further specify that the second mechanical stop structure includes a quasi-kinematic coupling.

[0211] Example 85 may include the subject matter of any of Examples 79-84, and may further specify that the second mechanical stop structure is not deformed under a compression force less than 100 Newtons.

[0212] Example 86 may include the subject matter of any of Examples 79-85, and may further specify that the one or more third stop elements include a dielectric material.

[0213] Example 87 may include the subject matter of any of Examples 79-86, and may further specify that the one or more third stop elements include a metal.

[0214] Example 88 may include the subject matter of any of Examples 56-87, and may further specify that the lid is mechanically secured to the package substrate, and the lid is electrically coupled to the quantum processing die and to the package substrate.

[0215] Example 89 may include the subject matter of any of Examples 45-88, and may further specify that the quantum processing die includes one or more Josephson junctions.

[0216] Example 90 may include the subject matter of any of Examples 45-89, and may further specify that the quantum processing die includes a quantum well stack.

[0217] Example 91 is a method of manufacturing a quantum computing (QC) package, including: forming a package substrate; coupling a quantum processing die to the package substrate; and providing a lid above the quantum processing die such that the quantum processing die is between the package substrate and a top portion of the lid, wherein the lid is mechanically secured to the package substrate, and the lid is electrically coupled to the quantum processing die and to the package substrate.

[0218] Example 92 may include the subject matter of Example 91, and may further specify that providing the lid above the quantum processing die includes: depositing a conductive interface material on a top surface of the quantum processing die; and positioning a top portion of the lid at least partially on the conductive interface material.

[0219] Example 93 may include the subject matter of any of Examples 91-92, and may further specify that providing the lid above the quantum processing die includes: depositing conductive interface material on a top surface of the package substrate outside of a shadow of the quantum processing die; and positioning a footer portion of the lid at least partially on the conductive interface material.

[0220] Example 94 may include the subject matter of any of Examples 91-93, and may further specify that: the quantum processing die is a first quantum processing die; the method further includes coupling a second die to the package substrate; and the lid is provided above the first quantum processing die and the second die such that the second die is between the package substrate and a top portion of the lid.

[0221] Example 95 may include the subject matter of Example 94, and may further specify that the second die is a quantum processing die.

[0222] Example 96 may include the subject matter of Example 94, and may further specify that the second die is not a quantum processing die.

[0223] Example 97 is a method of manufacturing a quantum computing (QC) package, including: forming a package substrate; and electrically coupling a quantum processing die to the package substrate; wherein the quantum processing die includes one or more first stop elements, the package substrate includes one or more second stop elements, and coupling the quantum processing die to the package substrate includes aligning the first stop elements with the second stop elements to provide a mechanical stop structure between the quantum processing die and the package substrate.

[0224] Example 98 may include the subject matter of Example 97, and may further specify that the quantum processing die is electrically coupled to the package substrate with an indium solder.

[0225] Example 99 may include the subject matter of Example 98, and may further include performing a thermal compression bonding operation, wherein the mechanical stop structure prevents bridging of the indium solder.

[0226] Example 100 may include the subject matter of any of Examples 97-99, and may further include mechanically coupling a lid to the package substrate, wherein the quantum processing die is between a top portion of the lid and the package substrate.

[0227] Example 101 may include the subject matter of Example 100, and may further specify that the lid includes one or more third stop elements, the package substrate includes one or more fourth stop elements, and coupling the lid to the package substrate includes aligning the third stop elements with the fourth stop elements to provide a mechanical stop structure between the lid and the package substrate.

[0228] Example 102 may include the subject matter of any of Examples 100-101, and may further specify that the lid includes aluminum.

[0229] Example 103 is a quantum computing (QC) device, including: a package substrate; a quantum processing die coupled to the package substrate; one or more non-quantum processing dies, coupled to package substrate, to control electrical signals applied to and read from the quantum processing die; a memory device to store data generated during operation of the quantum processing die; and a lid above the quantum processing die such that the quantum processing die is between the package substrate and a top portion of the lid, wherein the lid is mechanically secured to the package substrate, and the lid is electrically coupled to the quantum processing die and to the package substrate.

[0230] Example 104 may include the subject matter of Example 103, and may further include a cooling apparatus to maintain a temperature of the quantum processing die below 5 Kelvin.

[0231] Example 105 may include the subject matter of any of Examples 103-104, and may further specify that the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing die.

[0232] Example 106 is a quantum computing (QC) device, including: a package substrate; a quantum processing die coupled to the package substrate; one or more non-quantum processing dies, coupled to package substrate, to control electrical signals applied to and read from the quantum processing die; and a memory device to store data generated during operation of the quantum processing die; wherein the quantum processing die includes one or more first stop elements, the package substrate includes one or more second stop elements, and the first stop elements are aligned with the second stop elements to provide a mechanical stop structure between the quantum processing die and the package substrate.

[0233] Example 107 may include the subject matter of Example 106, and may further include a cooling apparatus to maintain a temperature of the quantum processing die below 5 Kelvin.

[0234] Example 108 may include the subject matter of any of Examples 106-107, and may further specify that the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing die.

[0235] Example 109 is a computing device, including: a package substrate; a die coupled to the package substrate; and a lid above the processing die such that the die is between the package substrate and a top portion of the lid, wherein the lid is mechanically secured to the package substrate, and the lid is electrically coupled to the die and to the package substrate. [0236] Example 110 may include the subject matter of Example 109, and may further specify that the die is a non-quantum processing die.

[0237] Example 111 may include the subject matter of any of Examples 109-110, and may further specify that the die includes one or more first stop elements, the package substrate includes one or more second stop elements, and the first stop elements are aligned with the second stop elements to provide a mechanical stop structure between the die and the package substrate.

[0238] Example 112 is a computing device, including: a package substrate; and a die coupled to the package substrate, wherein the die includes one or more first stop elements, the package substrate includes one or more second stop elements, and the first stop elements are aligned with the second stop elements to provide a mechanical stop structure between the die and the package substrate.

[0239] Example 113 may include the subject matter of Example 112, and may further specify that the die is a non-quantum processing die.

[0240] Example 114 may include the subject matter of any of Examples 112-113, and may further specify that the die includes a processing device or a memory device.

[0241] Example 115 may include the subject matter of any of Examples 112-114, and may further include an antenna for wireless communications.

[0242] Example 116 may include the subject matter of any of Examples 112-115, and may further specify that the computing device is a tablet or smartphone.

Claims

Claims:

1. A quantum computing (QC) package, comprising:

a package substrate; and

a quantum processing die coupled to the package substrate;

wherein the quantum processing die includes one or more first stop elements, the package substrate includes one or more second stop elements, and the first stop elements are aligned with the second stop elements as part of a mechanical stop structure between the quantum processing die and the package substrate.

2. The QC package of claim 1, wherein the quantum processing die is electrically coupled to the package substrate with a solder, and the solder includes indium.

3. The QC package of claim 1, wherein the mechanical stop structure includes a kinematic coupling.

4. The QC package of claim 1, wherein the mechanical stop structure includes an elastic averaging coupling.

5. The QC package of claim 1, wherein the mechanical stop structure includes a quasi-kinematic coupling.

6. The QC package of any of claims 1-5, further comprising:

a lid above the quantum processing die such that the quantum processing die is between the package substrate and a top portion of the lid.

7. The QC package of claim 6, further comprising:

a conductive interface material between the quantum processing die and a top portion of the lid.

8. The QC package of claim 6, further comprising:

conductive interface material between a footer portion of the lid and the package substrate.

9. The QC package of claim 6, wherein the mechanical stop structure is a first mechanical stop structure, the lid includes one or more third stop elements, the package substrate includes one or more fourth stop elements, and the third stop elements are aligned with the fourth stop elements to provide a second mechanical stop structure between the lid and the package substrate.

10. A quantum computing (QC) package, comprising:

a package substrate;

a quantum processing die coupled to the package substrate; and

a lid above the quantum processing die such that the quantum processing die is between the package substrate and a top portion of the lid, wherein the lid is mechanically secured to the package substrate, and the lid is electrically coupled to the quantum processing die and to the package substrate.

11. The QC package of claim 10, wherein the lid includes a superconducting material.

12. The QC package of claim 10, further comprising:

a conductive interface material between the quantum processing die and the top portion of the lid.

13. The QC package of claim 12, wherein the conductive interface material includes a polymer.

14. The QC package of claim 12, wherein the conductive interface material includes indium.

15. The QC package of claim 12, wherein a top surface of the quantum processing die includes a conductive contact that is in contact with the conductive interface material.

16. The QC package of claim 10, wherein a top surface of the quantum processing die includes a conductive contact that is bonded to the lid with a metal-to-metal bond.

17. The QC package of claim 10, further comprising:

18. The QC package of any of claims 10-17, wherein the top portion of the lid includes one or more recesses.

19. The QC package of claim 18, wherein at least one of the recesses is aligned with a resonator on a top or bottom surface of the quantum processing die.

20. The QC package of any of claims 10-17, wherein the quantum processing die includes one or more Josephson junctions.

21. The QC package of any of claims 10-17, wherein the quantum processing die includes a quantum well stack.

22. A computing device, comprising:

a package substrate;

a die coupled to the package substrate; and

a lid above the processing die such that the die is between the package substrate and a top portion of the lid, wherein the lid is mechanically secured to the package substrate, and the lid is electrically coupled to the die and to the package substrate.

23. The computing device of claim 22, wherein the die includes one or more first stop elements, the package substrate includes one or more second stop elements, and the first stop elements are aligned with the second stop elements to provide a mechanical stop structure between the die and the package substrate.

24. A computing device, comprising:

a package substrate; and

a die coupled to the package substrate, wherein the die includes one or more first stop elements, the package substrate includes one or more second stop elements, and the first stop elements are aligned with the second stop elements to provide a mechanical stop structure between the die and the package substrate.

5. The computing device of claim 24, wherein the die is a non-quantum processing die.