WO2018231195A1

WO2018231195A1 - Air gap structures in integrated circuit components

Info

Publication number: WO2018231195A1
Application number: PCT/US2017/037122
Authority: WO
Inventors: Kevin L. Lin; Manish Chandhok
Original assignee: Intel Corporation
Priority date: 2017-06-13
Filing date: 2017-06-13
Publication date: 2018-12-20

Abstract

Disclosed herein are air gap structures in integrated circuit (IC) components. In some embodiments, an IC component may include: a first interconnect layer including an interconnect; a second interconnect layer including a conductive line and a conductive via, wherein the conductive via is in conductive contact with the interconnect; a sleeve of dielectric material at least partially laterally surrounding the conductive via; an anchor between the conductive line and the first interconnect layer, wherein the anchor includes a dielectric material; and an air gap around the sleeve and the anchor.

Description

AIR GAP STRUCTURES IN INTEGRATED CIRCUIT COMPONENTS

Background

[0001] In conventional integrated circuit (IC) components, an interlayer dielectric (ILD) may fill the space between conductive lines in different interconnect layers.

Brief Description of the Drawings

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0003] FIGS. 1A-1B are various views of an air gap structure, in accordance with various embodiments.

[0004] FIGS. 2 and 3 are various views of example air gap structures, in accordance with various embodiments.

[0005] FIGS. 4-5, 6A-6B, and 7-14 illustrate stages in an example process of manufacturing an air gap structure, in accordance with various embodiments.

[0006] FIG. 15 is a top cross-sectional view of an example air gap structure, in accordance with various embodiments.

[0007] FIG. 16 is a flow diagram of a method of manufacturing anchors and sleeves, in accordance with various embodiments.

[0008] FIG. 17 is a top view of a wafer and dies that may include an air gap structure, in accordance with any of the embodiments disclosed herein.

[0009] FIG. 18 is a cross-sectional side view of an IC device that may include an air gap structure, in accordance with any of the embodiments disclosed herein.

[0010] FIG. 19 is a cross-sectional side view of an IC package that may include an air gap structure, in accordance with various embodiments.

[0011] FIG. 20 is a cross-sectional side view of an IC device assembly that may include an air gap structure, in accordance with any of the embodiments disclosed herein.

[0012] FIG. 21 is a block diagram of an example electrical device that may include an air gap structure, in accordance with any of the embodiments disclosed herein.

Detailed Description

[0013] Disclosed herein are air gap structures for integrated circuit (IC) components. In some embodiments, an IC component may include: a first interconnect layer including an interconnect; a second interconnect layer including a conductive line and a conductive via, wherein the conductive via is in conductive contact with the interconnect; a sleeve of dielectric material at least partially laterally surrounding the conductive via; an anchor between the conductive line and the first interconnect layer, wherein the anchor includes a dielectric material; and an air gap around the sleeve and the anchor.

[0014] In some conventional IC components (e.g., dies, package substrates, or interposers) conductive lines within an interconnect layer, and between adjacent interconnect layers, are separated by an interlayer dielectric (ILD) material. As the size of an IC component is reduced, these conductive lines become closer together, which may result in undesirable cross-talk due to the capacitive coupling within and between interconnect layers. Various ones of the embodiments disclosed herein include air gap structures within and/or between different interconnect layers to reduce the capacitive coupling and improve performance. The air gap structures (and components thereof, such as anchors as sleeves) may provide one or more advantages over conventional IC designs, including improved device performance, improved manufacturability, and/or other benefits.

[0015] In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0016] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment.

Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0017] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features. As used herein, all example dimensions may be averages, minimums, or maximums; for example, an example thickness range for a particular material may, when the thickness of that material varies, refer to an average thickness range, a minimum thickness range, or a maximum thickness range.

[0018] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a "package" and an "IC package" are synonymous. When used to describe a range of dimensions, the phrase "between X and Y" represents a range that includes X and Y. For convenience, the phrase "FIG. 1" may be used to refer to the collection of drawings of FIGS. 1A-1B, the phrase "FIG. 6" may be used to refer to the collection of drawings of FIGS. 6A-6B. As used herein, an "air gap" may refer to a region of an IC component that is filled with a gas (e.g., air, a noble gas, etc.) and/or under vacuum.

[0019] FIGS. 1A-1B are various views of an air gap structure 100, in accordance with various embodiments. In particular, FIG. 1A is a perspective view of an air gap structure 100, and FIG. IB is a cross-sectional view along the section A-A of FIG. 1A. The perspective view of FIG. 1A includes a cross-section at the face corresponding to the section A-A, exposing a conductive via 104. The air gap structure 100 may be included in any suitable IC component. For example, the air gap structure 100 may be included in a die (e.g., as discussed below with reference to FIG. 18), a package substrate (e.g., as discussed below with reference to FIG. 19), or any other suitable component of an electrical device.

[0020] The air gap structure 100 may include a first interconnect layer 140-1 and a second interconnect layer 140-2. The use of the terms "first" and "second" to refer to the interconnect layers 140 of the air gap structure 100 does not imply that the interconnect layer 140-1 is the Ml (or "bottommost") layer in a metallization stack, nor that the interconnect layer 140-2 is the M2 layer in a metallization stack; the terms "first" and "second" are simply used to distinguish the interconnect layer 140-1 from the interconnect layer 140-2. Generally speaking, the first interconnect layer 140-1 and the second interconnect layer 140-2 may be any adjacent layers in a metallization stack.

Metallization stacks are discussed in further detail below with reference to FIG. 18.

[0021] The first interconnect layer 140-1 may include one or more conductive lines 102-1. The conductive lines 102-1 may include a conductive material, such as a metal. In some embodiments, the conductive lines 102-1 may include aluminum, tungsten, titanium, cobalt, copper, ruthenium, silicon (e.g., as cobalt silicide), and/or nickel (e.g., as nickel silicide). Although a particular number of conductive lines 102-1 are illustrated in FIG. 1A, any suitable number of conductive lines 102-1 may be included in the first interconnect layer 140-1. When the air gap structure 100 is included in a die (e.g., as discussed below with reference to FIG. 18), the conductive lines 102-1 may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of a substrate of the die. In some embodiments, the first interconnect layer 140-1 may include one or more conductive vias (not shown), in accordance with any of the embodiments disclosed herein. An insulating material 110 may be disposed around the conductive lines 102-1 (and conductive vias, not shown) in the first interconnect layer 140-1. The insulating material 110 any suitable insulating material, such as one or more of silicon, oxygen (e.g., in the form of silicon oxide), carbon (e.g., in the form of carbon-doped oxide), nitrogen (e.g., in the form of silicon nitride), an organic polymer, and/or an organosilicate. In some embodiments, the insulating material 110 may be an ILD.

[0022] The second interconnect layer 140-2 may include one or more conductive lines 102-2 and one or more conductive vias 104. When the air gap structure 100 is included in a die (e.g., as discussed below with reference to FIG. 18), the conductive vias 104 may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of a substrate of the die. In some embodiments, the conductive vias 104 may electrically couple conductive lines 102 and/or conductive vias 104 of different interconnect layers 140 together. For example, FIG. 1 illustrates conductive vias 104 that each couple a conductive line 102-2 of the second interconnect layer 140-2 with a conductive line 102-1 of the first interconnect layer. More generally, a conductive via 104 of the second interconnect layer 140-2 may be in conductive contact with any interconnect (e.g., a conductive line 102 or a conductive via 104) of the first interconnect layer 140-1. The conductive lines 102-2 and the conductive vias 104 may include any of the materials discussed above with reference to the conductive lines 102-1. In some embodiments, the conductive via 104 may include multiple materials; for example, the conductive via 104 may include a diffusion barrier layer (to mitigate diffusion of the material of the conductive via into proximate materials), an adhesion layer (to improve mechanical coupling between the conductive via 104 and any proximate materials), and/or a metal or other conductive fill. In some embodiments, the conductive material in the conductive via 104 may be the same as, or different from, the conductive material in the conductive lines 102; for example, the conductive via 104 may include one or more liners, and the conductive lines 102 may not.

[0023] An etch stop layer 108 may be disposed between the first interconnect layer 140-1 and the second interconnect layer 140-2. The conductive vias 104 may extend through the etch stop layer 108 to make contact with an interconnect (e.g., a conductive line 102-1) of the first interconnect layer 140-1. In some embodiments, the etch stop layer 108 may not be included. The etch stop layer 108 may have any suitable material composition. For example, in some embodiments, the etch stop layer 108 may include an oxide (e.g., a non-conductive metal oxide), a nitride, silicon carbide, silicon nitride, carbon-doped silicon nitride, or silicon oxycarbide. [0024] The air gap structure 100 may include one or more sleeves 112 of dielectric material. A sleeve 112 may at least partially laterally surround the conductive vias 104. As illustrated in FIG. 1, the sleeve 112 may extend from a bottom surface of a conductive line 102-2 down to the etch stop layer 108 (when present). The sleeve 112 may at least partially wrap around the conductive via 104 (e.g., in the x-y plane). The thickness 126 of the sleeve 112 may take any suitable value; for example, in some embodiments, the thickness 126 may be between 3 nanometers and 25 nanometers (e.g., between 4 nanometers and 20 nanometers, between 10 nanometers and 20 nanometers, or between 10 nanometers and 12 nanometers). The dielectric material of the sleeve 112 may have any suitable material composition. For example, in some embodiments, the sleeve 112 may include hafnium oxide, aluminum oxide, silicon nitride, zirconium oxide, titanium, or other dielectric materials. The sleeves 112 are shown in FIG. 1 as having substantially rectangular outer and inner perimeters, but this is simply for illustrative purposes, and the sleeves 112 may have any suitable footprint (e.g., as discussed below with reference to FIG. 3). Although a particular number and arrangement of sleeves 112 is shown in FIG. 1, this is simply for illustrative purposes, and any suitable number and arrangement of sleeves 112 may be included in an air gap structure 100 in an IC device.

[0025] One or more anchors 106 may be disposed between one or more of the conductive lines 102-2 and the etch stop layer 108 (when present). The anchors 106 may serve as mechanical supports for the conductive lines 102-2 with which the anchors 106 are in contact. In particular, the anchors 106 may help mitigate the risk of delamination of the conductive lines 102-2 by

mechanically "anchoring" them to the underlying structure (e.g., the etch stop layer 108 or other underlying structure). The anchors 106 are shown in FIG. 1 as having substantially rectangular footprints, but this is simply for illustrative purposes, and any suitable footprint may be used (e.g., as discussed below with reference to FIG. 3). In some embodiments, the anchors 106 may have a diameter 124 less than twice the thickness 126 of the sleeve 112 (discussed below). For example, the anchors 106 may have a diameter 124 (e.g., as measured along the length of the associated conductive line 102-2) between 10 nanometers and 100 nanometers. In some embodiments, the anchors 106 may have a height 122 between 20 nanometers and 200 nanometers. In some embodiments in which a single conductive line 102-2 has multiple anchors 106 underneath, the distance 132 between adjacent ones of these anchors 106 may be between 100 and 350 nanometers (e.g., between 150 and 300 nanometers).

[0026] In some embodiments, the anchors 106 may include a dielectric material with any suitable material composition. For example, the anchors 106 may include any of the materials discussed above with reference to the sleeves 112. In some embodiments, the anchors 106 and the sleeves 112 may have the same material composition (e.g., as discussed below with reference to the process of FIGS. 4-14). Although a particular number and arrangement of anchors 106 is shown in FIG. 1, this is simply for illustrative purposes, and any suitable number and arrangement of anchors 106 may be included in an air gap structure 100 in an IC device. For example, in some embodiments, a single conductive line 102-2 may have one or more sleeves 112 (and one or more associated conductive vias 104) and one or more anchors 106 disposed underneath the conductive line 102-2.

[0027] The air gap structure 100 may include an air gap 114 around the sleeves 112 and the anchors 106. Although a single air gap 114 is shown in FIG. 1 around the sleeves 112 and the anchors 106, this is simply for illustrative purposes, and any number of air gaps 114 may be included in an interconnect layer 140. The air gap 114 may be filled with a vacuum, air, a gas with a capacitance similar to the capacitance of air, and/or an inert gas (e.g., nitrogen, helium, or argon).

[0028] The air gap structure 100 may also include a capping material 116 between the conductive lines 102-2 of the interconnect layer 140-2. The capping material 116 may be a dielectric material that may serve to encapsulate the air gap 114. The capping material 116 may include any suitable dielectric material, such as a metal oxide, silicon nitride, or silicon carbide.

[0029] In some embodiments, hardmasks (not shown) may be included above some or all of the conductive lines 102 in an air gap structure 100. The hardmasks may be used to pattern the conductive lines 102, and may include carbon, silicon (e.g., in the form of silicon carbide or silicon oxycarbide), zirconium, hafnium, tungsten, oxygen (e.g., in the form of an oxide, such as zirconium oxide, hafnium oxide, or tungsten oxide), or any other suitable material.

[0030] As noted above, the particular shapes of the conductive vias 104, sleeves 112, and anchors 106 shown in FIG. 1 are simply illustrative, and other shapes may be used. For example, FIG. 2 illustrates a cross-sectional view of an air gap structure 100 (analogous to the cross-sectional view of FIG. IB) in which the anchors 106 have a tapered shape that narrows toward the first interconnect layer 140-1. Similarly, the conductive vias 104 may have a tapered shape that narrows toward the first interconnect layer 140-1. The sleeve 112 of FIG. 3 may be substantially conformal on the conductive via 104, and thus may also have inner and outer perimeter faces that taper toward to the first interconnect layer 140-1.

[0031] FIG. 3 is a top cross-sectional view of an air gap structure 100 similar to the air gap structure 100 of FIG. 1, showing that the footprints of the anchors 106, the conductive vias 104, and the sleeves 112 may be round (e.g., substantially circular) or otherwise curved. In some embodiments, the footprints of the anchors 106, the conductive vias 104, and/or the sleeves 112 may be curved rectangles or other appropriate shapes. [0032] The air gap structures 100 disclosed herein may be manufactured using any suitable technique. For example, FIGS. 4-14 illustrate stages in an example process of manufacturing an air gap structure 100, in accordance with various embodiments. Although FIGS. 4-14 show the manufacture of a particular embodiment of an air gap structure 100, this is simply for illustrative purposes, and the method of FIGS. 4-14 may be used to manufacture any appropriate embodiments of the air gap structures 100 disclosed herein. The example process of FIGS. 4-14 may

advantageously involve a single patterning operation (e.g., as discussed below with reference to FIG. 6) for the sleeves 112 and anchors 106, reducing the time, cost, and complexity relative to a process in which the sleeves 112 and anchors 106 are separately patterned.

[0033] FIG. 4 is a side cross-sectional view of an assembly 500 including a first interconnect layer 140-1 having an etch stop layer 108 disposed thereon. The first interconnect layer 140-1 and the etch stop layer 108 of the assembly 500 may take any of the forms of these elements disclosed herein.

[0034] FIG. 5 is a side cross-sectional view of an assembly 502 subsequent to forming a layer of sacrificial material 118 on the etch stop layer 108 of the assembly 500 (FIG. 4). The sacrificial material 118 may include any material suitable for patterning and eventual removal, as discussed below. For example, in some embodiments, the sacrificial material 118 may include silicon, oxygen (e.g., in the form of silicon oxide), titanium, nitrogen (e.g., in the form of titanium nitride), or another material. In some embodiments, the sacrificial material 118 may be a wet etchable material. The height of the layer of sacrificial material 118 in the assembly 502 may take the form of any of the embodiments of the height 122 of the anchors 106 discussed above. Any suitable technique may be used to form the layer of sacrificial material 118 (e.g., a spin-on process, chemical vapor deposition (CVD), or physical vapor deposition (PVD)).

[0035] FIG. 6A is a side cross-sectional view of an assembly 504 subsequent to patterning the sacrificial material 118 of the assembly 502 (FIG. 5) with one or more holes 142 and one or more holes 144; FIG. 6B is a top cross-sectional view of the assembly 504, through the patterned sacrificial material 118. The holes 142 and the holes 144 may extend down to, and expose, the etch stop layer 108. As discussed further below, the holes 142 may correspond to the locations of the conductive vias 104 and the sleeves 112, and the holes 144 may correspond to the locations of the anchors 106. The shapes of the holes 142 and the holes 144 may take the form of any of the corresponding conductive vias 104/sleeves 112 and anchors 106 discussed above; for example, in some embodiments, the holes 142 and the holes 144 may be tapered, narrowing toward the first interconnect layer 140-1. The diameter 147 of the holes 142 may be greater than the diameter 145 of the holes 144. The diameter 147 of the holes 142 may take any suitable value; for example, the diameter 147 may be equal to the diameter of the conductive via 104 that will be formed therein, plus twice the thickness 126 of the sleeve 112. The diameter 145 of the holes 144 may be less than twice the thickness 126 of the sleeve 112. The diameter 145 may take the form of any of the embodiments of the diameter 124 discussed above. Additionally, the distance 149 between adjacent holes 144 may take the form of any of the distances 132 discussed above.

[0036] FIG. 7 is a side cross-sectional view of an assembly 506 (analogous to the view of FIG. 6A) subsequent to forming a conformal layer of dielectric material 146 on the top surface of the assembly 504 (FIG. 6). The dielectric material 146 may have a thickness 148 that allows the dielectric material 146 to substantially uniformly fill the holes 144 without uniformly filling the holes 142 (e.g., as illustrated). In particular, the height of the dielectric material 146 in the holes 142 may be greatest at the sidewalls of the holes 142, and less in the interior. In some embodiments, the thickness 148 may be greater than or equal to the thickness 126. The dielectric material 146 may have any suitable material composition, such as any of the material compositions discussed above with reference to the anchors 106 and sleeves 112. The conformal layer of dielectric material 146 may be provided using any suitable technique (e.g., atomic layer deposition (ALD))

[0037] FIG. 8 is a side cross-sectional view of an assembly 508 subsequent to directionally etching the dielectric material 146 of the assembly 506 (FIG. 7) to remove the dielectric material 146 above the sacrificial material 118 and at the interior of the holes 142 (e.g., at the interior bottom of the holes 142). The remaining dielectric material 146 in the holes 144 may provide the anchors 106. After the directional etching, the dielectric material 146 may remain on the sidewalls of the holes 142, with the etch stop layer 108 exposed at the interior of the holes 142; the dielectric material 146 that remains in the holes 142 may provide the sleeves 112. The sleeves 112 and the anchors 106 of the assembly 508 may take the form of any of the embodiments discussed herein.

[0038] FIG. 9 is a side cross-sectional view of an assembly 510 subsequent to etching through the exposed etch stop layer 108 at the bottom of the holes 142 of the assembly 508 (FIG. 8) to form a hole 152. A portion of a top surface of the conductive line 102-1 (or other interconnect, such as a via) under the hole 152 may be exposed at the bottom of the hole 152. The etch process used to form the hole 152 may be selective to the etch stop layer 108, as shown.

[0039] FIG. 10 is a side cross-sectional view of an assembly 512 subsequent to filling the hole 152 of the assembly 510 (FIG. 9) with a conductive material to form a conductive via 104. The conductive via 104 may take the form of any of the embodiments discussed herein, and in particular, may provide a conductive pathway to a conductive line 102-1 (or other interconnect). As noted above, the conductive via 104 may include multiple materials. In some embodiments, the conductive via 104 may include a diffusion barrier liner (to mitigate diffusion of the material of the conductive via into proximate materials), an adhesion liner (to improve mechanical coupling between the conductive via 104 and any proximate materials), and/or a metal or other conductive fill. For example, the conductive via 104 may include a tantalum liner and a metal fill (e.g., copper). In another example, the conductive via 104 may include a silicon nitride liner and a metal fill (e.g., copper). In some embodiments, the conductive via 104 may be formed by overfilling the hole 152 with one or more conductive materials (e.g., a metal), then using a chemical mechanical polishing (CMP) technique to polish back the overburden and leave the conductive via 104. Any suitable technique or techniques may be used to fill the hole 152, including ALD, CVD, PVD, electroplating, electroless deposition, etc.

[0040] FIG. 11 is a side cross-sectional view of an assembly 514 subsequent to forming a layer of sacrificial material 120 on the top surface of the assembly 512 (FIG. 10). The sacrificial material 120 may take the form of any of the embodiments of the sacrificial material 118 discussed above. The thickness of the layer of sacrificial material 120 in the assembly 514 may be at least the thickness of any conductive lines 102-2 to be formed in the sacrificial material 120, as discussed below. The layer of sacrificial material 120 may be formed using any of the techniques discussed above with reference to the sacrificial material 118.

[0041] FIG. 12 is a side cross-sectional view of an assembly 516 subsequent to forming one or more conductive lines 102-2 in the sacrificial material 120 of the assembly 514 (FIG. 11). The conductive lines 102-2 may take the form of any of the conductive lines 102-2 disclosed herein, and may be formed using any suitable technique (e.g., lithographically patterning the sacrificial material 120, filling recesses in the patterned sacrificial material 120 with a conductive material, then performing a CMP technique to planarize the top surface). As discussed above with reference to FIG. 1, at least one of the conductive lines 102-2 may be in contact with the conductive via 104; thus, the conductive via 104 may provide a conductive pathway between the conductive lines 102-1 and 102- 2 in contact with the conductive via 104.

[0042] FIG. 13 is a side cross-sectional view of an assembly 518 subsequent to removing the sacrificial material 120 and the sacrificial material 118 from the assembly 516 (FIG. 12), forming an air gap 114 around the anchors 106 and the sleeve 112. The sacrificial material 120 and the sacrificial material 118 may be removed using any suitable process, such as one or more wet etches (e.g., a hydrofluoric (HF) or peroxide-based cleanse).

[0043] FIG. 14 is a side cross-sectional view of an assembly 520 subsequent to providing a capping material 116 between the conductive lines 102-1 of the assembly 518 (FIG. 13) to encapsulate the air gap 114. In some embodiments, after providing the capping material, the air gap 114 may be evacuated to achieve an internal vacuum, or filled with a desired gas. The capping material 116 may take the form of any of the embodiments disclosed herein. The capping material 116 may be provided using any suitable technique, such as a PVD or CVD process that deposits an overhang portion of material that encapsulates the air gap 114 without filling it (an effect that may be referred to as a "breadloaf").

[0044] Although many of the accompanying drawings illustrate the conductive vias 104 and anchors 106 perfectly aligned with (e.g., centered on) the associated conductive lines 102-2, practical manufacturing techniques typically result in some degree of misalignment between features patterned with different patterning steps due to limitations in the practical ability to align photomasks and other patterning equipment. Consequently, all features formed with a first round of patterning may be offset from all features formed with a second, different round of a patterning by a consistent direction and amount, representative of misalignment between the two rounds of patterning. When the patterning of the anchors 106 and sleeves 112/conductive vias 104 is performed in one patterning operation (e.g., as discussed above with reference to FIG. 6), and the patterning of the conductive lines 102-2 is performed in a different patterning operation (e.g., as discussed above with reference to FIG. 12), the anchors 106 and sleeves 112/conductive vias 104 may be offset from the conductive lines 102-2 by a substantially constant amount and direction. For example, FIG. 15 is a top view of the example air gap structure 100 of FIG. 1, but in which the anchors 106 and sleeves 112/conductive vias 104 are offset from the associated conductive lines 102-2 (shown in dashed lines). The conductive vias 104 are shown as offset by an offset distance 130, and the anchors 106 are shown as offset by an offset distance 128. When the anchors 106 and sleeves 112/conductive vias 104 are patterned together in one patterning operation (e.g., as discussed above with reference to FIG. 6), and the conductive lines 102-2 are patterned in a different patterning operation (e.g., as discussed above with reference to FIG. 12), the offset distance 128 may be the same as the offset distance 130. Although FIG. 15 illustrates a particular way of measuring the offset distances 128 and 130, the offset distances 128 and 130 may be measured using any suitable technique (e.g., the offset between the center points of features).

[0045] FIG. 16 is a flow diagram of a method 1000 of manufacturing anchors and sleeves, in accordance with various embodiments. Although the operations of the method 1000 may be illustrated with reference to particular embodiments of the anchors 106 and sleeves 112 disclosed herein, the method 1000 may be used to form any suitable anchors and sleeves. Operations are illustrated once each and in a particular order in FIG. 16, but the operations may be reordered and/or repeated as desired (e.g., with different operations performed in parallel when

manufacturing multiple electronic components simultaneously). [0046] At 1002, a first interconnect layer may be formed. The first interconnect layer may include an interconnect. For example, the first interconnect layer 140-1 may include one or more conductive lines 102-1 (and/or conductive vias).

[0047] At 1004, an anchor may be formed above the first interconnect layer. For example, one or more anchors 106 may be formed above the first interconnect layer 140-1. In some embodiments, one or more layers of intervening material may be disposed between the interconnect of the first interconnect layer and the anchor. For example, an etch stop layer 108 may be present between a conductive line 102-1 of the first interconnect layer 140-1 and the anchor 106.

[0048] At 1006, a sleeve may be formed above the first interconnect layer. For example, one or more sleeves 112 may be formed above the first interconnect layer 140-1. In some embodiments, one or more layers of intervening material may be disposed between the interconnect of the first interconnect layer and the sleeve. For example, an etch stop layer 108 may be present between a conductive line 102-1 of the first interconnect layer 140-1 and the sleeve 112.

[0049] At 1008, a conductive via may be formed in the sleeve. The conductive via may be in contact with the interconnect. For example, a conductive via 104 may be formed in the sleeve 112, and the conductive via 104 may be in contact with the conductive line 102-1 (or a conductive via) of the first interconnect layer 140-1.

[0050] At 1010, a conductive line may be formed at least partially on the anchor. For example, a conductive line 102-2 may be formed at least partially on one or more of the anchors 106. In some embodiments, a conductive line formed at least partially on an anchor may also be formed at least partially on the conductive via. For example, a conductive line 102-2 may be in contact with a conductive via 104 (and its associated sleeve 112) and one or more anchors 106.

[0051] Although the air gap structures 100 illustrated herein are typically shown as located between two interconnect layers in a metallization stack, the air gap structures disclosed herein may be used between a device layer (e.g., as discussed below with reference to FIG. 18) and an interconnect layer, or otherwise between a substrate and an interconnect layer, as appropriate.

[0052] The air gap structures 100, and components thereof, disclosed herein may be included in any suitable electronic component. FIGS. 17-21 illustrate various examples of apparatuses that may include any of the air gap structures 100 disclosed herein.

[0053] FIG. 17 is a top view of a wafer 1500 and dies 1502 that may include one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112), or may be included in an IC package whose package substrate includes one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112) (e.g., as discussed below with reference to FIG. 19) in accordance with any of the embodiments disclosed herein. The wafer 1500 may be composed of semiconductor material and may include one or more dies 1502 having IC structures formed on a surface of the wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer 1500 may undergo a singulation process in which each of the dies 1502 is separated from one another to provide discrete "chips" of the semiconductor product. The die 1502 may include one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112) (e.g., as discussed below with reference to FIG. 18), one or more transistors (e.g., some of the transistors 1640 of FIG. 18, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer 1500 or the die 1502 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on a same die 1502 as a processing device (e.g., the processing device 1802 of FIG. 21) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0054] FIG. 18 is a cross-sectional side view of an IC device 1600 that may include one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112), or may be included in an IC package whose substrate includes one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112) (e.g., as discussed below with reference to FIG. 19), in accordance with any of the embodiments disclosed herein. One or more of the IC devices 1600 may be included in one or more dies 1502 (FIG. 17). The IC device 1600 may be formed on a substrate 1602 (e.g., the wafer 1500 of FIG. 17) and may be included in a die (e.g., the die 1502 of FIG. 17). The substrate 1602 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. The substrate 1602 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 1602 may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group ll-VI, lll-V, or IV may also be used to form the substrate 1602. When the substrate 1602 is substantially monocrystalline, the orientation of the substrate 1602 may be any of (100), (111), (110), or others. Although a few examples of materials from which the substrate 1602 may be formed are described here, any material that may serve as a foundation for an IC device 1600 may be used. The substrate 1602 may be part of a singulated die (e.g., the dies 1502 of FIG. 17) or a wafer (e.g., the wafer 1500 of FIG. 17).

[0055] The IC device 1600 may include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in FIG. 18 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all- around gate transistors, such as nanoribbon and nanowire transistors.

[0056] Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some

embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0057] The gate electrode layer may be formed on the gate dielectric layer and may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor 1640 is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed below with reference to a PMOS transistor (e.g., for work function tuning).

[0058] In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is

substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0059] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0060] The S/D regions 1620 may be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S/D regions 1620 may be formed using either an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 1602 may follow the ion-implantation process. In the latter process, the substrate 1602 may first be etched to form recesses at the locations of the S/D regions 1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1620 may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1620.

[0061] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1640) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in FIG. 18 as interconnect layers 1606-1612). For example, electrically conductive features of the device layer 1604 (e.g., the gate 1622 and the S/D contacts 1624) may be electrically coupled with the interconnect structures 1628 of the interconnect layers 1606-1612. The one or more interconnect layers 1606-1612 may form a metallization stack (also referred to as an "ILD stack") 1619 of the IC device 1600. In some embodiments, one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112) may be disposed in one or more of the interconnect layers 1606-1612, in accordance with any of the techniques disclosed herein. In particular, any adjacent pair of interconnect layers in an IC device 1600 may be the interconnect layer 140-1 and the interconnect layer 140-2. FIG. 18 illustrates an air gap structure 100 in the interconnect layer 1608, and an air gap structure 100 in the interconnect layer 1612, for illustration purposes, but any number and structure of air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112) may be included in any one or more of the layers in a metallization stack 1619.

[0062] The interconnect structures 1628 may be arranged within the interconnect layers 1606-1612 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in FIG. 18). Although a particular number of interconnect layers 1606-1610 is depicted in FIG. 18, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0063] In some embodiments, the interconnect structures 1628 may include conductive lines 102 and/or conductive vias 104 filled with an electrically conductive material such as a metal. As discussed above, the conductive lines 102 may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 1602 upon which the device layer 1604 is formed. For example, the conductive lines 102 may route electrical signals in a direction in and out of the page from the perspective of FIG. 18. The conductive vias 104 may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 1602 upon which the device layer 1604 is formed. In some embodiments, the conductive vias 104 may electrically couple conductive lines 102 of different interconnect layers 1606-1612 together. [0064] Some of the interconnect layers 1606-1612 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in FIG. 18. In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different ones of the interconnect layers 1606-1612 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606-1612 may be the same. In some embodiments, an air gap 114 may be disposed between, under, and/or on various ones of the interconnect structures 1628 in one or more of the interconnect layers 1606- 1612; interconnect layers 1606-1612 that include air gaps 114 may include anchors 106 and sleeves 112, in accordance with any of the embodiments disclosed herein.

[0065] A first interconnect layer 1606 (referred to as Metal 1 or "Ml") may be formed directly on the device layer 1604. In some embodiments, the first interconnect layer 1606 may include conductive lines 102 and/or conductive vias 104, as shown. The conductive lines 102 of the first interconnect layer 1606 may be coupled with contacts (e.g., the S/D contacts 1624) of the device layer 1604.

[0066] A second interconnect layer 1608 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include conductive vias 104 to couple the conductive lines 102 of the second interconnect layer 1608 with the conductive lines 102 of the first interconnect layer 1606. Although the conductive lines 102 and the conductive vias 104 are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the conductive lines 102 and the conductive vias 104 may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

[0067] A third interconnect layer 1610 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are "higher up" in the metallization stack 1619 in the IC device 1600 (i.e., further away from the device layer 1604) may be thicker (i.e., "taller," in accordance with the perspective of FIG. 18.

[0068] As noted above, air gap structures 100 may be included in any one or more of the interconnect layers of an IC device 1600. In some embodiments, one or more air gap structures 100 may be included in interconnect layers equal to or higher up in the metallization stack than M3. For example, in some embodiments, air gaps 114 in an air gap structure 100 may be included in M4 and M6. [0069] The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In FIG. 18, the conductive contacts 1636 are illustrated as taking the form of bond pads. The conductive contacts 1636 may be electrically coupled with the interconnect structures 1628 and configured to route the electrical signals of the transistor(s) 1640 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 1636 to mechanically and/or electrically couple a chip including the IC device 1600 with another component (e.g., a circuit board). The IC device 1600 may include additional or alternate structures to route the electrical signals from the interconnect layers 1606-1610 ; for example, the conductive contacts 1636 may include other analogous features (e.g., posts) that route the electrical signals to external components.

[0070] FIG. 19 is a cross-sectional view of an example IC package 1650 that may include one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112). The package substrate 1652 may be formed of a dielectric material, and may have conductive pathways extending through the dielectric material between the face 1672 and the face 1674, or between different locations on the 1672, and/or between different locations on the face 1674. These conductive pathways may take the form of any of the interconnect structures 1628 discussed above with reference to FIG. 18. FIG. 19 schematically illustrates a single air gap structure 100 in the package substrate 1652, but this number and location of air gap structures 100 in the IC package 1650 is simply illustrative, and any number of air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112) (with any suitable structure) may be included in a package substrate 1652. In some embodiments, no air gap structures 100 may be included in the package substrate 1652.

[0071] The IC package 1650 may include a die 1656 coupled to the package substrate 1652 via conductive contacts 1654 of the die 1656, first-level interconnects 1658, and conductive contacts 1660 of the package substrate 1652. The conductive contacts 1660 may be coupled to conductive pathways 1662 through the package substrate 1652, allowing circuitry within the die 1656 to electrically couple to various ones of the conductive contacts 1664 or to other devices included in the package substrate 1652, not shown. The first-level interconnects 1658 illustrated in FIG. 19 are solder bumps, but any suitable first-level interconnects 1658 may be used. As used herein, a "conductive contact" may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket). [0072] In some embodiments, an underfill material 1666 may be disposed between the die 1656 and the package substrate 1652 around the first-level interconnects 1658, and a mold compound 1668 may be disposed around the die 1656 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the mold compound 1668. Example materials that may be used for the underfill material 1666 and the mold compound 1668 are epoxy mold materials, as suitable. Second-level interconnects 1670 may be coupled to the conductive contacts 1664. The second-level interconnects 1670 illustrated in FIG. 19 are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 16770 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects 1670 may be used to couple the IC package 1650 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to FIG. 20.

[0073] In FIG. 19, the IC package 1650 is a flip chip package, and includes an air gap structures 100 in the package substrate 1652. The number and location of air gap structures 100 in the package substrate 1652 of the IC package 1650 is simply illustrative, and any number of air gap structures 100 (with any suitable structure) may be included in a package substrate 1652. In some embodiments, no air gap structure 100 may be included in the package substrate 1652. The die 1656 may take the form of any of the embodiments of the die 1502 discussed herein (e.g., may include any of the embodiments of the IC device 1600). In some embodiments, the die 1656 may include one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112) (e.g., as discussed above with reference to FIG. 17 and FIG. 18); in other embodiments, the die 1656 may not include any air gap structures 100.

[0074] Although the IC package 1650 illustrated in FIG. 19 is a flip chip package, other package architectures may be used. For example, the IC package 1650 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 1650 may be a wafer-level chip scale package (WLCSP) or a panel fanout (FO) package. Although a single die 1656 is illustrated in the IC package 1650 of FIG. 19, an IC package 1650 may include multiple dies 1656. An IC package 1650 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face 1672 or the second face 1674 of the package substrate 1652. More generally, an IC package 1650 may include any other active or passive components known in the art.

[0075] FIG. 20 is a cross-sectional side view of an IC device assembly 1700 that may include one or more IC packages or other electronic components (e.g., a die) including one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112), in accordance with any of the embodiments disclosed herein. The IC device assembly 1700 includes a number of components disposed on a circuit board 1702 (which may be, e.g., a motherboard). The IC device assembly 1700 includes components disposed on a first face 1740 of the circuit board 1702 and an opposing second face 1742 of the circuit board 1702; generally, components may be disposed on one or both faces 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may take the form of any of the embodiments of the IC package 1650 discussed above with reference to FIG. 19 (e.g., may include one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112) in a package substrate 1652 or in a die).

[0076] In some embodiments, the circuit board 1702 may be a printed circuit board (PCB) including multiple interconnect layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the interconnect layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other interconnect layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.

[0077] The IC device assembly 1700 illustrated in FIG. 20 includes a package-on-interposer structure 1736 coupled to the first face 1740 of the circuit board 1702 by coupling components 1716. The coupling components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702, and may include solder balls (as shown in FIG. 20), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0078] The package-on-interposer structure 1736 may include an IC package 1720 coupled to an interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in FIG. 20, multiple IC packages may be coupled to the interposer 1704; indeed, additional interposers may be coupled to the interposer 1704. The interposer 1704 may provide an intervening substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be or include, for example, a die (the die 1502 of FIG. 17), an IC device (e.g., the IC device 1600 of FIG. 18), or any other suitable component. Generally, the interposer 1704 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1704 may couple the IC package 1720 (e.g., a die) to a set of BGA conductive contacts of the coupling components 1716 for coupling to the circuit board 1702. In the embodiment illustrated in FIG. 20, the IC package 1720 and the circuit board 1702 are attached to opposing sides of the interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to a same side of the interposer 1704. In some embodiments, three or more components may be interconnected by way of the interposer 1704.

[0079] The interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to through-silicon vias (TSVs) 1706. The interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art. In some embodiments, the interposer 1704 may include one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112).

[0080] The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.

[0081] The IC device assembly 1700 illustrated in FIG. 20 includes a package-on-package structure 1734 coupled to the second face 1742 of the circuit board 1702 by coupling components 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by coupling components 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling components 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The package-on-package structure 1734 may be configured in accordance with any of the package-on-package structures known in the art.

[0082] FIG. 21 is a block diagram of an example electrical device 1800 that may include one or more air gap structures 100 (or components thereof, such as anchors 106 and/or sleeves 112), in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the electrical device 1800 may include one or more of the IC packages 1650, IC devices 1600, or dies 1502 disclosed herein. A number of components are illustrated in FIG. 21 as included in the electrical device 1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

[0083] Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in FIG. 21, but the electrical device 1800 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include an audio input device 1824 or an audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1824 or audio output device 1808 may be coupled.

[0084] The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0085] In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0086] The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for

Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0087] In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For instance, a first communication chip 1812 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications, and a second communication chip 1812 may be dedicated to wired communications. [0088] The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).

[0089] The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0090] The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0091] The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[0092] The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800, as known in the art.

[0093] The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0094] The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0095] The electrical device 1800 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.

[0096] The following paragraphs provide various examples of the embodiments disclosed herein.

[0097] Example 1 is an integrated circuit (IC) component, including: a first interconnect layer including an interconnect; a second interconnect layer including a conductive line and a conductive via, wherein the conductive via is in conductive contact with the interconnect; a sleeve of dielectric material at least partially laterally surrounding the conductive via; an anchor between the conductive line and the first interconnect layer, wherein the anchor includes a dielectric material; and an air gap around the sleeve and the anchor.

[0098] Example 2 may include the subject matter of claim 1, and may further specify that the anchor and the sleeve have a same material composition.

[0099] Example 3 may include the subject matter of any of claims 1-2, and may further specify that a thickness of the dielectric material of the sleeve is between 3 nanometers and 25 nanometers.

[0100] Example 4 may include the subject matter of any of claims 1-3, and may further specify that the anchor is a first anchor, and the IC component further includes a second anchor between the conductive line and the first interconnect layer, wherein the second anchor is spaced apart from the first anchor by a distance between 150 nanometers and 300 nanometers.

[0101] Example 5 may include the subject matter of any of claims 1-4, and may further specify that a diameter of an outer perimeter of the sleeve is greater than a diameter of an outer perimeter of the anchor.

[0102] Example 6 may include the subject matter of any of claims 1-5, and may further specify that the sleeve includes aluminum, nitrogen, hafnium, titanium, or oxygen.

[0103] Example 7 may include the subject matter of any of claims 1-6, and may further specify that the sleeve fully laterally surrounds the conductive via.

[0104] Example 8 may include the subject matter of any of claims 1-7, and may further specify that the air gap is under vacuum or filled with an inert gas.

[0105] Example 9 may include the subject matter of any of claims 1-8, and may further specify that the air gap is in contact with the conductive line.

[0106] Example 10 may include the subject matter of any of claims 1-9, and may further specify that the conductive via has a tapered shape that narrows toward the first interconnect layer.

[0107] Example 11 may include the subject matter of any of claims 1-10, and may further specify that the anchor has a tapered shape that narrows toward the first interconnect layer.

[0108] Example 12 may include the subject matter of any of claims 1-11, and may further specify that the anchor is in contact with an etch stop material above the first interconnect layer. [0109] Example 13 may include the subject matter of any of claims 1-12, and may further specify that the conductive via includes a liner material and a fill material.

[0110] Example 14 may include the subject matter of any of claims 1-13, and may further specify that the conductive line is a first conductive line, the second interconnect layer includes a second conductive line, the conductive via is between the second conductive line and the first interconnect layer, the conductive via is offset from the second conductive line by an offset distance, and the anchor is offset from the first conductive line by a same offset distance.

[0111] Example 15 may include the subject matter of any of claims 1-14, and may further specify that the first interconnect layer is a layer in a metallization stack that is M3 or higher.

[0112] Example 16 may include the subject matter of any of claims 1-15, and may further specify that the interconnect includes a conductive via or a conductive line.

[0113] Example 17 is a method of manufacturing an integrated circuit (IC) component, including: forming a first interconnect layer including an interconnect; forming an anchor above the first interconnect layer, wherein the anchor includes a dielectric material; forming a sleeve above the first interconnect layer, wherein the sleeve includes a dielectric material; forming a conductive via in the sleeve, wherein the conductive via is in conductive contact with the interconnect; and forming a conductive line at least partially on the anchor.

[0114] Example 18 may include the subject matter of claim 17, and may further specify that forming the anchor and forming the sleeve are performed concurrently as part of a set of fabrication operations.

[0115] Example 19 may include the subject matter of claim 18, and may further specify that the set of fabrication operations includes: forming a sacrificial material above the first interconnect layer; forming a first hole and a second hole in the sacrificial material, wherein the first hole has a smaller diameter than the second hole; forming a layer of conformal dielectric material over the sacrificial material, the first hole, and the second hole, wherein the conformal dielectric material fills the first hole but does not fill the second hole; directionally etching the layer of conformal dielectric material to remove a portion of the conformal dielectric material at a bottom of the second hole; after directionally etching the layer of conformal dielectric material, exposing the interconnect at the bottom of the second hole; and after exposing the interconnect, forming a conductive material in the second hole; wherein the conductive via includes the conductive material in the second hole, the sleeve includes the conformal dielectric material in the second hole, and the anchor includes the conformal dielectric material in the first hole. [0116] Example 20 may include the subject matter of claim 19, and may further include, after forming the conductive line, removing the sacrificial material to form an air gap around the sleeve and the anchor.

[0117] Example 21 may include the subject matter of any of claims 19-20, and may further specify that the first hole and the second hole are patterned using a single common lithographic mask.

[0118] Example 22 is a computing device, including: an integrated circuit (IC) die, including a first interconnect layer including an interconnect, a second interconnect layer including a first conductive line, a second conductive line, and a conductive via, wherein the conductive via is in conductive contact with the interconnect and the second conductive line, an anchor between the first conductive line and the first interconnect layer, wherein the anchor includes a dielectric material, and an air gap around the anchor, wherein the conductive via is offset from the second conductive line by an offset distance, and the anchor is offset from the first conductive line by a same offset distance.

[0119] Example 23 may include the subject matter of claim 22, and may further include a sleeve of dielectric material at least partially laterally surrounding the conductive via, wherein the air gap is also around the sleeve.

[0120] Example 24 may include the subject matter of any of claims 22-23, and may further specify that the air gap is a first air gap, and the computing device further includes a second air gap between a third interconnect layer and a fourth interconnect layer of the IC die.

[0121] Example 25 may include the subject matter of any of claims 22-24, and may further specify that the second interconnect layer is an M4 layer in a metallization stack of the die.

Claims

Claims:

1. An integrated circuit (IC) component, comprising:

a first interconnect layer including an interconnect;

a second interconnect layer including a conductive line and a conductive via, wherein the conductive via is in conductive contact with the interconnect;

a sleeve of dielectric material at least partially laterally surrounding the conductive via;

an anchor between the conductive line and the first interconnect layer, wherein the anchor includes a dielectric material; and

an air gap around the sleeve and the anchor.

2. The IC component of claim 1, wherein the anchor and the sleeve have a same material composition.

3. The IC component of claim 1, wherein a thickness of the dielectric material of the sleeve is between 3 nanometers and 25 nanometers.

4. The IC component of claim 1, wherein the anchor is a first anchor, and the IC component further includes:

a second anchor between the conductive line and the first interconnect layer, wherein the second anchor is spaced apart from the first anchor by a distance between 150 nanometers and 300 nanometers.

5. The IC component of claim 1, wherein a diameter of an outer perimeter of the sleeve is greater than a diameter of an outer perimeter of the anchor.

6. The IC component of claim 1, wherein the sleeve includes aluminum, nitrogen, hafnium, titanium, or oxygen.

7. The IC component of claim 1, wherein the sleeve fully laterally surrounds the conductive via.

8. The IC component of any of claims 1-7, wherein the air gap is under vacuum or filled with an inert gas.

9. The IC component of any of claims 1-7, wherein the air gap is in contact with the conductive line.

10. The IC component of any of claims 1-7, wherein the conductive via has a tapered shape that narrows toward the first interconnect layer.

11. The IC component of any of claims 1-7, wherein the anchor has a tapered shape that narrows toward the first interconnect layer.

12. The IC component of any of claims 1-7, wherein the anchor is in contact with an etch stop material above the first interconnect layer.

13. The IC component of any of claims 1-7, wherein the conductive via includes a liner material and a fill material.

14. The IC component of any of claims 1-7, wherein the conductive line is a first conductive line, the second interconnect layer includes a second conductive line, the conductive via is between the second conductive line and the first interconnect layer, the conductive via is offset from the second conductive line by an offset distance, and the anchor is offset from the first conductive line by a same offset distance.

15. The IC component of any of claims 1-7, wherein the first interconnect layer is a layer in a metallization stack that is M3 or higher.

16. The IC component of any of claims 1-7, wherein the interconnect includes a conductive via or a conductive line.

17. A method of manufacturing an integrated circuit (IC) component, comprising:

forming a first interconnect layer including an interconnect;

forming an anchor above the first interconnect layer, wherein the anchor includes a dielectric material;

forming a sleeve above the first interconnect layer, wherein the sleeve includes a dielectric material; forming a conductive via in the sleeve, wherein the conductive via is in conductive contact with the interconnect; and

forming a conductive line at least partially on the anchor.

18. The method of claim 17, wherein forming the anchor and forming the sleeve are performed concurrently as part of a set of fabrication operations.

19. The method of claim 18, wherein the set of fabrication operations includes:

forming a sacrificial material above the first interconnect layer;

forming a first hole and a second hole in the sacrificial material, wherein the first hole has a smaller diameter than the second hole;

forming a layer of conformal dielectric material over the sacrificial material, the first hole, and the second hole, wherein the conformal dielectric material fills the first hole but does not fill the second hole;

directionally etching the layer of conformal dielectric material to remove a portion of the conformal dielectric material at a bottom of the second hole;

after directionally etching the layer of conformal dielectric material, exposing the interconnect at the bottom of the second hole; and

after exposing the interconnect, forming a conductive material in the second hole;

wherein the conductive via includes the conductive material in the second hole, the sleeve includes the conformal dielectric material in the second hole, and the anchor includes the conformal dielectric material in the first hole.

20. The method of claim 19, further comprising:

after forming the conductive line, removing the sacrificial material to form an air gap around the sleeve and the anchor.

21. The method of claim 19, wherein the first hole and the second hole are patterned using a single common lithographic mask.

22. A computing device, comprising:

an integrated circuit (IC) die, including:

a first interconnect layer including an interconnect,

a second interconnect layer including a first conductive line, a second conductive line, and a conductive via, wherein the conductive via is in conductive contact with the interconnect and the second conductive line,

an anchor between the first conductive line and the first interconnect layer, wherein the anchor includes a dielectric material, and

an air gap around the anchor,

wherein the conductive via is offset from the second conductive line by an offset distance, and the anchor is offset from the first conductive line by a same offset distance.

23. The computing device of claim 22, further comprising:

wherein the air gap is also around the sleeve.

24. The computing device of any of claims 22-23, wherein the air gap is a first air gap, and the computing device further includes a second air gap between a third interconnect layer and a fourth interconnect layer of the IC die.

25. The computing device of any of claims 22-23, wherein the second interconnect layer is an M4 layer in a metallization stack of the die.