WO2018230107A1 - Multilevel power conversion device - Google Patents

Multilevel power conversion device Download PDF

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Publication number
WO2018230107A1
WO2018230107A1 PCT/JP2018/014179 JP2018014179W WO2018230107A1 WO 2018230107 A1 WO2018230107 A1 WO 2018230107A1 JP 2018014179 W JP2018014179 W JP 2018014179W WO 2018230107 A1 WO2018230107 A1 WO 2018230107A1
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Prior art keywords
terminal
common
basic cell
semiconductor device
basic
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PCT/JP2018/014179
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French (fr)
Japanese (ja)
Inventor
長谷川　勇
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株式会社明電舎
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to a multi-level power converter, and more particularly, to a circuit configuration using a basic cell common to each phase.
  • FIG. 7 shows a circuit configuration of a multilevel power conversion device in which the number of levels of the output phase voltage described in the fourth embodiment of Patent Document 1 is 5 or more.
  • Non-Patent Document 1 If there are up to two DC link capacitors, it is possible to balance the voltage of the DC link capacitors by the control method shown in Non-Patent Document 1. However, when the DC link capacitor is divided into three or more, it is difficult to control the voltage balance of the divided DC link capacitor. Therefore, there is a problem that the voltage of the DC link capacitor cannot be balanced unless an external circuit is connected to maintain the voltage.
  • the present invention has been devised in view of the conventional problems, and one aspect thereof is a DC link capacitor common to each phase and each phase having a basic cell connected to the DC link capacitor common to each phase.
  • a first semiconductor device having one end connected to the third terminal, a second semiconductor device having one end connected to the first terminal, and the other end of the first semiconductor device and the other end of the second semiconductor device.
  • a common connection point of the third and fourth semiconductor devices is a second terminal, and the first common part is connected to the positive terminal of the direct current link capacitor, and the negative terminal of the direct current link capacitor.
  • Each of the basic cells connected to the first terminal, and the second to N-th common parts have 2 2-1 to 2 N-1 basic cells, respectively.
  • the odd-numbered basic cells counted from the side have the third terminal connected to the second terminal of the preceding basic cell, and the first terminal connected to the first terminal of the preceding basic cell,
  • the even-numbered basic cells counted from the first terminal side of the basic cells of the first common part are
  • the third terminal is connected to the third terminal of the basic cell, the first terminal is connected to the second terminal of the basic cell in the previous stage, and the phase module is connected to the basic cell of the Nth common portion.
  • the first to third terminals are input terminals, each of which has a switching device between the input terminal and the output terminal, and by selectively turning on or off the switching device, any one of the input terminals It is characterized in that the potential of the terminal is selected and output.
  • a DC link capacitor common to each phase, and first to Nth common parts (N 2 or more integers) connected to the DC link capacitor common to each phase and having basic cells and common to each phase
  • the basic cell includes a first semiconductor device having one end connected to a third terminal; A second semiconductor device having one end connected to a first terminal; a flying capacitor connected between the other end of the first semiconductor device and the other end of the second semiconductor device; the first semiconductor device; A common connection point of a flying capacitor, a third and a fourth semiconductor device connected between the second semiconductor device and a common connection point of the flying capacitor, and common to the third and fourth semiconductor devices
  • the connection point is a second terminal, and the first common unit is connected to the positive terminal of the DC link capacitor, the third terminal is connected to the negative terminal of the DC link capacitor, and the first terminal is connected to the negative terminal.
  • Each of the second to Nth common units includes 2 2-1 to 2 N-1 basic cells, and the third terminal of the adjacent basic cell in each common unit and the second cell 2 2-1 to 2 N-1 basic cells are connected in series with the first terminal, and the odd-numbered basic cells counted from the first terminal side of the basic cells of the first common part are:
  • the third terminal is connected to the second terminal of the basic cell in the previous stage, the first terminal is connected to the first terminal of the basic cell in the previous stage, and the first terminal of the basic cell of the first common part
  • the even-numbered basic cells counted from the side have the third terminal connected to the third terminal of the preceding basic cell.
  • the first terminal is connected to the second terminal of the basic cell in the previous stage, and the phase module has the first to third terminals of the basic cell of the Nth common unit as input terminals, and the input A switching device and a capacitor are provided between the terminal and the output terminal, and by selectively turning on and off the switching device, the potential of any one of the input terminals or any of the input terminals A potential obtained by adding or subtracting the voltage of the capacitor to the potential of the terminal is output from the output terminal.
  • Third and fourth semiconductor devices connected between the common connection points of the capacitors, the common connection point of the third and fourth semiconductor devices is a second terminal, and the first common portion is the A first basic cell in which the third terminal is connected to a positive terminal of
  • the first common The odd-numbered basic cells counted from the first terminal side of the first basic cell are connected to the second terminal of the basic cell in the previous stage, and the first terminal of the basic cell in the previous stage.
  • the first terminal is connected to a terminal, and the even-numbered basic cells counted from the first terminal side of the first basic cell of the first common portion are connected to the third terminal of the basic cell in the previous stage.
  • the phase module has the first to third terminals of the basic cell of the N-th common part as input terminals
  • Each of which has a switching device between the input terminal and the output terminal, and selectively turns on or off the switching device to select and output the potential of any one of the input terminals. It is characterized by.
  • Third and fourth semiconductor devices connected between the common connection points of the capacitors, the common connection point of the third and fourth semiconductor devices is a second terminal, and the first common portion is the A first basic cell in which the third terminal is connected to a positive terminal of
  • the first common The odd-numbered basic cells counted from the first terminal side of the first basic cell are connected to the second terminal of the basic cell in the previous stage, and the first terminal of the basic cell in the previous stage.
  • the first terminal is connected to a terminal, and the even-numbered basic cells counted from the first terminal side of the first basic cell of the first common portion are connected to the third terminal of the basic cell in the previous stage. 3 terminals are connected, the first terminal is connected to the second terminal of the basic cell in the previous stage, and the phase module has the first to third terminals of the basic cell of the Nth common part as input terminals.
  • a switching device and a capacitor between the input terminal and the output terminal by selectively turning on and off the switching device, the potential of any one of the input terminals or the input terminal Of either terminal Position to and outputs an addition or subtraction potentials voltage of the capacitor from the output terminal.
  • the present invention it is possible to provide a multi-level power conversion device having the number of DC link capacitors divided by 2 or less and the number of voltage levels of 5 levels or more.
  • the circuit diagram which shows the structure of a basic cell.
  • FIG. It shows a power conversion device of the M phase 2 N + 1 +1 level in the third embodiment.
  • FIG. The figure which shows the structural example of a phase module.
  • the DC link capacitor is divided into two or less even at a level of 5 levels or more by connecting a plurality of basic cells composed of a common flying capacitor and a semiconductor device common to each phase to the DC link capacitor. Is.
  • the charging / discharging of the flying capacitor can be performed freely according to the switching pattern, and multi-leveling of 9 levels or more can be realized without an external circuit.
  • Embodiments 1 to 3 of the multilevel power conversion device according to the present invention will be described in detail with reference to FIGS.
  • FIG. 1 A basic cell according to the first embodiment is shown in FIG. 1, and a switching pattern of the basic cell is shown in FIG.
  • a circle in FIG. 2 indicates a semiconductor device (for example, IGBT) that is conducting.
  • the basic cell of Embodiment 1 includes a flying capacitor FC1 and first to fourth semiconductor devices Sc1 to Sc4. This is the same cell as in Patent Document 1.
  • the basic cell 20 includes a first semiconductor device Sc1 having one end connected to the third terminal 3, a second semiconductor device Sc2 having one end connected to the first terminal 1, the other end of the first semiconductor device Sc1, A flying capacitor FC1 connected between the other ends of the two semiconductor devices Sc2, a common connection point of the first semiconductor device Sc1 and the flying capacitor FC1, and a common connection point of the second semiconductor device Sc2 and the flying capacitor FC1. And third and fourth semiconductor devices Sc3 and Sc4 connected in series. The common connection point of the third and fourth semiconductor devices Sc3 and Sc4 becomes the second terminal 2.
  • the switching pattern of the basic cell 20 is such that the first semiconductor device Sc1 and the fourth semiconductor device Sc4 are turned on as shown in FIG. 2A, or the second semiconductor device Sc2 and the third semiconductor device Sc4 are turned on as shown in FIG.
  • the semiconductor device Sc3 is turned on.
  • N stages of first to Nth common parts 11 to 1N are connected to the DC link capacitor DCC.
  • J 1 (first common unit 11)
  • 2 0 1 basic cells are connected.
  • J 2 (second common unit 12)
  • 2 1 2 basic cells
  • J 3 (third common unit 13)
  • the total number of the first to Nth common units 11 to 1N is 2 N ⁇ 1.
  • the third terminal 3 is connected to the positive electrode of the DC link capacitor DCC, and the first terminal 1 is connected to the negative electrode of the DC link capacitor DCC.
  • the basic cells of the second to Nth common parts 12 to 1N are connected in series by connecting the third terminal 3 and the first terminal 1 of the adjacent basic cells in each common part.
  • the odd-numbered basic cells counted from the first terminal side of the basic cell 21a (that is, the negative electrode side of the DC link capacitor DCC) are connected to the second terminal 2 of the previous basic cell, and the third terminal 3 is connected.
  • the first terminal 1 is connected to the first terminal 1 of the basic cell.
  • the third terminal 3 is connected to the third terminal 3 of the preceding basic cell, and the first terminal 1 is connected to the second terminal 2 of the preceding basic cell. Is connected.
  • the third terminal 3 of the first basic cell 22a counting from the first terminal 1 side of the basic cell 21a is connected to the first terminal 1 of the second basic cell 22b.
  • the first basic cell 22a counted from the first terminal 1 side of the basic cell 21a has the third terminal 3 connected to the second terminal 2 of the basic cell 21a of the first common part 11, and the first common part 11
  • the first terminal 1 is connected to the first terminal 1 of the basic cell 21a.
  • the second basic cell 22b counted from the first terminal 1 side has the third terminal 3 connected to the third terminal 3 of the basic cell 21a of the first common part 11, and the second basic cell 22b of the basic cell 21a of the first common part 11 is connected.
  • the first terminal 1 is connected to the two terminals 2.
  • the basic cells of the third to Nth common units 13 to 1N are connected in the same manner.
  • the DC voltage can be divided into 2 N +1 voltage levels by DCC.
  • the input terminal of the phase module is connected to the first terminal 1, the second terminal 2, and the third terminal 3 of the basic cell of the Nth common unit 1N.
  • the phase module is the same as in FIG.
  • the configuration of the phase module shown in FIG. The first and second switching devices S1 and S2 are connected in series between the first input terminal I1 and the second input terminal I2.
  • the third and fourth switching devices S3 and S4 are connected in series between the k-1 input terminal Ik-1 and the kth input terminal Ik.
  • the fifth to eighth switching devices S5 to S8 are connected in series between the common connection point of the first and second switching devices S1 and S2 and the third input terminal I3.
  • a capacitor FC1M is connected between the common connection point of the fifth and sixth switching devices S5 and S6 and the common connection point of the seventh and eighth switching devices S7 and S8.
  • the ninth to twelfth switching devices S9 to S12 are connected in series between the k-2 input terminal Ik-2 and the common connection point of the third and fourth switching devices.
  • a capacitor FCNM is connected between the common connection point of the ninth and tenth switching devices S9 and S10 and the common connection point of the eleventh and twelfth switching devices S11 and S12.
  • the thirteenth to sixteenth switching devices S13 to S16 are connected in series between the common connection point of the sixth and seventh switching devices S6 and S7 and the common connection point of the tenth and eleventh switching devices S10 and S11.
  • a capacitor FCMO is connected between the common connection point of the thirteenth and fourteenth switching devices S13 and S14 and the common connection point of the fifteenth and sixteenth switching devices S15 and S16.
  • the common connection point of the fourteenth and fifteenth switching devices S14 and S15 is an output terminal.
  • the first and second switching devices S1 and S2 are connected in series between the first input terminal I1 and the second input terminal I2.
  • the third and fourth switching devices S3 and S4 are connected in series between the k-1 input terminal Ik-1 and the kth input terminal Ik.
  • the fifth to tenth switching devices S5 to S10 are connected in series between the common connection point of the first and second switching devices S1 and S2 and the common connection point of the third and fourth switching devices S3 and S4.
  • the first and second diodes D1 and D2 are connected in series between the common connection point of the fifth and sixth switching devices S5 and S6 and the common connection point of the seventh and eighth switching devices S7 and S8.
  • a common connection point of the first and second diodes D1 and D2 is connected to the third input terminal I3.
  • the third and fourth diodes D3 and D4 are connected in series between the common connection point of the seventh and eighth switching devices S7 and S8 and the common connection point of the ninth and tenth switching devices S9 and S10.
  • a common connection point of the third and fourth diodes D3 and D4 is connected to the k-2 input terminal Ik-2.
  • the eleventh and twelfth switching devices S11 and S12 are connected in series between the common connection point of the sixth and seventh switching devices S6 and S7 and the common connection point of the eighth and ninth switching devices S8 and S9.
  • a common connection point of the eleventh and twelfth switching devices S11 and S12 is an output terminal.
  • the first and second switching devices S1 and S2 are connected in series between the first input terminal I1 and the second input terminal I2.
  • the third and fourth switching devices S3 and S4 are connected in series between the k-1 input terminal Ik-1 and the kth input terminal Ik.
  • the fifth and sixth switching devices S5 and S6 are connected in reverse series to the third input terminal I3.
  • the eighth and ninth switching devices S8 and S9 are connected in reverse series to the k-2 input terminal Ik-2.
  • a seventh switching device S7 is connected between the common connection point of the first and second switching devices S1 and S2 and the sixth switching device S6.
  • a tenth switching device S10 is connected between the common connection point of the third and fourth switching devices S3 and S4 and the ninth switching device S9.
  • connection point of the sixth and seventh switching devices S6 and S7 and the common connection point of the ninth and tenth switching devices S9 and S10 are connected, and the connection point becomes an output terminal.
  • the basic cell has two types of switching patterns shown in FIGS. 2 (a) and 2 (b). By selecting the pattern shown in FIGS. 2 (a) and 2 (b) according to the direction of one current, charging of the flying capacitor or The discharge can be arbitrarily selected.
  • FIG. 4 is a diagram showing an M-phase 2 N +1 level multi-level conversion device including the DC link capacitor DCC, the first to Nth common units 11 to 1N, and the phase module shown in FIG.
  • the multilevel power conversion device can output a phase voltage of 2 N +1 level.
  • the thing of the structure of patent document 1 and FIG. 8 is used for a phase module.
  • the number k of input terminals of the phase module of FIG. 8 is equal to the number of voltage levels 2 N +1.
  • the number of divisions of the DC link capacitor DCC is set to 2 or less (1 in the first embodiment), and a multilevel power conversion device having a number of voltage levels exceeding five levels is provided. It becomes possible.
  • the division number of the DC link capacitor DCC is 2 or less, the voltage balance of the divided DC link capacitor DCC can be easily obtained without connecting an external circuit. Thereby, it becomes possible to suppress that the harmonic component of the output phase voltage of the power converter increases due to the voltage balance being lost and adversely affects the load connected to the power converter.
  • FIG. 5 is a circuit diagram showing a multilevel power conversion device according to the second embodiment.
  • a 9-level voltage can be output while the DC voltage is divided into two.
  • the voltages of the DC link capacitors DCC1 and DCC2 are controlled to 4E.
  • DC link capacitors DCC1, DCC2 are connected in series.
  • a common connection point of the DC link capacitors DCC1 and DCC2 is defined as a neutral point NP.
  • the first common unit 11 is provided with two basic cells 21a and 21b.
  • the third terminal 3 of the basic cell 21a and the first terminal 1 of the basic cell 21b are connected.
  • first terminal 1 of the basic cell 21a is connected to the negative terminal of the DC link capacitor DCC1
  • third terminal 3 of the basic cell 21a is connected to the positive terminal of the DC link capacitor DCC1.
  • the first terminal 1 of the basic cell 21b is connected to the negative terminal of the DC link capacitor DCC2, and the third terminal 3 of the basic cell 21b is connected to the positive terminal of the DC link capacitor DCC2.
  • the second common unit 12 is provided with four basic cells 22a, 22b, 22c, and 22d.
  • the third terminal 3 of the basic cell 22a and the first terminal 1 of the basic cell 22b are connected, the third terminal 3 of the basic cell 22b and the first terminal of the basic cell 22c are connected, and the third terminal 3 of the basic cell 22c
  • the first terminal 1 of the basic cell 22d is connected.
  • the first terminal 1 of the basic cell 22 a is connected to the first terminal 1 of the basic cell 21 a of the first common unit 11.
  • the third terminal 3 of the basic cell 22 a is connected to the second terminal 2 of the basic cell 21 a of the first common unit 11.
  • the first terminal 1 of the basic cell 22 b is connected to the second terminal 2 of the basic cell 21 a of the first common unit 11.
  • the third terminal 3 of the basic cell 22 b is connected to the third terminal 3 of the basic cell 21 a of the first common unit 11.
  • the first terminal 1 of the basic cell 22 c is connected to the first terminal 1 of the basic cell 21 b of the first common unit 11.
  • the third terminal 3 of the basic cell 22 c is connected to the second terminal 2 of the basic cell 21 b of the first common unit 11.
  • the first terminal 1 of the basic cell 22d is connected to the second terminal 2 of the basic cell 21b of the first common unit 11.
  • the third terminal 3 of the basic cell 22 d is connected to the third terminal 3 of the basic cell 21 b of the first common unit 11.
  • the input terminals of the three-phase phase modules 31, 32, and 33 are connected to the first terminal 1, the second terminal 2, and the third terminal 3 of the basic cells 22a to 22d of the second common unit 12 that is the final stage. .
  • the phase module 31 will be described.
  • the first and second switching devices S1u and S2u are connected in series between the third terminal 3 and the second terminal 2 of the basic cell 22d.
  • Fifteenth and sixteenth switching devices S15u and S16u are connected in series between the second terminal 2 and the first terminal 1 of the basic cell 22a.
  • the third and fourth switching devices S3u and S4u are connected in series between the common connection point of the first and second switching devices S1u and S2u and the first terminal 1 of the basic cell 22d.
  • the thirteenth and fourteenth switching devices S13u and S14u are connected in series between the third terminal 3 of the basic cell 22a and the common connection point of the fifteenth and sixteenth switching devices S15u and S16u.
  • the fifth and sixth switching devices S5u and S6u are connected in series between the common connection point of the third and fourth switching devices S3u and S4u and the second terminal 2 of the basic cell 22c.
  • the eleventh and twelfth switching devices S11u and S12u are connected in series between the second terminal 2 of the basic cell 22b and the common connection point of the thirteenth and fourteenth switching devices S13u and S14u.
  • the seventh to tenth switching devices S7u to S10u are connected in series between the common connection point of the fifth and sixth switching devices S5u and S6u and the common connection point of the eleventh and twelfth switching devices S11u and S12u.
  • the first and second diodes D1u and D2u are connected in series between the common connection point of the seventh and eighth switching devices S7u and S8u and the common connection point of the ninth and tenth switching devices S9u and S10u.
  • a common connection point of the first and second diodes D1u and D2u is connected to the neutral point NP.
  • a common connection point of the eighth and ninth switching devices S8u and S9u is an output terminal.
  • Table 1 shows the phase module switching patterns.
  • the voltage level in Table 1 is the level of the output phase voltage of each phase with respect to the neutral point NP of the neutral point in FIG.
  • one of the switching patterns of the basic cells 21a, 21b, 22a, 22b, 22c, and 22d constituting the first and second common units 11 and 12 is selected from (a) and (b) of FIG. It shall be.
  • the potential of the input terminal of the phase module in FIG. 5 (that is, the output terminal of the second-stage basic cell) is as shown in FIG. 4E, 3E, 2E, E, 0, -E, -2E, -3E, and -4E. (Based on the potential of the NP terminal)
  • FIG. 6 is a circuit diagram showing a multilevel power conversion device according to the third embodiment.
  • the third embodiment is an M-phase 2 N + 1 +1 level multi-level power conversion device in which DC link capacitors DCC1 and DCC2 are connected in series in two stages.
  • the first to Nth common units 11 to 11N have 2 ⁇ (2 1-1 ) to 2 ⁇ (2 N-1 ) basic cells, respectively. Since two DC link capacitors DCC1 and DCC2 are provided, the number of basic cells is 2 ⁇ (2 N ⁇ 1), which is twice that of 2 N ⁇ 1 in FIG. By using 2 ⁇ (2 N ⁇ 1) basic cells, it is possible to output a voltage of 2 N + 1 +1 level.
  • the voltage of the DC link capacitors DCC1 and DCC2 is 4E, the Nth stage flying capacitor is divided into E / 2 N-1 voltage and controlled.
  • the phase module uses the configuration shown in FIG. 8 as in Patent Document 1 and Embodiment 1. At this time, the number k of input terminals of the phase module in FIG. 8 is equal to the number of voltage levels (2 N + 1 +1).
  • the first to third embodiments can be applied not only to a DC / AC converter that converts DC power into AC power but also to an AC / DC converter that converts AC power into DC power.
  • an AC / DC converter When applied to an AC / DC converter, there is an effect that the harmonic current of the AC input power source connected to the DC / AC converter can be reduced.

Abstract

First to N-th common portions 11 to 1N (N is an integer of 2 or more) common to each phase are connected to a DC link capacitor DCC common to each phase. M-phase (M is an integer of 2 or more) phase modules 31 to 3M are connected to the N-th common portion. 21-1 to 2N-1 basic cells are connected to the first to N-th common portions 11 to 1N, respectively. This makes the number of divisions of the DC link capacitor equal to 2 or less and provides a multilevel power conversion device having the number of voltage levels of 5 or more.

Description

マルチレベル電力変換装置Multi-level power converter
　本発明は、マルチレベル電力変換装置に係り、特に、各相共通の基本セルを用いた回路構成に関する。 The present invention relates to a multi-level power converter, and more particularly, to a circuit configuration using a basic cell common to each phase.
　図７は特許文献１の実施形態４に記載されている出力相電圧のレベル数が５以上となるマルチレベル電力変換装置の回路構成である。また、図８に、図７における相モジュールの構成例を示す。図８において、直流電圧群数Ｐ＝２のときに、５レベル電力変換装置の相モジュールとなる。 FIG. 7 shows a circuit configuration of a multilevel power conversion device in which the number of levels of the output phase voltage described in the fourth embodiment of Patent Document 1 is 5 or more. FIG. 8 shows a configuration example of the phase module in FIG. In FIG. 8, when the number of DC voltage groups P = 2, it becomes a phase module of a five-level power converter.
　例として、直流電圧群数Ｐ＝２の回路での動作を説明する。直流リンクコンデンサＤＣＣ１、ＤＣＣ２の電圧を２Ｅ、フライングキャパシタＦＣ１，ＦＣ２の電圧をＥに制御し、電力変換装置内の半導体デバイス（ＩＧＢＴなど）を適正にオンオフ制御することによって、＋２Ｅ，＋Ｅ，０、－Ｅ、－２Ｅの５レベルの出力相電圧（出力端子ＯＵＴ１，…，ＯＵＴＭの相電圧）を生成する。なお、直流リンクコンデンサＤＣＣ１、ＤＣＣ２の共通接続点を出力相電圧の基準点とする。 As an example, an operation in a circuit having a DC voltage group number P = 2 will be described. By controlling the voltage of the DC link capacitors DCC1 and DCC2 to 2E, the voltage of the flying capacitors FC1 and FC2 to E, and appropriately turning on and off the semiconductor device (IGBT or the like) in the power converter, + 2E, + E, 0, -E, -2E five-level output phase voltages (phase voltages of the output terminals OUT1, ..., OUTM) are generated. A common connection point of the DC link capacitors DCC1 and DCC2 is set as a reference point of the output phase voltage.
　直流電圧群数Ｐが３以上の場合でも、同様の動作によって、２Ｐ＋１レベルの出力相電圧を生成する
　しかしながら、特許文献１の実施形態４を用いて５レベルより上の多レベル化を実現しようとする場合、直流電圧群数Ｐが３以上となり、直流リンクコンデンサ（ＤＣＣ１，…，ＤＣＣＰ）を３つ以上直列に接続する必要がある。 Even when the number of DC voltage groups P is 3 or more, the output phase voltage of 2P + 1 level is generated by the same operation. However, using Embodiment 4 of Patent Document 1, it is attempted to realize multi-level higher than 5 levels. In this case, the DC voltage group number P becomes 3 or more, and it is necessary to connect three or more DC link capacitors (DCC1,..., DCCP) in series.
　直流リンクコンデンサは２つまでであれば、非特許文献１に示すような制御方法で直流リンクコンデンサの電圧のバランスをとることが可能である。しかし、直流リンクコンデンサを３つ以上に分割すると、分割した直流リンクコンデンサの電圧のバランスを制御することが難しい。そのため、電圧を維持するために外部回路を接続しないと直流リンクコンデンサの電圧のバランスが取れないという問題があった。 If there are up to two DC link capacitors, it is possible to balance the voltage of the DC link capacitors by the control method shown in Non-Patent Document 1. However, when the DC link capacitor is divided into three or more, it is difficult to control the voltage balance of the divided DC link capacitor. Therefore, there is a problem that the voltage of the DC link capacitor cannot be balanced unless an external circuit is connected to maintain the voltage.
　これは回路の原理上生じる問題である。電圧指令値の大きさに応じて接続されるコンデンサ（直流リンクコンデンサＤＣＣ１，…ＤＣＣＰ、および、フライングキャパシタＦＣ１，…，ＦＣＰ）が異なるため、各コンデンサ、フライングキャパシタを使用する電力の大きさに異なりが生じ、電圧バランスが崩れてしまう。 This is a problem caused by the circuit principle. Since the capacitors (DC link capacitors DCC1,..., DCCP, and flying capacitors FC1,..., FCP) connected according to the magnitude of the voltage command value are different, the power used by each capacitor and the flying capacitor is different. Will occur and the voltage balance will be lost.
　電圧バランスが崩れることで、電力変換装置の出力相電圧の高調波成分が増加し、電力変換装置に接続する負荷へ悪影響を与えるという問題があった。 When the voltage balance is broken, the harmonic component of the output phase voltage of the power converter increases, which has a problem of adversely affecting the load connected to the power converter.
　以上示したようなことから、直流リンクコンデンサの分割数を２以下とし、５レベル以上の電圧レベル数のマルチレベル電力変換装置を提供することが課題となる。 As described above, it is a problem to provide a multi-level power conversion device having the number of divisions of the DC link capacitor of 2 or less and the number of voltage levels of 5 levels or more.
特開２０１５－０４７０５６号公報Japanese Patent Laid-Open No. 2015-047056
　本発明は、前記従来の問題に鑑み、案出されたもので、その一態様は、各相共通の直流リンクコンデンサと、前記各相共通の直流リンクコンデンサに接続され、基本セルを有する各相共通の第１～第Ｎ共通部（Ｎ＝２以上の整数）と、前記第Ｎ共通部に接続されたＭ相（Ｍ＝２以上の整数）の相モジュールと、を備え、前記基本セルは、第３端子に一端が接続された第１半導体デバイスと、第１端子に一端が接続された第２半導体デバイスと、前記第１半導体デバイスの他端と前記第２半導体デバイスの他端との間に接続されたフライングキャパシタと、前記第１半導体デバイスと前記フライングキャパシタの共通接続点と前記第２半導体デバイスと前記フライングキャパシタの共通接続点との間に接続された第３，第４半導体デバイスと、を備え、前記第３，第４半導体デバイスの共通接続点を第２端子とし、前記第１共通部は、前記直流リンクコンデンサの正極端に前記第３端子が接続され、前記直流リンクコンデンサの負極端に前記第１端子が接続された１つの前記基本セルを有し、前記第２～第Ｎ共通部は、それぞれ前記基本セルを２2-1～２N-1個有し、各共通部内の隣り合う前記基本セルの前記第３端子と前記第１端子とを接続して２2-1～２N-1個の基本セルを直列接続し、前記第１共通部の基本セルの第１端子側から数えて奇数番目の前記基本セルは、前段の前記基本セルの前記第２端子に前記第３端子が接続され、前段の前記基本セルの前記第１端子に前記第１端子が接続され、前記第１共通部の基本セルの第１端子側から数えて偶数番目の前記基本セルは、前段の前記基本セルの前記第３端子に前記第３端子が接続され、前段の前記基本セルの前記第２端子に前記第１端子が接続され、前記相モジュールは、前記第Ｎ共通部の前記基本セルの前記第１～第３端子を入力端子とし、前記入力端子と出力端子との間にそれぞれスイッチングデバイスを有し、スイッチングデバイスを選択的にＯＮ，ＯＦＦすることにより、前記入力端子のうち何れかの端子の電位を選択して出力することを特徴とする。 The present invention has been devised in view of the conventional problems, and one aspect thereof is a DC link capacitor common to each phase and each phase having a basic cell connected to the DC link capacitor common to each phase. A common first to Nth common part (an integer equal to or greater than N = 2) and an M-phase (an integer greater than or equal to M = 2) phase module connected to the Nth common part; A first semiconductor device having one end connected to the third terminal, a second semiconductor device having one end connected to the first terminal, and the other end of the first semiconductor device and the other end of the second semiconductor device. Flying capacitors connected in between, and third and fourth semiconductor devices connected between a common connection point of the first semiconductor device and the flying capacitor, and a common connection point of the second semiconductor device and the flying capacitor When, A common connection point of the third and fourth semiconductor devices is a second terminal, and the first common part is connected to the positive terminal of the direct current link capacitor, and the negative terminal of the direct current link capacitor. Each of the basic cells connected to the first terminal, and the second to N-th common parts have 2 2-1 to 2 N-1 basic cells, respectively. the connecting said third terminals of adjacent said basic cell and the first terminal 2 2-1 ~ 2 N-1 pieces of basic cells connected in series, a first terminal of the basic cell of the first common portion The odd-numbered basic cells counted from the side have the third terminal connected to the second terminal of the preceding basic cell, and the first terminal connected to the first terminal of the preceding basic cell, The even-numbered basic cells counted from the first terminal side of the basic cells of the first common part are The third terminal is connected to the third terminal of the basic cell, the first terminal is connected to the second terminal of the basic cell in the previous stage, and the phase module is connected to the basic cell of the Nth common portion. The first to third terminals are input terminals, each of which has a switching device between the input terminal and the output terminal, and by selectively turning on or off the switching device, any one of the input terminals It is characterized in that the potential of the terminal is selected and output.
　また、他の態様として、各相共通の直流リンクコンデンサと、前記各相共通の直流リンクコンデンサに接続され、基本セルを有する各相共通の第１～第Ｎ共通部（Ｎ＝２以上の整数）と、前記第Ｎ共通部に接続されたＭ相（Ｍ＝２以上の整数）の相モジュールと、を備え、前記基本セルは、第３端子に一端が接続された第１半導体デバイスと、第１端子に一端が接続された第２半導体デバイスと、前記第１半導体デバイスの他端と前記第２半導体デバイスの他端との間に接続されたフライングキャパシタと、前記第１半導体デバイスと前記フライングキャパシタの共通接続点と前記第２半導体デバイスと前記フライングキャパシタの共通接続点との間に接続された第３，第４半導体デバイスと、を備え、前記第３，第４半導体デバイスの共通接続点を第２端子とし、前記第１共通部は、前記直流リンクコンデンサの正極端に前記第３端子が接続され、前記直流リンクコンデンサの負極端に前記第１端子が接続された１つの前記基本セルを有し、前記第２～第Ｎ共通部は、それぞれ前記基本セルを２2-1～２N-1個有し、各共通部内の隣り合う前記基本セルの前記第３端子と前記第１端子とを接続して２2-1～２N-1個の基本セルを直列接続し、前記第１共通部の基本セルの第１端子側から数えて奇数番目の前記基本セルは、前段の前記基本セルの前記第２端子に前記第３端子が接続され、前段の前記基本セルの前記第１端子に前記第１端子が接続され、前記第１共通部の基本セルの第１端子側から数えて偶数番目の前記基本セルは、前段の前記基本セルの前記第３端子に前記第３端子が接続され、前段の前記基本セルの前記第２端子に前記第１端子が接続され、前記相モジュールは、前記第Ｎ共通部の基本セルの前記第１～第３端子を入力端子とし、前記入力端子と出力端子との間にスイッチングデバイスとキャパシタを有し、前記スイッチングデバイスを選択的にＯＮ，ＯＦＦすることにより、前記入力端子のうち何れかの端子の電位、または、前記入力端子のうち何れかの端子の電位にキャパシタの電圧を加算または減算した電位を出力端子から出力することを特徴とする。 Further, as another aspect, a DC link capacitor common to each phase, and first to Nth common parts (N = 2 or more integers) connected to the DC link capacitor common to each phase and having basic cells and common to each phase And a phase module of M phase (an integer greater than or equal to M = 2) connected to the Nth common part, and the basic cell includes a first semiconductor device having one end connected to a third terminal; A second semiconductor device having one end connected to a first terminal; a flying capacitor connected between the other end of the first semiconductor device and the other end of the second semiconductor device; the first semiconductor device; A common connection point of a flying capacitor, a third and a fourth semiconductor device connected between the second semiconductor device and a common connection point of the flying capacitor, and common to the third and fourth semiconductor devices The connection point is a second terminal, and the first common unit is connected to the positive terminal of the DC link capacitor, the third terminal is connected to the negative terminal of the DC link capacitor, and the first terminal is connected to the negative terminal. Each of the second to Nth common units includes 2 2-1 to 2 N-1 basic cells, and the third terminal of the adjacent basic cell in each common unit and the second cell 2 2-1 to 2 N-1 basic cells are connected in series with the first terminal, and the odd-numbered basic cells counted from the first terminal side of the basic cells of the first common part are: The third terminal is connected to the second terminal of the basic cell in the previous stage, the first terminal is connected to the first terminal of the basic cell in the previous stage, and the first terminal of the basic cell of the first common part The even-numbered basic cells counted from the side have the third terminal connected to the third terminal of the preceding basic cell. The first terminal is connected to the second terminal of the basic cell in the previous stage, and the phase module has the first to third terminals of the basic cell of the Nth common unit as input terminals, and the input A switching device and a capacitor are provided between the terminal and the output terminal, and by selectively turning on and off the switching device, the potential of any one of the input terminals or any of the input terminals A potential obtained by adding or subtracting the voltage of the capacitor to the potential of the terminal is output from the output terminal.
　また、その一態様として、前記直流リンクコンデンサの電圧を２Ｅに制御し、第Ｊ共通部（Ｊ＝１～Ｎまでの整数）の前記フライングキャパシタの電圧をＥ／２J-1に制御することを特徴とする。 Also, as one aspect thereof, the voltage of the DC link capacitor is controlled to 2E, and the voltage of the flying capacitor of the Jth common part (J = 1 to N) is controlled to E / 2 J-1. It is characterized by.
　また、他の態様として、各相共通の第１直流リンクコンデンサと、前記第１直流リンクコンデンサの正極端に負極端が接続された各相共通の第２直流リンクコンデンサと、前記各相共通の第１，第２直流リンクコンデンサに接続され、基本セルを有する各相共通の第１～第Ｎ共通部（Ｎ＝２以上の整数）と、前記第Ｎ共通部に接続されたＭ相（Ｍ＝２以上の整数）の相モジュールと、を備え、前記基本セルは、第３端子に一端が接続された第１半導体デバイスと、第１端子に一端が接続された第２半導体デバイスと、前記第１半導体デバイスの他端と前記第２半導体デバイスの他端との間に接続されたフライングキャパシタと、前記第１半導体デバイスと前記フライングキャパシタの共通接続点と前記第２半導体デバイスと前記フライングキャパシタの共通接続点との間に接続された第３，第４半導体デバイスと、を備え、前記第３，第４半導体デバイスの共通接続点を第２端子とし、前記第１共通部は、前記第１直流リンクコンデンサの正極端に前記第３端子が接続され、前記第１直流リンクコンデンサの負極端に前記第１端子が接続された第１の前記基本セルと、前記第２直流リンクコンデンサの正極端に前記第３端子が接続され、前記第２直流リンクコンデンサの負極端に前記第１端子が接続された第２の前記基本セルと、を有し、前記第２～第Ｎ共通部は、それぞれ前記基本セルを２×（２2-1）～２×（２N-1）個有し、各共通部内の隣り合う前記基本セルの前記第３端子と前記第１端子とを接続して２×（２2-1）～２×（２N-1）個の基本セルを直列接続し、前記第１共通部の第１の基本セルの第１端子側から数えて奇数番目の前記基本セルは、前段の前記基本セルの前記第２端子に前記第３端子が接続され、前段の前記基本セルの前記第１端子に前記第１端子が接続され、前記第１共通部の第１の基本セルの第１端子側から数えて偶数番目の前記基本セルは、前段の前記基本セルの前記第３端子に前記第３端子が接続され、前段の前記基本セルの前記第２端子に前記第１端子が接続され、前記相モジュールは、前記第Ｎ共通部の前記基本セルの前記第１～第３端子を入力端子とし、前記入力端子と出力端子との間にそれぞれスイッチングデバイスを有し、スイッチングデバイスを選択的にＯＮ，ＯＦＦすることにより、前記入力端子のうち何れかの端子の電位を選択して出力することを特徴とする。 Further, as another aspect, a first DC link capacitor common to each phase, a second DC link capacitor common to each phase in which a negative end is connected to a positive end of the first DC link capacitor, and a common to each phase A first to N-th common part (an integer equal to or greater than N = 2) connected to the first and second DC link capacitors and having a basic cell, and an M-phase connected to the N-th common part (M = An integer greater than or equal to 2), and the basic cell includes a first semiconductor device having one end connected to a third terminal, a second semiconductor device having one end connected to a first terminal, A flying capacitor connected between the other end of the first semiconductor device and the other end of the second semiconductor device, a common connection point of the first semiconductor device and the flying capacitor, the second semiconductor device, and the flying key Third and fourth semiconductor devices connected between the common connection points of the capacitors, the common connection point of the third and fourth semiconductor devices is a second terminal, and the first common portion is the A first basic cell in which the third terminal is connected to a positive terminal of a first DC link capacitor, and a first terminal is connected to a negative terminal of the first DC link capacitor; and A second basic cell having the third terminal connected to a positive electrode end and the first terminal connected to a negative electrode end of the second DC link capacitor; and the second to Nth common parts are Each having 2 × (2 2-1 ) to 2 × (2 N-1 ) basic cells, and connecting the third terminal and the first terminal of the adjacent basic cells in each common portion. the 2 × (2 2-1) ~ 2 × (2 N-1) number of elementary cells connected in series Te, the first common The odd-numbered basic cells counted from the first terminal side of the first basic cell are connected to the second terminal of the basic cell in the previous stage, and the first terminal of the basic cell in the previous stage. The first terminal is connected to a terminal, and the even-numbered basic cells counted from the first terminal side of the first basic cell of the first common portion are connected to the third terminal of the basic cell in the previous stage. 3 terminals are connected, the first terminal is connected to the second terminal of the basic cell in the previous stage, and the phase module has the first to third terminals of the basic cell of the N-th common part as input terminals Each of which has a switching device between the input terminal and the output terminal, and selectively turns on or off the switching device to select and output the potential of any one of the input terminals. It is characterized by.
　また、他の態様として、各相共通の第１直流リンクコンデンサと、前記第１直流リンクコンデンサの正極端に負極端が接続された各相共通の第２直流リンクコンデンサと、前記各相共通の第１，第２直流リンクコンデンサに接続され、基本セルを有する各相共通の第１～第Ｎ共通部（Ｎ＝２以上の整数）と、前記第Ｎ共通部に接続されたＭ相（Ｍ＝２以上の整数）の相モジュールと、を備え、前記基本セルは、第３端子に一端が接続された第１半導体デバイスと、第１端子に一端が接続された第２半導体デバイスと、前記第１半導体デバイスの他端と前記第２半導体デバイスの他端との間に接続されたフライングキャパシタと、前記第１半導体デバイスと前記フライングキャパシタの共通接続点と前記第２半導体デバイスと前記フライングキャパシタの共通接続点との間に接続された第３，第４半導体デバイスと、を備え、前記第３，第４半導体デバイスの共通接続点を第２端子とし、前記第１共通部は、前記第１直流リンクコンデンサの正極端に前記第３端子が接続され、前記第１直流リンクコンデンサの負極端に前記第１端子が接続された第１の前記基本セルと、前記第２直流リンクコンデンサの正極端に前記第３端子が接続され、前記第２直流リンクコンデンサの負極端に前記第１端子が接続された第２の前記基本セルと、を有し、前記第２～第Ｎ共通部は、それぞれ前記基本セルを２×（２2-1）～２×（２N-1）個有し、各共通部内の隣り合う前記基本セルの前記第３端子と前記第１端子とを接続して２×（２2-1）～２×（２N-1）個の基本セルを直列接続し、前記第１共通部の第１の基本セルの第１端子側から数えて奇数番目の前記基本セルは、前段の前記基本セルの前記第２端子に前記第３端子が接続され、前段の前記基本セルの前記第１端子に前記第１端子が接続され、前記第１共通部の第１の基本セルの第１端子側から数えて偶数番目の前記基本セルは、前段の前記基本セルの前記第３端子に前記第３端子が接続され、前段の前記基本セルの前記第２端子に前記第１端子が接続され、前記相モジュールは、前記第Ｎ共通部の基本セルの前記第１～第３端子を入力端子とし、前記入力端子と出力端子との間にスイッチングデバイスとキャパシタを有し、前記スイッチングデバイスを選択的にＯＮ，ＯＦＦすることにより、前記入力端子のうち何れかの端子の電位、または、前記入力端子のうち何れかの端子の電位にキャパシタの電圧を加算または減算した電位を出力端子から出力することを特徴とする。 Further, as another aspect, a first DC link capacitor common to each phase, a second DC link capacitor common to each phase in which a negative end is connected to a positive end of the first DC link capacitor, and a common to each phase A first to N-th common part (an integer equal to or greater than N = 2) connected to the first and second DC link capacitors and having a basic cell, and an M-phase connected to the N-th common part (M = An integer greater than or equal to 2), and the basic cell includes a first semiconductor device having one end connected to a third terminal, a second semiconductor device having one end connected to a first terminal, A flying capacitor connected between the other end of the first semiconductor device and the other end of the second semiconductor device, a common connection point of the first semiconductor device and the flying capacitor, the second semiconductor device, and the flying key Third and fourth semiconductor devices connected between the common connection points of the capacitors, the common connection point of the third and fourth semiconductor devices is a second terminal, and the first common portion is the A first basic cell in which the third terminal is connected to a positive terminal of a first DC link capacitor, and a first terminal is connected to a negative terminal of the first DC link capacitor; and A second basic cell having the third terminal connected to a positive electrode end and the first terminal connected to a negative electrode end of the second DC link capacitor; and the second to Nth common parts are Each having 2 × (2 2-1 ) to 2 × (2 N-1 ) basic cells, and connecting the third terminal and the first terminal of the adjacent basic cells in each common portion. the 2 × (2 2-1) ~ 2 × (2 N-1) number of elementary cells connected in series Te, the first common The odd-numbered basic cells counted from the first terminal side of the first basic cell are connected to the second terminal of the basic cell in the previous stage, and the first terminal of the basic cell in the previous stage. The first terminal is connected to a terminal, and the even-numbered basic cells counted from the first terminal side of the first basic cell of the first common portion are connected to the third terminal of the basic cell in the previous stage. 3 terminals are connected, the first terminal is connected to the second terminal of the basic cell in the previous stage, and the phase module has the first to third terminals of the basic cell of the Nth common part as input terminals. A switching device and a capacitor between the input terminal and the output terminal, and by selectively turning on and off the switching device, the potential of any one of the input terminals or the input terminal Of either terminal Position to and outputs an addition or subtraction potentials voltage of the capacitor from the output terminal.
　また、その一態様として、前記直流リンクコンデンサの電圧を４Ｅに制御し、第Ｊ共通部（Ｊ＝１～Ｎまでの整数）の前記フライングキャパシタの電圧をＥ／２J-1に制御することを特徴とする。 Further, as one aspect thereof, the voltage of the DC link capacitor is controlled to 4E, and the voltage of the flying capacitor of the Jth common part (J = 1 to N) is controlled to E / 2 J-1. It is characterized by.
　本発明によれば、直流リンクコンデンサの分割数を２以下とし、５レベル以上の電圧レベル数のマルチレベル電力変換装置を提供することが可能となる。 According to the present invention, it is possible to provide a multi-level power conversion device having the number of DC link capacitors divided by 2 or less and the number of voltage levels of 5 levels or more.
基本セルの構成を示す回路図。The circuit diagram which shows the structure of a basic cell. 基本セルのスイッチングパターンを示す図。The figure which shows the switching pattern of a basic cell. Ｎ段の第１～第Ｎ共通部を示す図。The figure which shows the 1st-Nth common part of N steps. 実施形態１におけるＭ相２N＋１レベルの電力変換装置を示す図。The figure which shows the power converter device of M phase 2N + 1 level in Embodiment 1. FIG. 実施形態２におけるＮ＝２，Ｍ＝３とした場合のマルチレベル電力変換装置を示す図。The figure which shows the multilevel power converter device when N = 2 and M = 3 in Embodiment 2. FIG. 実施形態３におけるＭ相２N+1＋１レベルの電力変換装置を示す図。It shows a power conversion device of the M phase 2 N + 1 +1 level in the third embodiment. 特許文献１のマルチレベル電力変換装置の一例を示す図。The figure which shows an example of the multilevel power converter device of patent document 1. FIG. 相モジュールの構成例を示す図。The figure which shows the structural example of a phase module.
　本願は、直流リンクコンデンサに各相共通のフライングキャパシタと各相共通の半導体デバイスにより構成される基本セルを複数段接続することで、５レベル以上のレベルにおいても直流リンクコンデンサを２分割以下にするものである。 In the present application, the DC link capacitor is divided into two or less even at a level of 5 levels or more by connecting a plurality of basic cells composed of a common flying capacitor and a semiconductor device common to each phase to the DC link capacitor. Is.
　スイッチングパターンによりフライングキャパシタの充電・放電を自由に行うことが可能であり、９レベル以上の多レベル化を外部回路なしで実現できる。 The charging / discharging of the flying capacitor can be performed freely according to the switching pattern, and multi-leveling of 9 levels or more can be realized without an external circuit.
　以下、本願発明におけるマルチレベル電力変換装置の実施形態１～３を図１～図６に基づいて詳述する。 Hereinafter, Embodiments 1 to 3 of the multilevel power conversion device according to the present invention will be described in detail with reference to FIGS.
　［実施形態１］
　本実施形態１における基本セルを図１に示し、基本セルのスイッチングパターンを図２に示す。図２中の丸印は導通している半導体デバイス（例えば、ＩＧＢＴ）を示す。 [Embodiment 1]
A basic cell according to the first embodiment is shown in FIG. 1, and a switching pattern of the basic cell is shown in FIG. A circle in FIG. 2 indicates a semiconductor device (for example, IGBT) that is conducting.
　本実施形態１の基本セルはフライングキャパシタＦＣ１と第１～第４半導体デバイスＳｃ１～Ｓｃ４を備える。これは特許文献１と同一のセルである。 The basic cell of Embodiment 1 includes a flying capacitor FC1 and first to fourth semiconductor devices Sc1 to Sc4. This is the same cell as in Patent Document 1.
　基本セル２０は、第３端子３に一端が接続された第１半導体デバイスＳｃ１と、第１端子１に一端が接続された第２半導体デバイスＳｃ２と、第１半導体デバイスＳｃ１の他端と、第２半導体デバイスＳｃ２の他端との間に接続されたフライングキャパシタＦＣ１と、第１半導体デバイスＳｃ１とフライングキャパシタＦＣ１の共通接続点と、第２半導体デバイスＳｃ２とフライングキャパシタＦＣ１の共通接続点と、の間に直列接続された第３，第４半導体デバイスＳｃ３，Ｓｃ４と、を備えている。第３，第４半導体デバイスＳｃ３，Ｓｃ４の共通接続点が第２端子２となる。 The basic cell 20 includes a first semiconductor device Sc1 having one end connected to the third terminal 3, a second semiconductor device Sc2 having one end connected to the first terminal 1, the other end of the first semiconductor device Sc1, A flying capacitor FC1 connected between the other ends of the two semiconductor devices Sc2, a common connection point of the first semiconductor device Sc1 and the flying capacitor FC1, and a common connection point of the second semiconductor device Sc2 and the flying capacitor FC1. And third and fourth semiconductor devices Sc3 and Sc4 connected in series. The common connection point of the third and fourth semiconductor devices Sc3 and Sc4 becomes the second terminal 2.
　基本セル２０のスイッチングパターンは、図２（ａ）に示すように第１半導体デバイスＳｃ１と第４半導体デバイスＳｃ４をＯＮ、または、図２（ｂ）に示すように第２半導体デバイスＳｃ２と第３半導体デバイスＳｃ３をＯＮする。 The switching pattern of the basic cell 20 is such that the first semiconductor device Sc1 and the fourth semiconductor device Sc4 are turned on as shown in FIG. 2A, or the second semiconductor device Sc2 and the third semiconductor device Sc4 are turned on as shown in FIG. The semiconductor device Sc3 is turned on.
　この基本セル２０を用いた本実施形態１の共通部を図３に示す。本実施形態１は、直流リンクコンデンサＤＣＣにＮ段の第１～第Ｎ共通部１１～１Ｎ（Ｎ＝２以上の整数）が接続される。 The common part of the first embodiment using this basic cell 20 is shown in FIG. In the first embodiment, N stages of first to Nth common parts 11 to 1N (N = 2 or more integer) are connected to the DC link capacitor DCC.
　第Ｊ共通部１Ｊ（Ｊ＝１～Ｎの整数）には、２J-1個の基本セルが接続される。例えば、Ｊ＝１（第１共通部１１）の場合、２0＝１個の基本セルが接続される。同様に、Ｊ＝２（第２共通部１２）の場合は２1＝２個の基本セルが、Ｊ＝３（第３共通部１３）の場合は２2＝４個の基本セルが、Ｊ＝４（第４共通部１４）の場合は２3＝８個の基本セルが接続される。第１～第Ｎ共通部１１～１Ｎ合計で基本セルは２N－１個となる。 2 J-1 basic cells are connected to the J-th common unit 1J (J = 1 to N). For example, when J = 1 (first common unit 11), 2 0 = 1 basic cells are connected. Similarly, if J = 2 (second common unit 12), 2 1 = 2 basic cells, and if J = 3 (third common unit 13), 2 2 = 4 basic cells = 4 (fourth common unit 14), 2 3 = 8 basic cells are connected. The total number of the first to Nth common units 11 to 1N is 2 N −1.
　第１共通部１１の基本セル２１ａは、直流リンクコンデンサＤＣＣの正極に第３端子３が接続され、直流リンクコンデンサＤＣＣの負極に第１端子１が接続される。 In the basic cell 21a of the first common unit 11, the third terminal 3 is connected to the positive electrode of the DC link capacitor DCC, and the first terminal 1 is connected to the negative electrode of the DC link capacitor DCC.
　第２～第Ｎ共通部１２～１Ｎの基本セルは、各共通部内の隣り合う基本セルの第３端子３と第１端子１とを接続して直列接続する。また、基本セル２１ａの第１端子側（すなわち、直流リンクコンデンサＤＣＣの負極側）から数えて奇数番目の基本セルは、前段の基本セルの第２端子２に第３端子３が接続され、前段の基本セルの第１端子１に第１端子１が接続される。基本セル２１ａの第１端子側から数えて偶数番目の基本セルは、前段の基本セルの第３端子３に第３端子３が接続され、前段の基本セルの第２端子２に第１端子１が接続される。 The basic cells of the second to Nth common parts 12 to 1N are connected in series by connecting the third terminal 3 and the first terminal 1 of the adjacent basic cells in each common part. The odd-numbered basic cells counted from the first terminal side of the basic cell 21a (that is, the negative electrode side of the DC link capacitor DCC) are connected to the second terminal 2 of the previous basic cell, and the third terminal 3 is connected. The first terminal 1 is connected to the first terminal 1 of the basic cell. In the even-numbered basic cells counted from the first terminal side of the basic cell 21a, the third terminal 3 is connected to the third terminal 3 of the preceding basic cell, and the first terminal 1 is connected to the second terminal 2 of the preceding basic cell. Is connected.
　ここで、例として第２共通部１２の基本セル２２ａ，２２ｂについて説明する。基本セル２１ａの第１端子１側から数えて１番目の基本セル２２ａの第３端子３と２番目の基本セル２２ｂの第１端子１とを接続する。また、基本セル２１ａの第１端子１側から数えて１番目の基本セル２２ａは、第１共通部１１の基本セル２１ａの第２端子２に第３端子３が接続され、第１共通部１１の基本セル２１ａの第１端子１に第１端子１が接続される。第１端子１側から数えて２番目の基本セル２２ｂは、第１共通部１１の基本セル２１ａの第３端子３に第３端子３が接続され、第１共通部１１の基本セル２１ａの第２端子２に第１端子１が接続される。第３～第Ｎ共通部１３～１Ｎの基本セルも同様に接続される。 Here, the basic cells 22a and 22b of the second common unit 12 will be described as an example. The third terminal 3 of the first basic cell 22a counting from the first terminal 1 side of the basic cell 21a is connected to the first terminal 1 of the second basic cell 22b. The first basic cell 22a counted from the first terminal 1 side of the basic cell 21a has the third terminal 3 connected to the second terminal 2 of the basic cell 21a of the first common part 11, and the first common part 11 The first terminal 1 is connected to the first terminal 1 of the basic cell 21a. The second basic cell 22b counted from the first terminal 1 side has the third terminal 3 connected to the third terminal 3 of the basic cell 21a of the first common part 11, and the second basic cell 22b of the basic cell 21a of the first common part 11 is connected. The first terminal 1 is connected to the two terminals 2. The basic cells of the third to Nth common units 13 to 1N are connected in the same manner.
　図３に示すように、２N－１個の基本セル（Ｎ＝１，２，３，…）を用いて第１～第Ｎ共通部１１～１Ｎを接続することにより、１つの直流リンクコンデンサＤＣＣで２N＋１レベルの電圧レベルに直流電圧を分割することができる。 As shown in FIG. 3, one DC link capacitor is obtained by connecting the first to Nth common parts 11 to 1N using 2 N -1 basic cells (N = 1, 2, 3,...). The DC voltage can be divided into 2 N +1 voltage levels by DCC.
　直流リンクコンデンサＤＣＣの電圧を２Ｅとした時、第Ｊ共通部１Ｊ（Ｊ＝１～Ｎの整数）のフライングキャパシタの電圧をＥ／２J-1に制御する。すなわち、第１共通部１１のフライングキャパシタＦＣ１の電圧をＥ，第２共通部１２のフライングキャパシタＦＣ２の電圧をＥ／２，…，第Ｎ共通部１ＮのフライングキャパシタＦＣの電圧をＥ／２N-1の電圧に分割し制御する。この分割した電圧レベルを選択する相モジュールをＭ相接続することでＭ相に拡張することが可能である。 When the voltage of the DC link capacitor DCC is set to 2E, the voltage of the flying capacitor of the J-th common unit 1J (J = 1 to N) is controlled to E / 2 J-1 . That is, the voltage of the flying capacitor FC1 of the first common unit 11 is E, the voltage of the flying capacitor FC2 of the second common unit 12 is E / 2,..., And the voltage of the flying capacitor FC of the Nth common unit 1N is E / 2 N. Divide and control to -1 voltage. It is possible to expand to the M phase by connecting the phase modules for selecting the divided voltage levels to the M phase.
　第Ｎ共通部１Ｎの基本セルの第１端子１，第２端子２，第３端子３には、相モジュールの入力端子が接続される。相モジュールは図８と同様である。 The input terminal of the phase module is connected to the first terminal 1, the second terminal 2, and the third terminal 3 of the basic cell of the Nth common unit 1N. The phase module is the same as in FIG.
　図８（ａ）の相モジュールの構成を説明する。第１入力端子Ｉ１と第２入力端子Ｉ２との間に第１，第２スイッチングデバイスＳ１，Ｓ２が直列接続される。第ｋ－１入力端子Ｉｋ－１と第ｋ入力端子Ｉｋとの間に第３，第４スイッチングデバイスＳ３，Ｓ４が直列接続される。 The configuration of the phase module shown in FIG. The first and second switching devices S1 and S2 are connected in series between the first input terminal I1 and the second input terminal I2. The third and fourth switching devices S3 and S4 are connected in series between the k-1 input terminal Ik-1 and the kth input terminal Ik.
　第１，第２スイッチングデバイスＳ１，Ｓ２の共通接続点と第３入力端子Ｉ３との間に第５～第８スイッチングデバイスＳ５～Ｓ８が直列接続される。第５，第６スイッチングデバイスＳ５，Ｓ６の共通接続点と第７，第８スイッチングデバイスＳ７，Ｓ８の共通接続点との間にキャパシタＦＣ１Ｍが接続される。 The fifth to eighth switching devices S5 to S8 are connected in series between the common connection point of the first and second switching devices S1 and S2 and the third input terminal I3. A capacitor FC1M is connected between the common connection point of the fifth and sixth switching devices S5 and S6 and the common connection point of the seventh and eighth switching devices S7 and S8.
　第ｋ－２入力端子Ｉｋ－２と第３，第４スイッチングデバイスの共通接続点との間に第９～第１２スイッチングデバイスＳ９～Ｓ１２が直列接続される。第９，第１０スイッチングデバイスＳ９，Ｓ１０の共通接続点と第１１，第１２スイッチングデバイスＳ１１，Ｓ１２の共通接続点との間にキャパシタＦＣＮＭが接続される。 The ninth to twelfth switching devices S9 to S12 are connected in series between the k-2 input terminal Ik-2 and the common connection point of the third and fourth switching devices. A capacitor FCNM is connected between the common connection point of the ninth and tenth switching devices S9 and S10 and the common connection point of the eleventh and twelfth switching devices S11 and S12.
　第６，第７スイッチングデバイスＳ６，Ｓ７の共通接続点と第１０，第１１スイッチングデバイスＳ１０，Ｓ１１の共通接続点との間に第１３～第１６スイッチングデバイスＳ１３～Ｓ１６が直列接続される。第１３，第１４スイッチングデバイスＳ１３，Ｓ１４の共通接続点と第１５，第１６スイッチングデバイスＳ１５，Ｓ１６の共通接続点との間にキャパシタＦＣＭＯが接続される。また、第１４，第１５スイッチングデバイスＳ１４，Ｓ１５の共通接続点が出力端子となる。 The thirteenth to sixteenth switching devices S13 to S16 are connected in series between the common connection point of the sixth and seventh switching devices S6 and S7 and the common connection point of the tenth and eleventh switching devices S10 and S11. A capacitor FCMO is connected between the common connection point of the thirteenth and fourteenth switching devices S13 and S14 and the common connection point of the fifteenth and sixteenth switching devices S15 and S16. The common connection point of the fourteenth and fifteenth switching devices S14 and S15 is an output terminal.
　次に、図８（ｂ）の相モジュールの構成を説明する。第１入力端子Ｉ１と第２入力端子Ｉ２との間に第１，第２スイッチングデバイスＳ１，Ｓ２が直列接続される。第ｋ－１入力端子Ｉｋ－１と第ｋ入力端子Ｉｋとの間に第３，第４スイッチングデバイスＳ３，Ｓ４が直列接続される。 Next, the configuration of the phase module in FIG. 8B will be described. The first and second switching devices S1 and S2 are connected in series between the first input terminal I1 and the second input terminal I2. The third and fourth switching devices S3 and S4 are connected in series between the k-1 input terminal Ik-1 and the kth input terminal Ik.
　第１，第２スイッチングデバイスＳ１，Ｓ２の共通接続点と第３，第４スイッチングデバイスＳ３，Ｓ４の共通接続点との間に第５～第１０スイッチングデバイスＳ５～Ｓ１０が直列接続される。 The fifth to tenth switching devices S5 to S10 are connected in series between the common connection point of the first and second switching devices S1 and S2 and the common connection point of the third and fourth switching devices S3 and S4.
　第５，第６スイッチングデバイスＳ５，Ｓ６の共通接続点と第７，第８スイッチングデバイスＳ７，Ｓ８の共通接続点との間に第１，第２ダイオードＤ１，Ｄ２が直列接続される。第１，第２ダイオードＤ１，Ｄ２の共通接続点は第３入力端子Ｉ３と接続される。第７，第８スイッチングデバイスＳ７，Ｓ８の共通接続点と第９，第１０スイッチングデバイスＳ９，Ｓ１０の共通接続点との間に第３，第４ダイオードＤ３，Ｄ４が直列接続される。第３，第４ダイオードＤ３，Ｄ４の共通接続点は第ｋ－２入力端子Ｉｋ－２と接続される。 The first and second diodes D1 and D2 are connected in series between the common connection point of the fifth and sixth switching devices S5 and S6 and the common connection point of the seventh and eighth switching devices S7 and S8. A common connection point of the first and second diodes D1 and D2 is connected to the third input terminal I3. The third and fourth diodes D3 and D4 are connected in series between the common connection point of the seventh and eighth switching devices S7 and S8 and the common connection point of the ninth and tenth switching devices S9 and S10. A common connection point of the third and fourth diodes D3 and D4 is connected to the k-2 input terminal Ik-2.
　第６，第７スイッチングデバイスＳ６，Ｓ７の共通接続点と第８，第９スイッチングデバイスＳ８，Ｓ９の共通接続点との間に第１１，第１２スイッチングデバイスＳ１１，Ｓ１２が直列接続される。第１１，第１２スイッチングデバイスＳ１１，Ｓ１２の共通接続点が出力端子となる。 The eleventh and twelfth switching devices S11 and S12 are connected in series between the common connection point of the sixth and seventh switching devices S6 and S7 and the common connection point of the eighth and ninth switching devices S8 and S9. A common connection point of the eleventh and twelfth switching devices S11 and S12 is an output terminal.
　次に、図８（ｃ）の相モジュールの構成を説明する。第１入力端子Ｉ１と第２入力端子Ｉ２との間に第１，第２スイッチングデバイスＳ１，Ｓ２が直列接続される。第ｋ－１入力端子Ｉｋ－１と第ｋ入力端子Ｉｋとの間に第３，第４スイッチングデバイスＳ３，Ｓ４が直列接続される。 Next, the configuration of the phase module shown in FIG. The first and second switching devices S1 and S2 are connected in series between the first input terminal I1 and the second input terminal I2. The third and fourth switching devices S3 and S4 are connected in series between the k-1 input terminal Ik-1 and the kth input terminal Ik.
　第３入力端子Ｉ３には、第５，第６スイッチングデバイスＳ５，Ｓ６が逆直列接続される。第ｋ－２入力端子Ｉｋ－２には、第８，第９スイッチングデバイスＳ８，Ｓ９が逆直列接続される。 The fifth and sixth switching devices S5 and S6 are connected in reverse series to the third input terminal I3. The eighth and ninth switching devices S8 and S9 are connected in reverse series to the k-2 input terminal Ik-2.
　第１，第２スイッチングデバイスＳ１，Ｓ２の共通接続点と第６スイッチングデバイスＳ６との間には第７スイッチングデバイスＳ７が接続される。第３，第４スイッチングデバイスＳ３，Ｓ４の共通接続点と第９スイッチングデバイスＳ９との間には第１０スイッチングデバイスＳ１０が接続される。 A seventh switching device S7 is connected between the common connection point of the first and second switching devices S1 and S2 and the sixth switching device S6. A tenth switching device S10 is connected between the common connection point of the third and fourth switching devices S3 and S4 and the ninth switching device S9.
　第６，第７スイッチングデバイスＳ６，Ｓ７の共通接続点と第９，第１０スイッチングデバイスＳ９，Ｓ１０の共通接続点とが接続され、その接続点が出力端子となる。 The common connection point of the sixth and seventh switching devices S6 and S7 and the common connection point of the ninth and tenth switching devices S9 and S10 are connected, and the connection point becomes an output terminal.
　相モジュールとして、図８（ａ）～（ｃ）を説明したが、入力端子と出力端子との間にスイッチングデバイスを有し、入力端子の電位を選択して、または、入力端子の電位にキャパシタの電圧を加算・減算して出力するものであれば、他の構成でも良い。 8 (a) to 8 (c) have been described as the phase module. However, the switching device is provided between the input terminal and the output terminal, and the potential of the input terminal is selected or the capacitor is set to the potential of the input terminal Any other configuration may be used as long as the voltage is added and subtracted.
　基本セルには、図２（ａ）（ｂ）の２種類のスイッチングパターンがあり、一つの電流の方向に応じて図２（ａ）（ｂ）のパターンを選択することでフライングキャパシタの充電もしくは放電を任意に選択することができる。 The basic cell has two types of switching patterns shown in FIGS. 2 (a) and 2 (b). By selecting the pattern shown in FIGS. 2 (a) and 2 (b) according to the direction of one current, charging of the flying capacitor or The discharge can be arbitrarily selected.
　したがって、充電・放電により電圧バランスをとることができるため、従来技術（図７）のように、直流リンクコンデンサＤＣＣを多段に積むことなく、各フライングキャパシタで電圧を分担し、かつ、電圧バランスもとることが可能である。 Therefore, since voltage balance can be achieved by charging and discharging, the voltage is shared by each flying capacitor without stacking DC link capacitors DCC in multiple stages as in the prior art (FIG. 7), and voltage balance is also achieved. It is possible to take.
　図４は、図３に示す直流リンクコンデンサＤＣＣおよび第１～第Ｎ共通部１１～１Ｎと相モジュールから構成されるＭ相２N＋１レベルのマルチレベル変換装置を示す図である。２N－１個の基本セルを用いてＮ段の第１～第Ｎ共通部１１～１Ｎを多重接続することにより、マルチレベル電力変換装置は２N＋１レベルの相電圧を出力することができる。 FIG. 4 is a diagram showing an M-phase 2 N +1 level multi-level conversion device including the DC link capacitor DCC, the first to Nth common units 11 to 1N, and the phase module shown in FIG. By multi-connecting the N-th first to N-th common units 11 to 1N using 2 N -1 basic cells, the multilevel power conversion device can output a phase voltage of 2 N +1 level. .
　なお、相モジュールは、特許文献１や、図８の構成のものを使用する。この時、図８の相モジュールの入力端子数ｋ＝電圧レベル数２N＋１となる。 In addition, the thing of the structure of patent document 1 and FIG. 8 is used for a phase module. At this time, the number k of input terminals of the phase module of FIG. 8 is equal to the number of voltage levels 2 N +1.
　以上示したように、本実施形態１によれば、直流リンクコンデンサＤＣＣの分割数を２以下（本実施形態１では１）として、５レベルを超える電圧レベル数のマルチレベル電力変換装置を提供することが可能となる。 As described above, according to the first embodiment, the number of divisions of the DC link capacitor DCC is set to 2 or less (1 in the first embodiment), and a multilevel power conversion device having a number of voltage levels exceeding five levels is provided. It becomes possible.
　直流リンクコンデンサＤＣＣの分割数が２以下であるため、外部回路を接続することなく、容易に分割した直流リンクコンデンサＤＣＣの電圧バランスをとることができる。これにより、電圧バランスが崩れることで電力変換装置の出力相電圧の高調波成分が増加し、電力変換装置に接続する負荷へ悪影響を与えることを抑制することが可能となる。 Since the division number of the DC link capacitor DCC is 2 or less, the voltage balance of the divided DC link capacitor DCC can be easily obtained without connecting an external circuit. Thereby, it becomes possible to suppress that the harmonic component of the output phase voltage of the power converter increases due to the voltage balance being lost and adversely affects the load connected to the power converter.
　［実施形態２］
　図５は、本実施形態２におけるマルチレベル電力変換装置を示す回路図である。直流リンクコンデンサＤＣＣ１，ＤＣＣ２を２段直列接続し、Ｎ＝２，Ｍ＝３とした場合の回路構成である。これにより直流電圧を２分割にしたままで、９レベルの電圧を出力することができる。なお、図５では、直流リンクコンデンサＤＣＣ１、ＤＣＣ２の電圧を４Ｅに制御する。 [Embodiment 2]
FIG. 5 is a circuit diagram showing a multilevel power conversion device according to the second embodiment. In this circuit configuration, DC link capacitors DCC1 and DCC2 are connected in two stages in series, and N = 2 and M = 3. As a result, a 9-level voltage can be output while the DC voltage is divided into two. In FIG. 5, the voltages of the DC link capacitors DCC1 and DCC2 are controlled to 4E.
　本実施形態２におけるマルチレベル電力変換装置の具体的な構成を説明する。直流リンクコンデンサＤＣＣ１，ＤＣＣ２が直列接続される。直流リンクコンデンサＤＣＣ１，ＤＣＣ２の共通接続点を中性点ＮＰとする。 A specific configuration of the multilevel power conversion device according to the second embodiment will be described. DC link capacitors DCC1, DCC2 are connected in series. A common connection point of the DC link capacitors DCC1 and DCC2 is defined as a neutral point NP.
　第１共通部１１には、２つの基本セル２１ａ，２１ｂが設けられる。基本セル２１ａの第３端子３と基本セル２１ｂの第１端子１とが接続される。 The first common unit 11 is provided with two basic cells 21a and 21b. The third terminal 3 of the basic cell 21a and the first terminal 1 of the basic cell 21b are connected.
　また、基本セル２１ａの第１端子１は、直流リンクコンデンサＤＣＣ１の負極端に接続され、基本セル２１ａの第３端子３は、直流リンクコンデンサＤＣＣ１の正極端に接続される。基本セル２１ｂの第１端子１は直流リンクコンデンサＤＣＣ２の負極端に接続され、基本セル２１ｂの第３端子３は直流リンクコンデンサＤＣＣ２の正極端に接続される。 Further, the first terminal 1 of the basic cell 21a is connected to the negative terminal of the DC link capacitor DCC1, and the third terminal 3 of the basic cell 21a is connected to the positive terminal of the DC link capacitor DCC1. The first terminal 1 of the basic cell 21b is connected to the negative terminal of the DC link capacitor DCC2, and the third terminal 3 of the basic cell 21b is connected to the positive terminal of the DC link capacitor DCC2.
　第２共通部１２には、４つの基本セル２２ａ，２２ｂ，２２ｃ，２２ｄが設けられる。基本セル２２ａの第３端子３と基本セル２２ｂの第１端子１が接続され、基本セル２２ｂの第３端子３と基本セル２２ｃの第１端子が接続され、基本セル２２ｃの第３端子３と基本セル２２ｄの第１端子１が接続される。 The second common unit 12 is provided with four basic cells 22a, 22b, 22c, and 22d. The third terminal 3 of the basic cell 22a and the first terminal 1 of the basic cell 22b are connected, the third terminal 3 of the basic cell 22b and the first terminal of the basic cell 22c are connected, and the third terminal 3 of the basic cell 22c The first terminal 1 of the basic cell 22d is connected.
　また、基本セル２２ａの第１端子１は第１共通部１１の基本セル２１ａの第１端子１と接続される。基本セル２２ａの第３端子３は第１共通部１１の基本セル２１ａの第２端子２と接続される。 Also, the first terminal 1 of the basic cell 22 a is connected to the first terminal 1 of the basic cell 21 a of the first common unit 11. The third terminal 3 of the basic cell 22 a is connected to the second terminal 2 of the basic cell 21 a of the first common unit 11.
　基本セル２２ｂの第１端子１は第１共通部１１の基本セル２１ａの第２端子２と接続される。基本セル２２ｂの第３端子３は第１共通部１１の基本セル２１ａの第３端子３と接続される。 The first terminal 1 of the basic cell 22 b is connected to the second terminal 2 of the basic cell 21 a of the first common unit 11. The third terminal 3 of the basic cell 22 b is connected to the third terminal 3 of the basic cell 21 a of the first common unit 11.
　基本セル２２ｃの第１端子１は第１共通部１１の基本セル２１ｂの第１端子１と接続される。基本セル２２ｃの第３端子３は第１共通部１１の基本セル２１ｂの第２端子２と接続される。 The first terminal 1 of the basic cell 22 c is connected to the first terminal 1 of the basic cell 21 b of the first common unit 11. The third terminal 3 of the basic cell 22 c is connected to the second terminal 2 of the basic cell 21 b of the first common unit 11.
　基本セル２２ｄの第１端子１は第１共通部１１の基本セル２１ｂの第２端子２と接続される。基本セル２２ｄの第３端子３は第１共通部１１の基本セル２１ｂの第３端子３と接続される。 The first terminal 1 of the basic cell 22d is connected to the second terminal 2 of the basic cell 21b of the first common unit 11. The third terminal 3 of the basic cell 22 d is connected to the third terminal 3 of the basic cell 21 b of the first common unit 11.
　最終段である第２共通部１２の基本セル２２ａ～２２ｄの第１端子１，第２端子２，第３端子３には、３相の相モジュール３１，３２，３３の入力端子が接続される。 The input terminals of the three- phase phase modules 31, 32, and 33 are connected to the first terminal 1, the second terminal 2, and the third terminal 3 of the basic cells 22a to 22d of the second common unit 12 that is the final stage. .
　相モジュール３１について説明する。基本セル２２ｄの第３端子３と第２端子２との間に第１，第２スイッチングデバイスＳ１ｕ，Ｓ２ｕが直列接続される。基本セル２２ａの第２端子２と第１端子１との間に第１５，第１６スイッチングデバイスＳ１５ｕ，Ｓ１６ｕが直列接続される。 The phase module 31 will be described. The first and second switching devices S1u and S2u are connected in series between the third terminal 3 and the second terminal 2 of the basic cell 22d. Fifteenth and sixteenth switching devices S15u and S16u are connected in series between the second terminal 2 and the first terminal 1 of the basic cell 22a.
　第１，第２スイッチングデバイスＳ１ｕ，Ｓ２ｕの共通接続点と基本セル２２ｄの第１端子１との間に第３，第４スイッチングデバイスＳ３ｕ，Ｓ４ｕが直列接続される。基本セル２２ａの第３端子３と第１５，第１６スイッチングデバイスＳ１５ｕ，Ｓ１６ｕの共通接続点との間に第１３，第１４スイッチングデバイスＳ１３ｕ，Ｓ１４ｕが直列接続される。 The third and fourth switching devices S3u and S4u are connected in series between the common connection point of the first and second switching devices S1u and S2u and the first terminal 1 of the basic cell 22d. The thirteenth and fourteenth switching devices S13u and S14u are connected in series between the third terminal 3 of the basic cell 22a and the common connection point of the fifteenth and sixteenth switching devices S15u and S16u.
　第３，第４スイッチングデバイスＳ３ｕ，Ｓ４ｕの共通接続点と基本セル２２ｃの第２端子２の間に第５，第６スイッチングデバイスＳ５ｕ，Ｓ６ｕが直列接続される。基本セル２２ｂの第２端子２と第１３，第１４スイッチングデバイスＳ１３ｕ，Ｓ１４ｕの共通接続点との間に第１１，第１２スイッチングデバイスＳ１１ｕ，Ｓ１２ｕが直列接続される。 The fifth and sixth switching devices S5u and S6u are connected in series between the common connection point of the third and fourth switching devices S3u and S4u and the second terminal 2 of the basic cell 22c. The eleventh and twelfth switching devices S11u and S12u are connected in series between the second terminal 2 of the basic cell 22b and the common connection point of the thirteenth and fourteenth switching devices S13u and S14u.
　第５，第６スイッチングデバイスＳ５ｕ，Ｓ６ｕの共通接続点と第１１，第１２スイッチングデバイスＳ１１ｕ，Ｓ１２ｕの共通接続点との間に第７～第１０スイッチングデバイスＳ７ｕ～Ｓ１０ｕが直列接続される。第７，第８スイッチングデバイスＳ７ｕ，Ｓ８ｕの共通接続点と第９，第１０スイッチングデバイスＳ９ｕ，Ｓ１０ｕの共通接続点との間に第１，第２ダイオードＤ１ｕ，Ｄ２ｕが直列接続される。第１，第２ダイオードＤ１ｕ，Ｄ２ｕの共通接続点は、中性点ＮＰに接続される。第８，第９スイッチングデバイスＳ８ｕ，Ｓ９ｕの共通接続点が出力端子となる。 The seventh to tenth switching devices S7u to S10u are connected in series between the common connection point of the fifth and sixth switching devices S5u and S6u and the common connection point of the eleventh and twelfth switching devices S11u and S12u. The first and second diodes D1u and D2u are connected in series between the common connection point of the seventh and eighth switching devices S7u and S8u and the common connection point of the ninth and tenth switching devices S9u and S10u. A common connection point of the first and second diodes D1u and D2u is connected to the neutral point NP. A common connection point of the eighth and ninth switching devices S8u and S9u is an output terminal.
　相モジュールのスイッチングパターンを表１に示す。なお、表１の電圧レベルは、図５の中性点の中性点ＮＰに対する各相の出力相電圧のレベルである。 Table 1 shows the phase module switching patterns. The voltage level in Table 1 is the level of the output phase voltage of each phase with respect to the neutral point NP of the neutral point in FIG.
　この時、第１，第２共通部１１，１２を構成する各基本セル２１ａ，２１ｂ，２２ａ，２２ｂ，２２ｃ，２２ｄのスイッチングパターンは図２の（ａ），（ｂ）のいずれかが選択されているものとする。この各基本セル２１ａ，２１ｂ，２２ａ，２２ｂ，２２ｃ，２２ｄの動作によって、図５の相モジュールの入力端子（すなわち、２段目の基本セルの出力端子）の電位は、図５の上から、４Ｅ，３Ｅ，２Ｅ，Ｅ，０，－Ｅ，－２Ｅ，－３Ｅ，－４Ｅとなる。（ＮＰ端子の電位を基準とする。） At this time, one of the switching patterns of the basic cells 21a, 21b, 22a, 22b, 22c, and 22d constituting the first and second common units 11 and 12 is selected from (a) and (b) of FIG. It shall be. By the operation of each of the basic cells 21a, 21b, 22a, 22b, 22c, and 22d, the potential of the input terminal of the phase module in FIG. 5 (that is, the output terminal of the second-stage basic cell) is as shown in FIG. 4E, 3E, 2E, E, 0, -E, -2E, -3E, and -4E. (Based on the potential of the NP terminal)
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　以上示したように、本実施形態２によれば、直流電圧を２分割にしたままで、９レベルの電圧を出力することが可能となる。 As described above, according to the second embodiment, it is possible to output a 9-level voltage while keeping the DC voltage divided into two.
　［実施形態３］
　図６は、本実施形態３におけるマルチレベル電力変換装置を示す回路図である。本実施形態３は、直流リンクコンデンサＤＣＣ１，ＤＣＣ２を２段直列に接続したＭ相２N+1＋１レベルのマルチレベル電力変換装置である。第１～第Ｎ共通部１１～１１Ｎは、それぞれ２×（２1-1）～２×（２N-1）個の基本セルを有する。直流リンクコンデンサＤＣＣ１，ＤＣＣ２を２つ設けているため、基本セルも図４の２N－１の２倍の２×（２N－１）個となる。２×（２N－１）個の基本セルを使用することで、２N+1＋１レベルの電圧を出力することが可能となる。直流リンクコンデンサＤＣＣ１，ＤＣＣ２の電圧を４Ｅとすると、Ｎ段目のフライングキャパシタはＥ／２N-1の電圧に分割し制御する。 [Embodiment 3]
FIG. 6 is a circuit diagram showing a multilevel power conversion device according to the third embodiment. The third embodiment is an M-phase 2 N + 1 +1 level multi-level power conversion device in which DC link capacitors DCC1 and DCC2 are connected in series in two stages. The first to Nth common units 11 to 11N have 2 × (2 1-1 ) to 2 × (2 N-1 ) basic cells, respectively. Since two DC link capacitors DCC1 and DCC2 are provided, the number of basic cells is 2 × (2 N −1), which is twice that of 2 N −1 in FIG. By using 2 × (2 N −1) basic cells, it is possible to output a voltage of 2 N + 1 +1 level. When the voltage of the DC link capacitors DCC1 and DCC2 is 4E, the Nth stage flying capacitor is divided into E / 2 N-1 voltage and controlled.
　なお、実施形態２は図６の回路においてＮ＝２、Ｍ＝３としたものである。なお、相モジュールは、特許文献１や実施形態１と同様、図８の構成を使用する。
この時、図８の相モジュールの入力端子数ｋ＝電圧レベル数（２N+1＋１）となる。 In the second embodiment, N = 2 and M = 3 in the circuit of FIG. The phase module uses the configuration shown in FIG. 8 as in Patent Document 1 and Embodiment 1.
At this time, the number k of input terminals of the phase module in FIG. 8 is equal to the number of voltage levels (2 N + 1 +1).
　なお、本実施形態１～３は、直流電力を交流電力に変換するＤＣ／ＡＣ変換器だけではなく、交流電力を直流電力に変換するＡＣ／ＤＣ変換器にも適用できる。ＡＣ／ＤＣ変換器に適用した場合は、ＤＣ／ＡＣ変換器に接続する交流入力電源の高調波電流を低減できる効果がある。 The first to third embodiments can be applied not only to a DC / AC converter that converts DC power into AC power but also to an AC / DC converter that converts AC power into DC power. When applied to an AC / DC converter, there is an effect that the harmonic current of the AC input power source connected to the DC / AC converter can be reduced.
　以上、本発明において、記載された具体例に対してのみ詳細に説明したが、本発明の技術思想の範囲で多彩な変形および修正が可能であることは、当業者にとって明白なことであり、このような変形および修正が特許請求の範囲に属することは当然のことである。 Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

Claims (6)

  1. 　各相共通の直流リンクコンデンサと、
    　前記各相共通の直流リンクコンデンサに接続され、基本セルを有する各相共通の第１～第Ｎ共通部（Ｎ＝２以上の整数）と、
    　前記第Ｎ共通部に接続されたＭ相（Ｍ＝２以上の整数）の相モジュールと、を備え、
    　前記基本セルは、第３端子に一端が接続された第１半導体デバイスと、第１端子に一端が接続された第２半導体デバイスと、前記第１半導体デバイスの他端と前記第２半導体デバイスの他端との間に接続されたフライングキャパシタと、前記第１半導体デバイスと前記フライングキャパシタの共通接続点と前記第２半導体デバイスと前記フライングキャパシタの共通接続点との間に接続された第３，第４半導体デバイスと、を備え、前記第３，第４半導体デバイスの共通接続点を第２端子とし、
    　前記第１共通部は、前記直流リンクコンデンサの正極端に前記第３端子が接続され、前記直流リンクコンデンサの負極端に前記第１端子が接続された１つの前記基本セルを有し、
    　前記第２～第Ｎ共通部は、それぞれ前記基本セルを２2-1～２N-1個有し、各共通部内の隣り合う前記基本セルの前記第３端子と前記第１端子とを接続して２2-1～２N-1個の基本セルを直列接続し、前記第１共通部の基本セルの第１端子側から数えて奇数番目の前記基本セルは、前段の前記基本セルの前記第２端子に前記第３端子が接続され、前段の前記基本セルの前記第１端子に前記第１端子が接続され、前記第１共通部の基本セルの第１端子側から数えて偶数番目の前記基本セルは、前段の前記基本セルの前記第３端子に前記第３端子が接続され、前段の前記基本セルの前記第２端子に前記第１端子が接続され、
    　前記相モジュールは、前記第Ｎ共通部の前記基本セルの前記第１～第３端子を入力端子とし、前記入力端子と出力端子との間にそれぞれスイッチングデバイスを有し、スイッチングデバイスを選択的にＯＮ，ＯＦＦすることにより、前記入力端子のうち何れかの端子の電位を選択して出力するマルチレベル電力変換装置。     DC link capacitor common to each phase,
    First to Nth common parts (N = 2 or more integers) connected to the DC link capacitors common to the phases and having basic cells
    A phase module of M phase (an integer greater than or equal to M = 2) connected to the Nth common part,
    The basic cell includes a first semiconductor device having one end connected to a third terminal, a second semiconductor device having one end connected to the first terminal, the other end of the first semiconductor device, and the second semiconductor device. A flying capacitor connected between the other end, a third connection point connected between a common connection point of the first semiconductor device and the flying capacitor, and a common connection point of the second semiconductor device and the flying capacitor. A fourth semiconductor device, and a common connection point of the third and fourth semiconductor devices as a second terminal,
    The first common unit has one basic cell in which the third terminal is connected to the positive terminal of the DC link capacitor and the first terminal is connected to the negative terminal of the DC link capacitor;
    The second to Nth common parts have 2 2-1 to 2 N-1 basic cells, respectively, and connect the third terminal and the first terminal of the adjacent basic cells in each common part. 2 2-1 to 2 N-1 basic cells are connected in series, and the odd-numbered basic cells counted from the first terminal side of the basic cells of the first common part are connected to the basic cells of the preceding stage. The third terminal is connected to the second terminal, the first terminal is connected to the first terminal of the basic cell in the previous stage, and the even number counted from the first terminal side of the basic cell of the first common part In the basic cell, the third terminal is connected to the third terminal of the basic cell in the previous stage, and the first terminal is connected to the second terminal of the basic cell in the previous stage,
    The phase module has the first to third terminals of the basic cell of the Nth common unit as input terminals, and each has a switching device between the input terminal and the output terminal, and selectively selects a switching device. A multi-level power conversion device that selects and outputs the potential of one of the input terminals by turning on and off.
  2. 　各相共通の直流リンクコンデンサと、
    　前記各相共通の直流リンクコンデンサに接続され、基本セルを有する各相共通の第１～第Ｎ共通部（Ｎ＝２以上の整数）と、
    　前記第Ｎ共通部に接続されたＭ相（Ｍ＝２以上の整数）の相モジュールと、を備え、
    　前記基本セルは、第３端子に一端が接続された第１半導体デバイスと、第１端子に一端が接続された第２半導体デバイスと、前記第１半導体デバイスの他端と前記第２半導体デバイスの他端との間に接続されたフライングキャパシタと、前記第１半導体デバイスと前記フライングキャパシタの共通接続点と前記第２半導体デバイスと前記フライングキャパシタの共通接続点との間に接続された第３，第４半導体デバイスと、を備え、前記第３，第４半導体デバイスの共通接続点を第２端子とし、
    　前記第１共通部は、前記直流リンクコンデンサの正極端に前記第３端子が接続され、前記直流リンクコンデンサの負極端に前記第１端子が接続された１つの前記基本セルを有し、
    　前記第２～第Ｎ共通部は、それぞれ前記基本セルを２2-1～２N-1個有し、各共通部内の隣り合う前記基本セルの前記第３端子と前記第１端子とを接続して２2-1～２N-1個の基本セルを直列接続し、前記第１共通部の基本セルの第１端子側から数えて奇数番目の前記基本セルは、前段の前記基本セルの前記第２端子に前記第３端子が接続され、前段の前記基本セルの前記第１端子に前記第１端子が接続され、前記第１共通部の基本セルの第１端子側から数えて偶数番目の前記基本セルは、前段の前記基本セルの前記第３端子に前記第３端子が接続され、前段の前記基本セルの前記第２端子に前記第１端子が接続され、
    　前記相モジュールは、前記第Ｎ共通部の基本セルの前記第１～第３端子を入力端子とし、前記入力端子と出力端子との間にスイッチングデバイスとキャパシタを有し、前記スイッチングデバイスを選択的にＯＮ，ＯＦＦすることにより、前記入力端子のうち何れかの端子の電位、または、前記入力端子のうち何れかの端子の電位にキャパシタの電圧を加算または減算した電位を出力端子から出力するマルチレベル電力変換装置。     DC link capacitor common to each phase,
    First to Nth common parts (N = 2 or more integers) connected to the DC link capacitors common to the phases and having basic cells
    A phase module of M phase (an integer greater than or equal to M = 2) connected to the Nth common part,
    The basic cell includes a first semiconductor device having one end connected to a third terminal, a second semiconductor device having one end connected to the first terminal, the other end of the first semiconductor device, and the second semiconductor device. A flying capacitor connected between the other end, a third connection point connected between a common connection point of the first semiconductor device and the flying capacitor, and a common connection point of the second semiconductor device and the flying capacitor. A fourth semiconductor device, and a common connection point of the third and fourth semiconductor devices as a second terminal,
    The first common unit has one basic cell in which the third terminal is connected to the positive terminal of the DC link capacitor and the first terminal is connected to the negative terminal of the DC link capacitor;
    The second to Nth common parts have 2 2-1 to 2 N-1 basic cells, respectively, and connect the third terminal and the first terminal of the adjacent basic cells in each common part. 2 2-1 to 2 N-1 basic cells are connected in series, and the odd-numbered basic cells counted from the first terminal side of the basic cells of the first common part are connected to the basic cells of the preceding stage. The third terminal is connected to the second terminal, the first terminal is connected to the first terminal of the basic cell in the previous stage, and the even number counted from the first terminal side of the basic cell of the first common part In the basic cell, the third terminal is connected to the third terminal of the basic cell in the previous stage, and the first terminal is connected to the second terminal of the basic cell in the previous stage,
    The phase module includes the first to third terminals of the basic cell of the N-th common unit as input terminals, and includes a switching device and a capacitor between the input terminal and the output terminal, and selectively selects the switching device. The output terminal outputs a potential obtained by adding or subtracting the voltage of the capacitor to the potential of any one of the input terminals or the potential of any of the input terminals. Level power converter.
  3. 　前記直流リンクコンデンサの電圧を２Ｅに制御し、
    　第Ｊ共通部（Ｊ＝１～Ｎまでの整数）の前記フライングキャパシタの電圧をＥ／２J-1に制御する請求項１または２記載のマルチレベル電力変換装置。     Control the voltage of the DC link capacitor to 2E;
    The multilevel power conversion device according to claim 1 or 2, wherein the voltage of the flying capacitor in the J-th common part (J = integer from 1 to N) is controlled to E / 2 J-1 .
  4. 　各相共通の第１直流リンクコンデンサと、
    　前記第１直流リンクコンデンサの正極端に負極端が接続された各相共通の第２直流リンクコンデンサと、
    　前記各相共通の第１，第２直流リンクコンデンサに接続され、基本セルを有する各相共通の第１～第Ｎ共通部（Ｎ＝２以上の整数）と、
    　前記第Ｎ共通部に接続されたＭ相（Ｍ＝２以上の整数）の相モジュールと、を備え、
    　前記基本セルは、第３端子に一端が接続された第１半導体デバイスと、第１端子に一端が接続された第２半導体デバイスと、前記第１半導体デバイスの他端と前記第２半導体デバイスの他端との間に接続されたフライングキャパシタと、前記第１半導体デバイスと前記フライングキャパシタの共通接続点と前記第２半導体デバイスと前記フライングキャパシタの共通接続点との間に接続された第３，第４半導体デバイスと、を備え、前記第３，第４半導体デバイスの共通接続点を第２端子とし、
    　前記第１共通部は、前記第１直流リンクコンデンサの正極端に前記第３端子が接続され、前記第１直流リンクコンデンサの負極端に前記第１端子が接続された第１の前記基本セルと、前記第２直流リンクコンデンサの正極端に前記第３端子が接続され、前記第２直流リンクコンデンサの負極端に前記第１端子が接続された第２の前記基本セルと、を有し、
    　前記第２～第Ｎ共通部は、それぞれ前記基本セルを２×（２2-1）～２×（２N-1）個有し、各共通部内の隣り合う前記基本セルの前記第３端子と前記第１端子とを接続して２×（２2-1）～２×（２N-1）個の基本セルを直列接続し、前記第１共通部の第１の基本セルの第１端子側から数えて奇数番目の前記基本セルは、前段の前記基本セルの前記第２端子に前記第３端子が接続され、前段の前記基本セルの前記第１端子に前記第１端子が接続され、前記第１共通部の第１の基本セルの第１端子側から数えて偶数番目の前記基本セルは、前段の前記基本セルの前記第３端子に前記第３端子が接続され、前段の前記基本セルの前記第２端子に前記第１端子が接続され、
    　前記相モジュールは、前記第Ｎ共通部の前記基本セルの前記第１～第３端子を入力端子とし、前記入力端子と出力端子との間にそれぞれスイッチングデバイスを有し、スイッチングデバイスを選択的にＯＮ，ＯＦＦすることにより、前記入力端子のうち何れかの端子の電位を選択して出力するマルチレベル電力変換装置。     A first DC link capacitor common to each phase;
    A second DC link capacitor common to each phase, the negative electrode end of which is connected to the positive electrode end of the first DC link capacitor;
    First to Nth common parts (N = 2 or more integers) connected to the first and second DC link capacitors common to the respective phases and having basic cells and common to each phase;
    A phase module of M phase (an integer greater than or equal to M = 2) connected to the Nth common part,
    The basic cell includes a first semiconductor device having one end connected to a third terminal, a second semiconductor device having one end connected to the first terminal, the other end of the first semiconductor device, and the second semiconductor device. A flying capacitor connected between the other end, a third connection point connected between a common connection point of the first semiconductor device and the flying capacitor, and a common connection point of the second semiconductor device and the flying capacitor. A fourth semiconductor device, and a common connection point of the third and fourth semiconductor devices as a second terminal,
    The first common unit includes a first basic cell in which the third terminal is connected to a positive terminal of the first DC link capacitor and the first terminal is connected to a negative terminal of the first DC link capacitor. The second basic cell having the third terminal connected to the positive terminal of the second DC link capacitor and the first terminal connected to the negative terminal of the second DC link capacitor;
    The second to Nth common parts have 2 × (2 2-1 ) to 2 × (2 N-1 ) basic cells, respectively, and the third terminals of the adjacent basic cells in each common part And 2 × (2 2-1 ) to 2 × (2 N-1 ) basic cells are connected in series to connect the first terminal of the first basic cell of the first common part. In the odd-numbered basic cells counted from the terminal side, the third terminal is connected to the second terminal of the basic cell in the previous stage, and the first terminal is connected to the first terminal of the basic cell in the previous stage. The even-numbered basic cells counted from the first terminal side of the first basic cell of the first common part are connected to the third terminal of the basic cell in the previous stage, The first terminal is connected to the second terminal of the basic cell;
    The phase module has the first to third terminals of the basic cell of the Nth common unit as input terminals, and each has a switching device between the input terminal and the output terminal, and selectively selects a switching device. A multi-level power conversion device that selects and outputs the potential of one of the input terminals by turning on and off.
  5. 　各相共通の第１直流リンクコンデンサと、
    　前記第１直流リンクコンデンサの正極端に負極端が接続された各相共通の第２直流リンクコンデンサと、
    　前記各相共通の第１，第２直流リンクコンデンサに接続され、基本セルを有する各相共通の第１～第Ｎ共通部（Ｎ＝２以上の整数）と、
    　前記第Ｎ共通部に接続されたＭ相（Ｍ＝２以上の整数）の相モジュールと、を備え、
    　前記基本セルは、第３端子に一端が接続された第１半導体デバイスと、第１端子に一端が接続された第２半導体デバイスと、前記第１半導体デバイスの他端と前記第２半導体デバイスの他端との間に接続されたフライングキャパシタと、前記第１半導体デバイスと前記フライングキャパシタの共通接続点と前記第２半導体デバイスと前記フライングキャパシタの共通接続点との間に接続された第３，第４半導体デバイスと、を備え、前記第３，第４半導体デバイスの共通接続点を第２端子とし、
    　前記第１共通部は、前記第１直流リンクコンデンサの正極端に前記第３端子が接続され、前記第１直流リンクコンデンサの負極端に前記第１端子が接続された第１の前記基本セルと、前記第２直流リンクコンデンサの正極端に前記第３端子が接続され、前記第２直流リンクコンデンサの負極端に前記第１端子が接続された第２の前記基本セルと、を有し、
    　前記第２～第Ｎ共通部は、それぞれ前記基本セルを２×（２2-1）～２×（２N-1）個有し、各共通部内の隣り合う前記基本セルの前記第３端子と前記第１端子とを接続して２×（２2-1）～２×（２N-1）個の基本セルを直列接続し、前記第１共通部の第１の基本セルの第１端子側から数えて奇数番目の前記基本セルは、前段の前記基本セルの前記第２端子に前記第３端子が接続され、前段の前記基本セルの前記第１端子に前記第１端子が接続され、前記第１共通部の第１の基本セルの第１端子側から数えて偶数番目の前記基本セルは、前段の前記基本セルの前記第３端子に前記第３端子が接続され、前段の前記基本セルの前記第２端子に前記第１端子が接続され、
    　前記相モジュールは、前記第Ｎ共通部の基本セルの前記第１～第３端子を入力端子とし、前記入力端子と出力端子との間にスイッチングデバイスとキャパシタを有し、前記スイッチングデバイスを選択的にＯＮ，ＯＦＦすることにより、前記入力端子のうち何れかの端子の電位、または、前記入力端子のうち何れかの端子の電位にキャパシタの電圧を加算または減算した電位を出力端子から出力するマルチレベル電力変換装置。     A first DC link capacitor common to each phase;
    A second DC link capacitor common to each phase, the negative electrode end of which is connected to the positive electrode end of the first DC link capacitor;
    First to Nth common parts (N = 2 or more integers) connected to the first and second DC link capacitors common to the respective phases and having basic cells and common to each phase;
    A phase module of M phase (an integer greater than or equal to M = 2) connected to the Nth common part,
    The basic cell includes a first semiconductor device having one end connected to a third terminal, a second semiconductor device having one end connected to the first terminal, the other end of the first semiconductor device, and the second semiconductor device. A flying capacitor connected between the other end, a third connection point connected between a common connection point of the first semiconductor device and the flying capacitor, and a common connection point of the second semiconductor device and the flying capacitor. A fourth semiconductor device, and a common connection point of the third and fourth semiconductor devices as a second terminal,
    The first common unit includes a first basic cell in which the third terminal is connected to a positive terminal of the first DC link capacitor and the first terminal is connected to a negative terminal of the first DC link capacitor. The second basic cell having the third terminal connected to the positive terminal of the second DC link capacitor and the first terminal connected to the negative terminal of the second DC link capacitor;
    The second to Nth common parts have 2 × (2 2-1 ) to 2 × (2 N-1 ) basic cells, respectively, and the third terminals of the adjacent basic cells in each common part And 2 × (2 2-1 ) to 2 × (2 N-1 ) basic cells are connected in series to connect the first terminal of the first basic cell of the first common part. In the odd-numbered basic cells counted from the terminal side, the third terminal is connected to the second terminal of the basic cell in the previous stage, and the first terminal is connected to the first terminal of the basic cell in the previous stage. The even-numbered basic cells counted from the first terminal side of the first basic cell of the first common part are connected to the third terminal of the basic cell in the previous stage, The first terminal is connected to the second terminal of the basic cell;
    The phase module includes the first to third terminals of the basic cell of the N-th common unit as input terminals, and includes a switching device and a capacitor between the input terminal and the output terminal, and selectively selects the switching device. The output terminal outputs a potential obtained by adding or subtracting the voltage of the capacitor to the potential of any one of the input terminals or the potential of any of the input terminals. Level power converter.
  6. 　前記直流リンクコンデンサの電圧を４Ｅに制御し、
    　第Ｊ共通部（Ｊ＝１～Ｎまでの整数）の前記フライングキャパシタの電圧をＥ／２J-1に制御する請求項４または５記載のマルチレベル電力変換装置。     Control the voltage of the DC link capacitor to 4E;
    6. The multilevel power conversion device according to claim 4, wherein the voltage of the flying capacitor in the J-th common portion (J = 1 to N) is controlled to E / 2 J−1 .
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JP2010519890A (en) * 2007-02-21 2010-06-03 アメリカン パワー コンバージョン コーポレイション Three-phase, high power uninterruptible power supply
WO2014208232A1 (en) * 2013-06-25 2014-12-31 株式会社明電舎 Multilevel power convertor
JP2015047056A (en) * 2013-08-02 2015-03-12 株式会社明電舎 Multilevel power conversion device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010519890A (en) * 2007-02-21 2010-06-03 アメリカン パワー コンバージョン コーポレイション Three-phase, high power uninterruptible power supply
WO2014208232A1 (en) * 2013-06-25 2014-12-31 株式会社明電舎 Multilevel power convertor
JP2015047056A (en) * 2013-08-02 2015-03-12 株式会社明電舎 Multilevel power conversion device

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