WO2018218621A1

WO2018218621A1 - Method and apparatus for bits number calculation and scrambling for cyclic redundancy check/parity distributed polar codes

Info

Publication number: WO2018218621A1
Application number: PCT/CN2017/086884
Authority: WO
Inventors: Dongyang DU; Keeth Saliya JAYASINGHE; Jingyuan Sun; Jie Chen; Yu Chen
Original assignee: Nokia Technologies Oy; Alcatel-Lucent Shanghai Bell Co., Ltd.
Priority date: 2017-06-01
Filing date: 2017-06-01
Publication date: 2018-12-06
Also published as: CN110741698B; CN110741698A

Abstract

An apparatus and method that performs the steps of calculating, by an entity, one or more assistance bits, and allocating, by the entity, the one or more assistance bits. The one or more assistance bits comprise one or more primary parts and one or more secondary parts, wherein the one or more primary parts and the one or more secondary parts are used for error correction and/or error detection.

Description

METHOD AND APPARATUS FOR BITS NUMBER CALCULATION AND SCRAMBLING FOR CYCLIC REDUNDANCY CHECK/PARITY DISTRIBUTED POLAR CODES

BACKGROUND： Field：

Certain embodiments may relate to communication systems， and， for example， some embodiments may relate to polar codes for control channels of a communication system.

Description of the Related Art：

In a communication system， such as a Long-Term Evolution (LTE) network， each instance of user equipment (UE) in the system may be identified by a unique identifier， such as a multi-level radio network temporary identifier (RNTI) . Cyclic redundancy check (CRC) and parity bits may be used for tree pruning when associated reliable bits are decoded by a successive cancellation list (SCL) decoder. The number of CRC and parity bits for performing error detection and correction may depend upon an information block size， a coded block size， and/or a mother polar codeword. When a CRC is applied at the end of an information block， any required CRC bits may depend upon the size of the SCL. However， CRC and parity bits may have differing error correction and error detection capabilities， and it may be difficult to determine the number of CRC bits.

SUMMARY：

In accordance with an embodiment， there is a method that comprises calculating， by an entity， one or more assistance bits. The method further comprises allocating， by the entity， the one or more assistance bits. The one or more assistance bits comprise one or more primary parts and one or more secondary parts， wherein the one or more primary parts and the one or more secondary parts are used for error correction and/or error detection.

In accordance with an embodiment， there is a method that comprises generating， by an entity， a first level of a multi-level radio network temporary identifier. The method further comprises generating， by the entity， a second level of the multi-level radio network temporary identifier. The method further comprises scrambling， by the entity， a plurality of primary parts of assistance bits with the first level of the multi-level radio network temporary identifier. The method further comprises scrambling， by the entity， a plurality of secondary parts of assistance bits with the second level of the multi-level radio network temporary identifier.

In accordance with an embodiment， there is a method that comprises a method， wherein the method comprises a bit reordering process. The method comprises the step of reordering a plurality of radio network temporary identifier bits， wherein a reordered radio network temporary identifier supports scrambling or descrambling.

In accordance with an embodiment， there is an apparatus comprising at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to， with the at least one processor， cause the apparatus to at least calculate one or more assistance bits. The at least one memory and the computer program code are further configured to， with the at least one processor， cause the apparatus to at least allocate the one or more assistance bits generate one or more error correction bits. The one or more assistance bits comprise one or more primary parts and one or more secondary parts， wherein the one or more primary parts and the one or more secondary parts are used for error correction and/or error detection.

In accordance with an embodiment， there is an apparatus comprising at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to， with the at least one processor， cause the apparatus to at least generate a first level of a multi-level radio network temporary identifier. The at least one memory and the computer program code are further configured to， with the at least one processor， cause the apparatus to at least generate a second level of the multi-level radio network temporary identifier. The at least one memory and the computer program code are further configured to， with the at least one processor， cause the apparatus to at least scramble a plurality of primary parts of assistance bits with the first level of the multi-level radio network temporary identifier. The at least one memory and the computer program code are further configured to， with the at least one processor， cause the apparatus to at least scramble a plurality of secondary parts of assistance bits used for error correction with the second level of the multi-level radio network temporary identifier.

In accordance with an embodiment， there is an apparatus comprising at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to， with the at least one processor， cause the apparatus to at least reorder a plurality of radio network temporary identifier bits， wherein a reordered radio network temporary identifier supports scrambling or descrambling.

In accordance with an embodiment， an apparatus can include means for calculating one or more assistance bits. The apparatus can further include means for allocating the one or more assistance bits. The one or more assistance bits comprise one or more primary parts and one or more secondary parts， wherein the one or more primary parts and the one or more secondary parts are used for error correction and/or error detection.

In accordance with an embodiment， an apparatus can include means for generating a first level of a multi-level radio network temporary identifier. The apparatus can further include means for generating a second level of the multi-level radio network temporary identifier. The apparatus can further include means for scrambling a plurality of primary parts of assistance bits with the first level of the multi-level radio network temporary identifier. The apparatus can further include means for scrambling a plurality of secondary parts of assistance bits with the second level of the multi-level radio network temporary identifier.

In accordance with an embodiment， an apparatus can include means for a bit reordering process. The apparatus can further include means for reordering a plurality of radio network temporary identifier bits， wherein a reordered radio network temporary identifier supports scrambling or descrambling.

A non-transitory computer readable medium can， in certain embodiments， be encoded with instructions that， when executed in hardware， perform a process. The process can include a method that comprises calculating， by an entity， one or more assistance bits. The method further comprises allocating， by the entity， the one or more assistance bits. The one or more assistance bits comprise one or more primary parts and one or more secondary parts， wherein the one or more primary parts and the one or more secondary parts are used for error correction and/or error detection

A non-transitory computer readable medium can， in certain embodiments， be encoded with instructions that， when executed in hardware， perform a process. The process can include a method that comprises generating， by an entity， a first level of a multi-level radio network temporary identifier. The method further comprises generating， by the entity， a second level of the multi-level radio network temporary identifier. The method further comprises scrambling， by the entity， a plurality of primary parts of assistance bits with the first level of the multi-level radio network temporary identifier. The method further comprises scrambling， by the entity， a plurality of secondary parts of assistance bits with the second level of the multi-level radio network temporary identifier.

A non-transitory computer readable medium can， in certain embodiments， be encoded with instructions that， when executed in hardware， perform a process. The process can include a method that comprises reordering a plurality of radio network temporary identifier bits， wherein a reordered radio network temporary identifier supports scrambling or descrambling.

A computer program product can， according to certain embodiments， encode instructions for performing a process. The process can include a method that comprises calculating， by an entity， one or more assistance bits. The method further comprises allocating， by the entity， the one or more assistance bits. The one or more assistance bits comprise one or more primary parts and one or more secondary parts， wherein the one or more primary parts and the one or more secondary parts are used for error correction and/or error detection

A computer program product can， according to certain embodiments， encode instructions for performing a process. The process can include a method that comprises generating， by an entity， a first level of a multi-level radio network temporary identifier. The method further comprises generating， by the entity， a second level of the multi-level radio network temporary identifier. The method further comprises scrambling， by the entity， a plurality of primary parts of assistance bits with the first level of the multi-level radio network temporary identifier. The method further comprises scrambling， by the entity， a plurality of secondary parts of assistance bits with the second level of the multi-level radio network temporary identifier.

A computer program product can， according to certain embodiments， encode instructions for performing a process. The process can include a method that comprises reordering a plurality of radio network temporary identifier bits， wherein a reordered radio network temporary identifier supports scrambling or descrambling.

BRIEF DESCRIPTION OF THE DRAWINGS：

For proper understanding of this disclosure， reference should be made to the accompanying drawings， wherein：

Figure 1 illustrates an example of a system according to certain embodiments.

Figure 2 illustrates an example of a method performed by a network entity according to certain embodiments.

Figure 3 illustrates an example of a method performed by a network entity according to certain embodiments.

Figure 4 illustrates an example of a method performed by a network entity according to certain embodiments.

DETAILED DESCRIPTION：

The features， structures， or characteristics of certain embodiments described throughout this specification may be combined in any suitable manner in one or more embodiments. For example， the usage of the phrases “certain embodiments， ” “some embodiments， ” “other embodiments， ” or other similar language， throughout this specification refers to the fact that a particular feature， structure， or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. Thus， appearance of the phrases “in certain embodiments， ” “in some embodiments， ” “in other embodiments， ” or other similar language， throughout this specification does not necessarily refer to the same group of embodiments， and the described features， structures， or characteristics may be combined in any suitable manner in one or more embodiments.

During the construction of polar codes， a cyclic redundancy check (CRC) and early termination function may impact the RNTI that identifies UE. A CRC may be used for error detection and/or error correction.

In some embodiments， a CRC that is used for error detection may include a number of J bits， denoted by F_d. J bits may be fixed for any SCL decoding size， information block size K， coded block size M， and/or mother polar codeword N. J bits may be adjusted when used in conjunction with J’ bits. For polar code constructions that use J bits in CRC for error detection， the length of the CRC may be fixed and a conventional RNTI may be scrambled on the CRC.

In some embodiments， a CRC that is used for error correction may include a number of J’ bits， denoted by F_p. J’ bits may depend on various parameters， such as overhead R， information block size K， coded block size M， and/or a mother polar codeword N. J’ bits may also be used for error detection. For polar code constructions that use J’ bits in CRC for error correction， the length of the CRC may vary for a conventional RNTI.

It is desirable for a particular UE to terminate the decoding of an information block that belongs to different UE as soon as possible. In order to enable UE to decode received information blocks and perform early termination， if needed， scrambling may be performed on the CRC and/or parity bits that are used for tree pruning purposes. This may be accomplished by determining the length of J bits and J’ bits to scramble for the RNTI of a particular UE， as well as differentiating the beginning of RNTI among various UE.

Certain embodiments may have various benefits and/or advantages. For example， certain embodiments may enhance the performance of distributed CRC and/or the performance of an early termination process. Thus， certain embodiments are directed to improvements in computer-related technology on a transmitter side and/or receiver side. Furthermore， certain embodiments are directed to improvements in computer-related technology， such as efficient implementation of taking， interleaving， and reversing through the use of computer-implemented rules. Furthermore， certain embodiments are directed to additional improvements in computer-related technology， such as an improved block error ratio (BLER) performance and an improved false alarm rate (FAR) performance.

CALCULATION OF NUMBER OF J BITS AND NUMBER OF J’ BITS

J’ bits may be allocated in frozen bit positions with predetermined values and/or reliable bit positions. J and J’ bits may be calculated using an equation， where the equation may depend upon whether the J’ bits are allocated in both frozen bit positions and reliable bit positions， or are allocated in only reliable bit positions.

In an embodiment， J’ bits may be generated from both frozen and reliable bit positions， and all or some of the J’ bits may be later used for tree pruning. There may be no overhead if J’ bits are allocated in frozen bit positions. The number of J’ bits， F_p， and the number of J bits， F_d，may be calculated according to：

F_p ＝ min {ceil (α ＊Iog2 [min (M， N) ] ＊ [1.25 - ( (K/min (M， N) ) - (1/2) ) ²] ) ， R + min (M， N) -K -I} ，

F_d ＝ min [ceil (R - (F_p ＊b) ) ， S] ，

wherein：

F_p is the number of J’ bits，

F_d is the number of J bits，

α is a parameter which may be used to adjust F_p，

M is the bits number after rate matching，

N is the bits number of mother polar code，

K is the length of the information block，

R is the overall fixed overhead of reliable bits，

I is the restriction for polarization，

b is the ratio of the number of bits in reliable bits to the number of J’ bits，

β is the parameter to adjust the number of J’ bits which allocate into reliable bit positions，

is the parameter for overall overhead that should be limited， and

S is the fixed overhead for J bits.

In some embodiments， I may be a positive integer since all frozen bits and overhead on reliable bits may be occupied by CRC， resulting in no polarization of the codes. In some embodiments， some J’ bits may be used for error detection when F_d is less than S in order to improve error detection performance.

In some embodiments， the number of CRC bits used for error correction may depend upon an information block size， a code block size， and/or a mother codeword length. In some embodiments， CRC bits that are used for error correction may be allocated to frozen and non-frozen positions.

In some embodiments， a minimum number of frozen bit positions may be guaranteed when used to support various code rates and information sizes. In some embodiments， the number of J bits may be reduced when the J’ bits also provide error detection capabilities while continuing to improve a level of error detection capability.

In some embodiments， a total number of J’ bits (F_p) and J bits (F_d) may not exceed the total length of maximum overhead in information position， U， and/or the number of frozen bits， E.

In some embodiments， some or all J’ bits may be allocated among frozen bit positions and reliable bit positions for error correction and error detection purposes. Parameter b may be adjusted according to parameter R. For example， as R increases， more bits may be allocated into reliable bit positions， while the maximum number may be restricted by U.

In some embodiments， F_d may be fixed to S. For example， S may be decreased when the number of J’ bits allocated into reliable bit positions increases but U remains constant. In some embodiments， the number of J’ bits C in frozen bit positions may use error detection， and may cause the S bits to be used for error detection. In some embodiments， when U is not restricted， F_d may be decreased by increasing C to compensate for a decrease in U.

In some embodiments， the number of CRC bits used for error correction may vary depending on an information block size， a code block size， and/or a mother codeword length. In some embodiments， some CRC bits used for error correction may be distributed among non-frozen locations.

In some embodiments， a part of the error correcting CRC bits may be used for error detection， and may result in a reduction in the number of error detecting CRC bits.

In another embodiment， J’ bits may be generated from only reliable bits. In this embodiment， the number of bits that may be later used for tree pruning may be part of the J’ bits and/or may be used for error detection. Bits numbers not used for later tree pruning may be used for error detection， and/or may be allocated at frozen bit positions. There may be overhead for J if J’ bits are allocated in reliable bit positions. The error correction portion of J’ may be overhead of J since this may be in reliable bit positions. The number of J’ bits and number of J bits may be calculated according to：

F_p ＝ min {ceil (α ＊Iog2 [min (M， N) ] ＊ [1.25 - ( (K/min (M， N) ) - (1/2) ) ²] ) ， R + min (M， N) -K -1} ，

b ＝ min (L， (R/F_P)) ， and

F_d ＝ min [ceil (R - (F_p ＊b) ) ， S] ， wherein：

F_p is the number of J’ bits，

F_d is the number of J bits，

α is a parameter which may be used to adjust F_p，

M is the bits number after rate matching，

N is the bits number of mother polar code，

K is the length of the information block，

R is the overall fixed overhead on reliable bits，

I is the restriction for polarization， and may be a positive integer，

L is the ratio of number of bits that may be used for pruning the total J’ bits，

b is the ratio of the number of bits in reliable bits to the number of J’ bits， and

S is the fixed overhead number of J bits.

In some embodiments， L may be a fixed ratio in relation to b. In some embodiments， a subset of J’ bits may be distributed and used for error correction. In some embodiments， the value of L may vary depending on a polynomial of CRC. In some embodiments， the rate K/min (M， N) may provide the rate of polar encoding.

In some embodiments， the value R may correspond to a mother coding rate. The mother coding rate may be based upon an information bit length K， a transmit block size M， and/or a mother polar encoding length N. A mother coding rate may be defined without assuming repetition needed from a polar encoding length.

In some embodiments， a total number of dedicated J’ bits (F_p) and J bits (F_d) should not exceed the total length of maximum overhead in information position， U， and the number of frozen bits， E. In some embodiments， F_d may not exceed a fixed overhead number of J bits， S.In some embodiments， S may not exceed U. In some embodiments， I may be used to avoid at least some frozen bit positions that are occupied by CRC bits.

In some embodiments， F_p may be a variant of a code rate， R_c. R_c may be a variable of M and K. In some embodiments， F_p may increase when R_c increases from 0， may reach a maximum value at a certain value of R_c， and/or may decrease due to overhead and restrictions. In some embodiments， the relationship between the value of F_pand the value of R_c may be defined as a convex function.

In some embodiments， F_p may be related to an effect encoding length. In some embodiments， an effect encoding length may be a length of encoding without repetition length and/or puncturing/shortening length. For example， F_p may increase if the effect coding length increases.

RNTI DESIGN AND SCRAMBLING OF J’ BITS AND J BITS IN CRC

F_p and F_d may be calculated based on the techniques described above. Using F_p and F_d，two levels of RNTI with corresponding lengths of F_p and F_d for J’ bits and J bits， respectively， may be scrambled.

A first level RNTI with length F_d， which may be defined as X_rnti-1， 0， X_rnti-1， 1， ...， X_{rnti-1， Fd-1}， may be scrambled on J bits. This first level RNTI with length F_d may be calculated according to：

c_k ^J ＝ (b_k ^J + x_rnti-1， k) mod2 for k ＝ 0， ...， F_d -1，

wherein b^J is the CRC bit sequence for J， and c^J is the bit sequence after scrambling J.

A second level RNTI with length F_p， which may be defined as X_rnti-2， 0， X_rnti-2， 1， ...， X_{rnti-2， Fp-1}， may be scrambled on J’ bits. This second level RNTI may be calculated according to：

c_k ^J’ ＝ (b_k ^J’ + x_rnti-2， k) mod2 for k ＝ 0， ...， F_p-1

wherein b^J’ is the CRC bit sequence for J’ ， and c^J’ is the bit sequence after scrambling J’ .

In an embodiment， a conventional single RNTI x_rnti may be used to generate x_rnti-1 and x_rnti-2 with a bits taking method. For example， if x_rnti has 16 bits， x_rnti-1 and x_rnti-2 may be generated by removing bits from the right side of the sequence， the left side of the sequence， the most significant position， and/or the least significant position in x_rnti until the F_p and/or F_d are reached. In another example， if x_rnti has 16 bits， x_rnti-1 and x_rnti-2 may be generated by removing even and/or odd numbered bits in x_rnti until the F_p and/or F_d are reached.

In an embodiment， a long lookup sequence may be used to generate x_rnti-1 and x_rnti-2. For example， a lookup sequence may be stored offline， with 0 and/or 1 bits stored. Two levels of RNTI may be generated for a UE by removing bits from the sequence from a starting point. In some embodiments， the starting point may be different by using a bits shift number， and the bits shift number may vary between different UE. For example， using a 2000 bit lookup sequence， two levels of RNTI may be generated for a UE with 4 bits， while a 100 bits shift may be used to generate two levels of RNTI for other UE.

In some embodiments， a second RNTI may be generated based upon a first RNTI as a LTE RNTI. In some embodiments， prior to scrambling RNTI on a CRC sequence， a bits reordering process may be used to reallocate bits in x_rnti-1 and x_rnti-2； this may enhance the performance of early termination by avoiding multiple UE having the same bits sequence at the beginning of RNTI.

In some embodiments， an interleaver may be used to distribute bits in RNTI. An interleaver may uniformly re-distribute bits in an RNTI. For example， if the difference between the RNTI of a first UE and the RNTI of a second UE is located in a particular side or portion of the RNTI， an interleaver may uniformly distribute the differences across portions of and/or the entire RNTI block. If the decoding process is applied from a most significant position to a least significant position， the interleaver may enhance the performance of early termination by separating the two RNTI early in a decoding process.

In some embodiments， a bits reverse process may be used to distribute bits in RNTI. In a bit reverse process， bits may be converted from a least-important part to a most-important part. For example， where the difference between a first UE RNTI and a second UE RNTI are located in a least-important part， a simple bits reverse process may reverse these differences into most-important parts. If a decoding process is applied from most-important parts of the two RNTIs， it may enhance the performance of early termination.

In some embodiments， a lookup sequence， such as the lookup sequence described above to generate x_rnti-1 and x_rnti-2， may be used to distribute bits in a RNTI. A lookup sequence that distributes 0 and 1 bits uniformly may generate two levels of RNTI that are differentiated as much as possible and/or different bits positions may be uniform. For example， a single long lookup sequence may be designed to separate a sequence into two corresponding parts， and then place 0 bits and 1 bits into these two parts using a rule. For example， a rule may require that each corresponding bit position be different， which may generate RNTIs that contain every single bit different， which may benefit the early termination process.

In an embodiment， another RNTI and/or previous information bits may be used to scramble CRC bits. For example， where the RNTIs of different UE have the same beginning bits sequence， the sequences may adjusted by scrambling with information bits and/or another RNTI since these values are different for each UE. This may be scrambled using：

c_k ^J ＝ (b_k ^J + t_n + x_rnti-1， k) mod2 for k ＝ 0， ...， F_d -1 and n ＝ 0， ...T，

wherein t is the information bit sequence， b^J is the CRC bit sequence for J， and c^J is the bit sequence after scrambling J. In some embodiments， for a second RNTI which is x_rnti-2， T may be equal to F_p.

After scrambling and creation of the RNTI， UE and/or a base station (BS) may transmit the RNTI. For example， in a 5G control channel， a RNTI may be scrambled on a CRC， and then transmitted with information bits. A UE registration procedure may assign a RNTI for a specific UE.

Figure 1 illustrates a system according to certain embodiments. In one embodiment， a system may include multiple devices， such as， for example， network entity 110. Network entity 110 may include one or more user equipment. A network entity may also include a next generation radio access network， mobility management entity， serving gateway， base station， such as an evolved node B， a server， and/or other access node.

One or more of these devices may include at least one processor， respectively indicated as 111. At least one memory may be provided in one or more of devices indicated at 112. The memory may be fixed or removable. The memory may include computer program instructions or computer code contained therein. Processor 111 and memory 112， or a subset thereof， may be configured to provide means corresponding to the various blocks of Figure 2. Although not shown， the devices may also include positioning hardware， such as global positioning system (GPS) or micro electrical mechanical system (MEMS) hardware， which may be used to determine a location of the device. Other sensors are also permitted and may be included to determine location， elevation， orientation， and so forth， such as barometers， compasses， and the like.

As shown in Figure 1， transceiver 113 may be provided， and one or more devices may also include at least one antenna， respectively illustrated as 114. The device may have many antennas， such as an array of antennas configured for multiple input multiple output (MIMO) communications， or multiple antennas for multiple radio access technologies. Other configurations of these devices， for example， may be provided.

Transceiver 113 may be a transmitter， a receiver， or both a transmitter and a receiver， or a unit or device that may be configured both for transmission and reception.

Processor 111 may be embodied by any computational or data processing device， such as a central processing unit (CPU) ， application specific integrated circuit (ASIC) ， or comparable device. The processors may be implemented as a single controller， or a plurality of controllers or processors.

Memory 112 may independently be any suitable storage device， such as a non-transitory computer-readable medium. A hard disk drive (HDD) ， random access memory (RAM) ， flash memory， or other suitable memory may be used. The memories may be combined on a single integrated circuit as the processor， or may be separate from the one or more processors. Furthermore， the computer program instructions stored in the memory and which may be processed by the processors may be any suitable form of computer program code， for example， a compiled or interpreted computer program written in any suitable programming language.

The memory and the computer program instructions may be configured， with the processor for the particular device， to cause a hardware apparatus such as user equipment to perform any of the processes described below (see， for example， Figure 2) . Therefore， in certain embodiments， a non-transitory computer-readable medium may be encoded with computer instructions that， when executed in hardware， perform a process such as one of the processes described herein. Alternatively， certain embodiments may be performed entirely in hardware.

Figure 2 illustrates an example method of a network entity calculating J bits and J’ bits and scrambling a RNTI. In step 201， a network entity 110 may calculate one or more assistant bits. Assistant bits may include a number of J’ bits used for error correction， F_p. J’ bits may be allocated in both frozen and reliable bit positions， and all or some of the J’ bits may be used for tree pruning. There may be no overhead if J’ bits are allocated in frozen bit positions. The number of J’ bits， F_p， may be calculated according to：

wherein

F_p is the number of J’ bits，

α is a parameter which may be used to adjust F_p，

M is the bits number after rate matching，

N is the bits number of mother polar code，

K is the length of the information block，

R is the overall fixed overhead of reliable bits， and

I is the restriction for polarization.

In some embodiments， I may be a positive integer since all frozen bits and overhead on reliable bits may be occupied by CRC， resulting in no polarization of the codes. In some embodiments， some or all J’ bits may be allocated among frozen bit positions and reliable bit positions for error correction and error detection purposes.

In some embodiments， a minimum number of frozen bit positions may be used to support various code rates and information sizes. In some embodiments， the number of J bits may be reduced when the J’ bits also provide error detection capabilities while continuing to improve a level of error detection capability.

Network entity 110 may calculate a ratio of the number of bits in reliable bits to the number of J’ bits. Where J’ bits are allocated in both frozen and reliable bit positions， the ratio may be calculated as：

β is the parameter to adjust the number of J’ bits which allocate into reliable bit positions， and

is the parameter for overall overhead that should be limited.

Where J’ bits are generated from only reliable bits， the ratio may be calculated as：

b ＝ min (L， (R/F_P) ) ， wherein

R is the overall fixed overhead on reliable bits， and

L is the ratio of number of bits that may be used for pruning the total J’ bits.

Parameter b may be adjusted according to parameter R. For example， as R increases， more bits may be allocated into reliable bit positions， while the maximum number may be restricted by U.

Network entity 110 may calculate a number of J bits used for error detection， F_d. The number of J bits， F_d， may be calculated according to：

F_d ＝ min [ceil (R - (F_p ＊b) ) ， S] ， wherein

F_d is the number of J bits，

R is the overall fixed overhead of reliable bits，

F_p is the number of J’ bits，

S is the fixed overhead for J bits.

In step 203， network entity 110 may allocate the one or more assistant bits. A first level RNTI with length F_d， which may be defined as X_rnti-1， 0， X_rnti-1， 1， ...， X_{rnti-1， Fd-1}， may be scrambled on J bits. This first level RNTI with length F_d may be calculated according to：

c_k ^J ＝ (b_k ^J + x_rnti-1， k) mod2 for k ＝ 0， ...， F_d-1，

Network entity 110 may scramble a second level RNTI. A second level RNTI with length F_p， which may be defined as X_rnti-2， 0， X_rnti-2， 1， ...， X_{rnti-2， Fp-1}， may be scrambled on J’ bits. This second level RNTI may be calculated according to：

c_k ^J’ ＝ (b_k ^J’ + x_rnti-2， k) mod2 for k ＝ 0， ...， F_p-1

A conventional single RNTI x_rnti may be used to generate x_rnti-1 and x_rnti-2 with a bits taking method. For example， if x_rnti has 16 bits， x_rnti-1 and x_rnti-2 may be generated by removing bits from a most-important or least-important position in x_rnti until the F_p and/or F_d are reached. In another example， if x_rnti has 16 bits， x_rnti-1 and x_rnti-2 may be generated by removing even and/or odd numbered bits in x_rnti until the F_p and/or F_d are reached.

A long lookup sequence may be used to generate x_rnti-1 and x_rnti-2. For example， a lookup sequence may be stored offline， with 0 and/or 1 bits stored. Two levels of RNTI may be generated for a UE by removing bits from the sequence from a starting point. In some embodiments， the starting point may be different by using a bits shift number， and the bits shift number may vary between different UE. For example， using a 2000 bit lookup sequence， two levels of RNTI may be generated for a UE with 4 bits， while a 100 bits shift may be used to generate two levels of RNTI for other UE.

A second level RNTI may be generated based upon a first level RNTI as a LTE RNTI. In some embodiments， prior to scrambling RNTI on a CRC sequence， a bits reordering process may be used to reallocate bits in x_rnti-1 and x_rnti-2； this may enhance the performance of early termination by avoiding multiple UE having the same bits sequence at the beginning of RNTI.

An interleaver may be used to distribute bits in RNTI. In some embodiments， an interleaver may re-distribute bits of RNTI， and the difference between two UE’s RNTI may also re-distributed.

A bits reverse process may be used to distribute bits in RNTI. In some embodiments， if the difference between two UE’s RNTI are located at least significant positions， then the bit reverse process could re-allocate these differences at most significant positions， improving the performance of early termination if the decoding is applied from most significant position to least significant position.

A lookup sequence， such as the lookup sequence described above to generate x_rnti-1 and x_rnti-2， may be used to distribute bits in a RNTI. A lookup sequence that distributes 0 and 1 bits uniformly may generate two levels of RNTI that are differentiated as much as possible and/or different bits positions may be uniform.

Another RNTI and/or previous information bits may be used to scramble CRC bits. For example， where the RNTIs of different UE have the same beginning bits sequence， the sequences may adjusted by scrambling with information bits and/or another RNTI since these values are different for each UE. This may be scrambled using：

Network entity 110 may perform tree pruning based upon at least one or more of the one or more correction bits.

After calculating the number of J bits and J’ bits and scrambling the RNTI， network entity 110， such as a UE or BS， may transmit the RNTI.

Figure 3 illustrates an example method of a network entity generating a RNTI and scrambling assistance bits onto the RNTI. In step 301， network entity 110 may generate a first level of a multi-level radio network temporary identifier. In step 303， network entity 110 may generate a second level of a multi-level radio network temporary identifier. In step 305， network entity 110 may scramble a plurality of assistance bits used for error detection with the first level of the multi-level radio network temporary identifier. In step 307， network entity 110 may scramble a plurality of assistance bits used for error correction with the second level of the multi-level radio network temporary identifier.

Figure 4 illustrates an example method of reallocating assistance bits in a RNTI. In step 401， network entity 110 may reorder a plurality of radio network temporary identifier bits， wherein a reordered radio network temporary identifier supports scrambling or descrambling.

One having ordinary skill in the art will readily understand that certain embodiments discussed above may be practiced with steps in a different order， and/or with hardware elements in configurations which are different than those which are disclosed. Therefore， it would be apparent to those of skill in the art that certain modifications， variations， and alternative constructions would be apparent， while remaining within the spirit and scope of the invention. In order to determine the metes and bounds of the invention， therefore， reference should be made to the appended claims.

Partial Glossary

3GPP 3rd Generation Partnership Project

BLER Block Error Ratio

CRC Cyclic Redundancy CheckeMBB enhanced Mobile Broadband

FAR False Alarm Rate

LTE Long-Term Evolution

RNTI Radio Network Temporary Identifier

SCLSuccessive Cancellation List

UE User Equipment

Claims

A method， comprising：

calculating， by an entity， one or more assistance bits； and

allocating， by the entity， the one or more assistance bits，

wherein the one or more assistance bits comprise one or more primary parts and one or more secondary parts， wherein the one or more primary parts and the one or more secondary parts are used for error correction and/or error detection.
The method of claim 1， wherein a coding rate is calculated based upon an information bit length， a transmit block size， and/or a coding length.
The method of claim 1， wherein the sum of the number of assistance bits and the number of primary parts and secondary parts is less than the total length of a maximum overhead in information positions and a number of frozen bits.
The method of claim 1， wherein an offset value prevents all frozen bit positions from being occupied.
The method of claim 1， wherein the number of primary parts and secondary parts should not exceed a fixed overhead of assistance bits used for error correction and assistance bits used for error detection.
The method of claim 5， wherein the fixed overhead of primary parts and secondary parts is less than the total length of maximum overhead in information positions.
The method according to claim 1， wherein the total number of secondary parts increases as a code rate increases from 0， achieves a maximum value at a specified value of the code rate， and decreases with overhead and/or restrictions.
The method according to claim 1， wherein the total number of secondary parts is related to an effect coding length， wherein the effect coding length is related to a non-repetition length and puncturing/shortening length.
The method according to claim 1， wherein the total number of secondary parts increases as the effect coding length increases.
The method according to claim 1， wherein each secondary part is distributed and allocated into frozen bit positions and reliable bit positions.
The method according to claim 1， wherein a ratio of the number of bits in reliable bit positions to the number of secondary parts is adjusted by an overall fixed overhead on reliable bit positions.
The method according to claim 11， wherein as the overall fixed overhead on reliable bit positions increases， the number of bits that may be allocated into reliable bit positions increases， up to a maximum value.
The method according to claim 1， wherein at least one secondary part is distributed and used for error correction.
The method according to claim 1， wherein the ratio of the number of bits that may be used for pruning to the total number of secondary parts has a fixed ratio of the number of bits in reliable bit positions to the total number of secondary parts.
The method according to claim 1， wherein the number of primary parts is related to the number of fixed overhead of assistance bits used for error detection.
A method， comprising：

generating， by an entity， a first level of a multi-level radio network temporary identifier；

generating， by the entity， a second level of the multi-level radio network temporary identifier；

scrambling， by the entity， a plurality of primary parts of assistance bits with the first level of the multi-level radio network temporary identifier； and

scrambling， by the entity， a plurality of secondary parts of assistance bits with the second level of the multi-level radio network temporary identifier.
The method according to claim 16， wherein the multi-level radio network temporary identifier has at least two levels.
The method according to claim 16， wherein the multi-level radio network temporary identifier has at least two levels of radio network temporary identifiers.
The method according to claim 16， wherein the levels of the multi-level radio network temporary identifier are generated by selecting bits from a long designing sequence or one or more conventional radio network temporary identifiers， wherein the length is longer than the radio network temporary identifier.
A method， the method comprising a bit reordering process comprising the step of：

reordering a plurality of radio network temporary identifier bits， wherein a reordered radio network temporary identifier supports scrambling and/or descrambling.
The method according to claim 20， wherein the bit reordering process comprises one or more of：

an interleaver process which re-distributes bits throughout a radio network temporary identifier；

a bits reverse process which flips bits of the radio network temporary identifier；

a bits selection process from a designed sequence； or

an additional scrambling process that scrambles the radio network temporary identifier with another radio network temporary identifier and/or information bits.
An apparatus， comprising：

at least one processor； and

at least one memory including computer program code，

wherein the at least one memory and the computer program code are configured to， with the at least one processor， cause the apparatus to at least：

calculate one or more assistance bits； and

allocate the one or more assistance bits，

wherein the one or more assistance bits comprise one or more primary parts and one or more secondary parts， wherein the one or more primary parts and the one or more secondary parts are used for error correction and/or error detection.
An apparatus， comprising：

at least one processor； and

at least one memory including computer program code，

wherein the at least one memory and the computer program code are configured to， with the at least one processor， cause the apparatus to at least：

generate a first level of a multi-level radio network temporary identifier；

generate a second level of the multi-level radio network temporary identifier；

scramble a plurality of primary parts of assistance bits with the first level of the multi-level radio network temporary identifier； and

scramble a plurality of secondary parts of assistance bits with the second level of the multi-level radio network temporary identifier.
An apparatus， comprising：

at least one processor； and

at least one memory including computer program code，

wherein the at least one memory and the computer program code are configured to， with the at least one processor， cause the apparatus to at least：

reorder a plurality of radio network temporary identifier bits， wherein a reordered radio network temporary identifier supports scrambling or descrambling.
A non-transitory computer-readable medium encoding instructions that， when executed in hardware， perform a process comprising：

calculating， by an entity， one or more assistance bits； and

allocating， by the entity， the one or more assistance bits，

wherein the one or more assistance bits comprise one or more primary parts and one or more secondary parts， wherein the one or more primary parts and the one or more secondary parts are used for error correction and/or error detection.
A non-transitory computer-readable medium encoding instructions that， when executed in hardware， perform a process comprising：

generating， by an entity， a first level of a multi-level radio network temporary identifier；

generating， by the entity， a second level of the multi-level radio network temporary identifier；

scrambling， by the entity， a plurality of primary parts of assistance bits with the first level of the multi-level radio network temporary identifier； and

scrambling， by the entity， a plurality of secondary parts of assistance bits with the second level of the multi-level radio network temporary identifier.
A non-transitory computer-readable medium encoding instructions that， when executed in hardware， perform a process comprising：

reorder a plurality of radio network temporary identifier bits， wherein a reordered radio network temporary identifier supports scrambling or descrambling.