WO2018216081A1 - Semiconductor storage system - Google Patents

Abstract

A memory controller (3) is provided with: an SDRAM interface (21) connected to a memory (5); a control circuit (11) which controls the memory (5) by transmitting a plurality of commands to the memory (5) through the SDRAM interface (21); and a timing register (13) in which a plurality of timing parameters related to the operation of the memory (5) are stored. The timing parameters include a first time period (tRCD(W)) and a second time period (tRCD(R)) which indicate time differences between when an activation command is issued and when it becomes possible to issue a write command and a read command, respectively. The first time period (tRCD(W)) is shorter than the second time period (tRCD(R)). When writing data to the memory (5), the control circuit (11) issues a write command after a moment following the elapse of the time period (tRCD(W)) with reference to the moment of issuance of the activation command.

Description

Semiconductor memory system

The present invention relates to a DDRx-SDRAM or LPDDRx-SDRAM semiconductor memory device and control device, and further to a semiconductor memory system including these. The present invention also relates to a control method for such a semiconductor memory device.

In this specification, DDRx-SDRAM indicates DDR-SDRAM (Double Data Rate Synchronous Dynamic Random-Access Memory), DDR2-SDRAM, DDR3-SDRAM, DDR4-SDRAM, and their derived standards and successor standards. In this specification, LPDDRx-SDRAM indicates LPDDR-SDRAM (Low Power DDR-SDRAM), LPDDR2-SDRAM, LPDDR3-SDRAM, LPDDR4-SDRAM, and their derived standards and successor standards.

A memory system including a memory such as a DRAM and a memory controller is used as an external primary storage device for a processor such as a computer (see, for example, Patent Document 1). DDRx-SDRAM and LPDDRx-SDRAM are known as DRAMs capable of high-speed access. The memory of the DDRx-SDRAM and the LPDDRx-SDRAM includes one or a plurality of banks in its internal memory space, and data writing and reading access can be performed independently for each bank. Each bank includes a group of memory cells arranged two-dimensionally along a plurality of rows and a plurality of columns orthogonal to each other.

The memory and the memory controller are connected to each other via a bus including a plurality of signal lines (hereinafter referred to as “memory bus”). The memory controller communicates with the memory via the memory bus, thereby writing data to the memory or reading data from the memory. The memory bus has a signal line for transmitting a clock, a plurality of signal lines (command bus) for transmitting a command, a plurality of signal lines (address bus) for transmitting an address, and a data line for transmitting data A plurality of signal lines (external data bus) are included.

∙ By sending a clock from the memory controller to the memory, the memory and memory controller are synchronized with each other.

The memory controller issues an activate (ACT) command, a write (WRITE) command, a read (READ) command, and a precharge (PRE) command in synchronization with the clock, and these commands are transmitted via the command bus. Send command to memory. The activation command activates a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via a bit line. The write command instructs writing of data to a memory cell having a certain bank address and a certain column address. The read command instructs reading of data from a memory cell having a certain bank address and a certain column address. The precharge command deactivates the bank including the word line and the sense amplifier activated by the activation command.

The memory controller designates the address for writing and reading access to the memory via the address bus in synchronization with the clock. Each signal line of the address bus is assigned to a bank address and a row address or a column address.

The memory controller performs data write and read access to the memory via the data bus in synchronization with the clock.

The memory controller sends a command, a bank address, a row address, and a column address to the memory, thereby enabling write and read access to the memory cell at the target access position.

More specifically, the memory controller sends an activation command, a bank address, and a row address to the memory in synchronization with the clock, so that the memory selects a word line corresponding to the row address of the target bank, Information on the memory cell group connected to the selected word line is stored in the corresponding page latch group. The stored data is called “page data”. Further, as described above, the operation of storing the page data of the selected row address of the target bank in the page latch group by the activation command is referred to as “bank activation”.

By issuing a write command or read command to the bank activated bank, a data write operation or read operation is performed on the memory. In a read operation, the memory controller sends a read command and the bank address and column address of the activated bank to the memory, so that part of the page data selected by the column address of the target bank is stored in the memory. Is read out to the outside. In the write operation, the memory controller sends a write command, the bank address and column address of the activated bank, and the write data to the memory, so that the memory corresponds to the page corresponding to the column address of the target bank. Part of the data is rewritten to write data sent from the outside of the memory.

Subsequently, when the memory controller sends a precharge command and a bank address to the memory, the page data of the activated bank is rewritten to the memory cell group connected to the selected word line, and the selected memory cell group is selected. The word line is deactivated.

The above-described series of activation command, read command, write command, and precharge command operations complete the write / read access to the memory.

The memory controller selects a target bank from a plurality of banks by sending a bank address to the memory together with the activation command, the write command, the read command, and the precharge command. Controls writing and reading.

By activating multiple banks and issuing multiple write commands to write data to these banks continuously, data can be written continuously without interruption, and the external data bus must be used almost 100% effectively Can do. Similarly, when multiple banks are activated and multiple read commands for reading data from these banks are issued continuously, the data can be read continuously without interruption, and the external data bus is used almost 100% effectively. can do.

Special table 2009-526323

However, more random access may be required depending on the application. In this specification, “random access” indicates a case where data is written and / or read by a command sequence including a precharge command. In this command sequence, a bank is activated by an activation command, page data is accessed by one or a small number of write commands and / or read commands, and then the bank is deactivated by a precharge command. Including. When such a random access operation is repeated, data cannot be written to or read from the memory without interruption, and the use efficiency of the external data bus decreases. In particular, when writing and / or reading access to page data of different row addresses in the same bank is repeated, it is necessary to issue an activation command and a precharge command for each access, and the use efficiency of the external data bus is further increased. The problem of deteriorating arises.

In a memory system using the current general-purpose DDRx-SDRAM or LPDDRx-SDRAM timing parameters compliant with the JEDEC standard, when random write and / or read access is performed, the use efficiency of the external data bus of the memory system is the operation clock. There is a problem that it decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that hardly reduces the use efficiency of an external data bus even when data is written to and / or read from one or more banks by a command sequence including a precharge command. It is another object of the present invention to provide a control device and a semiconductor memory system including them. Another object of the present invention is to provide a control method for such a semiconductor memory device.

According to the control device of the first aspect of the present invention,
A control device for a semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
The semiconductor memory device includes at least one bank connected to at least one internal data bus, and the bank includes a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to each other. A memory array including a plurality of sense amplifiers respectively connected to the plurality of bit lines, and a plurality of column selection lines respectively connected to the plurality of sense amplifiers;
The control device includes a communication circuit connected to the semiconductor memory device, a control circuit that controls the semiconductor memory device by issuing a plurality of commands and transmitting the command to the semiconductor memory device via the communication circuit; A timing register for storing a plurality of timing parameters related to the operation of the semiconductor memory device;
The plurality of commands are:
An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
The plurality of timing parameters include a first time period (tRCD (W)) indicating a time difference from when the activation command is issued until the write command can be issued, and after the activation command is issued. A second time period (tRCD (R)) indicating a time difference until the read command can be issued, wherein the first time period has a smaller value than the second time period;
The control circuit includes:
When writing data to the semiconductor memory device, issue the write command after the moment separated by the first time period (tRCD (W)) with reference to the moment when the activation command is issued,
When reading data from the semiconductor memory device, the read command is issued after the moment separated by the second time period (tRCD (R)) with reference to the moment when the activation command is issued.

According to the control device according to the second aspect of the present invention, in the control device according to the first aspect,
The first time period (tRCD (W)) has a negative value;
When writing data to the semiconductor memory device, the control circuit starts from the moment preceding by a time period equal to the absolute value of the first time period (tRCD (W)) with reference to the moment when the activation command is issued. In addition, the write command is issued before the moment of issuing the activation command.

According to the control device according to the third aspect of the present invention, in the control device according to the second aspect,
When writing data to the semiconductor memory device, the control circuit transmits a first control signal notifying that the write command is issued before the activation command to the semiconductor memory device.

According to the control device of the fourth aspect of the present invention, in the control device according to one of the first to third aspects,
The bank includes a plurality of subarrays separated from each other by at least one sense amplifier row including a plurality of sense amplifiers,
The write command includes a part of a row address of a subarray including a storage cell to which data is written.

According to the control device of the fifth aspect of the present invention,
A control device for a semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
The semiconductor memory device includes at least one bank connected to at least one internal data bus, and the bank includes a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to each other. A memory array including a plurality of sense amplifiers respectively connected to the plurality of bit lines, and a plurality of column selection lines respectively connected to the plurality of sense amplifiers;
The control device includes a communication circuit connected to the semiconductor memory device, a control circuit that controls the semiconductor memory device by issuing a plurality of commands and transmitting the command to the semiconductor memory device via the communication circuit; A timing register for storing a plurality of timing parameters related to the operation of the semiconductor memory device;
The plurality of commands are:
An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
The plurality of timing parameters are a third time period (WL2) indicating a time difference from when the write command is issued to when data is transmitted from the control device to the semiconductor memory device, and conforming to the JEDEC standard A third time period (WL2) that is shorter than the write latency (WL)
When writing data to the semiconductor memory device, the control circuit transfers data from the control device to the semiconductor memory device at a moment separated by the third time period (WL2) with reference to the moment when the write command is issued. Start sending.

According to the control device according to the sixth aspect of the present invention, in the control device according to the fifth aspect,
The timing parameter further includes a fourth time period (WL1) equal to a write latency (WL) according to the JEDEC standard;
The control circuit, when writing data to the semiconductor memory device, at a moment separated by the third time period (WL2) or the fourth time period (WL1) with reference to the moment when the write command is issued. Data transmission from the control device to the semiconductor memory device is started.

According to the control device according to the seventh aspect of the present invention, in the control device according to the fifth or sixth aspect,
The third time period (WL2) has a negative value;
The control circuit, when writing data to the semiconductor memory device, at the moment preceding the moment when the write command is issued by a time period equal to the absolute value of the third time period (WL2). Starts to transmit data to the semiconductor memory device.

According to the control device of the eighth aspect of the present invention, in the control device according to one of the first to seventh aspects,
The semiconductor memory device includes a plurality of banks,
The control circuit includes:
When writing data to the semiconductor memory device, the same data is written to at least two of the plurality of banks,
When reading data from the semiconductor memory device, data is read from at least one of the plurality of banks in which the same data is written.

According to the control device according to the ninth aspect of the present invention, in the control device according to the eighth aspect,
The timing parameter further includes a fifth time period (tRC (R)) indicating the shortest time in which the activation command for a certain bank can be issued continuously.
The control circuit is configured to read data from at least two banks in which the same data is written out of the plurality of banks at a time shorter than the fifth time period (tRC (R)). When the activation command is issued, the second command including a bank address different from the bank address included in the first activation command is issued.

According to the control device of the tenth aspect of the present invention, in the control device according to the eighth or ninth aspect,
The plurality of banks have bank addresses including a plurality of bits,
When the control circuit writes data to the semiconductor memory device, the control circuit stores the memory cell having the same row address in at least two banks each having a bank address including at least one same bit value. Write the same data.

According to the control device of the eleventh aspect of the present invention,
A control device for a semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
The semiconductor memory device includes a plurality of banks connected to at least one internal data bus, and each one of the plurality of banks extends along a plurality of bit lines and a plurality of word lines orthogonal to each other. A memory array comprising a plurality of memory cells arranged, a plurality of sense amplifiers connected to the plurality of bit lines, respectively, and a plurality of column selection lines connected to the plurality of sense amplifiers, respectively.
The control device includes a communication circuit connected to the semiconductor memory device, a control circuit that controls the semiconductor memory device by issuing a plurality of commands and transmitting the command to the semiconductor memory device via the communication circuit; A timing register for storing a plurality of timing parameters related to the operation of the semiconductor memory device;
The plurality of commands are:
An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
The plurality of timing parameters include a sixth time period (tRRD) indicating the shortest time in which the activation commands for two different banks can be issued in succession, and the write command or the read for any two banks. A seventh time period (tCCD) indicating the shortest time in which commands can be issued continuously; and an eighth time period (tFAW) indicating the shortest time in which the four activation commands can be issued in succession. The seventh time period (tCCD) is set equal to the sixth time period (tRRD), and the eighth time period (tFAW) is set equal to four times the sixth time period (tRRD). And
The control circuit includes:
When continuously writing data to the semiconductor memory device, the activation command and the write command are issued at a period equal to the sixth time period (tRRD),
When data is continuously read from the semiconductor memory device, the activation command and the read command are issued with a period equal to the sixth time period (tRRD).

According to the control device according to the twelfth aspect of the present invention, in the control device according to the eleventh aspect,
The semiconductor memory device has a first operation mode and a second operation mode,
When the semiconductor memory device is in the first operation mode, the upper limit voltage of the word line has a first voltage value, and the seventh time period (tCCD) is the sixth time period (tRRD). The eighth time period (tFAW) is longer than four times the sixth time period (tRRD),
When the semiconductor memory device is in the second operation mode, the upper limit voltage of the word line has a second voltage value higher than the first voltage value, and the seventh time period (tCCD) is The sixth time period (tRRD) is equal to the eighth time period (tFAW) is equal to four times the sixth time period (tRRD);
The control circuit transmits a second control signal for selectively operating the semiconductor memory device in one of the first operation mode and the second operation mode to the semiconductor memory device.

According to the control device of the thirteenth aspect of the present invention, in the control device according to the eleventh or twelfth aspect,
The plurality of timing parameters include a plurality of sixth time periods (tRRD) having different lengths depending on different combinations of two banks.

According to the control device of the fourteenth aspect of the present invention,
A control device for a semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
The semiconductor memory device includes a plurality of banks connected to at least one internal data bus, and each one of the plurality of banks extends along a plurality of bit lines and a plurality of word lines orthogonal to each other. A memory array comprising a plurality of memory cells arranged, a plurality of sense amplifiers connected to the plurality of bit lines, respectively, and a plurality of column selection lines connected to the plurality of sense amplifiers, respectively.
The control device includes a communication circuit connected to the semiconductor memory device, a control circuit that controls the semiconductor memory device by issuing a plurality of commands and transmitting the command to the semiconductor memory device via the communication circuit; A timing register for storing a plurality of timing parameters related to the operation of the semiconductor memory device;
The plurality of commands are:
An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
The plurality of timing parameters are transmitted from the control device to the semiconductor memory device in order to write data to a first bank of the plurality of banks, and then a second one of the plurality of banks. A plurality of ninth time periods (tWTR) indicating a time difference until the read command can be issued to read data from the bank, wherein the plurality of ninth time periods (tWTR) Different lengths according to different combinations of the second bank,
When the data is read from the second bank immediately after writing the data to the first bank, the control circuit transmits the data to the semiconductor memory device, and then the combination of the first and second banks. The read command is issued after waiting for the ninth time period (tWTR) having a length corresponding to.

According to the semiconductor memory device of the fifteenth aspect of the present invention,
A semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
The semiconductor memory device
An internal data bus;
And at least one bank connected to the internal data bus,
The bank includes a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to each other, a plurality of sense amplifiers respectively connected to the plurality of bit lines, and the plurality of sense amplifiers. A memory array having a plurality of column selection lines connected to each other;
The semiconductor memory device includes a communication circuit connected to a control device via an external bus, a control circuit that receives a plurality of commands from the control device via the communication circuit and controls operations of the semiconductor memory device. With
The plurality of commands are:
An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
When writing data to the semiconductor memory device, the control circuit precedes by a time period equal to an absolute value of a first time period (tRCD (W)) determined in advance with reference to the moment when the activation command is received. The write command can be received from the control device after the moment when the activation command is received and before the moment when the activation command is received.

According to the semiconductor memory device in accordance with the sixteenth aspect of the present invention, in the semiconductor memory device in accordance with the fifteenth aspect,
The semiconductor memory device includes a plurality of circuits respectively associated with at least a part of the plurality of commands,
The control circuit includes:
When writing data to the semiconductor memory device, a first control signal for notifying that the write command is issued before the activation command is received from the control device,
When the first control signal is received, a circuit associated with the write command is activated.

According to the semiconductor memory device in accordance with the seventeenth aspect of the present invention, in the semiconductor memory device in accordance with the fifteenth or sixteenth aspect,
The semiconductor memory device
A first voltage source for applying a first voltage to the column selection line when reading data from the semiconductor memory device;
And a second voltage source for applying a second voltage higher than the first voltage to the column selection line when writing data to the semiconductor memory device.

According to the semiconductor memory device in accordance with the eighteenth aspect of the present invention, in the semiconductor memory device in accordance with the seventeenth aspect,
When reading data from the semiconductor memory device, the first voltage source applies the first voltage to the column selection line over a first time length;
When writing data to the semiconductor memory device, the second voltage source applies the second voltage to the column selection line for a second time length longer than the first time length.

According to a semiconductor memory device in accordance with a nineteenth aspect of the present invention, in the semiconductor memory device according to one of the fifteenth to eighteenth aspects,
When writing data to the semiconductor memory device, the control circuit activates the column selection line after receiving the write command and before activating the sense amplifier.

According to the semiconductor memory device in accordance with the twentieth aspect of the present invention, in the semiconductor memory device in accordance with the nineteenth aspect,
When writing data into the semiconductor memory device, the control circuit activates the column selection line after receiving the write command and before activating the sense amplifier and the word line.

According to the semiconductor memory device in accordance with the twenty-first aspect of the present invention, in the semiconductor memory device in accordance with the nineteenth or twentieth aspect,
Each one of the plurality of sense amplifiers includes at least one NMOS transistor and at least one PMOS transistor;
When deactivating the sense amplifier, a voltage equal to the upper limit voltage of the bit line is applied to the source of the NMOS transistor,
When the sense amplifier is activated, a voltage equal to the lower limit voltage of the bit line is applied to the source of the NMOS transistor.

According to the semiconductor memory device in accordance with the twenty-second aspect of the present invention, in the semiconductor memory device according to one of the fifteenth to twenty-first aspects,
The bank includes a plurality of subarrays separated from each other by at least one sense amplifier row including a plurality of sense amplifiers,
The write command includes a part of a row address of a subarray including a storage cell to which data is written,
The control circuit includes:
Activate a sub-array designated by the row address of the write command;
Activate the column selection line specified by the column address of the write command,
The voltage of the bit line corresponding to the activated column selection line is set to the upper limit voltage.

According to a semiconductor memory device in accordance with a twenty-third aspect of the present invention, in the semiconductor memory device according to one of the fifteenth to twenty-second aspects,
The semiconductor memory device includes a plurality of banks,
The control circuit includes:
When writing data to the semiconductor memory device, the same data is written to at least two of the plurality of banks,
When reading data from the semiconductor memory device, data is read from at least one of the plurality of banks in which the same data is written.

According to the semiconductor memory device in accordance with the twenty-fourth aspect of the present invention, in the semiconductor memory device in accordance with the twenty-third aspect,
The control circuit includes first and second activation commands issued to read data from at least two banks in which the same data of the plurality of banks is written, and a predetermined first command When the first and second activation commands issued at intervals shorter than the time period of 5 (tRC (R)) are received, at least the same data is written according to the first activation command. Data is read from a first bank of the two banks, and data is read from a second bank of at least two banks in which the same data is written in response to the second activation command.

According to the semiconductor memory device in the twenty-fifth aspect of the present invention, in the semiconductor memory device in the twenty-third or twenty-fourth aspect,
The plurality of banks have bank addresses including a plurality of bits,
When the control circuit writes data to the semiconductor memory device, the control circuit stores the memory cell having the same row address in at least two banks each having a bank address including at least one same bit value. Write the same data.

According to the semiconductor memory device in the twenty-sixth aspect of the present invention,
A semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
The semiconductor memory device
An internal data bus;
A plurality of banks connected to the internal data bus,
Each one of the plurality of banks includes a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to each other, and a plurality of senses respectively connected to the plurality of bit lines. A memory array including an amplifier and a plurality of column selection lines connected to the plurality of sense amplifiers,
The semiconductor memory device includes a communication circuit connected to a control device via an external bus, a control circuit that receives a plurality of commands from the control device via the communication circuit and controls operations of the semiconductor memory device. With
The plurality of commands are:
An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
The semiconductor memory device has a plurality of timing parameters related to the operation of the semiconductor memory device, and the plurality of timing parameters has a minimum time during which the activation commands for two different banks can be continuously received. A sixth time period (tRRD) shown, a seventh time period (tCCD) showing the shortest time in which the write command or the read command for any two banks can be continuously received, and the four activations An eighth time period (tFAW) indicating the shortest time in which commands can be continuously received, and the seventh time period (tCCD) is equal to the sixth time period (tRRD). The time period (tFAW) is equal to four times the sixth time period (tRRD),
The control circuit includes:
When continuously writing data to the semiconductor memory device, the activation command and the write command can be received from the control circuit at a period equal to the sixth time period (tRRD), respectively.
When data is continuously read from the semiconductor memory device, the activation command and the read command can be received from the control circuit at a period equal to the sixth time period (tRRD).

According to the semiconductor memory device in accordance with the twenty-seventh aspect of the present invention, in the semiconductor memory device in accordance with the twenty-sixth aspect,
In the semiconductor memory device, the seventh time period (tCCD) is equal to the sixth time period (tRRD), and the eighth time period (tFAW) is equal to the sixth time period (tFAW). a third voltage source for applying a voltage set to be equal to four times tRRD) to the word line.

According to the semiconductor memory device in accordance with the twenty-eighth aspect of the present invention, in the semiconductor memory device in accordance with the twenty-sixth or twenty-seventh aspect,
The semiconductor memory device has a first operation mode and a second operation mode,
When the semiconductor memory device is in the first operation mode, the upper limit voltage of the word line has a first voltage value, and the seventh time period (tCCD) is the sixth time period (tRRD). The eighth time period (tFAW) is longer than four times the sixth time period (tRRD),
When the semiconductor memory device is in the second operation mode, the upper limit voltage of the word line has a second voltage value higher than the first voltage value, and the seventh time period (tCCD) is The sixth time period (tRRD) is equal to the eighth time period (tFAW) is equal to four times the sixth time period (tRRD);
The control circuit receives the second control signal for selectively operating the semiconductor memory device in one of the first operation mode and the second operation mode from the control device. One of the first operation mode and the second operation mode is selectively operated according to a signal.

According to a semiconductor memory device in accordance with a twenty-ninth aspect of the present invention, in the semiconductor memory device according to one of the twenty-sixth to twenty-eighth aspects,
The plurality of timing parameters include a plurality of sixth time periods (tRRD) having different lengths depending on different combinations of two banks.

According to the semiconductor memory system of the thirtieth aspect of the present invention,
A control device according to one of the first to tenth aspects;
And a semiconductor memory device according to one of the fifteenth to twenty-fifth aspects.

According to the semiconductor memory system of the thirty-first aspect of the present invention,
A control device according to one of the eleventh to thirteenth aspects;
A semiconductor memory device according to one of the twenty-sixth to twenty-ninth aspects.

According to the semiconductor memory system of the thirty-second aspect of the present invention,
A control device according to a fourteenth aspect;
A semiconductor memory device.

According to the semiconductor memory device control method of the thirty-third aspect of the present invention,
A control method for a semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
The semiconductor memory device includes at least one bank connected to at least one internal data bus, and the bank includes a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to each other. A memory array including a plurality of sense amplifiers respectively connected to the plurality of bit lines, and a plurality of column selection lines respectively connected to the plurality of sense amplifiers;
The control method is:
Issuing an activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address and a sense amplifier connected to the memory cell via the bit line;
Issuing a write command instructing to write data to a memory cell having a certain bank address and a certain column address;
Issuing a read command instructing to read data from a memory cell having a certain bank address and a certain column address;
When writing data to the semiconductor memory device, issuing the write command after a moment separated by a first time period (tRCD (W)) with reference to the moment of issuing the activation command;
Issuing the read command after reading a second time period (tRCD (R)) with reference to the moment when the activation command is issued when reading data from the semiconductor memory device;
The first time period (tRCD (W)) indicates a time difference from when the activation command is issued until the write command can be issued, and the second time period (tRCD (R)) is A time difference is indicated from when the activation command is issued until the read command can be issued, and the first time period has a smaller value than the second time period.

According to the present invention, there is provided a semiconductor memory device in which use efficiency of an external data bus is not easily lowered even when data is written to and / or read from one or a plurality of banks by a command sequence including a precharge command. A control device and a semiconductor storage system including these can be provided.

According to the present invention, a control method for such a semiconductor memory device can also be provided.

1 is a block diagram showing a processing device including a memory system according to Embodiment 1. FIG. FIG. 2 is a block diagram illustrating a configuration of a memory controller 3 in FIG. 1. It is a block diagram which shows the structure of the memory 5 of FIG. FIG. 4 is a block diagram showing a detailed configuration of a chip control circuit 22 in FIG. 3. FIG. 4 is a block diagram showing a configuration of a memory array 23-n, a row decoder 24-n, and a column decoder 25-n in FIG. FIG. 6 is a block diagram showing a detailed configuration of a subarray 51 and a sense amplifier array 52 in FIG. 5. FIG. 7 is a circuit diagram illustrating a detailed configuration of sense amplifiers SA11 and SA02, an IO switch IOSW, and a memory cell C00 in FIG. FIG. 8 is a circuit diagram showing a configuration of an equalize circuit connected to the bit line of FIG. 7. FIG. 6 is a circuit diagram showing a configuration of a subarray selection switch SASW in FIG. 5. 3 is a timing chart illustrating a data read operation according to the first embodiment. 11 is a timing chart showing waveforms of signals when the read operation of FIG. 10 is performed. 6 is a timing chart illustrating a data write operation according to a comparative example of the first embodiment. FIG. 13 is a timing chart showing waveforms of signals when the write operation of FIG. 12 is performed. FIG. 3 is a timing chart illustrating a data write operation according to the first embodiment. FIG. 15 is a timing chart showing waveforms of signals when the write operation of FIG. 14 is performed. 10 is a block diagram showing a column decoder 25-n and its periphery in a memory system according to Embodiment 2. FIG. 6 is a timing chart showing waveforms of signals when a data write operation according to a comparative example of Embodiment 2 is performed. 9 is a timing chart showing waveforms of signals when performing a data write operation according to the second embodiment. 10 is a timing chart showing waveforms of signals when a data write operation according to the third embodiment is performed. 10 is a timing chart showing waveforms of signals when a data write operation according to a modification of the third embodiment is performed. FIG. 10 is a block diagram illustrating a configuration of a chip control circuit 22A of a memory system according to a fourth embodiment. FIG. 10 is a circuit diagram showing a configuration of an equalize circuit connected to a bit line of a memory system according to a fourth embodiment. FIG. 10 is a circuit diagram illustrating a configuration of a subarray selection switch SASW in the memory system according to the fourth embodiment. 10 is a timing chart showing waveforms of signals when a data write operation according to the fourth embodiment is performed. FIG. 10 is a block diagram illustrating a configuration of a memory controller 3A of a memory system according to Embodiment 5. 10 is a timing chart illustrating a data write operation according to the fifth embodiment. FIG. 10 is a block diagram illustrating a configuration of a memory controller 3B of a memory system according to a sixth embodiment. FIG. 16 is a block diagram for explaining an operation of writing data to the memory 5 of the memory system according to the sixth embodiment. FIG. 10 is a block diagram for explaining an operation of reading data from a memory 5 of a memory system according to a sixth embodiment. It is a figure which shows the activation command used in the memory system which concerns on Embodiment 6. FIG. FIG. 10 is a diagram illustrating a write command used in a memory system according to a sixth embodiment. 18 is a timing chart illustrating a data write operation according to a modification of the sixth embodiment. FIG. 20 is a block diagram illustrating a configuration of a memory controller 3C of a memory system according to a seventh embodiment. FIG. 20 is a block diagram showing a row decoder 24-n and its periphery in a memory system according to a seventh embodiment. FIG. 35 is a circuit diagram showing a configuration of a VPP generation circuit 91 of FIG. 34. 12 is a timing chart illustrating a data read operation according to the seventh embodiment. 16 is a timing chart illustrating a data write operation according to the seventh embodiment. FIG. 10 is a block diagram illustrating a configuration of a VPP generation circuit 100 of a memory system according to an eighth embodiment. FIG. 20 is a block diagram illustrating a configuration of a memory controller 3D of a memory system according to Embodiment 9. FIG. 20 is a block diagram showing a configuration of a memory 5D of a memory system according to Embodiment 9. 10 is a timing chart illustrating a data write operation according to a comparative example of the ninth embodiment. 10 is a timing chart illustrating a data write operation according to the ninth embodiment. FIG. 25 is a diagram showing a write command used in the memory system according to the ninth embodiment. FIG. 22 is a block diagram illustrating a configuration of a memory controller 3E of the memory system according to the tenth embodiment. FIG. 18 is a block diagram for explaining a data write / read operation to / from a memory 5 of the memory system according to the tenth embodiment. 12 is a timing chart showing data write and read operations according to the first example of Embodiment 10. 22 is a timing chart showing data write and read operations according to the second example of Embodiment 10. FIG. 29 is a block diagram showing a configuration of a memory controller 3E of a memory system according to a modification example of Embodiment 10. 22 is a timing chart showing data write and read operations according to the third example of Embodiment 10. 6 is a timing chart showing the operation of the memory system according to the first comparative example.

Before describing an embodiment of the present invention, the operation of a memory system according to a comparative example and its problems will be described.

FIG. 50 is a timing chart showing the operation of the memory system according to the first comparative example. FIG. 50 shows clocks, commands, bank addresses, and data transmitted on the memory bus when performing write and read accesses to the memory of the DDR2-SDRAM. “A” indicates an activation command, “W” indicates a write command, “R” indicates a read command, and “P” indicates a precharge command. The memory includes eight banks B0 to B7, and “0” to “7” indicate bank addresses of the banks B0 to B7, respectively. “Dn” (n = 0 to 7) indicates write data to the bank Bn, and “Qn” (n = 0 to 7) indicates read data from the bank Bn. The clock, command, bank address, and write data are transmitted from the controller to the memory, and read data is transmitted from the memory to the controller. The memory controller performs write or read access to the memory by sending an activation command, a write command, a read command, and a precharge command for each bank to the memory.

The activation command for the bank Bn (n = 0 to 7) is represented as ACTn, the write command for the bank Bn is represented as WRITEn, the read command for the bank Bn is represented as READn, and the precharge command for the bank Bn is represented as PREn. The write command and the read command sent together with the column address are collectively referred to as “column command (COL)”, and the column command for the bank Bn is represented as COLn.

The timing parameters associated with each command are defined as follows.

tCK: The length of one cycle of the clock.
tCCD-ij: The length of the time period from when the column command COLi for a certain bank Bi is issued until the column command COLj for the next arbitrary bank Bj can be issued.
tRRD-ij: The length of the time period from when the activation command ACTi for a certain bank Bi is issued until the activation command ACTj for a different bank Bj can be issued.
tRCD-i: The length of the time period from when the activation command ACTi for a certain bank Bi is issued until the column command COLi can be issued for the same bank Bi.
tRTPi: The length of the time period from when the read command READi for a certain bank Bi is issued until the precharge command PREi for the same bank Bi can be issued.
tWR-i: The length of the time period from when the write command WRITEi for a certain bank Bi is issued until the precharge command PREi for the same bank Bi can be issued.
tRAS-i: The length of the time period from when the activation command ACTi for a certain bank Bi is issued until the precharge command PREi for the same bank Bi can be issued.
tRP-i: The length of the time period from when the precharge command PREi for a certain bank Bi is issued until the activation command ACTi for the same bank Bi can be issued.
tWTR-ij: The length of the time period from when the write data for a certain bank Bi is transmitted (that is, from the end of the burst data) until the read command READi for the next arbitrary bank Bj can be issued.
tRCi: The length of the time period from when the activation command ACTi for a certain bank Bi is issued until the activation command ACTi for the next same bank can be issued.
tFAW-ijkl: Time from when four activation commands are successively issued to each of the four banks Bi, Bj, Bk, B1, until the activation command can be issued to another bank Bm The length of the period.
CL: The number of clock cycles (CAS latency) from when the read command READi is issued to a certain bank Bi until the head of the read data Qi is output to the external data bus.
CWL: The number of clock cycles (CAS write latency) from the issuance of the write command WRITEi to a certain bank Bi until the beginning of the write data Di reaches the memory.
BL: Number of data units (burst length) that are continuously written to or read from the memory after issuing one write command or read command.

Hereinafter, for simplification of description, the timing parameters “i”, “j”, “k”, and “l” may be omitted.

In the case of a DDR-SDRAM, since data access is performed twice in one clock, the time that the write data or read data occupies the external data bus when one write command or read command is issued is 1/2 × BL XtCK.

DDRx-SDRAM and LPDDRx-SDRAM memory system interfaces are specified as JEDEC (Joint Electron Device Engineering Council) standards. The timing parameters are also defined in the JEDEC standard. For example, when the clock period tCK is 1.875 nanoseconds, the minimum value of each timing parameter in the DDR2-SDRAM is as follows.

tCK = 1.875 nanoseconds tCCD = 4tCK
tRRD = 6tCK
tRCD = 7tCK
tRTP = 4tCK
tWR = 8tCK
tRP = 7tCK
tRAS = 20tCK
tWTR = 4tCK
tFAW = 27tCK
BL = 8
CL = 7tCK
CWL = 6tCK

In DDR2-SDRAM, burst length BL = 8 is used. Therefore, when one write command or read command is issued to the memory, eight consecutive data units are written to the memory or read from the memory over a time of 4 × tCK. Therefore, when a single write command or read command is issued, the write data or read data occupies the external data bus for a time of 4 × tCK.

Based on the timing parameters compliant with the above JEDEC standard, the minimum value tCCD (min) of the time period tCCD is equal to the data input / output time of one write or read access, that is, 1/2 × BL × tCK. Accordingly, when a plurality of write commands for activating a plurality of banks and continuously writing data to these banks are issued every time period tCCD (min) = 4 × tCK, data is continuously read without interruption. The external data bus can be used almost 100% effectively. Similarly, when a plurality of read commands for activating a plurality of banks and reading data from these banks are issued continuously every time period tCCD (min) = 4 × tCK, the data is continuously transmitted without interruption. The external data bus can be used almost 100% effectively.

However, as described above, more random access may be required depending on the application. When such a random access operation is repeated, it becomes impossible to issue a write command or a read command continuously every time period tCCD (min) = 4 × tCK, and the use efficiency of the external data bus is lowered. In particular, when writing and / or reading access to page data of different row addresses in the same bank is repeated, it is necessary to issue an activation command and a precharge command for each access, and the use efficiency of the external data bus is further increased. The problem of deteriorating arises.

The random access will be described with reference to FIG.

In the 0th to 28th clock cycles in FIG. 50, the write operation is continuously performed on the three different banks B3, B2, and B1. First, the memory controller issues an activation command ACT3 to the bank B3, issues a write command WRITE3 to the bank B3 after the elapse of the time period tRCD-3, and after the elapse of the time period CWL-3, Write data D3 for B3 is transmitted to the memory. As described above, data is written to the bank B3. Separately from the write operation of bank B3, the memory controller starts the write operation of bank B2 after the elapse of time period tRRD-32 from the issuance of activation command ACT3. First, the memory controller issues an activation command ACT2 to the bank B2, issues a write command WRITE2 to the bank B2 after the elapse of the time period tRCD-2, and after the elapse of the time period CWL-2, Write data D2 for B2 is transmitted to the memory. As described above, data is written to the bank B2. Further, separately from the write operations of the banks B3 and B2, the memory controller starts the write operation of the bank B1 after the elapse of the time period tRRD-21 from the issue of the activation command ACT2. First, the memory controller first issues an activation command ACT1 to the bank B1, and after the time period tRCD-1, elapses, issues a write command WRITE1 to the bank B1. After the elapse of 1, the write data D1 for the bank B1 is transmitted to the memory. As described above, data is written to the bank B1. By the above command sequence, the write operation can be sequentially performed on the bank B3, the bank B2, and the bank B1.

However, in the case of performing random access using the above timing parameter compliant with the JEDEC standard, when the minimum value tRRD (min) of the time period tRRD is compared with the minimum value tCCD (min) of the time period tCCD, tCCD (min ) <TRRD (min). Therefore, when a plurality of banks are activated every time period tRRD (min) and the write command WRITE is issued sequentially to these banks, the transmission time of write data for a certain bank and the transmission of write data for a different bank There will be a time when the external data bus becomes empty. That is, a gap is generated between the write data D3, D2, and D1 in FIG. Due to this gap, the efficiency of use of the external data bus is reduced to 2/3 of the case where data is continuously written without interruption. Therefore, there is a problem that the external data bus cannot be used efficiently with respect to the operation clock frequency used.

The same problem occurs in the read operation. In the 44th to 80th clock cycles in FIG. 50, the read operation is performed on four consecutive different banks B7, B6, B5, and B4. As in the case of the write operation, a gap occurs between the read data Q7, Q6, Q5, and Q4 due to the restriction of tCCD (min) <tRRD (min), and the external data bus cannot be used efficiently. Invite the problem.

Further, in the 0th to 48th clock cycles of FIG. 50, continuous writing is performed on different row addresses of the same bank B3, that is, page data of different selected word lines. An interval equal to or longer than the time period tRC (min) is required between successive activation commands ACT for the same bank. Here, the time period tRC (min) during the write operation is defined by “tRC (min) = tRCD (min) + CWL + 1/2 × BL + tWR (min) + tRP (min)”. In the case of FIG. −3 = 32 × tCK ”is required. On the other hand, the time during which write data occupies the external data bus by one write command WRITE during this time period is at most ½ × BL = 4 × tCK. Therefore, when writing to page data of different row addresses in the same bank continues, the use efficiency of the external data bus is reduced to 1/8 of the case where data is continuously written without interruption.

Although not shown in FIG. 50, when continuous reading is performed from different row addresses of the same bank B3, that is, page data of different selected word lines, there is a time interval between successive activation commands ACT. An interval equal to or longer than the period tRC (min) is necessary. Here, the time period tRC (min) during the read operation is defined by “tRC (min) = tRAS (min) + tRP (min)”. In the case of FIG. 50, “tRC (min) = 27 × tCK”. Is required. Therefore, when reading for page data of different row addresses in the same bank is continued, the use efficiency of the external data bus is reduced to 4/27 when reading data continuously without interruption.

Further, the limitation on the time period tFAW will be described with reference to the 44th to 106th clock cycles in FIG. Here, an operation of sequentially activating eight banks B7, B6, B5, B4, B3, B2, B1, and B0 in order and reading a part of the page data of each bank once is shown. In this case, the restriction on continuous bank activation given by the time period tFAW becomes a problem. For the first four bank activations, it is possible to issue an activation command every time period tRRD (min). However, when “4 × tRRD (min) <tFAW (min)”, the fifth bank activation needs to be performed after waiting for the time period tRRD (min) or more according to the definition of the time period tFAW. . Due to this restriction, a gap larger than the time period tRRD (min) is generated between the read data Q4 and Q3 (a gap of 5 × tCK in FIG. 50), and the external data bus cannot be used efficiently. Invite.

As described above, when performing random write or read access within the same bank or across different banks, there is a problem that the efficiency of use of the external data bus is greatly degraded. Even in a system that requires random write or read access, it is required to increase the use efficiency of the external data bus and to effectively increase the access speed between the memory controller and the memory.

In each of the following embodiments, a memory system in which the use efficiency of an external data bus is unlikely to be lowered even when data is written to and / or read from one or more banks by a command sequence including a precharge command explain.

Embodiments according to the present invention will be described below with reference to the drawings.

In Embodiments 1 to 6, a memory system capable of speeding up a write operation or a read operation will be described.

Embodiment 1. FIG.
FIG. 1 is a block diagram illustrating a processing apparatus including a memory system according to the first embodiment. The processing apparatus in FIG. 1 includes a processor 1, a processor bus 2, a memory controller 3, a memory bus 4, and a memory 5.

The processor 1 is connected to the memory controller 3 via the processor bus 2. The memory controller 3 is connected to the memory 5 via the memory bus 4. As will be described later, the memory 5 includes a plurality of banks each including a plurality of subarrays. The memory 5 has an interface conforming to the JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM. The memory controller 3 and the memory 5 communicate with each other using a signal group conforming to the JEDEC standard via the memory bus 4. The memory bus 4 includes signal lines of a clock bus, a command bus, an address bus, and an external data bus. The memory controller 3 and the memory 5 operate as a memory system for the processor.

The memory controller 3 is configured as, for example, SoC (silicon chip) or FPGA (field programmable gate array).

The DDRx-SDRAM memory 5 is an example of a semiconductor memory device. The memory controller 3 is an example of a control device for a semiconductor memory device. A memory system including the memory controller 3 and the memory 5 is an example of a semiconductor storage system.

FIG. 2 is a block diagram showing a configuration of the memory controller 3 of FIG. The memory controller 3 includes a control circuit 11, a PHY interface 12, and a timing register 13. The PHY interface 12 is a communication circuit connected to the memory 5. The control circuit 11 controls the memory 5 by issuing a plurality of commands and transmitting them to the memory 5 via the PHY interface 12. The timing register 13 stores a plurality of timing parameters related to the operation of the memory 5.

The timing parameters include, for example, time periods tRCD (W), tRCD (R), tRP, and CL. The time period tRCD (W) indicates a minimum value of a time difference from when an activation command for a certain bank is issued until a write command can be issued for the same bank. The time period tRCD (R) indicates a minimum value of a time difference from when an activation command for a certain bank is issued until a read command can be issued for the same bank. The time period tRP indicates the minimum value of the time difference from when the precharge command for a certain bank is issued until the activation command for the same bank can be issued. The time period CL indicates the number of clock cycles (CAS latency) from when a read command is issued to a certain bank until the beginning of the read data is output to the external data bus. The timing register 13 includes registers that store time periods tRCD (W), tRCD (R), tRP, and CL, respectively.

In this specification, the time period tRCD (W) is also referred to as a “first time period”, and the time period tRCD (R) is also referred to as a “second time period”.

In the block diagram of FIG. 2, only the timing parameters necessary for the description of the embodiment are shown, but the timing register 13 actually stores other timing parameters. The same applies to block diagrams of memory controllers according to other embodiments.

In the memory controller of the prior art, the time period tRCD (W) and tRCD (R) are not distinguished, and the activation command for a certain bank is issued until the read command and write command for the same bank can be issued. A single value indicating the minimum time difference was stored. On the other hand, in the memory controller 3 according to the first embodiment, the timing register 13 stores the time periods tRCD (W) and tRCD (R) individually in the tRCD (W) register and the tRCD (R) register. . Furthermore, the memory controller 3 according to the first embodiment is characterized in that a value smaller than the value stored in the tRCD (R) register can be stored in the tRCD (W) register. Furthermore, in the memory controller 3 according to the first embodiment, a negative value smaller than “0” can be stored in the tRCD (W) register, and a negative value is stored in the tRCD (W) register. In this case, the memory controller 3 can issue a write command for the same bank before issuing an activation command for a certain bank.

FIG. 3 is a block diagram showing a configuration of the memory 5 of FIG. The memory 5 includes an SDRAM interface 21, a chip control circuit 22, banks B1 to B4, and internal data buses DB1 and DB2. The SDRAM interface 21 is a communication circuit connected to the memory controller 3 via the memory bus 4. The SDRAM interface 21 communicates with the memory controller 3 and controls the operation timing of the memory 5. The chip control circuit 22 is a control circuit that receives a plurality of commands from the memory controller 3 via the SDRAM interface 21 and controls the operation of the memory 5. The SDRAM interface 21 and the chip control circuit 22 transmit / receive internal control signals to / from each other through a plurality of control lines (represented by one in FIG. 3). Banks B1 and B2 are connected to the SDRAM interface 21 via the internal data bus DB1, and banks B3 and B4 are connected to the SDRAM interface 21 via the internal data bus DB2.

Bank B1 includes a memory array 23-1, a row decoder 24-1, and a column decoder 25-1. As will be described later, the memory array 23-1 includes a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to each other, and a plurality of sense amplifiers respectively connected to the plurality of bit lines. And a plurality of column selection lines respectively connected to the plurality of sense amplifiers. The row decoder 24-1 and the column decoder 25-1 designate a two-dimensional access position for the memory array 23-1. The other banks B2 to B4 are also provided with memory arrays 23-2 to 23-4, row decoders 24-2 to 24-4, and column decoders 25-2 to 25-4, respectively, similarly to the bank B1.

The chip control circuit 22 includes bank control circuits 31-1 to 31-4. The bank control circuits 31-1 to 31-4 are connected to the corresponding banks B1 to B4, respectively, and control is performed by transmitting control signals to the banks B1 to B4. That is, the bank control circuit 31-1 activates the row decoder 24-1 of the bank B1 by the row address activation signal RAE-1, and supplies the row address signal RA-1 to the row decoder 24-1 of the bank B1. Further, the bank control circuit 31-1 activates the column decoder 25-1 of the bank B1 by the column address activation signal CAE-1, and supplies the column address signal CA-1 to the column decoder 25-1 of the bank B1. Similarly to the bank control circuit 31-1, the other bank control circuits 31-2 to 31-4 also control the corresponding banks B2 to B4.

FIG. 4 is a block diagram showing a detailed configuration of the chip control circuit 22 of FIG. Specifically, the chip control circuit 22 includes a logical sum (OR) circuit 32 and an activation control circuit 33 in addition to the bank control circuits 31-1 to 31-4.

Referring to FIG. 4, the configuration of bank control circuits 31-1 to 31-4 will be further described. The bank control circuit 31-1 includes a row address control circuit 41, a column address control circuit 42, a logical sum (OR) circuit 43, and a logical product (AND) circuit 44. The row address control circuit 41 and the column address control circuit 42 receive a bank control signal including a row address and a column address as internal control signals from the SDRAM interface 21. The row address control circuit 41 receives the bank control signal and generates a row address activation signal RAE-1 and a row address signal RA-1. The column address control circuit 42 receives the bank control signal and generates an internal signal CAEF-1 and a column address (CA-2). Internal signal CAEF-1 is an original signal for generating column address activation signal CAE-1. Column address activation signal CAE-1 is activated when both row address activation signal RAE-1 and internal signal CAEF-1 are activated. That is, when the activation state is represented by a logical value “1”, when the logical product of the internal signal CAEF-1 and the row address activation signal RAE-1 becomes “1”, the column address activation signal CAE-1 is Activated. An AND circuit 44 is provided for the logical product operation. This logic ensures that column access is possible only when the bank B1 is activated. In other words, the column access is prohibited when the bank B1 is inactive to prevent malfunction of the memory array 23-1.

Referring further to FIG. 4, a tRC (W) shortening signal is further input to the bank control circuit 31-1. As will be described later with reference to FIGS. 14 and 15, the tRC (W) shortening signal is a control signal (this is also referred to as a “first control signal”) for notifying that a write command is transmitted before the activation command. Is transmitted from the memory controller 3 to the memory 5 as an internal control signal of the memory 5 from the SDRAM interface 21 to the chip control circuit 22. When the tRC (W) shortening signal is inactive (that is, when the logical value is “0”), the column address activation signal CAE-1 is both the row address activation signal RAE-1 and the internal signal CAEF-1. It is activated only when is activated. As described above, this logic ensures that column access is possible only when the bank B1 is activated. On the other hand, when the tRC (W) shortening signal is activated (that is, when the logical value is “1”), the row address activation signal RAE-1 and the column address activation signal CAE-1 are controlled independently of each other. The That is, the restriction that the column access is enabled only when the bank B1 is activated is invalidated, and the column access is enabled before the bank B1 is activated. The AND circuit 44 receives the logical sum of the row address activation signal RAE-1 and the tRC (W) shortening signal. An OR circuit 43 is provided for this logical sum operation.

The other bank control circuits 31-2 to 31-4 are also configured similarly to the bank control circuit 31-1.

Further referring to FIG. 4, the row address activation signals RAE-1 to RAE-4 output from the bank control circuits 31-1 to 31-4 are input to the OR circuit 32. The output signal RAOR of the OR circuit 32 has a logical value “1” when at least one row address activation signal has a logical value “1” (that is, when at least one bank is activated). The activation control circuit 33 generates a control signal COLACT and a control signal IOACT when the output signal RAOR of the OR circuit 32 becomes a logical value “1”. The control signal COLACT is sent to the column address control circuit 42 of each bank control circuit 31-1 to 31-4. The column address control circuit 42 of each of the bank control circuits 31-1 to 31-4 receives a control signal COLACT and activates part or all of the circuit. This operation reduces the operating current of the column address control circuit 42 of each of the bank control circuits 31-1 to 31-4 when all the banks B1 to B4 are inactive. On the other hand, the control signal IOACT is sent to the SDRAM interface 21 and other circuits (such as an internal voltage generation circuit of the memory 5). The SDRAM interface 21 and other circuits receive a control signal IOACT and activate part or all of the circuits. This operation reduces the operating current of the SDRAM interface 21 and other circuits when all the banks B1 to B4 are inactive.

Referring further to FIG. 4, the tRC (W) shortening signal is also input to the activation control circuit 33. When the tRC (W) shortening signal is inactive (that is, when the logical value is “0”), the activation control circuit 33 outputs the output signal RAOR of the OR circuit 32 (that is, the activation / inactivation of the banks B1 to B4). ), The control signal COLACT and the control signal IOACT are generated. On the other hand, when the tRC (W) shortening signal is activated (that is, when the logical value is “1”), the activation control circuit 33 controls the control signal COLACT and the control signal regardless of the output signal RAOR of the OR circuit 32. Generate IOACT. Therefore, even before the activation command is issued, when the activation control circuit 33 receives the tRC (W) shortening signal, the column address control circuit 42 of each of the bank control circuits 31-1 to 31-4 In response to the control signal COLACT, part or all of the circuit is activated. Similarly, even before the activation command is issued, when the activation control circuit 33 receives the tRC (W) shortening signal, the SDRAM interface 21 and other circuits (such as an internal voltage generation circuit) are controlled. In response to the signal IOACT, part or all of the circuit is activated. In this way, the column address control circuit 42 of each of the bank control circuits 31-1 to 31-4 is activated, and further, the SDRAM interface 21 and other circuits are activated. Therefore, before the activation command is issued. Even so, the memory 5 is ready to receive a write command.

As described above, the memory 5 includes a plurality of circuits respectively associated with at least a part of the plurality of commands. When the tRC (W) shortening signal is activated, the chip control circuit 22 is connected to a circuit associated with the write command (the column address control circuit 42 of each bank control circuit 31-1 to 31-4, the SDRAM interface 21 and others). The circuit, etc.).

As described above, the memory 5 has an interface conforming to the JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM. Therefore, any of the signal lines of the memory bus 4 cannot be occupied in order to transmit a control signal notifying that the write command is transmitted before the activation command from the memory controller 3 to the memory 5. Therefore, for example, the write command is transmitted from the memory controller 3 to the memory 5 using an unused bit of an existing command such as a mode register setting or using a combination of unused bits. Notice.

It is not always necessary to notify the memory 5 from the memory controller 3 that the write command is transmitted before the activation command. When it is known in advance that the write command is always transmitted before the activation command, fuse trimming or electrical trimming of the fuse 5 before shipping of the memory 5 or upper metal wiring of the memory 5 is performed. The memory 5 may be configured to generate the tRC (W) shortening signal fixed in the activated state in the memory 5 by revising

FIG. 5 is a block diagram showing the configuration of the memory array 23-n, row decoder 24-n, and column decoder 25-n in FIG. Hereinafter, the reference numerals “˜n” of the constituent elements indicate that they correspond to the banks Bn (n = 1 to 4). Further, the symbol DB in FIG. 5 indicates the internal data bus DB1 or DB2 in FIG.

Referring to FIG. 5, the memory array 23-n includes a plurality of memory cells C arranged along a plurality of rows (rows along the Y direction) and a plurality of columns (columns along the X direction) orthogonal to each other. Is provided. The memory array 23-n includes a plurality of subarrays 51 that are separated from each other by at least one sense amplifier row 52 including a plurality of sense amplifiers. Each sub-array 51 also includes a plurality of memory cells C arranged along a plurality of rows and a plurality of columns. In FIG. 5, only one memory cell C is shown for simplicity of illustration.

Referring to FIG. 5, the row decoder 24-n is arranged over a plurality of rows (that is, along the X direction) of the memory array 23-n. In each subarray 51, a plurality of word lines WDL extending in the Y direction are arranged at predetermined intervals in the X direction over the entire subarray 51. All the word lines WDL are connected to the row decoder 24-n. The row decoder 24-n receives the row address signal RA-n and the row address activation signal RAE-n from the bank control circuit 31-n, and selects one word line WDL. FIG. 5 shows only one activated word line WDL among a plurality of word lines WDL. The subarray 51 connected to the selected word line WDL is referred to as “activated subarray” (indicated by hatching in FIG. 5).

Referring to FIG. 5, the column decoder is arranged across a plurality of columns of the memory array 23-n (that is, along the Y direction). In the memory array 23-n, a plurality of column selection lines CSL extending in the X direction are arranged at predetermined intervals in the Y direction over the entire memory array 23-n. All the column selection lines CSL are connected to the column decoder 25-n. The column decoder 25-n receives the column address signal CA-n and the column address activation signal CAE-n from the bank control circuit 31-n, and selects one column selection line CSL. FIG. 5 shows only one activated column selection line CSL among the plurality of column selection lines CSL.

Write access and read access are performed on the selected memory cell C at the intersection of the activated word line WDL and the activated column selection line CSL.

The internal data buses DB1 and DB2 in FIG. 3 are actually connected to the banks B1 to B4 via the input / output (IO) control circuit 26-n. As shown in FIG. 5, the internal data bus DB for transmitting a plurality of data signals is connected to the plurality of GIO buses GIOB via the IO control circuit 26-n. The GIO bus GIOB is connected to the LIO bus LIOB via the subarray selection switch SASW.

When data is written, the data on the internal data bus DB is written to the selected memory cell C via the IO control circuit 26-n, the GIO bus GIOB, the subarray selection switch SASW, and the LIO bus LIOB in this order. When reading data, the data stored in the selected memory cell C is read onto the internal data bus DB via the LIO bus LIOB, the subarray selection switch SASW, the GIO bus GIOB, and the IO control circuit 26-n in order. It is.

FIG. 6 is a block diagram showing a detailed configuration of the subarray 51 and the sense amplifier array 52 of FIG. The subarray 51 includes bit lines BTL00, BTL01,... And memory cells C00, C01,... Arranged along the word line WDL0. Sense amplifiers SA00, SA01,... Are connected to the bit lines BTL00, BTL01,. Column select lines CSL0 and CSL1 are connected to the sense amplifiers SA00, SA01,. In the subarray 51, a plurality of word lines WDL extending in the Y direction are arranged at predetermined intervals in the X direction. However, in FIG. 6, only one word line WDL0 is shown for simplification of illustration. In the subarray 51, a plurality of bit lines BTL00, BTL01,... Extending in the X direction are arranged at a predetermined interval in the Y direction. Each of the memory cells C00, C01,... Is arranged at the intersection of each word line WDL and each bit line BTL. In the sense amplifier row 52, a plurality of sense amplifiers SA00, SA01, SA10, SA11 and input / output (IO) switches are arranged at predetermined intervals in the Y direction. Further, LIO buses LIOB_0, LIOB_1,... The column selection line CSL is connected to the IO switch IOSW and controls its opening / closing. When the column selection line CSL0 is activated, the sense amplifier SA00 and the LIO bus LIOB_0 are connected, the sense amplifier SA02 and the LIO bus LIOB_2 are connected, the sense amplifier SA01 and the LIO bus LIOB_1 are connected, and the sense amplifier SA03. Are connected to the LIO bus LIOB_3. Similarly, when the column selection line CSL1 is activated, the sense amplifier SA10 and the LIO bus LIOB_0 are connected, the sense amplifier SA12 and the LIO bus LIOB_2 are connected, and the sense amplifier SA11 and the LIO bus LIOB_1 are connected. Sense amplifier SA13 and LIO bus LIOB_3 are connected. Sense amplifier activation signals SAPE and SANE are input from the row decoder 24-n to each sense amplifier SA.

FIG. 6 shows one word line WDL0, two column selection lines CSL0 and CSL1, four LIO buses LIOB_0, LIOB_2, LIOB_1, and LIOB_3, and other components connected to them. The sub-array 51 and the sense amplifier array 52 include more word lines WDL, column selection lines CSL, LIO buses LIOB, and other components connected to them.

FIG. 7 is a circuit diagram showing a detailed configuration of the sense amplifiers SA11 and SA02, the IO switch IOSW, and the memory cell C00 of FIG.

Each sense amplifier SA00, SA02 includes two pairs of PMOS transistors SAPT and NMOS transistors SANT that are cross-coupled. A sense amplifier activation signal SANE is applied to the sources of the two NMOS transistors SANT, and their drains are connected to the bit line BTL00 and the inverted bit line / BTL00, respectively. A sense amplifier activation signal SAPE is applied to the sources of the two PMOS transistors SAPT, and their drains are connected to the bit line BTL00 and the inverted bit line / BTL00, respectively. The LIO bus LIOB_0 includes a pair of signal lines LIO_0 and / LIO_0, and the LIO bus LIOB_2 includes a pair of signal lines LIO_2 and / LIO_2.

The IO switch IOSW includes an input / output (IO) transistor IOT that is a pair of NMOS transistors. The source of one IO transistor IOT is connected to the bit line BTL00, its drain is connected to the signal line LIO_0 of the LIO bus, the source of the other IO transistor IOT is connected to the inverted bit line / BTL00, and its drain is connected to the LIO bus. To the signal line / LIO_0.

The memory cell C00 includes a cell transistor CT and a cell capacitor CS, and data (information “1” or “0”) stored in the memory cell C00 is held as voltage information in the storage node SN. The cell transistor CT is, for example, an NMOS transistor.

Memory cell C is an example of a memory cell of a semiconductor memory device.

Since the bit line BTL00 has a very high resistance, a parasitic resistance RBTL is generated between a section in the vicinity of the sense amplifier SA00 and a section in the vicinity of the memory cell C00.

Other sense amplifiers SA, IO switches IOSW, and memory cells C are configured in the same manner as the sense amplifiers SA11, SA02, IO switches IOSW, and memory cells C00 in FIG.

FIG. 8 is a circuit diagram showing a configuration of an equalize circuit connected to the bit line of FIG. Although not shown in FIG. 7, the equalize circuit (or a circuit having an equivalent function) of FIG. 8 is connected to all bit line and inverted bit line pairs for the normal operation of the memory 5. . The equalize circuit of FIG. 8 includes transistors T1 to T3 controlled by a bit line equalize signal BTLEQ. The pair of bit lines BTL, / BTL are fixed to the voltage VBTL by the activation of the bit line equalize signal BTLEQ. The voltage VBTL is the final voltage VARY after the signal on the bit line BTL is amplified to the “H” (high level) side, and the final voltage after the signal on the bit line BTL is amplified to the “L” (low level) side. This is a voltage intermediate to the typical voltage VSS.

FIG. 9 is a circuit diagram showing a configuration of the subarray selection switch SASW in FIG. The GIO bus GIOB includes a pair of signal lines GIO and / GIO. 9 includes transistors T11 and T12 controlled by signal lines GIO and / GIO of the GIO bus, and transistors T13 and T14 controlled by a bit line equalize signal BTLEQ, respectively. The sub-array selection switch SASW is a switch for connecting a pair of signal lines GIO, / GIO of the GIO bus and a pair of signal lines LIO, / LIO of the LIO bus. The subarray selection switch SASW further has a function of fixing the voltage of the pair of signal lines LIO, / LIO of the LIO bus to the voltage VBTL. The subarray selection switch SASW connects the signal lines GIO and / GIO of the GIO bus and the signal lines LIO and / LIO of the LIO bus to each other when the subarray selection signal SUBASEL is activated to “H”. Sub-array selection switch SASW also fixes the voltage of signal lines LIO, / LIO of the LIO bus to voltage VBTL when bit line equalize signal BTLEQ is activated to “H”. Here, except for the internal read operation period t (iRD) and the internal write operation period t (iWR) by the column selection line CSL, the voltages of the IO bus signal lines GIO and / GIO are at the “H” level, that is, the voltage VARY or The voltage is higher than that.

Next, the operation of the memory system according to the first embodiment will be described with reference to FIGS.

FIG. 10 is a timing chart showing a data read operation according to the first embodiment. FIG. 10 shows a case where read access is continuously made to the same bank. FIG. 10 shows the clock CLK and command CMD transmitted from the memory controller 3 to the memory 5, the internal state of the memory 5, and the transmission of data on the external data bus. The command CMD “A” indicates an activation command, “R” indicates a read command, and “P” indicates a precharge command. “QD” of the external data bus represents read data read from the memory 5. The internal state iRD indicates a state in which a read operation is actually performed in the memory array 23-n in the memory 5. The command is captured at the rising edge of the clock CLK. The time period tRC (R) indicates the time from the activation command A to the activation command A when continuously reading from the same bank, and represents the actual cycle time of the read operation. When tRCD (R) = 4 × tCK, tRP = 4 × tCK, tRTP = 2 × tCK, CL = 5, and BL = 4, tRC (R) = 10 × tCK. The time period tD (R) indicates the time from when the read command R is received until the internal state iRD starts. In the example of FIG. 10, continuous reading of tRC (R) = 10 × tCK is performed. The time occupied by the read data on the external data bus is 2 × tCK, and the utilization rate of the external data bus is 2/10.

As described above, the time period tRCD (R) indicates the minimum value of the time difference from when the activation command A for a certain bank is issued until the read command R can be issued for the same bank. Accordingly, when reading data from the memory 5, the control circuit 11 of the memory controller 3 issues the read command R after the moment separated by the time period tRCD (R) with reference to the moment when the activation command A is issued. In the example of FIG. 10, the control circuit 11 of the memory controller 3 issues the read command R at the moment when the time period tRCD (R) has elapsed since the activation command A was issued.

FIG. 10 shows an example of a memory system compliant with the DDR2-SDRAM JEDEC standard. Other SDRAMs such as DDR1 / 3 / 4-SDRAM and LPDDR2 / 3 / 4-SDRAM can operate in the same manner as in FIG.

FIG. 11 is a timing chart showing the waveform of each signal when the read operation of FIG. 10 is performed. FIG. 11 shows the internal state of the memory 5 in the case of FIG. 10, the horizontal axis shows time, and the vertical axis shows voltage. FIG. 11 is an example showing voltage waveforms of internal signals of the memory 5 shown in FIGS. 5, 6, and 7. FIG. 11 shows the column selection line CSL signal, sense amplifier activation signals SAPE and SANE, the word line WDL signal, and the bit line BTL signal as internal signals of the memory 5.

Referring to FIG. 11, after elapse of time period tDWL (A) from the input of activation command A, word line WDL is activated and cell transistor CT is turned on (that is, becomes conductive), whereby memory cell C To the bit line BTL, data is read as a potential difference ΔV. A voltage waveform when data “1” is read to the bit line BTL is indicated by BTL (H), and a voltage waveform when data “0” is read to the bit line BTL is indicated by BTL (L). Sense amplifier activation signals SAPE and SANE are activated after elapse of time period tDSA (A) from activation of word line WDL. The sense amplifier activation signal SAPE is at the voltage VARY when activated and at the voltage VBTL when inactivated. The sense amplifier activation signal SANE is at the voltage VSS (that is, the ground potential = 0 V) when activated, and at the voltage VBTL when deactivated. Here, normally, VBTL = 1/2 × VARY. By activation of the sense amplifier activation signals SAPE and SANE, the voltage BTL (H) is amplified to the voltage VARY, and the voltage BTL (L) is amplified to the voltage VSS (= 0V).

Referring to FIG. 11, after the elapse of the time period tD (R) from the input of the read command R, the signal of the column selection line CSL is activated over the time period t (iRD). In this time period t (iRD), an internal read (internal state iRD) is actually performed on the memory array 23-n. Over a time period t (iRD), the IO switch IOSW is turned on by the activation of the column selection line CSL, and the pair of bit lines BTL, / BTL are connected to the pair of signal lines LIO, / LIO of the LIO bus via the IO switch IOSW. Connected, the data of the bit line BTL is read to the LIO bus. At this time, in particular, when data “0” is read out to the bit line BTL, the voltage BTL (L) of the bit line is disturbed and rises from the voltage VSS.

Referring to FIG. 11, the word line WDL is deactivated after the time period tDWL (P) has elapsed since the input of the precharge command P. By deactivation of the word line WDL, the cell transistor CT is turned off (that is, becomes non-conductive), and the data of the bit line BTL is confined in the storage node SN of the memory cell C. That is, data is rewritten in the memory cell C. This is called a memory cell restore operation. At this time, after the bit line voltage BTL (L) is subjected to the above disturbance, it is necessary to deactivate the word line WDL after the voltage of the bit line BTL returns to the voltage VSS after a sufficient time. . This time determines the time period tRTP. After the time period tDSA (P) elapses after the word line WDL is deactivated, the sense amplifier activation signal is deactivated, and the voltage BTL (H) or BTL (L) of the bit line returns to the voltage VBTL. Thereafter, the next activation command A can be received again.

In the above description, the time periods tRCD (R), tRTP, and tRP are defined by the operation of the memory array 23-n in the memory 5, particularly the operation speed of the word line WDL and the bit line BTL. In particular, the operation speed of the bit line BTL is determined by the parasitic resistance RBTL of the bit line BTL. In general, as the memory array becomes finer, the parasitic resistance RBTL increases and the operation speed of the bit line BTL decreases.

Next, the write operation of the memory system according to the comparative example will be described with reference to FIGS.

As described above, in the prior art memory controller, the time period tRCD (W) from the time when the activation command for a certain bank is issued until the time when the write command for the same bank can be issued is the activation command for a certain bank. It was the same as the time period tRCD (R) from when it was issued until it became possible to issue a read command for the same bank.

FIG. 12 is a timing chart showing a data write operation according to the comparative example of the first embodiment. FIG. 12 shows a case where continuous write access is made to the same bank. FIG. 12 also shows the clock CLK and command CMD transmitted from the memory controller 3 to the memory 5, the internal state of the memory 5, and the transmission of data on the external data bus, as in FIG. The command CMD “A” indicates an activation command, “W” indicates a read command, and “P” indicates a precharge command. “WD” in the external data bus represents write data output from the memory controller 3. The internal state iWR indicates a state in which a write operation is actually performed in the memory array 23-n in the memory 5. The time period tRC (W) indicates the time from the activation command A to the activation command A when writing continuously in the same bank, and represents the actual cycle time of the write operation. When tRCD (W) = 4 × tCK, tRP = 4 × tCK, tWR = 4 × tCK, WL = 4, and BL = 4, tRC (W) = 18 × tCK. The time period tD (W) indicates a time from when the memory 5 completes reception of the entire data WD transmitted from the memory controller 3 to when the internal state iWR starts. In the example of FIG. 12, tRC (W) = 18 × tCK is necessary to write data continuously. In general, the time period tRC (W) for the write operation is longer than the time period tRC (R) for the read operation. The time that the write data occupies in the external data bus is 2 × tCK, the utilization rate of the external data bus is 2/18, and the utilization efficiency is lower than in the case of the read operation.

FIG. 12 shows an example in the case of a memory system conforming to the DDR2-SDRAM JEDEC standard. Other SDRAMs such as DDR3 / 4-SDRAM and LPDDR2 / 3 / 4-SDRAM can operate in the same manner as in FIG. Generally, the external data bus utilization efficiency at the time of writing is lower than that at the time of reading.

FIG. 13 is a timing chart showing the waveform of each signal when the write operation of FIG. 12 is performed. FIG. 13 shows the internal state of the memory 5 in the case of FIG. 12, the horizontal axis shows time, and the vertical axis shows voltage. FIG. 11 is an example showing voltage waveforms of internal signals of the memory 5 shown in FIGS. 5, 6, and 7. In FIG. 13, as internal signals of the memory 5, a signal of the column selection line CSL, sense amplifier activation signals SAPE and SANE, a signal of the word line WDL, and a signal of the bit line BTL are shown. The voltages SN (H) and SN (L) are shown.

Referring to FIG. 13, from the input of the activation command A to the activation of the sense amplifier SA (that is, activation of the sense amplifier activation signals SAPE and SANE) is the same as in the read operation of FIG. After waiting for the time period WL of the write latency and the time period BL / 2 × tCK for the memory 5 to capture the write data WD, the signal of the column selection line CSL is timed after the elapse of the time period tD (W). Activate over t (iWR). At this time t (iWR), internal write (internal state iWR) is actually executed for the memory array 23-n. Over a time period t (iWR), the IO switch IOSW is turned on by the activation of the column selection line CSL, and the pair of bit lines BTL, / BTL are connected to the pair of signal lines LIO, / LIO of the LIO bus via the IO switch IOSW. Connected, data of the LIO bus is written to the bit line BTL. At this time, if the data of the bit lines BTL, / BTL is different from the data of the signal lines LIO, / LIO of the LIO bus, the data of the bit line amplified by the sense amplifier SA is inverted. However, due to the parasitic resistance RBTL of the bit line BTL, in the bit line BTL, the data line in the section far from the sense amplifier SA and the IO switch IOSW is completely inverted, that is, the bit line voltage BTL (H ) Becomes voltage BTL (L) = VSS, and conversely, it takes time for the voltage BTL (L) of the bit line to become voltage BTL (H) = VARY. In general, since the PMOS transistor has a weaker driving capability than the NMOS transistor, the transition time from “L” to “H” of the bit line BTL is particularly longer than the transition time from “H” to “L”. long. Furthermore, since the cell transistor CT has a low driving capability and is constituted by an NMOS transistor, the transition time of the storage node SN from “L” to “H” becomes even longer.

Referring to FIG. 13, the word line WDL is deactivated after the time period tDWL (P) has elapsed since the input of the precharge command P. The cell transistor CT is turned off by deactivation of the word line WDL, and the data of the bit line BTL is confined in the storage node SN. That is, new data is written into the memory cell C. This is called an inversion write operation of the memory cell C. As described above, it takes a long time to transition the storage node SN from “L” to “H” due to the bit line parasitic resistance RBTL, the weak driving capability of the PMOS transistor SAPT of the sense amplifier SA, and the resistance of the cell transistor CT. . The length of the time period tWR is determined according to the characteristics of the memory array 23-n, and a relatively long time is required. After the time period tDSA (P) elapses after the word line WDL is deactivated, the sense amplifier activation signal is deactivated, and the voltage BTL (L) or BTL (L) of the bit line returns to the voltage VBTL. . Thereafter, the next activation command A can be received again.

12 and 13, the time period tWR is particularly long. In general, as the memory array becomes finer, the parasitic resistance RBTL increases, the driving capability of the PMOS transistor SAPT of the sense amplifier SA decreases, and the driving capability of the cell transistor CT decreases. For these reasons, the time period tWR increases.

In contrast, the write operation of the memory system according to the first embodiment will be described next with reference to FIGS. 14 and 15.

FIG. 14 is a timing chart showing the data write operation according to the first embodiment. FIG. 14 shows a case where continuous write access is made to the same bank. In the write operation of FIG. 14, the greatest feature is that the write command W is issued before the activation command A. That is, the time period tRCD (W) has a negative value. In this embodiment, tRCD (W) = − 2 × tCK. When writing data to the memory 5, the control circuit 11 of the memory controller 3 sends the write command W to the memory 5 ahead of the time period tRCD (W) before sending the activation command A to the memory 5. . By using the command sequence of FIG. 14, it is possible to shorten the time from when the activation command A is issued to when the write operation (internal state iWR) is actually performed on the memory array 23-n in the memory 5. As a result, the time period tRC (W) can be shortened. In the example of the first embodiment, tRC (W) = 13 × tCK, which is shortened by a time of 5 × tCK compared to tRC (W) = 18 × tCK in the comparative example of FIGS. ing. The time that the write data occupies in the external data bus is 2 × tCK, and the utilization rate of the external data bus is improved to 2/13.

As described above, the time period tRCD (W) indicates the minimum value of the time difference from when the activation command A for a certain bank is issued until the write command W can be issued for the same bank. tRCD (W) has a smaller value than the time period tRCD (R). Therefore, when writing data into the memory 5, the control circuit 11 of the memory controller 3 issues the write command W after the moment separated by the time period tRCD (W) with reference to the moment when the activation command A is issued.

Also, the time period tRCD (W) may have a negative value. In this case, when the control circuit 11 of the memory controller 3 writes data to the memory 5, after the moment preceding by the time period equal to the absolute value of the time period tRCD (W) with reference to the moment when the activation command A is issued. The write command W is issued prior to the moment of issuing the activation command. The chip control circuit 22 of the memory 5 operates in response to the tRC (W) shortening signal, so that when writing data into the memory 5, the absolute value of the time period tRCD (W) with reference to the moment of receiving the activation command. The write command can be received from the memory controller 3 after the moment preceding by the time period equal to and before the moment of receiving the activation command. In the example of FIG. 14, the control circuit 11 of the memory controller 3 issues the write command W at the moment preceding by a time period equal to the absolute value of the time period tRCD (W) with reference to the moment when the activation command A is issued. is doing.

FIG. 14 shows an example of a memory system compliant with the DDR2-SDRAM JEDEC standard. Other SDRAMs such as DDR3 / 4-SDRAM and LPDDR2 / 3 / 4-SDRAM can operate in the same manner as in FIG.

FIG. 15 is a timing chart showing the waveform of each signal when the write operation of FIG. 14 is performed. FIG. 15 shows the internal state of the memory 5 in the case of FIG. 14, the horizontal axis indicates time, and the vertical axis indicates voltage. When the sense amplifier activation signals SAPE and SANE are activated, the column selection line CSL is activated during the amplification of the bit line voltage BTL (H) or BTL (L) or immediately after the amplification, and the write operation (internal state) iWR). Thereby, the time period tRC (W) can be significantly shortened.

According to the memory system according to the first embodiment, the time period tRC (W) when the write operation is performed can be set independently of the time period tRC (R) when the read operation is performed.

As described above, according to the memory system of the first embodiment, even when data is written to one or a plurality of banks by a command sequence including a precharge command, the use efficiency of the external data bus is improved. It can be made difficult to reduce.

By operating the memory system according to the first embodiment, it is possible to increase the use efficiency of the external data bus rather than using the current general-purpose DRAM timing parameters disclosed in the JEDEC standard. As a result, the operation speed of the memory system can be increased.

Embodiment 2. FIG.
In the second embodiment, a configuration for further speeding up the write operation as compared with the memory system according to the first embodiment will be described.

FIG. 16 is a block diagram showing the column decoder 25-n and its periphery in the memory system according to the second embodiment. The column decoder 25-n includes individual decoders 61-0, 61-1, 61-2,... And CSL drivers 62-0, 62-1, 62-2,. ... with. Each of the CSL drivers 62-0, 62-1, 62-2,... Is supplied with a voltage VCSL from an external power source. The voltage when each column selection line CSL0, CSL1, CSL2,... Is activated is determined by the voltage VCSL. As a power source for each CSL driver 62-0, 62-1, 62-2,... With. When reading data from the memory 5, the switch SWR is turned on to supply the voltage VCSLR to each of the CSL drivers 62-0, 62-1, 62-2,. When data is written to the memory 5, the switch SWW is turned on to supply the voltage VCSLW to each of the CSL drivers 62-0, 62-1, 62-2,. .. By switching the voltage VCSL supplied to the CSL drivers 62-0, 62-1, 62-2,... Of the column decoder 25-n between the read period and the write period. The voltage at the time is switched between read access and write access.

FIG. 17 is a timing chart showing waveforms of signals when a data write operation according to a comparative example of the second embodiment is performed. With reference to FIG. 17, a problem when the time period tRC (W) of the first embodiment is further shortened will be described. FIG. 17 shows the internal state of the memory 5 in the case of FIG. 14 as in FIG. 15, the horizontal axis shows time, and the vertical axis shows voltage. FIG. 17 shows voltages SN (H) and SN (L) of the storage node SN of the memory cell C in addition to the signals of FIG. In particular, when the bit line voltage BTL (L) is rewritten to “H” by activating the column selection line CSL and performing a write operation (internal state iWR), the bit line parasitic resistance RBTL and the PMOS transistor SAPT of the sense amplifier SA Due to the weak driving capability and the resistance of the cell transistor CT, it takes a long time to transition the storage node SN from “L” to “H”. This is a problem that the time period tWR described with reference to FIG. 13 is large. If the time period tWR is not sufficiently long, insufficient writing of the voltage of the storage node SN to “H” occurs. Insufficient writing of the voltage of the storage node SN causes a shortage of the voltage read when the memory cell C is next read-accessed, which causes a malfunction. From the above, in order to further shorten the time period tRC (W), it is essential to shorten the time period tWR.

FIG. 18 is a timing chart showing waveforms of signals when performing a data write operation according to the second embodiment. FIG. 18 shows an example in which the time period tRC (W) of the data write operation according to the first embodiment is further shortened. FIG. 18 shows the internal state of the memory 5 in the case of FIG. 14 as in FIG. If the voltage for activating the column selection line CSL is too high at the time of reading, the operation of the sense amplifier SA becomes unstable, and there is a possibility that the data amplified in the bit line BTL is destroyed. Therefore, the voltage for activating the column selection line CSL at the time of reading is limited. On the other hand, at the time of writing, it is necessary to reliably rewrite the data on the bit line BTL with data from the outside. It can be rewritten at high speed. Further, particularly when the bit line voltage BTL (L) is rewritten to “H” by activating the column selection line CSL and performing the write operation (internal state iWR), the capacity of the PMOS transistor SAPT of the sense amplifier SA is insufficient. Therefore, it takes time to charge the bit line BTL to “H”. However, by increasing the voltage of the column selection line CSL, it is possible to inject current for directly writing “H” data from the pair of signal lines of the LIO bus in the “H” state to the pair of sense amplifiers SA. The charging time to “H” of the bit line BTL can be shortened.

Further, when reading data from the memory 5, the time for activating the column selection line CSL and applying the voltage VCSLW when writing data to the memory 5 is longer than the time length for activating the column selection line CSL and applying the voltage VCSLR. The length may be increased. This can further improve the effect of speeding up the write operation.

In addition to the effect of the first embodiment, the memory system according to the second embodiment can further shorten the time period tRC (W) by shortening the time period tWR.

Embodiment 3. FIG.
In the third embodiment, a configuration for further speeding up the write operation as compared with the memory system according to the first embodiment will be described.

FIG. 19 is a timing chart showing waveforms of signals when performing a data write operation according to the third embodiment. FIG. 19 shows an example in which the time period tRC (W) of the data write operation according to the first embodiment is further shortened. FIG. 19 shows the internal state of the memory 5 when the time period tRCD (W) is a negative value according to the first embodiment. The signal BTLEQ is deactivated (transition from “H” to “L”) after the elapse of the time period tDF (A) since the activation command A is taken in, and the subarray selection signal SUBASEL is activated at the same time or almost simultaneously ( Transition from “L” to “H”). At the same time, the pair of signal lines LIO and / LIO of the LIO bus changes from the voltage VBTL to the voltage VARY (or higher voltage). The above operation is similarly executed in the first and second embodiments, and is also executed in a normal DRAM. In the third embodiment, when writing data to the memory 5, the chip control circuit 22 activates the column selection line after receiving the write command and before activating the sense amplifier. Alternatively, in the third embodiment, when writing data to the memory 5, the chip control circuit 22 activates the column selection line after receiving the write command and before activating the sense amplifier and the word line. It is characterized by that. With this operation, the pair of bit lines BTL and / BTL corresponding to the unselected column selection line CSL performs the same operation as in the first embodiment. On the other hand, in the pair of bit lines BTL, / BTL corresponding to the selected column selection line CSL, the activation of the column selection line CSL causes the pair of bit lines BTL, / LIO from the pair of signal lines LIO, / LIO of the LIO bus. A current flows into the BTL, and the pair of bit lines BTL and / BTL are both fixed to the voltage VARY. Subsequently, the write operation is started by supplying write data to the pair of signal lines LIO and / LIO of the LIO bus via the pair of signal lines GIO and / GIO of the GIO bus (time period t (iWR)). At this time, since both of the pair of bit lines BTL and / BTL are at the voltage VARY in advance, only the transition from “H” to “L” occurs in the bit line.

As described with reference to FIGS. 13 and 17, the time period tWR becomes longer due to the time required for the transition from “L” to “H” of the bit line. By the operation of FIG. 19, it is possible to eliminate the transition from “L” to “H” of the bit line after the write operation, and the time period tWR is shortened. By shortening the time period tWR, the time period tRC (W) can be further shortened.

FIG. 20 is a timing chart showing waveforms of signals when a data write operation according to a modification of the third embodiment is performed. In the write operation of FIG. 19, by writing “H” data of the voltage VARY to the pair of bit lines BTL, / BTL corresponding to the selected column selection line CSL, the sense amplifier corresponding to the selected column selection line CSL There is a possibility that the pair of SA NMOS transistors SANT starts operating before the activation of the sense amplifier SA, resulting in malfunction. In order to avoid such a malfunction, the voltage when the sense amplifier activation signal SANE is inactive is changed from the voltage VBTL = 1/2 × VARY to the voltage VARY. When the sense amplifier SA is deactivated, a voltage VARY equal to the upper limit voltage of the bit line BTL is applied to the source of the NMOS transistor of the sense amplifier SA, and when the sense amplifier SA is activated, it is equal to the lower limit voltage of the bit line BTL. The voltage VSS is applied to the source of the NMOS transistor of the sense amplifier SA. By setting this voltage, malfunction of the pair of NMOS transistors SANT of the sense amplifier SA can be prevented. It should be noted that the voltage when the pair of PMOS transistors SAPT of the sense amplifier SA is inactive may be the voltage VSS as shown in FIG. 20 or may be the voltage VBTL as in the prior art.

Embodiment 4 FIG.
In the fourth embodiment, a configuration for further speeding up the write operation as compared with the memory system according to the first embodiment will be described.

FIG. 21 is a block diagram illustrating a configuration of a chip control circuit 22A of the memory system according to the fourth embodiment. In the memory system according to the fourth embodiment, the memory 5 includes a chip control circuit 22A in FIG. 21 instead of the chip control circuit 22 in FIG. The chip control circuit 22A includes a command decoder 34 and a bank address control circuit 35 in addition to the components of the chip control circuit 22 of FIG. The column address control circuit 36 and the row address control circuit 37 provide functions similar to the column address control circuit 42 and the row address control circuit 41 of FIG. 4 and also provide functions according to the fourth embodiment. In FIG. 21, only the command decoder 34, the bank address control circuit 35, the column address control circuit 36, and the row address control circuit 37 are shown for simplification of illustration.

In the memory system according to the fourth embodiment, the memory controller 3 issues a write command before the activation command, as in the first embodiment. In the memory system according to the fourth embodiment, the memory controller 3 issues a special write command (first write command FW) including a part of the row address of the subarray including the memory cell to which data is written as a write command. In the write command, a part of the row address of the subarray activated by the subsequent activation command is given in advance, so that the memory 5 can select the subarray to be activated prior to the reception of the activation command. And

In the chip control circuit 22A, the command decoder 34 recognizes the fast write command, thereby generating a bank address and a column address as a target of the write operation, and further generates a sub-array row address. The row address of the subarray is an address that designates the subarray (FIG. 5) to be activated, and is a part of the row address. The chip control circuit 22A outputs the bank address and column address used for these write operations to the address bus of the column address signal CA-n, and outputs the row address to the address bus of the row address signal RA-n. The row address of the subarray activates the subarray selection signal SUBASEL corresponding to the subarray activated when the next activation command is issued (FIG. 5), and turns on the subarray selection switch SASW of the activated subarray. . By turning on the subarray selection switch SASW, the voltage VARY is applied only to the pair of signal lines LIO and / LIO of the LIO bus of the activated subarray. The memory 5 can perform the above operation when it receives the first write command before receiving the activation command.

FIG. 22 is a circuit diagram showing a configuration of an equalize circuit connected to the bit line of the memory system according to the fourth embodiment. In the bit line equalize circuit of FIG. 22, the bit line equalize circuit of FIG. 8 includes a circuit for fixing a pair of bit lines BTL and / BTL to voltage VBTL by a first bit line equalize signal BTLEQ1, and a second bit line equalize The signal BTLEQ2 separates the pair of bit lines BTL and / BTL into circuits that equalize the same voltage. Although not shown, the first bit line equalize signal BTLEQ1 signal is further separated into signals BTLEQ10 and BTLEQ11, the signal BTLEQ10 is used to fix the voltage VBTL of one bit line BTL, and the other bit line / BTL The signal BTLEQ11 may be used to fix the voltage VBTL.

FIG. 23 is a circuit diagram showing a configuration of a sub-array selection switch SASW in the memory system according to the fourth embodiment. According to the sub-array selection switch SASW in FIG. 23, in the sub-array selection switch SASW in FIG. Done.

FIG. 24 is a timing chart showing waveforms of signals when a data write operation according to the fourth embodiment is performed. FIG. 24 shows an example in which the time period tRC (W) of the data write operation according to the first embodiment is further shortened. FIG. 24 shows the internal state of the memory 5 when the time period tRCD (W) is a negative value according to the first embodiment. In the data write operation according to the fourth embodiment, a special fast write command FW is used instead of the write command W. The first write command FW is input prior to the activation command A of the corresponding bank. That is, the time period tRCD (W) has a negative value. Further, the first write command FW is characterized in that a part of the row address of the sub-array can be designated in addition to the normal column address and column bank address. After the time period tDF (W) has elapsed since the first write command FW was received, the bit line equalize signal BTLEQ1 is deactivated and the subarray selection signal SUBASEL is activated. Further, the column selection line CSL is activated almost simultaneously. At the same time, the pair of signal lines LIO and / LIO of the LIO bus changes from the voltage VBTL to the voltage VARY (or higher voltage). With this operation, the pair of bit lines BTL and / BTL corresponding to the unselected column selection line CSL operates in the same manner as in the first embodiment. On the other hand, in the pair of bit lines BTL, / BTL corresponding to the selected column selection line CSL, the activation of the column selection line CSL causes the pair of bit lines BTL, / LIO from the pair of signal lines LIO, / LIO of the LIO bus. A current flows into the BTL, and the pair of bit lines BTL and / BTL are both fixed to the voltage VARY. Here, since the change from the voltage VBTL to the voltage VARY of the pair of bit lines BTL and / BTL corresponding to the selected column selection line CSL is performed under the activation of the bit line equalization signal BTLEQ2, the pair of bit lines BTL. , / BTL voltage equalization is continued. Therefore, noise to the pair of bit lines BTL and / BTL corresponding to the unselected column selection line CSL in the vicinity of the pair of bit lines BTL and / BTL corresponding to the selected column selection line CSL is reduced, and the malfunction is caused. Is prevented. Thereafter, the bit line equalize signal BTLEQ2 is deactivated after the elapse of the time period tDF (A) since the activation command A was received. Subsequently, the write operation is started by supplying write data to the pair of signal lines LIO and / LIO of the LIO bus via the pair of signal lines GIO and / GIO of the GIO bus (time period t (iWR)). At this time, since both of the pair of bit lines BTL and / BTL are at the voltage VARY in advance, only the transition from “H” to “L” occurs in the bit line.

As described above, in the fourth embodiment, the chip control circuit 22A of the memory 5 activates the subarray specified by the row address of the first write command, and sets the column selection line specified by the column address of the first write command. The bit line voltage corresponding to the activated column selection line is set to an upper limit voltage.

As described with reference to FIGS. 13 and 17, the time period tWR becomes longer due to the time required for the transition from “L” to “H” of the bit line. With the operation in FIG. 24, it is possible to eliminate the transition from “L” to “H” of the bit line after the write operation, and the time period tWR is shortened. At the same time, a stable write operation is guaranteed. By shortening the time period tWR, the time period tRC (W) can be further shortened.

Embodiment 5. FIG.
In the fifth embodiment, a configuration for further speeding up the write operation by a method different from that of the first embodiment will be described.

FIG. 25 is a block diagram illustrating a configuration of the memory controller 3A of the memory system according to the fifth embodiment. 25 includes a control circuit 11A and a timing register 13A instead of the control circuit 11 and the timing register 13 of the memory controller 3 of FIG. The timing register 13 </ b> A stores a plurality of timing parameters related to the operation of the memory 5. These timing parameters include time periods tRCD, tRP, CL, WL1, and WL2. The time period tRCD indicates a minimum value of a time difference from when an activation command for a certain bank is issued until a read command and a write command can be issued for the same bank. The time periods tRP and CL are the same as those in the first embodiment. The time period WL1 is a time difference from when the write command is issued to when data is transmitted from the memory controller 3A to the memory 5, and indicates the length of the time period equal to the write latency (WL) conforming to the JEDEC standard. The time period WL2 is a time difference from when the write command is issued to when data is transmitted from the memory controller 3A to the memory 5, and indicates a length of time period shorter than the write latency (WL) based on the JEDEC standard. . The control circuit 11A is characterized by switching the write latency time periods WL1 and WL2 as appropriate according to the operating state. The control circuit 11A uses the time period WL1 in a normal write operation in accordance with the JEDEC standard, and uses the time period WL2 in a write operation in which the time period tRC (W) is shortened.

In this specification, the time period WL2 is also referred to as a “third time period”, and the time period WL1 is also referred to as a “fourth time period”.

The operating state of the memory system may be set, for example, by the memory controller 3A receiving a control signal from the processor 1, or by providing a signal source fixed in the activated state inside the memory controller 3A.

FIG. 26 is a timing chart showing a data write operation according to the fifth embodiment. In the fifth embodiment, the write latency can be set to a time period WL2 that is shorter than the time period WL defined in the JEDEC standard. For example, the time period WL2 may be set to 4 clock cycles. In particular, FIG. 26 shows the case where a negative time period WL2 is used. When writing data to the memory 5, the control circuit 11 </ b> A transmits data from the memory controller 3 </ b> A to the memory 5 by preceding the write command to the memory 5 by a time period equal to the absolute value of the time period WL <b> 2. . By using the negative time period WL2, even when the time period tRCD is a value stipulated in the JEDEC standard, it is possible to shorten the time from the capture of the write command W to the write operation (internal state iWR) in the memory 5. is there.

When writing data to the memory 5, the control circuit 11 of the memory controller 3 transmits data from the memory controller 3 to the memory 5 at the moment separated by the time period WL 1 or the time period WL 2 with reference to the moment when the write command W is issued. Start. When the time period WL2 has a negative value, the control circuit 11 of the memory controller 3 only writes a time period equal to the absolute value of the time period WL2 based on the moment when the write command is issued when writing data to the memory 5. At the preceding moment, data transmission from the memory controller 3 to the memory 5 is started.

The time period WL2 may have a positive length shorter than the write latency (WL) conforming to the JEDEC standard.

According to the fifth embodiment, the time period tRC (W) can be shortened by a method different from that of the first embodiment, and the write operation can be speeded up.

Embodiment 6. FIG.
In the sixth embodiment, a memory system capable of speeding up a read operation will be described.

FIG. 27 is a block diagram illustrating a configuration of the memory controller 3B of the memory system according to the sixth embodiment. The memory controller 3B in FIG. 27 includes a control circuit 11B and a timing register 13B instead of the control circuit 11 and the timing register 13 of the memory controller 3 in FIG. The timing register 13B stores a plurality of timing parameters related to the operation of the memory 5. These timing parameters include time periods tRC (W) and tRC (R). The time period tRC (W) indicates the shortest time during which an activation command for a certain bank can be issued continuously when data is written to the memory. The time period tRC (R) indicates the shortest time during which an activation command for a certain bank can be issued continuously when data is read from the memory. The control circuit 11B controls the memory based on the time period tRC (R).

In this specification, the time period tRC (R) is also referred to as a “fifth time period”.

The memory of the memory system according to the sixth embodiment is configured similarly to the memory 5 of the memory system according to the first embodiment, for example. In this case, the memory 5 may include a chip control circuit in which a circuit portion related to the tRC (W) shortening signal is removed from the chip control circuit 22 in FIG. 4 instead of the chip control circuit 22 in FIG. Hereinafter, the memory of the memory system according to the sixth embodiment is referred to as “memory 5”.

When the chip control circuit 22 of the memory 5 writes data to the memory 5, it writes the same data to at least two of the plurality of banks. When reading data from the memory 5, the chip control circuit 22 of the memory 5 reads data from one of at least two banks in which the same data of the plurality of banks is written. The control circuit 11B of the memory controller 3B controls the memory 5 so as to execute such writing and reading.

FIG. 28 is a block diagram for explaining an operation of writing data to the memory 5 of the memory system according to the sixth embodiment. FIG. 29 is a block diagram for explaining a data read operation from the memory 5 of the memory system according to the sixth embodiment. The memory 5 in FIGS. 28 and 29 has the same configuration as the memory 5 in FIG. Hereinafter, a case where data is written to the banks B1 and B2 connected to the common internal data bus DB1 and data is read from the banks B1 and B2 will be described.

Referring to FIG. 28, first, banks B1 and B2 are simultaneously activated with the same row address. That is, the row address signals RA-1 and RA-2 are the same address, and the row address activation signals RAE-1 and RAE-2 are activated simultaneously. As a result, in these two banks B1 and B2, the word lines WDL having the same address in the memory array 23-n are simultaneously activated. During the subsequent write operation in the memory 5, the same column addresses of these two banks B1 and B2 are simultaneously activated. That is, the column address signals CA-1 and CA-2 are the same address, and the column address activation signals CAE-1 and CAE-2 are activated simultaneously. At the same time, these two banks B1 and B2 are simultaneously supplied with the same write data from the internal data bus DB1. As a result, in these two banks B1 and B2, the column selection line CSL having the same address in the memory array 23-n is simultaneously activated, and the same data is written to the memory cell C having the same address. By repeating such a write operation, the data stored in the banks B1 and B2 can be completely matched.

During the write operation, according to the first to fourth embodiments, the time period tRCD (W) having a value smaller than the time period tRCD (R) is set, or the time period tRCD (W) having a negative value is set. The time period tRC (W) may be shortened by issuing a write command before issuing an activation command. In the write operation, according to the fifth embodiment, the write latency time period WL may be shortened or set to a negative value to shorten the time period tRC (W).

As described above, when data is written to the memory 5 or when data is read from the memory 5, the shortest time (time period tRC (W) and tRC (R)) in which an activation command for a certain bank can be issued continuously is determined. Exists. In the fifth embodiment, when reading data from the memory 5, the memory controller 3B and the memory 5 operate as follows. The control circuit 11B of the memory controller 3B reads the first and second activation commands at intervals shorter than the time period tRC (R) in order to read data from at least two banks in which the same data among the plurality of banks is written. Is issued, a second command including a bank address different from the bank address included in the first activation command is issued. When the chip control circuit 22 of the memory 5 receives the first and second activation commands, the chip control circuit 22 of the memory 5 responds to the first activation command and the first of the at least two banks in which the same data is written. Data is read from one bank, and data is read from a second bank of at least two banks in which the same data is written in response to a second activation command. In this way, the first and second activation commands are issued at intervals shorter than the time period tRC (R) to read data from the memory 5, thereby equivalently shortening the time period tRC (R), The read operation of the memory system can be speeded up.

Referring to FIG. 29, at the time of a read operation, first, banks B1 and B2 are activated separately. In other words, the row address signal RA-1 is applied to the bank B1 and the row address activation signal RAE-1 is activated to access the bank B1, and the row address signal RA different from the row address signal RA-1 is accessed to the bank B2. -2 is applied to activate the row address activation signal RAE-2. As a result, in these two banks B1 and B2, the word lines WDL of the memory array 23-n are activated independently. During the subsequent read operation in the memory 5, column addresses are activated independently in these two banks B1 and B2. For example, in the even-numbered read operation, the column address signal CA-1 is supplied to the bank B1 and the column address activation signal CAE-1 is activated. In the odd-numbered read operation, the column address signal CA1 is supplied to the bank B2. CA-2 is applied, and the column address activation signal CAE-2 is activated. Thereafter, reading is similarly controlled. As a result, in these two banks B1 and B2, the column selection lines CSL of the different column addresses of the memory array 23-n are alternately activated by the even-numbered read operation and the odd-numbered read operation. Data is alternately read from the memory cells C at different addresses of B2, and the read data is read to the internal data bus DB1. As a result, data is alternately read from memory cells C having different row and different column addresses in two banks having different bank addresses and having the same data written therein.

Since the same data is written in the memory cell C at the same address in these two banks B1 and B2, the time period tRC that defines the cycle of read access in the same bank using the two banks B1 and B2. (R) allows two read operations. That is, the time period tRC (R) can be equivalently reduced to ½ on average as compared with the first embodiment.

FIG. 28 and FIG. 29 are examples in the case where the memory 5 includes four banks B1 to B4. Even when the memory 5 includes two banks, eight banks, etc., the read operation can be similarly accelerated. Can do.

FIG. 28 and FIG. 29 show an example in which two banks are simultaneously written and read independently from two banks. However, even when data is simultaneously written in four banks and read independently from four banks, the read operation is similarly performed at high speed. Can be In this case, the time period tRC (R) can be equivalently shortened to ¼ on average compared to the first embodiment.

Next, a command format for realizing the write operation according to the sixth embodiment will be described with reference to FIG. 30 and FIG.

FIG. 30 is a diagram illustrating an activation command used in the memory system according to the sixth embodiment. FIG. 31 is a diagram illustrating a write command used in the memory system according to the sixth embodiment. 30 and 31, a case where the memory 5 and the memory controller 3B are LPDDR4-SDRAMs will be described. FIG. 30 shows an example of an activation command for LPDDR4-SDRAM, and FIG. 31 shows an example of a write command for LPDDR4-SDRAM.

• Multiple banks have bank addresses that include multiple bits. When the chip control circuit 22 of the memory 5 writes data to the memory 5, the memory cell having the same row address in at least two banks each having a bank address including at least one same bit value among the plurality of banks. Write the same data. The control circuit 11B of the memory controller 3B controls the memory 5 so as to execute such writing.

In the example of FIGS. 30 and 31, the memory controller 3B and the memory 5 degenerate one bit among a plurality of bits of the bank address using mode register setting or fuse trimming that is not defined in the JEDEC standard. Enter the mode.

The activation command in FIG. 30 is configured using four periods (four rising edges) of the clock CK_t, and the first two periods are referred to as a command part ACT-1, and the latter two periods are referred to as ACT-2. Call. The activation command of FIG. 30 includes a bank address consisting of three bits BA2, BA1, and BA0, so that eight banks can be addressed. The bit CA3 of the second period of the command part ACT-1 is empty. Bit BD (Bank-Degeneration) is newly allocated to this bit. When “BD = 1”, bit BA0 is degenerated, and when “BD = 0”, bit BA0 is not degenerated.

The write command in FIG. 31 is configured using four periods (four rising edges) of the clock CK_t, the first two periods are referred to as a command part WR-1, and the latter two periods are referred to as a command part CAS-2. Call it. The write command of FIG. 31 also includes a bank address consisting of three bits BA2, BA1, BA0, so that eight banks can be addressed. The bit CA3 of the second period of the command part WR-1 is empty. Bit BD (Bank-Degeneration) is newly allocated to this bit. When “BD = 1”, bit BA0 is degenerated, and when “BD = 0”, bit BA0 is not degenerated.

When the write operation of FIG. 28 is performed, the control circuit 11B of the memory controller 3B sets “BD = 1” when issuing the activation command, and also when “BD ==” is issued when issuing the write command. 1 ”is set. By configuring and setting the memory controller 3B and the memory 5 as described above, the bit BA0 of the bank address is degenerated, so that the same data can be simultaneously written in the banks B1 and B2.

On the other hand, when the read operation of FIG. 29 is performed, the control circuit 11B of the memory controller 3B sets “BD = 0” when issuing the activation command, and also when the write command is issued. BD = 0 "is set. By configuring and setting the memory controller 3B and the memory 5 as described above, it is possible to read data independently from the banks B1 and B2 without degenerating the bit BA0 of the bank address during the read operation.

As described above, data can be simultaneously written to two banks during a write operation using an activation command and a write command, and data can be read independently from the two banks during a read operation using an activation command and a read command. It is. Therefore, the time period tRC (R) can be equivalently shortened to ½ compared to the first embodiment.

As for the precharge command, the BD bit for determining the presence / absence of degeneration can be set as in the case of the activation command and the write command.

In place of the example of FIGS. 30 and 31, the memory controller 3B and the memory 5 may use two or more bits of a plurality of bits of the address by using mode register setting or fuse trimming not defined in the JEDEC standard. You may enter a mode to degenerate. For example, the bits BA0 and BA1 are degenerated when “BD = 1”, and the bits BA0 and BA1 are not degenerated when “BD = 0”. In this case, the same data can be simultaneously written in the four banks during the write operation using the activation command and the write command, and independent from the four banks during the read operation using the activation command and the read command. It is possible to read out data. Therefore, the time period tRC (R) can be equivalently shortened to ¼ compared to the first embodiment. In this case, if tCCD (R) = tRC (R) / 4 can be realized for the time period tCCD (R) at the time of reading, the read operation can maximize the efficiency of the external data bus regardless of bank competition. Is possible.

FIG. 32 is a timing chart showing a data write operation according to a modification of the sixth embodiment. FIG. 32 illustrates a case where the memory 5 and the memory controller 3B are LPDDR4-SDRAMs. In the example of FIG. 32, the memory controller 3B and the memory 5 are in a mode in which at least one bit of the plurality of bits of the bank address is degenerated using mode register setting or fuse trimming that is not defined in the JEDEC standard. enter. In this degenerated mode, the memory controller 3B and the memory 5 operate by linking with the shortening of the time period tRC (W) according to the first to fourth embodiments. That is, in a write operation, a write command is issued before issuing an activation command. Further, the non-degenerate bits in the bank addresses of the write command and the activation command are the same (that is, the bank address includes bits BA1 and BA0, the bit BA0 is degenerated, and the activation command and the write command Bits BA1 have the same value). Thereafter, the issue of the activation command and the write operation in the memory 5 are performed in a state where the bit BA0 of the bank address is degenerated. That is, word lines WDL having the same row address in a plurality of banks are simultaneously activated, column selection lines CSL having the same column address in the same plurality of banks are simultaneously selected, and the same data is simultaneously transmitted to these Written to the bank. This state continues until a precharge command is issued having a bank address that includes the same non-degenerate bit. By this precharge command, a plurality of simultaneously activated banks are precharged simultaneously. On the other hand, the read operation is performed independently without degeneration of the bank address.

According to the memory system according to the sixth embodiment, the time period tRC (R) when the read operation is performed can be set independently of the time period tRC (W) when the write operation is performed.

According to the memory system according to the sixth embodiment, it is possible to speed up both the write operation and the read operation by combining with the configurations and operations of the first to fifth embodiments.

Next, in the seventh to ninth embodiments, the use efficiency of the external data bus is improved when the column operation is successively executed for different banks.

Embodiment 7. FIG.
FIG. 33 is a block diagram illustrating a configuration of the memory controller 3C of the memory system according to the seventh embodiment. A memory controller 3C in FIG. 33 includes a control circuit 11C and a timing register 13C instead of the control circuit 11 and the timing register 13 in the memory controller 3 in FIG. The timing register 13 </ b> C stores a plurality of timing parameters related to the operation of the memory 5. These timing parameters include time periods tRRD, tCCD, and tFAW. The time period tRRD is the length of the time period from when an activation command for a certain bank is issued until an activation command for a different bank can be issued, that is, the activation commands for two different banks are consecutive. The shortest time that can be issued. The time period tCCD is the length of the time period from when a write command or read command for a certain bank is issued until it becomes possible to issue a write command or read command for the next arbitrary bank, that is, any two banks This indicates the shortest time in which a write command or a read command can be issued continuously. The time period tFAW is the length of the time period from when four activation commands are successively issued to the four banks until the activation command can be issued to another bank, ie, Indicates the shortest time in which four activation commands can be issued in succession. The time period tCCD is set equal to the time period tRRD, and the time period tFAW is set equal to four times the time period. The control circuit 11C controls the memory 5 based on the time periods tRCD, tCCD, and tFAW.

In this specification, the time periods tRRD, tCCD, and tFAW are also referred to as “sixth to eighth time periods”, respectively.

FIG. 34 is a block diagram showing the row decoder 24-n and its periphery of the memory system according to the seventh embodiment. The row decoder 24-n includes, for each word line WDL0, WDL1, WDL2,..., Individual decoders 81-0, 81-1, 81-2,... And WDL drivers 82-0, 82-1, 82-2,. Is provided. Each of the WDL drivers 82-0, 82-1, 82-2,... Is supplied with a voltage VPP from a VPP generation circuit 91 that is an external power source of the row decoder 24-n. The voltage when each word line WDL0, WDL1, WDL2,... Is activated is determined by the voltage VPP. The VPP generation circuit 91 operates in response to the operation clock, boosts the voltage VDD supplied from the outside of the memory 5, and generates and outputs a higher voltage VPP.

FIG. 35 is a circuit diagram showing a configuration of the VPP generation circuit 91 of FIG. The VPP generation circuit 91 is a switched capacitor circuit including switches SW1 to SW19 and boost capacitors Ca1 to Ca4. The VPP generation circuit 91 has the following two operation modes that can be switched in accordance with a control signal from the chip control circuit 22. In the first operation mode, the input voltage is boosted by 2.5 times. In the second operation mode, the input voltage is boosted three times. In the first operation mode, the amount of current that can be supplied is not large, but it has high power conversion efficiency and power consumption can be kept low. In the second operation mode, the power conversion efficiency is deteriorated, but the current that can be supplied can be increased. In FIG. 35, the following signals are applied to the switches SW1 to SW19 according to the operation mode. The signal Φ1 matches the two-phase operation clock, and the signal Φ2 matches the inverted signal of the operation clock. Furthermore, the signal Φ1A is always off in the first operation mode and coincides with the operation clock in the second operation mode. The signal Φ1B coincides with the operation clock in the first operation mode, and is always off in the second operation mode. The switches SW3, SW7, SW13, SW15 are always off.

FIG. 36 is a timing chart showing a data read operation according to the seventh embodiment. FIG. 36 shows a case where a plurality of banks are continuously read-accessed. FIG. 36 shows the clock CLK and command CMD transmitted from the memory controller 3 to the memory 5 and the transmission of data on the external data bus. The commands CMD A1, A2, A3,... Represent activation commands for the banks B1, B2, B3,. The commands CMD R1, R2, R3,... Represent read commands for the banks B1, B2, B3,. QD1, QD2, QD3,... On the external data bus represent read data read from the banks B1, B2, B3,. The command CMD is fetched at the rising edge of the clock CLK. tCCD = 4 × tCK, tRRD = 4 × tCK, tFAW = 16 × tCK, tRCD (R) = 7 × tCK, tBL = 1/2 × tCK, CL = 7, BL = 8. When the time periods tRRD, tCCD, tFAW satisfy 1/2 × BL × tCK = tCCD = tRRD = 1/4 × tFAW, the read data QD can be continuously output on the external data bus without interruption, 100% utilization efficiency of external data bus can be realized.

FIG. 37 is a timing chart showing a data write operation according to the seventh embodiment. FIG. 37 shows a case where a plurality of banks are continuously accessed for writing. FIG. 37 also shows the clock CLK and command CMD transmitted from the memory controller 3 to the memory 5, and the transmission of data on the external data bus. The commands CMD A1, A2, A3,... Represent activation commands for the banks B1, B2, B3,. The command CMD W1, W2, W3,... Represents a write command for the banks B1, B2, B3,. WD1, WD2, WD3,... On the external data bus represent write data written from the memory controller 3 to each bank B1, B2, B3,. Commands are captured on the rising edge of CLK. tCCD = 4 × tCK, tRRD = 4 × tCK, tFAW = 16 × tCK, tRCD (R) = 7 × tCK, tBL = 1/2 × tCK, WL = 6, BL = 8. When the time periods tRRD, tCCD, tFAW satisfy 1/2 × BL × tCK = tCCD = tRRD = 1/4 × tFAW, the write data WD can be continuously transmitted on the external data bus without interruption, 100% utilization efficiency of external data bus can be realized.

FIG. 36 and FIG. 37 show an example in the case of a memory system compliant with the DDR3-SDRAM JEDEC standard. Other SDRAMs such as DDR1 / 2 / 4-SDRAM and LPDDR2 / 3 / 4-SDRAM can operate in the same manner as in FIG. 36 and FIG.

However, in the timing parameter compliant with the JEDEC standard, 1/4 × tFAW (min)> tRRD (min)> tCCD (min). The reason why such a restriction occurs in the operation of the DDR-SDRAM will be described. In the DDR-SDRAM, a column selection is performed by amplifying and storing data of a memory cell connected to a word line activated in response to an activation command by a sense amplifier, and activated in response to a write command or a read command (column command). Data is read from or written to the sense amplifier connected to the line CSL. The time period tCCD, ie, the minimum value of the cycle time between write operations or read operations by successive column commands is constrained by the access timing in the memory array when continuously executed in the same bank. With reference to FIGS. 5 and 6, this restriction refers to the capability of the IO switch IOSW arranged in the sense amplifier SA and the data in the bank used for data transmission between the column selection line CSL and the sense amplifier SA. It is practically defined by the parasitic resistance and parasitic capacitance of the bus (GIO bus and LIO bus). Actually, the minimum cycle time of column operation defined by the JEDEC standard is about 4 to 5 nanoseconds in any of the standards of DDR1, DDR2, DDR3, and DDR4-SDRAM. On the other hand, in order to perform the column operation as described above, it is necessary to issue an activation command and activate the word line as a previous step. When read or write access occurs at random, it is necessary to continuously issue activation commands to different banks. However, the minimum cycle time of time period tRRD is defined mainly depending on the supply capability of the VPP generation circuit used for activating word line WDL. Furthermore, from the viewpoint of the average consumption current of the boosted voltage, there is a restriction on the number of activation commands that may be issued within a certain time, that is, the time period tFAW. Accordingly, in the JEDEC standard, 1/4 × tFAW (min)> tRRD (min)> tCCD (min).

In order to achieve 1/4 × tFAW (min) = tRRD (min) = tCCD (min), it is necessary to shorten the time periods tFAW (min) and tRRD (min). In order to shorten the time periods tFAW (min) and tRRD (min), it is necessary to increase the current supply capability of the VPP generation circuit 91.

The VPP generation circuit 91 applies to the word line WDL a voltage VPP set so that the time period tCCD is equal to the time period tRRD and the time period tFAW is equal to four times the time period tRRD. By applying such a voltage VPP to the word lines, the memory 5 sends an activation command and a write command from the chip control circuit 22 with a period equal to the time period tRRD when writing data continuously to the memory 5. It is configured to be receivable. Similarly, when data is continuously read from the memory 5, an activation command and a read command can be received from the chip control circuit 22 with a period equal to the time period tRRD. The control circuit 11 of the memory controller 3 issues an activation command and a write command at a period equal to the time period tRRD when data is continuously written to the memory 5. Similarly, when the control circuit 11 of the memory controller 3 continuously reads data from the memory 5, it issues an activation command and a read command with a period equal to the time period tRRD.

When the memory 5 is in the first operation mode, the upper limit voltage of the word line has a first voltage value, the time period tCCD is shorter than the time period tRRD, and the time period tFAW is more than four times the time period tRRD. long. When the memory 5 is in the second operation mode, the upper limit voltage of the word line has a second voltage value higher than the first voltage value, the time period tCCD is equal to the time period tRRD, and the time period tFAW is the time Equal to four times the period tRRD. The control circuit 11 of the memory controller 3 transmits a control signal (second control signal) for selectively operating the memory 5 in one of the first operation mode and the second operation mode to the memory 5. When the chip control circuit 22 of the memory 5 receives from the memory controller 3 a control signal for selectively operating the memory 5 in one of the first operation mode and the second operation mode, One of the operation mode and the second operation mode is selectively operated.

The operation of the VPP generation circuit 91 in FIG. 35 will be specifically described. When the memory 5 is frequently accessed and the current consumption associated with the boosted voltage is large, that is, in the operation of shortening the time period tRRD (min), the operation is performed in the mode in which the input voltage VDD is boosted three times. . In this ideal circuit configuration, a current of (input voltage × 3 times-target value of boosted voltage) × Ca can be supplied, and the power conversion efficiency is (target value of boosted voltage / (3 × input voltage). )). On the other hand, when the power consumption is kept low as in the self-refresh operation, the operation is performed in the input voltage × 2.5 times boost mode. In this ideal circuit configuration, it is possible to supply a current of (input voltage × 2.5 times−target value of boosted voltage) × Ca, and the power conversion efficiency is (target value of boosted voltage / (2. 5 × input voltage)).

In general, increasing the current supply capability of the booster circuit causes an increase in the layout area of the booster circuit. In the VPP generation circuit 91 of FIG. 35, the step-up ratio is changed according to the control signal instructing the operation mode, and the current supply capability associated with the voltage VPP is increased without significantly increasing the layout area of the VPP generation circuit. be able to.

As shown in FIG. 35, by additionally arranging the extra boost capacitors Ca1 to Ca4, the operation of maximizing the occupancy ratio of the external data bus can be performed without significantly affecting the chip area.

The boost ratios of 2.5 times and 3 times described above are examples, and the optimum boost ratio is set according to the relationship between the input voltage in accordance with each standard and the boost voltage required for the memory array 23-n. The

According to the memory system of the seventh embodiment, the voltage VPP set so that the time period tCCD is equal to the time period tRRD and the time period tFAW is equal to four times the time period tRRD is applied to the word line WDL. By applying to, the use efficiency of the external data bus can be improved when column operations are successively executed for different banks.

Embodiment 8. FIG.
FIG. 38 is a block diagram showing a configuration of the VPP generation circuit 100 of the memory system according to the eighth embodiment. The VPP generation circuit 100 includes a logical sum operation (OR) circuit 101, a logical product operation (AND) circuit 102, and VPP generation circuit portions 103 and 104. In order to generate different output voltages and / or different output currents, the VPP generation circuit 100 includes a plurality of VPP generation circuit portions 103 and 104. Each of VPP generation circuit portions 103 and 104 is configured in the same manner as VPP generation circuit 91 in FIG. However, the VPP generation circuit portions 103 and 104 include capacitors having different capacities.

The VPP generation circuit 100 selectively enables the VPP generation circuit portions 103 and 104 according to the enable signal, the DDR3L signal for instructing the operation mode, and the large current mode signal. The enable signal is input to the AND operation circuit 102 and the VPP generation circuit portion 103. The DDR3L signal and the large current mode signal are input to the logical sum operation circuit 101, and the output signal of the logical sum operation circuit 101 is input to the VPP generation circuit portion 104.

The VPP generation circuit 100 is used in a memory that supports two standards that differ only in input voltage, such as DDR3-SDRAM and DDR3L-SDRAM. The VPP generation circuit portion 103 includes a capacitor having a sufficient capacitance value for generating a voltage for the DDR3-SDRAM, while the VPP generation circuit portion 104 provides a voltage for generating the voltage for the DDR3L-SDRAM. A capacitor with a large capacitance value is provided. By activating the signal DDR3L mode signal indicating which standard is supported, the VPP generation circuit portions 103 and 104 are selectively made operable. Also, when the time periods tRRD and tFAW are to be shortened, the large current mode signal is activated. When the DDR3L signal and the large current mode signal are deactivated, only the VPP generation circuit portion 103 is enabled. When one of the DDR3L signal and the large current mode signal is activated, the VPP generation circuit portion 103 is activated. , 104 are enabled.

Thus, by selectively changing the number of operating VPP generation circuit portions 103 and 104, the boosted voltage VPP can be supplied with a sufficiently large current to improve the utilization efficiency of the external data bus. it can.

Embodiment 9. FIG.
FIG. 39 is a block diagram illustrating a configuration of the memory controller 3D of the memory system according to the ninth embodiment. The memory controller 3D of FIG. 39 includes a control circuit 11D and a timing register 13D instead of the control circuit 11C and the timing register 13C of the memory controller 3C of FIG. The timing register 13D stores a plurality of timing parameters related to the operation of the memory 5D. These timing parameters include time periods tRRD1, tRRD2, tCCD, and tFAW. The time periods tRRD1 and tRRD2 are the lengths of time periods from when an activation command for a certain bank is issued until an activation command for a different bank can be issued, that is, activation commands for two different banks. Indicates the shortest time that can be issued continuously. In the embodiment of FIG. 39, the plurality of time periods tRRD1, tRRD2 are characterized by having different lengths according to different combinations of the two banks. Other time periods tCCD and tFAW are the same as those in the seventh embodiment.

The memory controller 3D is characterized by performing control so that the time periods tRRD1 and tRRD2 are properly used in accordance with the bank addresses of successive activation commands. In particular, in the case of tRRD1 <tRRD2, if the lengths of the time periods tRRD1 and tCCD are set to be the same, the operation according to the first embodiment can be performed although the order of activating the banks is limited.

FIG. 40 is a block diagram illustrating a configuration of the memory 5D of the memory system according to the ninth embodiment. The memory 5D includes a chip control circuit 22D instead of the chip control circuit 22 of the memory 5 of FIG. 3, and further includes power supply circuits 27-1 and 27-2. The power supply circuits 27-1 and 27-2 include VPP generation circuits 91-1 and 91-2 and VARY generation circuits 92-1 and 92-2, respectively. VPP generation circuits 91-1 and 91-2 supply voltage VPP to row decoders 24-1 to 24-4, and VARY generation circuits 92-1 and 92-2 supply voltage VARY to memory arrays 23-1 to 23-4. To supply. In addition to performing the operation according to the first embodiment, the chip control circuit 22D controls the power supply circuits 27-1 and 27-2.

The power supply circuit occupies a large area in the chip, and further, it is necessary to reduce the impedance between the power supply circuit and the power consumption place (mainly the memory array and the row decoder). For this reason, there are cases where a plurality of power supply circuits are arranged and each one of the power supply circuits is shared among a plurality of banks. In the example of FIG. 40, the power supply circuit 27-1 is shared between the banks B1 and B2, and the power supply circuit 27-2 is shared between the banks B3 and B4. Among the power supply circuits 27-1 and 27-2, in particular, the power consumption of the VPP generation circuits 91-1 and 91-2 for driving the word lines WDL and the generation of VARY for driving the bit lines BTL of the memory array 23-n. The power consumption of the circuits 92-1 and 92-2 is large. These powers are further consumed by the activation operation. Therefore, in the example of FIG. 40, it is difficult to supply sufficient power when performing the continuous activation operation of the banks B1 and B2, and further when performing the continuous activation operation of the banks B3 and B4. . Accordingly, the time period tRRD1 (min) is acquired between the banks B1 and B2 as the shortest time period tRRD (min) in which activation commands for two different banks can be issued in succession, and between the banks B1 and B3. If the time period is tRRD2 (min), there may be a case where tRRD2 (min) <tRRD1 (min). When realizing tCCD (min) = tRRD (min) which is a requirement of the operation according to the eighth embodiment, it is necessary to use tRRD2 (min) between the bank B1 and the bank B3.

FIG. 41 is a timing chart showing a data write operation according to the comparative example of the ninth embodiment. FIG. 41 is a diagram in which write operations iWR1, iWR2, iWR3,... To the memory array 23-n are added as the internal state of the memory 5D to the timing chart of FIG. FIG. 41 shows a case where BL = 8. After the burst data WD1, WD2, WD3,..., Etc. on the external data bus are taken into the memory 5D, these burst data are stored in the memory array 23- Write to n simultaneously. This is called a BL8 write operation.

FIG. 42 is a timing chart showing a data write operation according to the ninth embodiment. 42 shows, as internal states of the memory 5D, write operations iWR1, iWR2, iWR3,... To the memory array 23-n. In FIG. 42, the command CMD “W1 (8)” indicates a command for the BL8 write operation to the bank B1, and “W2 (4)” and “W3 (4)” indicate the BL4 write operation to the banks B2 and B3, respectively. Indicates a command. That is, simultaneously with the write command, burst length (BL) information is given to the memory 5D, and BL8 write or BL4 write can be selected based on the BL information. Further, in the BL8 write operation (W1 (8)), after the time period tD (W) has elapsed after the input of 8 burst data, the write operation (internal state iWR1) to the memory array 23-n is performed. The write operation (W2 (4)) is characterized in that the write operation (internal state iWR1) is performed in the memory array 23-n after the elapse of the time period tD (W) after the input of 4 burst data.

When the amount of data written in a single write operation is called “unit data amount”, the unit data amount increases especially when the burst length BL is long, and the possibility of actually writing an excessive amount of data increases. In that case, a DRAM compliant with the JEDEC standard prohibits writing of data other than necessary data by using a write mask function. However, in this case, it is necessary to wait for the burst length specified by the mode register etc. before performing the internal write operation on the external data bus even though the amount of data that needs to be written is small. This increases the time that wasteful data occupies. On the other hand, according to the memory system according to the ninth embodiment, since a burst length suitable for valid data can be designated for each write command, the effective utilization efficiency of the external data bus can be improved.

This operation is also applicable to the burst chop (BC4) operation of DDR3-DRAM conforming to the JEDEC standard.

Also, the same technique as described with reference to FIG. 42 can be applied to the read operation.

FIG. 43 is a diagram illustrating a write command used in the memory system according to the ninth embodiment. FIG. 43 shows an example in which the method of giving the burst length BL information to the memory 5D simultaneously with the write command described with reference to FIG. 42 is applied to the JEDEC standard LPDDR4-SDRAM. In the example of FIG. 43, the memory controller 3D and the memory 5D enter the variable burst length mode according to the ninth embodiment by using mode register setting or fuse trimming that is not defined in the JEDEC standard. In particular, in a memory capable of high-speed operation such as LPDDR4-SDRAM, the burst length BL becomes long (for example, BL = 32 or BL = 16), and there is a high possibility that unnecessary data reading and writing will occur. In LPDDR4-SDRAM conforming to the JEDEC standard, tCCD (min) = 8 × tCK, and reading and writing of data in the memory is performed in units of 16 bursts. Therefore, particularly when the LPDDR4-SDRAM is operated at a low frequency, use efficiency of the external data bus is wasted. In low frequency operation, tCCD = tRRD = 2 × tCK is possible, and it is efficient to change from BL = 16 to BL = 8 accordingly. The write command of the LPDDR4-SDRAM requires four cycles of the external clock CK_t, but BL = 32 and BL = 16 are specified by bit CA5 (BL0) in the first cycle of CK_t. In the example of FIG. 43, it is possible to specify BL = 8 by using the bit CA3 (BL1) in the second cycle of the clock CK_t.

Next, in the tenth embodiment, a memory system capable of improving the use efficiency of the external data bus when transitioning from a write operation to a read operation will be described.

Embodiment 10 FIG.
FIG. 44 is a block diagram illustrating a configuration of the memory controller 3E of the memory system according to the tenth embodiment. A memory controller 3E in FIG. 44 includes a control circuit 11E and a timing register 13E instead of the control circuit 11 and the timing register 13 of the memory controller 3 in FIG. The timing register 13E stores a plurality of timing parameters related to the operation of the memory 5. These timing parameters include a plurality of time periods tWRT1, tWRT2,. The plurality of time periods tWTR1, tWTR,... Are transmitted from the memory controller 3 to the memory 5 in order to write data to the first bank of the plurality of banks, and then the second of the plurality of banks. Indicates the time difference until a read command can be issued to read data from the bank. The plurality of time periods tWTR1, tWTR,... Have different lengths depending on different combinations of the first and second banks. When the control circuit 11E reads data from the second bank immediately after writing data to the first bank, the control circuit 11E transmits the data to the memory 5 and then the length corresponding to the combination of the first and second banks. After waiting for time periods tWTR1, tWTR2,..., A read command is issued.

In this specification, the time periods tWTR1, tWTR,... Are also referred to as “ninth time periods”.

FIG. 45 is a block diagram for explaining a data write / read operation to / from the memory 5 of the memory system according to the tenth embodiment. The memory 5 in FIG. 45 is actually configured in the same manner as the memory 5 in FIG. 3, but for the purpose of explanation, the components omitted in FIG. 3 are shown. Internal data buses DB1 and DB2 are connected to banks B1 to B4 via input / output (IO) control circuits 26-1 to 26-4 as described with reference to FIG. As shown in FIG. 45, the internal data buses DB1 and DB2 shared among the banks B1 to B4 and the in-bank data buses IO-1 to IO-4 of the banks B1 to B4 are used. Including. In the description of the tenth embodiment, the internal data buses DB1 and DB2 are referred to as “interbank data buses”. Here, the in-bank data buses IO-1 to IO-6 include the GIO bus GIOB and the LIO bus LIOB in the memory array 23-n of FIG. In FIG. 45, the row address signal, the column address signal, and their activation signals in FIG. 3 are omitted for the sake of simplicity of illustration.

During write operation, write data is transmitted from the memory controller 3E to the memory 5 via the memory bus 4. When the SDRAM interface 21 of the memory 5 receives the write data, the inter-bank data buses IO-1 to IO-4 of the banks B1 to B4 are further connected via the interbank data bus DB1 or DB2 and the IO control circuit 26-n. Then, the data is transferred to the memory arrays 23-1 to 23-4. On the other hand, during the read operation, the read data is transmitted from the memory 5 to the memory controller 3E in the reverse order of the write operation.

When changing from a write operation to a read operation, data contention on the data bus inside the memory 5 defines the command interval.

FIG. 46 is a timing chart showing data write and read operations according to the first example of the tenth embodiment. FIG. 46 shows a case where data is written to a certain bank and subsequently read access is made to the same bank. A write command W is issued, and then, after a write latency time period WL has elapsed, write data WD is applied to the external data bus. After the burst time of the external data bus (in this embodiment, BL / 2 × tCK = 2 cycles), the write data dbWR appears on the interbank data bus DB1. Further, after the elapse of the time period tD (W), the write data ioWR appears on the in-bank data bus IO-1. On the other hand, after the end of the burst time of the external data bus, a read command R is input to the external command bus after a time period tWTR representing the time from internal write to internal read, and the time period tD (R ), The read data appears on the bank data bus IO-1. Due to a delay in data transfer inside the memory 5, read data dbRD appears on the inter-bank data bus DB1. The read data QD is read to the external data bus after the elapse of the time period CL from the issue of the read command R. As described above, the transition from the write operation to the read operation for the same bank requires at least “tWTR + CL × tCK” time. However, according to the JEDEC standard, a single value time period tWTR is used regardless of whether the bank into which data is written and the bank from which data is subsequently read out are the same or different.

FIG. 47 is a timing chart showing data write and read operations according to the second example of the tenth embodiment. FIG. 47 shows a case where data is written to a certain bank and subsequently data is read from a different bank. A write command W1 to the bank B1 is issued, and then the write data WD is given to the external data bus after the write latency time period WL elapses. After the burst time of the external data bus (BL / 2 × tCK = 2 cycles in this embodiment), the write data dbWR appears on the interbank data bus DB1. Further, after the elapse of the time period tD (W), the write data ioWR appears on the bank data bus IO-1 of the bank B1. On the other hand, a read command R2 to the bank B2 is input to the command bus after the elapse of the time period tWTR indicating the time from the internal write to the internal read after the burst time of the external data bus ends. After the elapse of tD (R), read data appears on the bank data bus IO-2 of the bank B2. However, since the banks are different and the bank data buses IO-1 and IO-2 are not shared, there is no collision between the write data and the read data on the bank data buses IO-1 and IO-2. Therefore, tWTR can be shortened until it becomes possible to avoid data collision on the interbank data bus DB1. In the present embodiment, a case where tWTR is shortened to 0 is shown.

FIG. 48 is a block diagram illustrating a configuration of the memory controller 3E of the memory system according to the modification of the tenth embodiment. The memory controller 3E of FIG. 48 is configured in the same manner as the memory controller 3E of FIG. 44, except that the number of time periods tWTR1, tWTR2, tWTR3,... Stored in the timing register 13E is different. The values of the time periods tWTR1, tWTR2, and tWTR3 are different from each other, and the time periods tWTR1, tWTR2, and tWTR3 are selectively used according to the bank address of successive activation commands. When tWTR1 <tWTR2 <tWTR3, for example, the time periods tWTR1, tWTR2, and tWTR3 are selectively used as follows. The time period tWTR3 can be used when writing data to the same bank and then reading the data. The time period tWTR2 can be used when writing data to different banks connected to the same interbank data bus and then reading the data. The time period tWTR1 can be used when writing data to different banks connected to different interbank data buses and then reading the data. For this reason, the control circuit 11E holds information on whether or not the interbank data buses D1 and D2 are shared for each of the banks B1 to B4. The control circuit 11E selects one of the time periods tWTR1, tWTR2, and tWTR3 based on the above conditions, and issues each command according to the selected time period.

FIG. 49 is a timing chart showing data write and read operations according to the third example of the tenth embodiment. A case where data is written to a different bank and then data is read is shown. A write command W1 to the bank B1 is issued, and the write data WD is applied to the external data bus after the write latency time period WL elapses. After the burst time of the external data bus (BL / 2 × tCK = 2 cycles in this embodiment), the write data dbWR appears on the interbank data bus DB1. Further, after the elapse of the time period tDW, the write data ioWR appears on the in-bank data bus IO-1. On the other hand, after the time period tWTR indicating the time from the internal write to the internal read after the burst time of the external data bus ends, the read command R3 to the bank B3 is input to the command bus, and the time period starts from that. After the elapse of tD (R), read data appears on the bank data bus IO-3 of the bank B3. However, since the banks B1 and B3 do not share the interbank data buses DB1 and DB2, there is no collision between the write data and the read data on the interbank data buses DB1 and DB2. Therefore, the time period tWTR can be shortened until it is possible to avoid data collision between writing and reading on the SDRAM interface 21 or the external data bus. In the example of FIG. 49, the time period tWTR is a negative value (tWTR = −2 × tCK).

According to the memory system according to the tenth embodiment, the use efficiency of the external data bus can be improved when the write operation is changed to the read operation.

The configurations and operations of the memory systems according to Embodiments 1 to 10 described above may be combined with each other.

According to the present invention, a memory and a memory controller that hardly reduce the use efficiency of an external data bus even when data is written to and / or read from one or more banks by a command sequence including a precharge command. Furthermore, a memory system including these can be provided.

1 ... Processor
2 ... Processor bus,
3, 3A-3E ... Memory controller,
4 ... Memory bus,
5,5D ... memory,
11, 11A to 11E ... control circuit,
12 ... PHY interface,
13, 13A to 13E ... timing register,
21 ... SDRAM interface,
22, 22D ... chip control circuit,
23-1 to 23-4 ... Memory array,
24-1 to 24-4 ... row decoder,
25-1 to 25-4 ... column decoder,
26-1 to 26-4. Input / output (IO) control circuit,
27-1, 27-2 ... power supply circuit,
31-1 to 31-4 ... Bank control circuit,
32 ... OR operation (OR) circuit,
33 ... Activation control circuit,
34 ... Command decoder,
35 ... Bank address control circuit,
36: Column address control circuit,
37 ... row address control circuit,
41 ... row address control circuit,
42 ... Column address control circuit,
43 ... logical sum operation (OR) circuit,
44 ... AND operation circuit
51 ... Subarray,
52. Sense amplifier array,
61-0 to 61-2 ... Individual decoder,
62-0 to 62-2 ... CSL driver,
71 ... VCSLR generation circuit,
72 ... VCSLW generating circuit,
81-0 to 81-2: Individual decoder,
82-0 to 82-2 ... WDL driver,
91, 91-1, 91-2 ... VPP generation circuit,
92-1 and 92-2 VARY generation circuit,
100 ... VPP generation circuit,
101: OR operation circuit (OR),
102: logical product (AND) circuit,
103, 104 ... VPP generation circuit part,
B1 ~ B4 ... Bank,
BTL, BTL00 to BTL13 ... bit lines,
C, C00 to C13 ... memory cells,
Ca1 to Ca4 ... boost capacitors,
CSL, CSL0, CSL1, CSL2 ... column selection line,
CS: Cell capacitor,
CT: Cell transistor,
DB, DB1, DB2 ... internal data bus,
GIOB ... GIO bus,
IOSW: Input / output (IO) switch,
IOT: Input / output (IO) transistor,
LIOB, LIOB_1 to LIOB_3 ... LIO bus,
RBTL: Parasitic resistance,
SA00 to SA13 ... sense amplifier,
SANT ... NMOS transistor,
SAPT ... PMOS transistor,
SASW: Subarray selection switch,
SN ... Storage node,
SW1 to SW19, SWW, SWR ... switch,
T1 to T14 ... transistor,
WDL, WDL0... Word line.

Claims (33)

1. A control device for a semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
   The semiconductor memory device includes at least one bank connected to at least one internal data bus, and the bank includes a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to each other. A memory array including a plurality of sense amplifiers respectively connected to the plurality of bit lines, and a plurality of column selection lines respectively connected to the plurality of sense amplifiers;
   The control device includes a communication circuit connected to the semiconductor memory device, a control circuit that controls the semiconductor memory device by issuing a plurality of commands and transmitting the command to the semiconductor memory device via the communication circuit; A timing register for storing a plurality of timing parameters related to the operation of the semiconductor memory device;
   The plurality of commands are:
   An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
   A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
   A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
   The plurality of timing parameters include a first time period (tRCD (W)) indicating a time difference from when the activation command is issued until the write command can be issued, and after the activation command is issued. A second time period (tRCD (R)) indicating a time difference until the read command can be issued, wherein the first time period has a smaller value than the second time period;
   The control circuit includes:
   When writing data to the semiconductor memory device, issue the write command after the moment separated by the first time period (tRCD (W)) with reference to the moment when the activation command is issued,
   When reading data from the semiconductor memory device, the read command is issued after the moment separated by the second time period (tRCD (R)) with reference to the moment when the activation command is issued.
   Control device.
2. The first time period (tRCD (W)) has a negative value;
   When writing data to the semiconductor memory device, the control circuit starts from the moment preceding by a time period equal to the absolute value of the first time period (tRCD (W)) with reference to the moment when the activation command is issued. And before the moment of issuing the activation command, issue the write command,
   The control device according to claim 1.
3. The control circuit transmits, to the semiconductor memory device, a first control signal notifying that the write command is issued before the activation command when writing data to the semiconductor memory device.
   The control device according to claim 2.
4. The bank includes a plurality of subarrays separated from each other by at least one sense amplifier row including a plurality of sense amplifiers,
   The write command includes a part of a row address of a subarray including a storage cell to which data is written.
   The control device according to any one of claims 1 to 3.
5. A control device for a semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
   The semiconductor memory device includes at least one bank connected to at least one internal data bus, and the bank includes a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to each other. A memory array including a plurality of sense amplifiers respectively connected to the plurality of bit lines, and a plurality of column selection lines respectively connected to the plurality of sense amplifiers;
   The control device includes a communication circuit connected to the semiconductor memory device, a control circuit that controls the semiconductor memory device by issuing a plurality of commands and transmitting the command to the semiconductor memory device via the communication circuit; A timing register for storing a plurality of timing parameters related to the operation of the semiconductor memory device;
   The plurality of commands are:
   An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
   A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
   A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
   The plurality of timing parameters are a third time period (WL2) indicating a time difference from when the write command is issued to when data is transmitted from the control device to the semiconductor memory device, and conforming to the JEDEC standard A third time period (WL2) that is shorter than the write latency (WL)
   When writing data to the semiconductor memory device, the control circuit transfers data from the control device to the semiconductor memory device at a moment separated by the third time period (WL2) with reference to the moment when the write command is issued. Start sending,
   Control device.
6. The timing parameter further includes a fourth time period (WL1) equal to a write latency (WL) according to the JEDEC standard;
   The control circuit, when writing data to the semiconductor memory device, at a moment separated by the third time period (WL2) or the fourth time period (WL1) with reference to the moment when the write command is issued. Start transmitting data from the control device to the semiconductor memory device;
   The control device according to claim 5.
7. The third time period (WL2) has a negative value;
   The control circuit, when writing data to the semiconductor memory device, at the moment preceding the moment when the write command is issued by a time period equal to the absolute value of the third time period (WL2). Starting to transmit data to the semiconductor memory device,
   The control device according to claim 5 or 6.
8. The semiconductor memory device includes a plurality of banks,
   The control circuit includes:
   When writing data to the semiconductor memory device, the same data is written to at least two of the plurality of banks,
   When reading data from the semiconductor memory device, reading data from one of at least two banks in which the same data of the plurality of banks is written;
   The control device according to one of claims 1 to 7.
9. The timing parameter further includes a fifth time period (tRC (R)) indicating the shortest time in which the activation command for a certain bank can be issued continuously.
   The control circuit is configured to read data from at least two banks in which the same data is written out of the plurality of banks at a time shorter than the fifth time period (tRC (R)). Issuing the second command including a bank address different from the bank address included in the first activation command.
   The control device according to claim 8.
10. The plurality of banks have bank addresses including a plurality of bits,
    When the control circuit writes data to the semiconductor memory device, the control circuit stores the memory cell having the same row address in at least two banks each having a bank address including at least one same bit value. Write the same data,
    The control device according to claim 8 or 9.
11. A control device for a semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
    The semiconductor memory device includes a plurality of banks connected to at least one internal data bus, and each one of the plurality of banks extends along a plurality of bit lines and a plurality of word lines orthogonal to each other. A memory array comprising a plurality of memory cells arranged, a plurality of sense amplifiers connected to the plurality of bit lines, respectively, and a plurality of column selection lines connected to the plurality of sense amplifiers, respectively.
    The control device includes a communication circuit connected to the semiconductor memory device, a control circuit that controls the semiconductor memory device by issuing a plurality of commands and transmitting the command to the semiconductor memory device via the communication circuit; A timing register for storing a plurality of timing parameters related to the operation of the semiconductor memory device;
    The plurality of commands are:
    An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
    A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
    A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
    The plurality of timing parameters include a sixth time period (tRRD) indicating the shortest time in which the activation commands for two different banks can be issued in succession, and the write command or the read for any two banks. A seventh time period (tCCD) indicating the shortest time in which commands can be issued continuously; and an eighth time period (tFAW) indicating the shortest time in which the four activation commands can be issued in succession. The seventh time period (tCCD) is set equal to the sixth time period (tRRD), and the eighth time period (tFAW) is set equal to four times the sixth time period (tRRD). And
    The control circuit includes:
    When continuously writing data to the semiconductor memory device, the activation command and the write command are issued at a period equal to the sixth time period (tRRD),
    When continuously reading data from the semiconductor memory device, the activation command and the read command are issued with a period equal to the sixth time period (tRRD), respectively.
    Control device.
12. The semiconductor memory device has a first operation mode and a second operation mode,
    When the semiconductor memory device is in the first operation mode, the upper limit voltage of the word line has a first voltage value, and the seventh time period (tCCD) is the sixth time period (tRRD). The eighth time period (tFAW) is longer than four times the sixth time period (tRRD),
    When the semiconductor memory device is in the second operation mode, the upper limit voltage of the word line has a second voltage value higher than the first voltage value, and the seventh time period (tCCD) is The sixth time period (tRRD) is equal to the eighth time period (tFAW) is equal to four times the sixth time period (tRRD);
    The control circuit transmits a second control signal for selectively operating the semiconductor memory device in one of the first operation mode and the second operation mode to the semiconductor memory device;
    The control device according to claim 11.
13. The plurality of timing parameters include a plurality of sixth time periods (tRRD) having different lengths depending on different combinations of the two banks.
    The control device according to claim 11 or 12.
14. A control device for a semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
    The semiconductor memory device includes a plurality of banks connected to at least one internal data bus, and each one of the plurality of banks extends along a plurality of bit lines and a plurality of word lines orthogonal to each other. A memory array comprising a plurality of memory cells arranged, a plurality of sense amplifiers connected to the plurality of bit lines, respectively, and a plurality of column selection lines connected to the plurality of sense amplifiers, respectively.
    The control device includes a communication circuit connected to the semiconductor memory device, a control circuit that controls the semiconductor memory device by issuing a plurality of commands and transmitting the command to the semiconductor memory device via the communication circuit; A timing register for storing a plurality of timing parameters related to the operation of the semiconductor memory device;
    The plurality of commands are:
    An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
    A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
    A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
    The plurality of timing parameters are transmitted from the control device to the semiconductor memory device in order to write data to a first bank of the plurality of banks, and then a second one of the plurality of banks. A plurality of ninth time periods (tWTR) indicating a time difference until the read command can be issued to read data from the bank, wherein the plurality of ninth time periods (tWTR) Different lengths according to different combinations of the second bank,
    When the data is read from the second bank immediately after writing the data to the first bank, the control circuit transmits the data to the semiconductor memory device, and then the combination of the first and second banks. Issuing the read command after waiting for the ninth time period (tWTR) having a length corresponding to
    Control device.
15. A semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
    The semiconductor memory device
    An internal data bus;
    And at least one bank connected to the internal data bus,
    The bank includes a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to each other, a plurality of sense amplifiers respectively connected to the plurality of bit lines, and the plurality of sense amplifiers. A memory array having a plurality of column selection lines connected to each other;
    The semiconductor memory device includes a communication circuit connected to a control device via an external bus, a control circuit that receives a plurality of commands from the control device via the communication circuit and controls operations of the semiconductor memory device. With
    The plurality of commands are:
    An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
    A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
    A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
    When writing data to the semiconductor memory device, the control circuit precedes by a time period equal to an absolute value of a first time period (tRCD (W)) determined in advance with reference to the moment when the activation command is received. The write command is configured to be received from the control device after the moment of performing and before the moment of receiving the activation command.
    Semiconductor memory device.
16. The semiconductor memory device includes a plurality of circuits respectively associated with at least a part of the plurality of commands,
    The control circuit includes:
    When writing data to the semiconductor memory device, a first control signal for notifying that the write command is issued before the activation command is received from the control device,
    Activating a circuit associated with the write command when receiving the first control signal;
    The semiconductor memory device according to claim 15.
17. The semiconductor memory device
    A first voltage source for applying a first voltage to the column selection line when reading data from the semiconductor memory device;
    A second voltage source that applies a second voltage higher than the first voltage to the column selection line when writing data to the semiconductor memory device;
    17. The semiconductor memory device according to claim 15 or 16.
18. When reading data from the semiconductor memory device, the first voltage source applies the first voltage to the column selection line over a first time length;
    When writing data to the semiconductor memory device, the second voltage source applies the second voltage to the column selection line for a second time length longer than the first time length;
    The semiconductor memory device according to claim 17.
19. The control circuit activates the column selection line after writing the write command and before activating the sense amplifier when writing data to the semiconductor memory device.
    The semiconductor memory device according to any one of claims 15 to 18.
20. The control circuit activates the column selection line after writing the write command and before activating the sense amplifier and the word line when writing data to the semiconductor memory device.
    20. The semiconductor memory device according to claim 19.
21. Each one of the plurality of sense amplifiers includes at least one NMOS transistor and at least one PMOS transistor;
    When deactivating the sense amplifier, a voltage equal to the upper limit voltage of the bit line is applied to the source of the NMOS transistor,
    When activating the sense amplifier, a voltage equal to the lower limit voltage of the bit line is applied to the source of the NMOS transistor,
    21. The semiconductor memory device according to claim 19 or 20.
22. The bank includes a plurality of subarrays separated from each other by at least one sense amplifier row including a plurality of sense amplifiers,
    The write command includes a part of a row address of a subarray including a storage cell to which data is written,
    The control circuit includes:
    Activate a sub-array designated by the row address of the write command;
    Activate the column selection line specified by the column address of the write command,
    A bit line voltage corresponding to the activated column selection line is set to an upper limit voltage;
    The semiconductor memory device according to any one of claims 15 to 21.
23. The semiconductor memory device includes a plurality of banks,
    The control circuit includes:
    When writing data to the semiconductor memory device, the same data is written to at least two of the plurality of banks,
    When reading data from the semiconductor memory device, reading data from one of at least two banks in which the same data of the plurality of banks is written;
    The semiconductor memory device according to any one of claims 15 to 22.
24. The control circuit includes first and second activation commands issued to read data from at least two banks in which the same data of the plurality of banks is written, and a predetermined first command When the first and second activation commands issued at intervals shorter than the time period of 5 (tRC (R)) are received, at least the same data is written according to the first activation command. Read data from a first bank of two banks, and read data from a second bank of at least two banks to which the same data is written in response to the second activation command.
    24. The semiconductor memory device according to claim 23.
25. The plurality of banks have bank addresses including a plurality of bits,
    When the control circuit writes data to the semiconductor memory device, the control circuit stores the memory cell having the same row address in at least two banks each having a bank address including at least one same bit value. Write the same data,
    25. The semiconductor memory device according to claim 23 or 24.
26. A semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
    The semiconductor memory device
    An internal data bus;
    A plurality of banks connected to the internal data bus,
    Each one of the plurality of banks includes a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to each other, and a plurality of senses respectively connected to the plurality of bit lines. A memory array including an amplifier and a plurality of column selection lines connected to the plurality of sense amplifiers,
    The semiconductor memory device includes a communication circuit connected to a control device via an external bus, a control circuit that receives a plurality of commands from the control device via the communication circuit and controls operations of the semiconductor memory device. With
    The plurality of commands are:
    An activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address, and a sense amplifier connected to the memory cell via the bit line;
    A write command for instructing writing of data to a memory cell having a certain bank address and a certain column address;
    A read command for instructing to read data from a memory cell having a certain bank address and a certain column address,
    The semiconductor memory device has a plurality of timing parameters related to the operation of the semiconductor memory device, and the plurality of timing parameters has a minimum time during which the activation commands for two different banks can be continuously received. A sixth time period (tRRD) shown, a seventh time period (tCCD) showing the shortest time in which the write command or the read command for any two banks can be continuously received, and the four activations An eighth time period (tFAW) indicating the shortest time in which commands can be continuously received, and the seventh time period (tCCD) is equal to the sixth time period (tRRD). The time period (tFAW) is equal to four times the sixth time period (tRRD),
    The control circuit includes:
    When continuously writing data to the semiconductor memory device, the activation command and the write command can be received from the control circuit at a period equal to the sixth time period (tRRD), respectively.
    When continuously reading data from the semiconductor memory device, the activation command and the read command are configured to be received from the control circuit in a cycle equal to the sixth time period (tRRD), respectively.
    Semiconductor memory device.
27. In the semiconductor memory device, the seventh time period (tCCD) is equal to the sixth time period (tRRD), and the eighth time period (tFAW) is equal to the sixth time period (tFAW). a third voltage source for applying to the word line a voltage set to be equal to four times tRRD).
    27. The semiconductor memory device according to claim 26.
28. The semiconductor memory device has a first operation mode and a second operation mode,
    When the semiconductor memory device is in the first operation mode, the upper limit voltage of the word line has a first voltage value, and the seventh time period (tCCD) is the sixth time period (tRRD). The eighth time period (tFAW) is longer than four times the sixth time period (tRRD),
    When the semiconductor memory device is in the second operation mode, the upper limit voltage of the word line has a second voltage value higher than the first voltage value, and the seventh time period (tCCD) is The sixth time period (tRRD) is equal to the eighth time period (tFAW) is equal to four times the sixth time period (tRRD);
    The control circuit receives the second control signal for selectively operating the semiconductor memory device in one of the first operation mode and the second operation mode from the control device. Selectively operating in one of the first operating mode and the second operating mode according to a signal;
    28. The semiconductor memory device according to claim 26 or 27.
29. The plurality of timing parameters include a plurality of sixth time periods (tRRD) having different lengths depending on different combinations of the two banks.
    The semiconductor memory device according to any one of claims 26 to 28.
30. A control device according to one of claims 1 to 10,
    A semiconductor memory device according to one of claims 15 to 25,
    Semiconductor storage system.
31. A control device according to one of claims 11 to 13,
    A semiconductor memory device according to one of claims 26 to 29,
    Semiconductor storage system.
32. A control device according to claim 14;
    A semiconductor memory device;
    Semiconductor storage system.
33. A control method for a semiconductor memory device having an interface compliant with JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM,
    The semiconductor memory device includes at least one bank connected to at least one internal data bus, and the bank includes a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to each other. A memory array including a plurality of sense amplifiers respectively connected to the plurality of bit lines, and a plurality of column selection lines respectively connected to the plurality of sense amplifiers;
    The control method is:
    Issuing an activation command for activating a word line connected to a memory cell having a certain bank address and a certain row address and a sense amplifier connected to the memory cell via the bit line;
    Issuing a write command instructing to write data to a memory cell having a certain bank address and a certain column address;
    Issuing a read command instructing to read data from a memory cell having a certain bank address and a certain column address;
    When writing data to the semiconductor memory device, issuing the write command after a moment separated by a first time period (tRCD (W)) with reference to the moment of issuing the activation command;
    Issuing the read command after reading a second time period (tRCD (R)) with reference to the moment when the activation command is issued when reading data from the semiconductor memory device;
    The first time period (tRCD (W)) indicates a time difference from when the activation command is issued until the write command can be issued, and the second time period (tRCD (R)) is A time difference from when the activation command is issued until the read command can be issued, and the first time period has a smaller value than the second time period;
    Control method.

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