WO2018210048A1

WO2018210048A1 - Fpga-based hardware iris recognition system and method, and readable storage medium

Info

Publication number: WO2018210048A1
Application number: PCT/CN2018/079553
Authority: WO
Inventors: 高俊雄; 易开军; 托马斯费尔兰德斯·
Original assignee: 武汉虹识技术有限公司
Priority date: 2017-05-16
Filing date: 2018-03-20
Publication date: 2018-11-22
Also published as: CN106980849A

Abstract

An FPGA-based hardware iris recognition system and method, and a readable storage medium, relating to the technical field of biometric recognition. The FPGA-based hardware iris recognition system acquires an image of an iris to be recognized by means of an image acquisition unit (110); a preprocessing module preprocesses the image of the iris; an encoding module encodes the preprocessed image of the iris to extract iris characteristic information; a comparison and recognition module compares the iris characteristic information with pre-stored user's iris template information to obtain a matching similarity, and if the matching similarity is within a preset range, determines that the image of the iris is successfully recognized, or otherwise, determines that the image of the iris is not successfully recognized. The FPGA-based hardware iris recognition system implements acquisition and processing of the image of the iris by means of a hardware circuit, significantly improves the speed of recognition, ensures both stability and security of iris recognition, has prominent advantages in system integration and ease of use, and features relatively good user experience.

Description

FPGA-based hardware iris recognition system, method and readable storage medium

Cross-reference to related applications

The present application claims priority to Chinese Patent Application No. JP-A No. No. No. No. No. No. No. No. No. No. No. No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No

Technical field

The present disclosure relates to the field of biometrics, and in particular to an FPGA-based hardware iris recognition system, method, and readable storage medium.

Background technique

Biometric technology is an emerging identification technology in recent years. Compared with traditional identification technologies (such as keys, passwords, electronic tags, etc.), it has higher security, convenience, and versatility. Common biometric technologies have fingerprints. , face, iris, voice recognition, etc. Among them, the iris recognition technology is simply a security detection technology based on the iris in the eye for identification, and has higher accuracy and superiority with the popular biometric recognition technologies such as fingerprint recognition and face recognition. The reason why iris recognition technology has become a hot research hotspot is because the human iris has the following characteristics: 1. Anti-counterfeiting, symbiosis of iris and human life, can ensure the authenticity of physiological organization, and have high anti-counterfeiting; Contactability, digital image of iris can be obtained within a certain distance, without the user touching the device, it is not infringed on the human body and is easily accepted by the public; 3. Uniqueness, the information contained in each iris is different, and has unique personal characteristics; 4, stability, the iris is quite stable in people's life, basically will not change. Therefore, the iris recognition system has a good development prospect.

The existing iris recognition systems are mainly divided into two categories: iris recognition system based on PC platform and embedded iris recognition system. Among them, the iris recognition system based on PC platform has complex structure, high cost and inconvenient use, and embedded iris recognition system. Although the system structure is simple, the hardware resources are limited, the scalability of the system is not strong, the storage space is limited, and the application has high requirements, and the iris recognition speed needs to be improved.

Therefore, how to solve the above problems has always been the focus of attention of those skilled in the art.

Summary of the invention

Objects of the present disclosure include, but are not limited to, providing an FPGA-based hardware iris recognition system to improve the above problems.

In order to achieve the above object, the technical solution adopted by the embodiment of the present disclosure is as follows:

An embodiment of the present disclosure provides an FPGA-based hardware iris recognition system, including an image acquisition unit and an iris image core processing unit, wherein the image acquisition unit is electrically connected to the iris image core processing unit; the image acquisition unit is configured to collect An iris image to be recognized; the iris image core processing unit configured to process the iris image to extract iris property information, and compare the iris property information with pre-stored user iris template information to obtain a comparison result And determining, according to the comparison result, whether the iris image passes the recognition.

Further, the iris image core processing unit is an FPGA.

Further, the iris image core processing unit includes a main control module, a pre-processing module, an encoding module, and a comparison identification module, and the pre-processing module, the encoding module, and the comparison identification module are both electrically connected to the main control module. Connecting; the pre-processing module is configured to pre-process the iris image, the encoding module configured to encode the pre-processed iris image to extract the iris property information, the alignment recognition module configuration Comparing the iris characteristic information with the pre-stored user iris template information to obtain a matching similarity, and if the matching similarity is within a preset range, the comparison identifying module determines the iris The image is identified, otherwise, the iris image is determined not to pass the recognition.

Further, the pre-processing module is specifically configured to perform image enhancement, image filtering, or image segmentation on the image acquired by the image acquisition unit.

Further, the encoding module is specifically configured to perform image template creation, feature extraction or target recognition on the preprocessed iris image.

Further, the iris image core processing unit further includes an image acquisition control module, the image acquisition control module is electrically connected to the main control module and the image acquisition unit, and the image acquisition control module is configured to be in the The image acquisition unit controls the image acquisition unit to collect the iris image under the control of the main control module.

Further, the FPGA-based hardware iris recognition system further includes an auxiliary illumination unit electrically connected to the image acquisition control module, and the image acquisition control module is further configured to be controlled by the main control module The auxiliary lighting unit is controlled to provide illumination for the collection of the iris image.

Further, the FPGA-based hardware iris recognition system further includes a storage unit electrically connected to the iris image core processing unit, and the storage unit is configured to store the user iris template information.

Further, the FPGA-based hardware iris recognition system further includes an information encryption unit, the information encryption unit is electrically connected to the iris image core processing unit and the storage unit, and the information encryption unit is configured to The user iris template information stored by the storage unit and the iris image algorithm are encrypted.

Further, the image acquisition unit includes an image sensor and an optical lens module.

Further, the FPGA-based hardware iris recognition system further includes a display unit electrically connected to the iris image core processing unit, and the display unit is configured to display an identification process of the iris image.

Further, the FPGA-based hardware iris recognition system further includes a communication interface unit configured to transmit data.

An embodiment of the present disclosure further provides an FPGA-based hardware iris recognition system, where the FPGA-based hardware iris recognition system includes an image acquisition unit and an iris image core processing unit electrically connected to the image acquisition unit, the iris image core The processing unit includes a main control module, a pre-processing module, an encoding module, and a comparison identification module, wherein the pre-processing module, the encoding module, and the comparison identification module are electrically connected to the main control module; the image acquisition unit is configured Acquiring an iris image to be identified; the preprocessing module is configured to preprocess the iris image, and the encoding module is configured to encode the preprocessed iris image to extract iris characteristic information, the ratio The identification module is configured to compare the iris characteristic information with pre-stored user iris template information to obtain a matching similarity, and if the matching similarity is within a preset range, the comparison identifying module determines The iris image is identified by, otherwise, the iris image is determined not to pass the recognition.

The embodiment of the present disclosure further provides an iris recognition method, which is applied to the FPGA-based hardware iris recognition system provided by the embodiment of the present disclosure, and the method includes:

Collecting an iris image to be identified by the image acquisition unit;

The iris image is processed by the iris image core processing unit to extract iris characteristic information, and the iris characteristic information is compared with pre-stored user iris template information to obtain a comparison result, and according to the comparison As a result, it is determined whether the iris image passes the recognition.

The embodiment of the present disclosure further provides a readable storage medium, which is applied to an FPGA-based hardware iris recognition system, where the FPGA-based hardware iris recognition system includes an image acquisition unit, an iris image core processing unit, and the iris image core processing unit. Implemented on the FPGA; the readable storage medium stores instructions that, when invoked or executed by the iris image core processing unit, cause the iris image core processing unit to form a hardware circuit to acquire the image acquisition unit The obtained iris image is processed to extract iris characteristic information, the iris characteristic information is compared with pre-stored user iris template information to obtain a comparison result, and it is determined whether the iris image passes the recognition according to the comparison result. .

Compared with the prior art, the beneficial effects achieved by the embodiments of the present disclosure include:

An FPGA-based hardware iris recognition system, method, and readable storage medium provided by an embodiment of the present disclosure, the FPGA-based hardware iris recognition system includes an image acquisition unit, an iris image core processing unit, the image acquisition unit and the iris The image core processing unit is electrically connected, and the iris image core processing unit includes a main control module, a preprocessing module, an encoding module, and a comparison identification module, and the preprocessing module, the encoding module, and the comparison identification module are both The main control module is electrically connected; after the image acquisition unit collects the iris image to be identified, the preprocessing module performs preprocessing on the iris image, and the encoding module encodes the preprocessed iris image to Extracting iris characteristic information, the comparison identifying module compares the iris characteristic information with pre-stored user iris template information to obtain matching similarity, if the matching similarity is within a preset range, The comparison recognition module determines that the iris image is recognized, otherwise, determines the iris image By identifying. The FPGA-based hardware iris recognition system realizes the iris image acquisition and processing through the hardware circuit, which has a significant improvement in the recognition speed, and ensures the stability and security of the iris recognition, and is obvious in system integration and use convenience. The advantage of the user experience is better.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings to be used in the embodiments will be briefly described below. It should be understood that the following drawings show only certain embodiments of the present disclosure, and thus It should be seen as a limitation on the scope, and those skilled in the art can obtain other related drawings according to these drawings without any creative work.

FIG. 1 is a structural block diagram of an FPGA-based hardware iris recognition system provided by a first embodiment of the present disclosure.

FIG. 2 is a block diagram showing the structure of the iris image core processing unit of FIG. 1.

FIG. 3 is a structural block diagram of an FPGA-based hardware iris recognition system provided by a second embodiment of the present disclosure.

FIG. 4 is a schematic diagram showing the connection between an FPGA-based hardware iris recognition system and an external device according to a second embodiment of the present disclosure.

Icon: 100-FPGA-based hardware iris recognition system; 200-external device; 110-image acquisition unit; 120-iris image core processing unit; 130-auxiliary lighting unit; 140-storage unit; 150-information encryption unit; Display unit; 170-communication interface unit; 121-image acquisition control module; 122-main control module; 124-pre-processing module; 126-encoding module; 128-alignment identification module.

detailed description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings in the embodiments of the present disclosure. It is a partial embodiment of the present disclosure, and not all of the embodiments. The components of the disclosed embodiments, which are generally described and illustrated in the figures herein, can be arranged and designed in various different configurations. The detailed description of the embodiments of the present disclosure, which is set forth in the claims All other embodiments obtained by a person skilled in the art based on the embodiments of the present disclosure without creative efforts are within the scope of the present disclosure.

It should be noted that similar reference numerals and letters indicate similar items in the following figures, and therefore, once an item is defined in a drawing, it is not necessary to further define and explain it in the subsequent drawings. Meanwhile, in the description of the present disclosure, the terms "first", "second", and the like are used merely to distinguish a description, and are not to be construed as indicating or implying a relative importance.

First embodiment

Please refer to FIG. 1 , which is a structural block diagram of an FPGA-based hardware iris recognition system 100 according to a first embodiment of the present disclosure. The FPGA-based hardware iris recognition system 100 can be used for user identification, which can include an image acquisition unit 110 and an iris image core processing unit 120. The image acquisition unit 110 and the iris image core processing unit 120 are electrically connected.

The image acquisition unit 110 is configured to acquire an iris image to be identified.

In this embodiment, the image acquisition unit 110 is configured to collect an iris image to be recognized and transmit the iris image to the iris image core processing unit 120 so that the iris image core processing unit 120 identifies the user corresponding to the iris image. .

The image capturing unit 110 may further include an image sensor and an optical lens module, the image sensor is electrically connected to the iris image core processing unit 120, and the image collecting unit 110 performs iris image capturing on a human eye region of the user. And imaging the image sensor to generate the iris image to be recognized by the optical lens module, and the image sensor transmits the collected iris image to be recognized to the iris image core processing unit 120 . Preferably, the image sensor may employ a CCD or CMOS image sensor, wherein the CCD or CMOS image sensor may be used in an amount of 1 or 2.

The iris image core processing unit 120 is configured to process the iris image to extract iris characteristic information, compare the iris characteristic information with pre-stored user iris template information to obtain a comparison result, and according to the The comparison result determines whether the iris image passes the recognition.

In this embodiment, the iris image core processing unit 120 can be implemented based on an FPGA (Field-Programmable Gate Array). FPGA can be flexibly programmed according to user requirements to achieve user functions, with rich logic resources and I / O resources and short development cycle, low design cost, easy product replacement and so on.

Specifically, as shown in FIG. 2, the iris image processing unit 120 includes a main control module 122, a preprocessing module 124, an encoding module 126, and a comparison identification module 128. Both the encoding module 126 and the alignment identifying module 128 are electrically coupled to the main control module 122. For example, after the iris image core processing unit 120 based on the FPGA is initialized, a hardware circuit module corresponding to each module of the iris image core processing unit 120 is formed.

The pre-processing module 124 is configured to pre-process the iris image.

Since the iris image collected by the image capturing unit 110 includes not only the iris but also the pupil, the eyelashes, the eyelids, and the like, and is affected by many uncertain factors such as illumination during the iris image collection process, the present embodiment is In an example, a targeted pre-processing of the iris image is required for subsequent processing of the iris image. Preferably, the preprocessing process of the iris image includes operations such as image enhancement, image filtering, image segmentation, and the like, but is not limited thereto.

The encoding module 126 is configured to encode the preprocessed iris image to extract the iris property information.

Since the iris is different mainly in the iris texture, in the present embodiment, the encoding module 126 is configured to extract the detail features in the iris texture and encode them, thereby obtaining iris characteristic information in the iris image. Preferably, the process of extracting iris characteristic information may include operations such as image template creation, feature extraction, target recognition, algorithm encoding, and the like, but is not limited thereto.

The comparison identifying module 128 is configured to compare the iris characteristic information with the pre-stored user iris template information to obtain a matching similarity, if the matching similarity is within a preset range, The alignment recognition module 128 determines that the iris image passes the recognition, otherwise, determines that the iris image does not pass the recognition.

In this embodiment, the comparison identification module 128 calculates the matching similarity between the iris characteristic information extracted by the encoding module 126 and the pre-stored user iris template information by using a comparison algorithm, if the matching similarity is obtained in advance Within the set range, the iris image is identified to have the same bio-iris feature as the pre-stored user iris template information, and the iris image is determined to be recognized, that is, the user's identity is successfully identified; if the obtained matching similarity is not within the preset range Then, it is determined that the iris image does not pass the recognition, that is, the identity of the user fails. Preferably, the alignment recognition process of the iris image may include operations such as feature sequence coding, sequence similarity matching, and the like, but is not limited thereto. It can be understood that the pre-stored user iris template information includes at least one, and the comparison identification module 128 compares the extracted iris characteristic information with each user iris template information and calculates the matching similarity.

Further, the iris image processing unit 120 may further include an image acquisition control module 121, and the image acquisition control module 121 is electrically connected to the main control module 122 and the image acquisition unit 110, and the image acquisition control is performed. The module 121 is configured to control the image acquisition unit 110 to acquire the iris image under the control of the main control module 122. For example, the image acquisition control module 121 can control operations such as autofocus of the optical lens module to obtain a clear iris image, and control the image sensor to transmit the iris image and the like.

In the iris recognition, it is required to quickly identify the iris image and obtain the recognition result. In the embodiment, the functions of the iris image core processing unit 120 are implemented by using an FPGA, and the iris image processing is performed compared with the software. In this way, the hardware circuit formed by the FPGA can complete the iris image processing more quickly, and is more suitable for the iris recognition scene.

In this embodiment, the FPGA-based hardware iris recognition system 100 may further include an auxiliary illumination unit 130, wherein the auxiliary illumination unit 130 is electrically connected to the image acquisition control module 121, and the image acquisition control module 121 It is also configured to control the auxiliary lighting unit 130 to provide illumination for the collection of the iris image under the control of the main control module 122. Since the human iris is illuminated by infrared light of a certain wavelength (generally between 700 and 900 nanometers), it generally has a radial structure from the inside to the outside, including many interlaced spots, stripes, crypts, etc. The subtle structure of the shape, these subtle features are called the texture features of the iris, so it is necessary to provide a near-infrared fill light when collecting the iris image. In the embodiment, when the image capturing unit 110 collects the iris image, the auxiliary lighting unit 130 provides a good collection environment for the iris image collection under the control of the image capturing control module 121, so as to obtain clearer and more complete iris characteristics. Information image.

Further, the FPGA-based hardware iris recognition system 100 may further include a storage unit 140 and an information encryption unit 150. The storage unit 140 is electrically connected to the iris image core processing unit 120, and the information encryption unit 150 and the The iris image core processing unit 120 and the storage unit 140 are all electrically connected.

In this embodiment, the storage unit 140 is configured to store the user iris template information. In this embodiment, the user can register the iris characteristic information by using the FPGA-based hardware iris recognition system 100, that is, the iris image of the user is collected by the image acquisition unit 110, and the iris image is processed by the iris image core processing unit 120. Extracting the iris characteristic information, and then storing the iris characteristic information as the user iris template information in the storage unit 140; when the user performs the identification, the comparison identifying module 128 will acquire the iris characteristic information and the pre-stored user each time. The iris template information is compared and the matching similarity is calculated. In this embodiment, the storage unit 140 is electrically connected to the main control module 122. Preferably, when storing the user iris template information, the storage unit 140 may further store the one-to-one correspondence between the user's personal information (such as a name, an ID, and the like) and the user's iris template information in the storage unit 140.

In this embodiment, the storage unit 140 may include a volatile memory or a non-volatile memory. For example, the non-volatile memory can be NAND Flash, EEPROM, etc., and the volatile memory can be SRAM, DDR2 or DDR3.

Further, in this embodiment, the storage unit 140 may also serve as a readable storage medium for storing the initialization instruction of the iris image core processing unit 120. For example, the readable storage medium stores instructions that are invoked or executed by the FPGA when the FPGA image initialization of the film image core processing unit 120 is initiated, causing the FPGA to form various modules with the iris image core processing unit 120. Corresponding hardware circuit module.

The information encryption unit 150 is configured to encrypt the user iris template information and the iris image algorithm stored by the storage unit 140. In this embodiment, in order to prevent information leakage and ensure the security of iris recognition, the information encryption unit 150 may encrypt the user iris template information, and process the iris image in the iris image core processing unit 120. In the process, the iris image algorithm is used for encryption. Preferably, the information encryption unit 150 is electrically connected to the main control module 122.

Further, the FPGA-based hardware iris recognition system 100 may further include a display unit 160 electrically connected to the iris image core processing unit 120.

In the embodiment, the display unit 160 is configured to display an identification process or a recognition result of the iris image. For example, when the iris image passes the recognition, the display unit 160 displays "identification success", and when the iris image does not pass the recognition, the display unit 160 displays "identification failure" to prompt the user to recognize the result. Preferably, the display unit 160 is electrically connected to the main control module 122.

It should be noted that, in this embodiment, the FPGA-based hardware iris recognition system 100 further includes a power supply module (not shown) configured to give all of the FPGA-based hardware iris recognition system 100 Units and modules provide power. Preferably, the power module employs stepped control logic to effectively control the power consumption of the entire FPGA-based hardware iris recognition system 100.

It can be understood that, in this embodiment, the main control module 122 is configured to perform management control of the FPGA-based hardware iris recognition system 100, for example, logic control, communication control, algorithm control, authority setting control, and flow control of the system. Wait.

It should be noted that the modules and units involved in the processing of the iris image are preferably implemented by a hardware circuit inside the FPGA chip, and each of the internal hardware algorithm units in the image processing adopts a parallel processing structure of the pipeline. In order to make the speed of the iris image in the process of processing and recognition significantly improved, the hardware circuit also ensures the stability and security of the FPGA-based hardware iris recognition system 100. Moreover, in the embodiment, the FPGA chip is used as an interface for the image sensor to collect the iris image, and can be flexibly compatible with various types of image sensors to meet the application requirements of image sensors with different application requirements in different environments.

Second embodiment

Please refer to FIG. 3 , which is a structural block diagram of an FPGA-based hardware iris recognition system 100 according to a second embodiment of the present disclosure. In this embodiment, the FPGA-based hardware iris recognition system 100 and the FPGA-based hardware iris recognition system 100 provided by the first embodiment have substantially the same system structure and function, and thus the structure and function in this embodiment. The same parts will not be described again, and only the different parts will be described in detail. As can be seen from FIG. 4, the FPGA-based hardware iris recognition system 100 in this embodiment further includes a communication interface unit 170, which is processed with the iris image core, as compared with the first embodiment. Unit 120 is electrically coupled and configured to transmit data. Preferably, the communication interface unit 170 may be an Ethernet interface, an Inter-Integrated Circuit (IIC) interface, a communication interface such as a UART or a USB.

As shown in FIG. 4, it is a schematic diagram of the connection between the FPGA-based hardware iris recognition system 100 and the external device 200. In this embodiment, the FPGA-based hardware iris recognition system 100 can be connected to the external device 200 through the communication interface unit 170 for information interaction and setting authority, etc., for example, the communication interface unit 170 is in the iris image core. Data such as a recognition result, a control command, and the like are transmitted to the external device 200 under the control of the processing unit 120. The FPGA-based hardware iris recognition system 100 can be connected to the external device 200 through the communication interface unit 170 to acquire or update the correspondence between the user iris template information or the user iris template information stored in the storage unit 140 and the user's personal information. Relationships, etc.

In summary, the FPGA-based hardware iris recognition system provided by the embodiments of the present disclosure includes an image acquisition unit, an iris image core processing unit, an auxiliary illumination unit, a storage unit, an information encryption unit, a display unit, and a communication interface unit. The image acquisition unit, the auxiliary illumination unit, the storage unit, the information encryption unit, the display unit, and the communication interface unit are all electrically connected to the iris image core processing unit, the information encryption unit and the iris image core processing unit and the The storage unit is electrically connected; the image acquisition unit includes an image sensor and an optical lens module, and the iris image core processing unit includes a main control module, a preprocessing module, an encoding module, a comparison recognition module, and an image acquisition control module. The image acquisition control module, the pre-processing module, the encoding module, and the comparison identification module are all electrically connected to the main control module, and the image acquisition control module is electrically connected to the image acquisition unit and the auxiliary illumination unit. When the FPGA-based hardware iris recognition system performs the recognition of the human iris characteristic information, the image acquisition control module controls the image acquisition unit to collect the iris image to be recognized under the control of the main control module, The pre-processing module pre-processes the iris image, the encoding module encodes the pre-processed iris image to extract the iris characteristic information, and the alignment recognition module compares the iris characteristic information with the Pre-stored user iris template information is compared to obtain matching similarity. If the matching similarity is within a preset range, the comparison identifying module determines that the iris image is recognized, otherwise, determining the iris The image is not recognized, and the recognition result is displayed by the display unit. The FPGA-based hardware iris recognition system realizes the iris image acquisition and processing through the hardware circuit, and has a significant improvement in the recognition speed, and ensures the stability and safety of the iris recognition, and has very powerful ease of use and It is versatile and has obvious advantages in system integration and ease of use, and the user experience is better.

It should be noted that, in this context, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these There is any such actual relationship or order between entities or operations. Furthermore, the term "comprises" or "comprises" or "comprises" or any other variations thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that comprises a plurality of elements includes not only those elements but also Other elements, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising a ..." does not exclude the presence of additional equivalent elements in the process, method, item, or device that comprises the element.

The above description is only a preferred embodiment of the present disclosure, and is not intended to limit the disclosure, and various changes and modifications may be made to the present disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the present disclosure are intended to be included within the scope of the present disclosure. It should be noted that similar reference numerals and letters indicate similar items in the following figures, and therefore, once an item is defined in a drawing, it is not necessary to further define and explain it in the subsequent drawings.

Industrial applicability

The FPGA-based hardware iris recognition system, method and readable storage medium realize the iris image acquisition and processing through the hardware circuit of the FPGA, and the recognition speed is significantly improved, and the stability and safety of the iris recognition are ensured. It has very powerful ease of use and versatility, and has obvious advantages in system integration and ease of use, and the user experience is better.

Claims

An FPGA-based hardware iris recognition system, comprising: an image acquisition unit and an iris image core processing unit, wherein the image acquisition unit is electrically connected to the iris image core processing unit;

The image acquisition unit is configured to collect an iris image to be identified; the iris image core processing unit is configured to process the iris image to extract iris characteristic information, and the iris characteristic information and pre-stored user iris template information The comparison is performed to obtain a comparison result, and it is determined whether the iris image passes the recognition based on the comparison result.
The FPGA-based hardware iris recognition system of claim 1 , wherein the iris image core processing unit is an FPGA.
The FPGA-based hardware iris recognition system according to claim 1 or 2, wherein the iris image core processing unit comprises a main control module, a preprocessing module, an encoding module, and a comparison identification module, and the preprocessing module And the encoding module and the comparison identifying module are electrically connected to the main control module;

The pre-processing module is configured to pre-process the iris image, the encoding module is configured to encode the pre-processed iris image to extract the iris property information, and the alignment recognition module is configured to The iris characteristic information is compared with the pre-stored user iris template information to obtain a matching similarity. If the matching similarity is within a preset range, the comparison identifying module determines that the iris image passes Identifying, otherwise, determining that the iris image does not pass the recognition.
The FPGA-based hardware iris recognition system of claim 3, wherein the pre-processing module is specifically configured to perform image enhancement, image filtering or image segmentation on the image acquisition unit.
The FPGA-based hardware iris recognition system of claim 3, wherein the encoding module is specifically configured to perform image template creation, feature extraction or target recognition on the preprocessed iris image.
The FPGA-based hardware iris recognition system of claim 3, wherein the iris image core processing unit further comprises an image acquisition control module, the image acquisition control module and the main control module, and the image acquisition The units are all electrically connected, and the image acquisition control module is configured to control the image acquisition unit to collect the iris image under the control of the main control module.
The FPGA-based hardware iris recognition system of claim 6, wherein the FPGA-based hardware iris recognition system further comprises an auxiliary illumination unit, the auxiliary illumination unit being electrically connected to the image acquisition control module, The image acquisition control module is further configured to control the auxiliary illumination unit to provide illumination for the collection of the iris image under control of the main control module.
The FPGA-based hardware iris recognition system according to claim 1 or 2, wherein the FPGA-based hardware iris recognition system further comprises a storage unit, the storage unit being electrically connected to the iris image core processing unit, The storage unit is configured to store the user iris template information.
The FPGA-based hardware iris recognition system of claim 8, wherein the FPGA-based hardware iris recognition system further comprises an information encryption unit, the information encryption unit and the iris image core processing unit, The storage units are all electrically connected, and the information encryption unit is configured to encrypt the user iris template information and the iris image algorithm stored by the storage unit.
The FPGA-based hardware iris recognition system according to claim 1 or 2, wherein the image acquisition unit comprises an image sensor and an optical lens module.
The FPGA-based hardware iris recognition system of claim 1 or 2, wherein the FPGA-based hardware iris recognition system further comprises a display unit, the display unit being electrically connected to the iris image core processing unit, The display unit is configured to display an identification process or a recognition result of the iris image.
The FPGA-based hardware iris recognition system according to claim 1 or 2, wherein the FPGA-based hardware iris recognition system further comprises a communication interface unit configured to transmit data.
An FPGA-based hardware iris recognition system, wherein the FPGA-based hardware iris recognition system comprises an image acquisition unit and an iris image core processing unit electrically connected to the image acquisition unit, the iris image core processing unit The main control module, the pre-processing module, the encoding module, and the comparison identification module, the pre-processing module, the encoding module, and the comparison identification module are all electrically connected to the main control module;

The image acquisition unit is configured to collect an iris image to be identified; the pre-processing module is configured to pre-process the iris image, and the encoding module is configured to encode the pre-processed iris image to extract an iris Characteristic information, the comparison identification module is configured to compare the iris characteristic information with pre-stored user iris template information to obtain a matching similarity, if the matching similarity is within a preset range, The comparison recognition module determines that the iris image passes the recognition, otherwise, determines that the iris image does not pass the recognition.
An iris recognition method, characterized in that the method is applied to the FPGA-based hardware iris recognition system according to any one of claims 1 to 13, the method comprising:

Collecting an iris image to be identified by the image acquisition unit;

The iris image is processed by the iris image core processing unit to extract iris characteristic information, and the iris characteristic information is compared with pre-stored user iris template information to obtain a comparison result, and according to the comparison As a result, it is determined whether the iris image passes the recognition.
A readable storage medium is characterized in that it is applied to an FPGA-based hardware iris recognition system, and the FPGA-based hardware iris recognition system includes an image acquisition unit and an iris image core processing unit, and the iris image core processing unit is based on an FPGA. Implementing; the readable storage medium storing instructions that, when invoked or executed by the iris image core processing unit, cause the iris image core processing unit to form a hardware circuit to acquire the image acquisition unit The iris image is processed to extract iris characteristic information, and the iris characteristic information is compared with pre-stored user iris template information to obtain a comparison result, and whether the iris image passes the recognition is determined according to the comparison result.