WO2018209787A1 - 均衡保护电路和电池均衡系统 - Google Patents

均衡保护电路和电池均衡系统 Download PDF

Info

Publication number
WO2018209787A1
WO2018209787A1 PCT/CN2017/093373 CN2017093373W WO2018209787A1 WO 2018209787 A1 WO2018209787 A1 WO 2018209787A1 CN 2017093373 W CN2017093373 W CN 2017093373W WO 2018209787 A1 WO2018209787 A1 WO 2018209787A1
Authority
WO
WIPO (PCT)
Prior art keywords
module
signal
equalization
fault
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/093373
Other languages
English (en)
French (fr)
Inventor
叶伏明
刘祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Contemporary Amperex Technology Co Ltd
Original Assignee
Contemporary Amperex Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Contemporary Amperex Technology Co Ltd filed Critical Contemporary Amperex Technology Co Ltd
Publication of WO2018209787A1 publication Critical patent/WO2018209787A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or discharging batteries or for supplying loads from batteries

Definitions

  • the present invention relates to the field of power batteries, and in particular, to a balanced protection circuit and a battery equalization system.
  • the battery module includes a plurality of batteries. Due to individual differences or temperature differences of the plurality of cells in the battery module, the consistency of the cells in the battery module is affected, so that the power, voltage or current of each battery cell in the battery module is inconsistent, thereby Reduce the life of the battery module.
  • a balancing strategy is adopted for each battery cell in the battery module. For example, to add electric energy to a cell with a low voltage, increase the voltage of a cell with a low voltage, and make the voltage of the cell reach an equilibrium voltage. Alternatively, the battery with a high voltage is discharged to lower the voltage of the battery with a high voltage, so that the voltage of the battery reaches an equalized voltage. In the equalization strategy, the equalization voltage is required to remain within a certain safe range. However, in the process of equalization, the cell may be overcharged or overdischarged by the equalization strategy due to some unexpected factors, and the equilibrium voltage of the cell exceeds the safe range. In turn, the battery module has a safety failure, which reduces the safety of the battery module.
  • the equalization voltage is detected by the equalization protection circuit. If the equalization voltage exceeds the safe range, a fault signal is generated, and the control equalization control chip stops working immediately. When the equalization control chip stops working, the equalization voltage disappears and the fault signal disappears. In other words, the fault signal exists for a very short time and is difficult to capture. As a result, it is difficult to record the time when the safety fault occurs, and thus the safety fault cannot be located according to the time when the battery module is maintained in the later stage.
  • the embodiment of the invention provides a balance protection circuit and a battery module system, which can record the time when the safety fault occurs, thereby realizing the positioning of the safety fault when the battery module is maintained in the later stage.
  • an equalization protection circuit including:
  • An undervoltage detection module wherein the input end of the undervoltage detection module is connected to the equalization voltage sampling end and the first voltage supply end, and the output end of the undervoltage detection module is connected to the input end of the fault signal triggering module, the undervoltage
  • the detecting module is configured to convert the voltage of the first voltage supply end into a reference lower limit voltage, and if the equalization voltage of the equalization voltage sampling end is less than the reference lower limit voltage, output an undervoltage trigger signal to the fault signal triggering module;
  • An overvoltage detection module wherein an input end of the overvoltage detection module is connected to the equalization voltage sampling end and a second voltage supply end, and an output end of the overvoltage detection module is connected to an input end of the fault signal triggering module,
  • the overvoltage detection module is configured to convert the voltage of the second voltage supply terminal into a reference upper limit voltage, and if the equalization voltage of the equalization voltage sampling end is greater than the reference upper limit voltage, output an overvoltage trigger signal to the fault signal trigger module.
  • the fault signal triggering module the output end of the fault signal triggering module is connected to the input end of the fault signal holding module, and the fault signal triggering module is configured to receive the undervoltage triggering signal or the overvoltage triggering signal,
  • the fault signal holding module outputs a fault trigger signal
  • the fault signal holding module, the output end of the fault signal holding module is connected to the input end of the protection control module and the external signal output end, and the fault signal holding module is configured to receive the fault trigger signal and generate the hold for a period of time. a fault reporting signal and outputting the fault report signal to the protection control module and the external signal output;
  • the protection control module the output end of the protection control module is connected to the equalization control chip, the protection control module is configured to receive the fault report signal, output a work stop signal to the equalization control chip, and control the equalization control The chip stopped working.
  • an embodiment of the present invention provides a battery equalization system including the equalization protection circuit in the above embodiment.
  • the embodiment of the invention provides an equalization protection circuit and a battery equalization system
  • the equalization protection circuit comprises an undervoltage detection module, an overvoltage detection module, a fault signal triggering module, a fault signal holding module and a protection control module.
  • Fault signal when receiving undervoltage trigger signal or overvoltage trigger signal
  • the trigger module outputs a fault trigger signal to the fault signal holding module.
  • the fault signal holding module receives the fault trigger signal, generates a fault report signal that is kept for a period of time, and outputs a fault report signal to the protection control module and the external signal output end.
  • the external signal output can be connected to the micro control unit. Since the fault report signal can be kept for a period of time, the micro control unit can easily capture the fault report signal. In turn, it is possible to record the time when the safety fault occurs, and to locate the safety fault when the battery module is maintained in the later stage.
  • 1 is a schematic structural diagram of an equalization protection circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of an equalization protection circuit according to an example of an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an equalization protection circuit according to another embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an equalization protection circuit in an example of another embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of an equalization protection circuit according to still another embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of an equalization protection circuit in an example of another embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of an equalization protection circuit according to an embodiment of the present invention.
  • the equalization protection circuit includes an undervoltage detection module P1, an overvoltage detection module P2, a fault signal triggering module P3, a fault signal holding module P4, and a protection control module P5.
  • the input end of the undervoltage detection module P1 is connected to the equalization voltage sampling terminal Vin and the first voltage supply terminal V1, and the output terminal of the undervoltage detection module P1 is connected to the input terminal of the fault signal triggering module P3.
  • the undervoltage detection module P1 is configured to convert the voltage of the first voltage supply terminal V1 into a reference lower limit voltage. If the equalization voltage of the equalization voltage sampling terminal Vin is less than the reference lower limit voltage, the undervoltage trigger signal is output to the fault signal triggering module P3.
  • the equalization voltage sampling terminal Vin can provide the collected equalization voltage.
  • the undervoltage trigger signal indicates that the equalization voltage is undervoltage.
  • the input end of the overvoltage detecting module P2 is connected to the equalization voltage sampling terminal Vin and the second voltage supply terminal V2, and the output end of the overvoltage detecting module P2 is connected to the input terminal of the fault signal triggering module P3.
  • the overvoltage detection module P2 is configured to convert the voltage of the second voltage supply terminal V2 into a reference upper limit voltage. If the equalization voltage of the equalization voltage sampling terminal Vin is greater than the reference upper limit voltage, the overvoltage trigger signal is output to the fault signal triggering module P3.
  • the voltage of the first voltage supply terminal V1 and the voltage of the second voltage supply terminal V2 may be the same or different, but the reference upper limit voltage is greater than the reference lower limit voltage.
  • the overvoltage trigger signal indicates that the equalization voltage has an overvoltage phenomenon.
  • the output of the fault signal triggering module P3 is connected to the input of the fault signal holding module P4.
  • the fault signal triggering module P3 is configured to receive an undervoltage trigger signal or an overvoltage trigger signal, and output a fault trigger signal to the fault signal holding module P4.
  • the output of the fault signal holding module P4 is connected to the input of the protection control module P5 and the external signal output terminal Vout.
  • the fault signal holding module P4 is configured to receive the fault trigger signal, generate a fault report signal that is held for a period of time, and output a fault report signal to the protection control module P5 and the external signal output terminal Vout.
  • the fault trigger signal lasts for a very short time.
  • a fault report signal is generated.
  • the fault report signal can be held for a period of time, which is equivalent to locking the fault trigger signal with a short duration, so that the fault trigger signal can be captured by the fault report signal.
  • the initial time of the fault report signal that remains for a period of time is the same as the time when the fault trigger signal is received. Therefore, the output fault report signal can be collected from the external signal output terminal Vout, and the initial time of the fault report signal for a period of time can be regarded as the time when the safety fault occurs.
  • the output of the protection control module P5 is connected to the equalization control chip.
  • the protection control module P5 is configured to receive the fault report signal, output a work stop signal to the equalization control chip, and control the equalization control chip to stop working.
  • the equalization control chip stops working, indicating that the battery equalization process is aborted.
  • the equalization protection circuit and the battery equalization system include an undervoltage detection module P1, an overvoltage detection module P2, a fault signal triggering module P3, a fault signal holding module P4, and a protection control module P5.
  • the fault signal triggering module P3 When receiving the undervoltage trigger signal or the overvoltage trigger signal, the fault signal triggering module P3 outputs a fault trigger signal to the fault signal holding module P4.
  • the fault signal holding module P4 receives the fault trigger signal, generates a fault report signal that is held for a period of time, and outputs a fault report signal to the protection control module P5 and the external signal output terminal Vout.
  • the external signal output terminal Vout can be connected to the micro control unit. Since the fault report signal can be maintained for a period of time, the micro control unit can easily capture the fault report signal. In turn, it is possible to record the time when the safety fault occurs, and to locate the safety fault when the battery module is maintained in the later stage.
  • FIG. 2 is a schematic structural diagram of an equalization protection circuit according to an example of an embodiment of the present invention.
  • the undervoltage detection module P1, the overvoltage detection module P2, the fault signal triggering module P3, the fault signal holding module P4, and the protection control module P5 in FIG. 1 may each be composed of components.
  • the specific structure of the undervoltage detecting module P1, the overvoltage detecting module P2, the fault signal triggering module P3, the fault signal holding module P4, and the protection control module P5 will be described below.
  • the undervoltage detecting module P1 includes a first resistor combination, a second resistor combination, and a first comparator M1.
  • one end of the first resistor combination is connected to the first voltage supply terminal V1
  • the other end of the first resistor combination is connected to one end of the second resistor combination
  • the other end of the second resistor combination is grounded to GND1.
  • the non-inverting input terminal of the first comparator M1 is connected to the equalization voltage sampling terminal Vin, and the inverting input terminal of the first comparator M1 is connected to the other end of the first resistor combination and the second resistor combination, and the first comparator is connected.
  • the output of M1 is connected to the fault signal triggering module P3.
  • the first resistor combination includes resistors R3 and R4, and the second resistor combination includes resistor R2.
  • the first resistor combination and the second resistor combination are in a series relationship, and the reference lower limit voltage received by the inverting input terminal of the first comparator M1 is the voltage of one end of the second resistor combination. So can In the circuit design, according to the working scene or the work requirement, the resistance of the first resistor combination and the resistance of the second resistor combination are adjusted, so that the voltage provided by the first voltage supply terminal V1 is converted into the reference lower limit voltage.
  • the first resistor combination includes at least one resistor
  • the second resistor combination includes at least one resistor.
  • the combination of the resistors in the first resistor combination and the resistor combination in the second resistor combination are not limited herein. It is also possible to provide a protection resistor in the undervoltage detection module P1 to ensure that the current flowing through the undervoltage detection module P1 is not excessively large, for example, the resistor R1 in FIG. 2 is a protection resistor.
  • the first comparator M1 is further connected to the seventh voltage supply terminal V7 and the ground terminal GND2, and the seventh voltage supply terminal V7 can supply the operating voltage to the first comparator M1.
  • a capacitor C1 for filtering may be provided in the undervoltage detection module P1.
  • One end of the capacitor C1 is connected to the non-inverting input terminal of the first comparator M1, and the capacitor C1 is further connected. One end is grounded.
  • the overvoltage detecting module P2 includes a third resistor combination, a fourth resistor combination, and a second comparator M2.
  • one end of the third resistor combination is connected to the second voltage supply terminal V2
  • the other end of the third resistor combination is connected to one end of the fourth resistor combination
  • the other end of the fourth resistor combination is grounded to GND3.
  • the non-inverting input terminal of the second comparator M2 is connected to the other end of the combination of the third resistor and the fourth resistor, and the inverting input terminal of the second comparator M2 is connected to the equalization voltage sampling terminal Vin, and the second comparator The output of M2 is connected to the fault signal triggering module P3.
  • the third resistor combination includes a resistor R8, and the fourth resistor combination includes resistors R6 and R7.
  • the third resistor combination and the fourth resistor combination are in a series relationship, and the reference upper limit voltage received by the non-inverting input terminal of the second comparator M2 is the voltage of one end of the fourth resistor combination. Therefore, in the circuit design, according to the working scene or the work requirement, the resistance value of the third resistor combination and the resistance of the fourth resistor combination can be adjusted, so that the voltage provided by the second voltage supply terminal V2 is converted into the reference upper limit voltage.
  • the reference lower limit voltage and the reference upper limit voltage can be set more precisely, reducing the protection range of the equalization voltage, making the protection of the equalization voltage more precise.
  • the third resistor combination includes at least one resistor
  • the fourth resistor combination includes at least one resistor
  • the combination of the resistors in the third resistor combination and the resistor combination in the fourth resistor combination are not limited herein.
  • a protection resistor can be provided in the overvoltage detection module P2 to ensure that the current flowing through the voltage detection module P2 is not excessive.
  • the resistor R5 in FIG. 2 is a protection resistor.
  • the second comparator M2 is also connected to the eighth voltage supply terminal V8 and the ground terminal GND4, and the fourth voltage supply terminal V4 can provide an operating voltage for the eighth comparator.
  • a capacitor C2 for filtering may be disposed in the overvoltage detection module P2.
  • One end of the capacitor C2 is connected to the inverting input terminal of the second comparator M2, and the capacitor C2 is further connected. One end is grounded.
  • the fault signal triggering module P3 includes a first optical coupler OC1.
  • the first photocoupler OC1 includes a first light emitting diode L1 and a first photosensitive semiconductor tube T1.
  • the anode of the first LED L1 is connected to the third voltage supply terminal V3, and the cathode of the first LED L1 is connected to the output of the undervoltage detection module P1 and the output of the overvoltage detection module P2.
  • One end of the first photosensitive semiconductor tube T1 is connected to the input terminal of the fault signal holding module P4, and the other end of the first photosensitive semiconductor tube T1 is grounded to GND5.
  • the resistor R9 in FIG. 2 is a protection resistor.
  • the fault signal holding module P4 includes a first transistor Q1 and a second transistor Q2.
  • the control terminal of the first transistor Q1 is connected to the output terminal of the fault signal triggering module P3, the first terminal of the first transistor Q1 is connected to the fourth voltage supply terminal V4, and the second terminal of the first transistor Q1 is connected to the external signal output terminal. Vout connection.
  • the external signal output terminal Vout can be externally connected to a Micro Control Unit (MCU), and the micro control unit records the time when the safety fault occurs.
  • MCU Micro Control Unit
  • the control terminal of the second transistor Q2 is connected to the second terminal of the first transistor Q1 and the input terminal of the protection control module P5.
  • the first terminal of the second transistor Q2 is grounded to GND6, and the second terminal of the second transistor Q2 is triggered by a fault signal.
  • the output of module P3 is connected.
  • the protection control module P5 includes a third transistor Q3 and a second photocoupler OC2.
  • Second optocoupler The combiner OC2 includes a second light emitting diode L2 and a second photosensitive semiconductor tube T2.
  • the control terminal of the third transistor Q3 is connected to the output terminal of the fault signal holding module P4, the first terminal of the third transistor Q3 is connected to the ground GND7, and the second terminal of the third transistor Q3 is connected to the cathode of the second light emitting diode L2.
  • the anode of the second light emitting diode L2 is connected to the fifth voltage supply terminal V5.
  • One end of the second photosensitive semiconductor tube T2 is connected to the equalization control chip, and the other end of the second photosensitive semiconductor tube T2 is grounded to GND8.
  • one end of the second photosensitive semiconductor tube T2 can be coupled to an enable pin of the equalization control chip.
  • protection resistor in the protection control module P5 to ensure that the current flowing through the protection control module P5 is not excessively large, and to prevent the transistor from being burnt out.
  • the resistors R16, R17 and R18 in FIG. 2 are protection resistors.
  • the first transistor Q1 is a PNP transistor
  • the second transistor Q2 and the third transistor Q3 are both NPN transistors
  • the control terminal is a base
  • the first end is an emitter
  • the second end is a collector.
  • the non-inverting input terminal of the first comparator M1 receives the equalization voltage of the input of the equalization voltage sampling terminal Vin, and the inverting input terminal of the first comparator M1 receives the reference lower limit voltage. If the equalization voltage is less than the reference lower limit voltage, the output of the first comparator M1 outputs a low level signal (ie, an undervoltage trigger signal).
  • the inverting input of the second comparator M2 receives the equalized voltage of the input of the equalized voltage sampling terminal Vin, and the non-inverting input of the second comparator M2 receives the reference upper limit voltage. If the equalization voltage is greater than the reference upper limit voltage, the output of the second comparator M2 outputs a low level signal (ie, an overvoltage trigger signal).
  • the first light emitting diode L1 in the first photocoupler OC1 receives the low level signal, the first light emitting diode L1 is turned on and emits light.
  • the first photosensitive semiconductor tube T1 in the first photocoupler OC1 receives the light emitted from the first light emitting diode L1 and is turned on, pulling the signal of one end of the first photosensitive semiconductor tube T1 low.
  • the control terminal of the first transistor Q1 receives a low level signal (ie, a fault trigger signal) at one end of the first photosensitive semiconductor tube T1, and the first transistor Q1 is turned on.
  • the first transistor Q1 transmits a high level signal provided by the fourth voltage supply terminal V4 of the first terminal to the control terminal of the second transistor Q2 and The control terminal of the three transistor Q3.
  • the second transistor Q2 is turned on to pull the signal of the control terminal of the first transistor Q1 to a low level signal.
  • the first transistor Q1 will continue to be in an on state, and the external signal output terminal Vout outputs a high level signal (ie, a fault report signal) for a period of time until the fault signal holding module P4 is reset.
  • the control terminal of the third transistor Q3 receives a high level signal, and the third transistor Q3 is turned on.
  • the cathode of the second light-emitting transistor in the second photocoupler OC2 is in communication with the ground, and the second light-emitting transistor is turned on and emits light.
  • the second photosensitive semiconductor tube T2 in the second photocoupler OC2 is turned on to output a low level signal (ie, a work stop signal) to the equalization control chip.
  • the equalization control chip receives the low level signal and stops working to protect the battery module.
  • FIG. 3 is a schematic structural diagram of an equalization protection circuit according to another embodiment of the present invention. 3 is different from FIG. 1 in that the equalization protection circuit of FIG. 3 further includes a reset module P6.
  • the input end of the reset module P6 is connected to the external signal input terminal Vr, and the output end of the reset module P6 is connected to the input end of the fault signal holding module P4 for receiving the control signal of the external signal input terminal Vr, and outputting to the fault signal holding module P4.
  • the reset signal controls the fault signal holding module P4 to reset.
  • the reset module P6 can control the reset of the fault signal holding module P4 to start a new round of equalization voltage detection.
  • FIG. 4 is a schematic structural diagram of an equalization protection circuit in an example of another embodiment of the present invention. 4 is different from FIG. 2 in that the new reset module P6 in FIG. 4 can be composed of components. The specific structure of the reset module P6 will be described below.
  • the reset module P6 includes a fourth transistor Q4.
  • the control terminal of the fourth transistor Q4 is connected to the external signal input terminal Vr, the first terminal of the fourth transistor Q4 is connected to the sixth voltage supply terminal V6, and the second terminal of the fourth transistor Q4 is connected to the input terminal of the fault signal holding module P4. .
  • the external signal input terminal Vr can be connected to the micro control unit, and the micro control unit sends a signal to control the reset module P6.
  • the resistors R19 and R20 are protection resistors to prevent the current flowing through the reset module P6 from being excessively large, and to prevent the transistor from being burned out.
  • the fourth transistor Q4 will be described as an example of a PNP transistor.
  • the signal of the external signal input terminal Vr is initially a high level signal, and the fourth transistor Q4 is turned off.
  • the micro control unit monitors When the battery voltage in the battery module is normal and the communication of the battery module is normal, the low-level signal is input through the external signal input terminal Vr.
  • the control terminal of the fourth transistor Q4 receives the low level signal, and the fourth transistor Q4 is turned on to transmit the high level signal to the control terminal of the first transistor Q1.
  • the control terminal of the first transistor Q1 receives a high-level signal (ie, a reset signal), the first transistor Q1 is turned off, the control terminal of the second transistor Q2 has no high-level signal input, and the external signal output terminal Vout has no signal output, thereby achieving a fault.
  • a high-level signal ie, a reset signal
  • the control terminal of the third transistor Q3 has no high level signal input, and the third transistor Q3 is turned off.
  • the second photocoupler OC2 is turned off, and the low level signal (ie, the operation stop signal) cannot be supplied to the equalization control chip.
  • the equalization control chip can continue to work.
  • FIG. 5 is a schematic structural diagram of an equalization protection circuit according to still another embodiment of the present invention. 5 is different from FIG. 3 in that the equalization protection circuit of FIG. 5 further includes an operation signal providing module P7.
  • the input end of the working signal providing module P7 is connected to the working signal providing end, and the output end of the working signal providing module P7 is connected to the equalization control chip.
  • the working signal providing module P7 is configured to provide a working signal for the equalization control chip when the protection control module P5 does not receive the fault report signal.
  • FIG. 6 is a schematic structural diagram of an equalization protection circuit in an example of another embodiment of the present invention. 6 is different from FIG. 4 in that the new work signal providing module P7 in FIG. 6 can be composed of components. The specific structure of the operation signal providing module P7 will be described below.
  • the operational signal supply module P7 includes an equivalent resistance combination and a diode.
  • the diodes may be one or more than one.
  • the first end of the equivalent resistance combination is connected to the equalization control chip, the second end of the equivalent resistance combination is grounded, and the third end of the equivalent resistance combination is connected to the negative pole of the diode.
  • the anode of the diode is connected to the working signal supply terminal.
  • the equivalent resistance combination may include resistors R21 and R22.
  • resistors R21 and R22 There are three diodes, D1, D2 and D3.
  • the positive electrode of the diode D1, the positive electrode of D2, and the positive electrode of D3 are connected to the operation signal supply terminals Vw1, Vw2, and Vw3, respectively.
  • One end of the resistor R21 is connected to the equalization control chip, and the other end of the resistor R21 is connected to one end of the resistor R22, the cathode of the diode D1, the cathode of D2, and the cathode of D3.
  • the other end of the resistor R22 is grounded.
  • the third transistor Q3 does not receive a high level signal (ie, a fault report signal)
  • the working signal supply terminals Vw1, Vw2, and/or Vw3 provide a high level signal to the equalization control chip (ie, Signaling), so that the equalization control chip works normally.
  • first voltage supply terminal V1, the second voltage supply terminal V2, the third voltage supply terminal V3, the fourth voltage supply terminal V4, the fifth voltage supply terminal V5, and the sixth voltage supply terminal in the above embodiment V6, the seventh voltage supply terminal V7, and the eighth voltage supply terminal V8 each provide a voltage higher than 0V.
  • the first voltage supply terminal V1, the second voltage supply terminal V2, the third voltage supply terminal V3, the fourth voltage supply terminal V4, the fifth voltage supply terminal V5, the sixth voltage supply terminal V6, the seventh voltage supply terminal V7, and the first The voltage of the eight voltage supply terminals V8 may be the same or different, and may be adjusted according to the working requirements of the equalization protection circuit.
  • the embodiment of the invention further provides a battery equalization system, which includes the equalization protection circuit in the above embodiment.
  • the battery equalization system may further include an equalization control chip, a battery module or other functional chips and functional modules, which are not limited herein.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Protection Of Static Devices (AREA)

Abstract

一种均衡保护电路和电池均衡系统，涉及动力电池领域。该均衡保护电路包括欠压检测模块（P1）、过压检测模块（P2）、故障信号触发模块（P3）、故障信号保持模块（P4）和保护控制模块（P5）。其中，故障信号保持模块（P4）的输出端与保护控制模块（P5）的输入端和外接信号输出端（Vout）连接，故障信号保持模块（P4）用于接收故障触发信号，生成保持一段时间的故障报告信号，并向保护控制模块（P5）和外接信号输出端（Vout）输出故障报告信号，由于故障报告信号可保持一段时间，所以微控制单元能够轻易捕捉到故障报告信号，进而能够实现安全故障发生时间的记录，从而实现后期对电池模组进行维护时对安全故障的定位。

Description

均衡保护电路和电池均衡系统 技术领域
本发明涉及动力电池领域，尤其涉及一种均衡保护电路和电池均衡系统。
背景技术
随着动力电池技术的发展，为了满足用户的各种设备对于电池模组电量的要求，电池模组的容量也在逐渐增大。电池模组包括多个电芯。由于电池模组中的多个电芯的个体差异或温度差异等，电池模组中的电芯的一致性受到影响，使得电池模组中的各个电芯的电量、电压或电流等不一致，从而降低了电池模组的寿命。
为了保证电池模组的寿命，对电池模组中的各个电芯采取均衡策略。比如，为电压低的电芯补充电能，提高电压低的电芯的电压，使电芯的电压达到均衡电压。或者，对电压高的电芯进行放电，降低电压高的电芯的电压，使电芯的电压达到均衡电压。在均衡策略中要求均衡电压保持在一定安全范围内。但可能在均衡过程中会因为某些意外因素，导致采用均衡策略的电芯过充或过放，电芯的均衡电压超出了安全范围。进而使得电池模组发生安全故障，降低了电池模组的安全性。
为了保证电池模组的安全性，通过均衡保护电路来检测均衡电压，若均衡电压超出安全范围，则产生故障信号，控制均衡控制芯片立刻停止工作。均衡控制芯片停止工作时，均衡电压消失，故障信号也随之消失。也就是说，故障信号存在时间非常短暂，难以捕捉。从而导致难以记录安全故障发生的时间，进而使得后期对电池模组进行维护时无法根据时间来定位安全故障。
发明内容
本发明实施例提供了一种均衡保护电路和电池模组系统，能够实现安全故障发生的时间的记录，从而实现后期对电池模组进行维护时对安全故障的定位。
一方面，本发明实施例提供了一种均衡保护电路，包括：
欠压检测模块，所述欠压检测模块的输入端与均衡电压采样端和第一电压提供端连接，所述欠压检测模块的输出端与故障信号触发模块的输入端连接，所述欠压检测模块用于将所述第一电压提供端的电压转化为基准下限电压，若均衡电压采样端的均衡电压小于所述基准下限电压，则向所述故障信号触发模块输出欠压触发信号；
过压检测模块，所述过压检测模块的输入端与所述均衡电压采样端和第二电压提供端连接，所述过压检测模块的输出端与所述故障信号触发模块的输入端连接，所述过压检测模块用于将所述第二电压提供端的电压转化为基准上限电压，若均衡电压采样端的均衡电压大于所述基准上限电压，则向所述故障信号触发模块输出过压触发信号；
所述故障信号触发模块，所述故障信号触发模块的输出端与故障信号保持模块的输入端连接，所述故障信号触发模块用于接收所述欠压触发信号或所述过压触发信号，向所述故障信号保持模块输出故障触发信号；
所述故障信号保持模块，所述故障信号保持模块的输出端与保护控制模块的输入端和外接信号输出端连接，所述故障信号保持模块用于接收所述故障触发信号，生成保持一段时间的故障报告信号，并向所述保护控制模块和所述外接信号输出端输出所述故障报告信号；以及
所述保护控制模块，所述保护控制模块的输出端与均衡控制芯片连接，所述保护控制模块用于接收所述故障报告信号，向所述均衡控制芯片输出工作停止信号，控制所述均衡控制芯片停止工作。
另一方面，本发明实施例提供了一种电池均衡系统，该电池均衡系统包括上述实施例中的均衡保护电路。
本发明实施例提供了一种均衡保护电路和电池均衡系统，该均衡保护电路包括欠压检测模块、过压检测模块、故障信号触发模块、故障信号保持模块和保护控制模块。当接收欠压触发信号或过压触发信号时，故障信 号触发模块向故障信号保持模块输出故障触发信号。故障信号保持模块接收故障触发信号，会生成保持一段时间的故障报告信号，并向保护控制模块和外接信号输出端输出故障报告信号。外接信号输出端可以连接微控制单元，由于故障报告信号可保持一段时间，所以微控制单元能够轻易捕捉到故障报告信号。进而能够实现安全故障发生的时间的记录，实现后期对电池模组进行维护时对安全故障的定位。
附图说明
从下面结合附图对本发明的具体实施方式的描述中可以更好地理解本发明，其中，相同或相似的附图标记表示相同或相似的特征。
图1为本发明一实施例中的均衡保护电路的结构示意图；
图2为本发明一实施例中一示例的均衡保护电路的结构示意图；
图3为本发明另一实施例中的均衡保护电路的结构示意图；
图4为本发明另一实施例的示例中的均衡保护电路的结构示意图；
图5为本发明又一实施例中的均衡保护电路的结构示意图；
图6为本发明又一实施例的示例中的均衡保护电路的结构示意图。
具体实施方式
下面将详细描述本发明的各个方面的特征和示例性实施例。在下面的详细描述中，提出了许多具体细节，以便提供对本发明的全面理解。但是，对于本领域技术人员来说很明显的是，本发明可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本发明的示例来提供对本发明的更好的理解。本发明决不限于下面所提出的任何具体配置和算法，而是在不脱离本发明的精神的前提下覆盖了元素、部件和算法的任何修改、替换和改进。在附图和下面的描述中，没有示出公知的结构和技术，以便避免对本发明造成不必要的模糊。
图1为本发明一实施例中的均衡保护电路的结构示意图。如图1所示，均衡保护电路包括欠压检测模块P1、过压检测模块P2、故障信号触发模块P3、故障信号保持模块P4和保护控制模块P5。
欠压检测模块P1的输入端与均衡电压采样端Vin和第一电压提供端V1连接，欠压检测模块P1的输出端与故障信号触发模块P3的输入端连接。欠压检测模块P1用于将第一电压提供端V1的电压转化为基准下限电压，若均衡电压采样端Vin的均衡电压小于基准下限电压，向故障信号触发模块P3输出欠压触发信号。
其中，均衡电压采样端Vin可提供采集到的均衡电压。欠压触发信号表示均衡电压发生欠压现象。
过压检测模块P2的输入端与均衡电压采样端Vin和第二电压提供端V2连接，过压检测模块P2的输出端与故障信号触发模块P3的输入端连接。过压检测模块P2用于将第二电压提供端V2的电压转化为基准上限电压，若均衡电压采样端Vin的均衡电压大于基准上限电压，向故障信号触发模块P3输出过压触发信号。
其中，第一电压提供端V1的电压和第二电压提供端V2的电压可以相同，也可以不同，但要保证基准上限电压大于基准下限电压。过压触发信号表示均衡电压发生过压现象。
故障信号触发模块P3的输出端与故障信号保持模块P4的输入端连接。故障信号触发模块P3用于接收欠压触发信号或过压触发信号，向故障信号保持模块P4输出故障触发信号。
故障信号保持模块P4的输出端与保护控制模块P5的输入端和外接信号输出端Vout连接。故障信号保持模块P4用于接收故障触发信号，生成保持一段时间的故障报告信号，并向保护控制模块P5和外接信号输出端Vout输出故障报告信号。
其中，故障触发信号持续的时间非常短暂。当故障信号保持模块P4接收到故障触发信号时，生成故障报告信号。故障报告信号能够保持一段时间，相当于将持续时间短暂的故障触发信号锁死，使得可以通过故障报告信号来捕捉故障触发信号。且保持一段时间的故障报告信号的初始时刻与接收到故障触发信号的时刻相同。因此，从外接信号输出端Vout可以采集输出的故障报告信号，保持一段时间的故障报告信号的初始时刻即可看作安全故障发生的时间。
保护控制模块P5的输出端与均衡控制芯片连接。保护控制模块P5用于接收故障报告信号，向均衡控制芯片输出工作停止信号，控制均衡控制芯片停止工作。
其中，均衡控制芯片停止工作，表示电池均衡过程中止。
本发明实施例提供的均衡保护电路和电池均衡系统包括欠压检测模块P1、过压检测模块P2、故障信号触发模块P3、故障信号保持模块P4和保护控制模块P5。当接收欠压触发信号或过压触发信号时，故障信号触发模块P3向故障信号保持模块P4输出故障触发信号。故障信号保持模块P4接收故障触发信号，会生成保持一段时间的故障报告信号，并向保护控制模块P5和外接信号输出端Vout输出故障报告信号。外接信号输出端Vout可以连接微控制单元，由于故障报告信号可保持一段时间，所以微控制单元能够轻易捕捉到故障报告信号。进而能够实现安全故障发生的时间的记录，实现后期对电池模组进行维护时对安全故障的定位。
图2为本发明一实施例中一示例的均衡保护电路的结构示意图。如图2所示，图1中的欠压检测模块P1、过压检测模块P2、故障信号触发模块P3、故障信号保持模块P4和保护控制模块P5均可以由元器件组成。下面说明欠压检测模块P1、过压检测模块P2、故障信号触发模块P3、故障信号保持模块P4和保护控制模块P5的具体结构。
欠压检测模块P1包括第一电阻组合、第二电阻组合和第一比较器M1。
其中，第一电阻组合的一端与第一电压提供端V1连接，第一电阻组合的另一端与第二电阻组合的一端连接，第二电阻组合的另一端接地GND1。
第一比较器M1的正相输入端与均衡电压采样端Vin连接，第一比较器M1的反相输入端与第一电阻组合的另一端和第二电阻组合的一端均连接，第一比较器M1的输出端与故障信号触发模块P3连接。
如图2所示，第一电阻组合包括电阻R3和R4，第二电阻组合包括电阻R2。第一电阻组合和第二电阻组合为串联关系，第一比较器M1的反相输入端接收到的基准下限电压为第二电阻组合的一端的电压。因此，可以 在电路设计中，根据工作场景或工作需求，调整第一电阻组合的阻值和第二电阻组合的阻值，使得第一电压提供端V1提供的电压转换为基准下限电压。需要说明的是，第一电阻组合包括至少一个电阻，第二电阻组合包括至少一个电阻，第一电阻组合中的电阻的组合方式和第二电阻组合中的电阻组合方式在此并不限定。还可以在欠压检测模块P1中设置保护电阻，来保证流经欠压检测模块P1的电流不会过大，比如图2中的电阻R1即为保护电阻。
如图2所示，第一比较器M1还连接第七电压提供端V7和接地端GND2，第七电压提供端V7可为第一比较器M1提供工作电压。
为了提高欠压检测模块P1检测的精确度，还可以在欠压检测模块P1中设置用于滤波的电容C1，电容C1的一端与第一比较器M1的正相输入端连接，电容C1的另一端接地。
过压检测模块P2包括第三电阻组合、第四电阻组合和第二比较器M2。
其中，第三电阻组合的一端与第二电压提供端V2连接，第三电阻组合的另一端与第四电阻组合的一端连接，第四电阻组合的另一端接地GND3。
第二比较器M2的正相输入端与第三电阻组合的另一端和第四电阻组合的一端均连接，第二比较器M2的反相输入端与均衡电压采样端Vin连接，第二比较器M2的输出端与故障信号触发模块P3连接。
如图2所示，第三电阻组合包括电阻R8，第四电阻组合包括电阻R6和R7。第三电阻组合和第四电阻组合为串联关系，第二比较器M2的正相输入端接收到的基准上限电压为第四电阻组合的一端的电压。因此，可以在电路设计中，根据工作场景或工作需求，调整第三电阻组合的阻值和第四电阻组合的阻值，使得第二电压提供端V2提供的电压转换为基准上限电压。基准下限电压和基准上限电压可以设置的更加精确，缩小均衡电压的保护范围，使得对均衡电压的保护更加精准。需要说明的是，第三电阻组合包括至少一个电阻，第四电阻组合包括至少一个电阻，第三电阻组合中的电阻的组合方式和第四电阻组合中的电阻组合方式在此并不限定。还 可以在过压检测模块P2中设置保护电阻，来保证流经过压检测模块P2的电流不会过大，比如图2中的电阻R5即为保护电阻。
如图2所示，第二比较器M2还连接第八电压提供端V8和接地端GND4，第四电压提供端V4可为第八比较器提供工作电压。
为了提高过压检测模块P2检测的精确度，还可以在过压检测模块P2中设置用于滤波的电容C2，电容C2的一端与第二比较器M2的反相输入端连接，电容C2的另一端接地。
故障信号触发模块P3包括第一光耦合器OC1。第一光耦合器OC1包括第一发光二极管L1和第一光敏半导体管T1。
其中，第一发光二极管L1的正极与第三电压提供端V3连接，第一发光二极管L1的负极与欠压检测模块P1的输出端和过压检测模块P2的输出端均连接。
第一光敏半导体管T1的一端与故障信号保持模块P4的输入端连接，第一光敏半导体管T1的另一端接地GND5。
还可以在故障信号触发模块P3中设置保护电阻，来保证流经故障信号触发模块P3的电流不会过大，比如图2中的电阻R9即为保护电阻。
故障信号保持模块P4包括第一晶体管Q1和第二晶体管Q2。
其中，第一晶体管Q1的控制端与故障信号触发模块P3的输出端连接，第一晶体管Q1的第一端与第四电压提供端V4连接，第一晶体管Q1的第二端与外接信号输出端Vout连接。在一个示例中，外接信号输出端Vout可以外接微控制单元(MCU，Micro Control Unit)，由微控制单元来记录安全故障发生的时间。
第二晶体管Q2的控制端与第一晶体管Q1的第二端和保护控制模块P5的输入端均连接，第二晶体管Q2的第一端接地GND6，第二晶体管Q2的第二端与故障信号触发模块P3的输出端连接。
还可以在故障信号保持模块P4中设置保护电阻，来保证流经故障信号保持模块P4的电流不会过大，以及避免晶体管被烧坏，比如图2中的电阻R10、R11、R12、R13、R14和R15均为保护电阻。
保护控制模块P5包括第三晶体管Q3和第二光耦合器OC2。第二光耦 合器OC2包括第二发光二极管L2和第二光敏半导体管T2。
第三晶体管Q3的控制端与故障信号保持模块P4的输出端连接，第三晶体管Q3的第一端接地GND7，第三晶体管Q3的第二端与第二发光二极管L2的负极连接。
第二发光二极管L2的正极与第五电压提供端V5连接。
第二光敏半导体管T2的一端与均衡控制芯片连接，第二光敏半导体管T2的另一端接地GND8。在一个示例中，第二光敏半导体管T2的一端可以与均衡控制芯片的使能脚连接。
还可以在保护控制模块P5中设置保护电阻，来保证流经保护控制模块P5的电流不会过大，以及避免晶体管被烧坏，比如图2中的电阻R16、R17和R18均为保护电阻。
下面以第一晶体管Q1为PNP三极管，第二晶体管Q2和第三晶体管Q3均为NPN三极管，控制端为基极，第一端为发射极，第二端为集电极为例，来说明如图2所示的均衡保护电路的工作原理：
第一比较器M1的正相输入端接收均衡电压采样端Vin的输入的均衡电压，第一比较器M1的反相输入端接收基准下限电压。若均衡电压小于基准下限电压，则第一比较器M1的输出端输出低电平信号(即欠压触发信号)。
第二比较器M2的反相输入端接收均衡电压采样端Vin的输入的均衡电压，第二比较器M2的正相输入端接收基准上限电压。若均衡电压大于基准上限电压，则第二比较器M2的输出端输出低电平信号(即过压触发信号)。
若第一光耦合器OC1中的第一发光二极管L1的负极接收低电平信号，则第一发光二极管L1导通并发光。第一光耦合器OC1中的第一光敏半导体管T1接收到第一发光二极管L1发出的光而导通，将第一光敏半导体管T1的一端的信号拉低。
第一晶体管Q1的控制端接收第一光敏半导体管T1的一端的低电平信号(即故障触发信号)，第一晶体管Q1导通。第一晶体管Q1将第一端的第四电压提供端V4提供的高电平信号传输至第二晶体管Q2的控制端和第 三晶体管Q3的控制端。第二晶体管Q2导通，将第一晶体管Q1的控制端的信号拉低为低电平信号。第一晶体管Q1将继续处于导通状态，外接信号输出端Vout输出高电平信号(即故障报告信号)，并保持一段时间，直至故障信号保持模块P4复位。
第三晶体管Q3的控制端接收高电平信号，第三晶体管Q3导通。第二光耦合器OC2中的第二发光晶体管的负极与地连通，第二发光晶体管导通并发光。第二光耦合器OC2中的第二光敏半导体管T2导通，向均衡控制芯片输出低电平信号(即工作停止信号)。均衡控制芯片接收到低电平信号，停止工作，实现对电池模组的保护。
图3为本发明另一实施例中的均衡保护电路的结构示意图。图3与图1的不同之处在于，图3中的均衡保护电路还包括复位模块P6。
复位模块P6的输入端与外接信号输入端Vr连接，复位模块P6的输出端与故障信号保持模块P4的输入端连接，用于接收外接信号输入端Vr的控制信号，向故障信号保持模块P4输出复位信号，控制故障信号保持模块P4复位。
复位模块P6可以控制故障信号保持模块P4复位，从而开始新一轮的均衡电压检测。
图4为本发明另一实施例的示例中的均衡保护电路的结构示意图。图4与图2的不同之处在于，图4中新增的复位模块P6可由元器件组成。下面说明复位模块P6的具体结构。
复位模块P6包括第四晶体管Q4。第四晶体管Q4的控制端与外接信号输入端Vr连接，第四晶体管Q4的第一端与第六电压提供端V6连接，第四晶体管Q4的第二端与故障信号保持模块P4的输入端连接。外接信号输入端Vr可以与微控制单元连接，由微控制单元发出信号，控制复位模块P6。
如图4所示，其中的电阻R19和R20为保护电阻，避免流经复位模块P6的电流过大，还能避免晶体管被烧坏。
下面以第四晶体管Q4为PNP三极管为例来进行说明。外接信号输入端Vr的信号初始为高电平信号，第四晶体管Q4截止。当微控制单元监测 电池模组中的电芯电压正常，且电池模组的通讯正常，则通过外接信号输入端Vr输入低电平信号。第四晶体管Q4的控制端接收低电平信号，第四晶体管Q4导通，将高电平信号传输至第一晶体管Q1的控制端。第一晶体管Q1的控制端接收高电平信号(即复位信号)，第一晶体管Q1截止，第二晶体管Q2的控制端无高电平信号输入，外接信号输出端Vout无信号输出，实现了故障信号保持模块P4的复位。
第三晶体管Q3的控制端无高电平信号输入，第三晶体管Q3截止。第二光耦合器OC2断开，无法向均衡控制芯片提供低电平信号(即工作停止信号)。均衡控制芯片能够继续工作。
图5为本发明又一实施例中的均衡保护电路的结构示意图。图5与图3的不同之处在于，图5中的均衡保护电路还包括工作信号提供模块P7。
工作信号提供模块P7的输入端与工作信号提供端连接，工作信号提供模块P7的输出端与均衡控制芯片连接。工作信号提供模块P7用于保护控制模块P5未接收故障报告信号时，为均衡控制芯片提供工作信号。
图6为本发明又一实施例的示例中的均衡保护电路的结构示意图。图6与图4的不同之处在于，图6中新增的工作信号提供模块P7可由元器件组成。下面说明工作信号提供模块P7的具体结构。
工作信号提供模块P7包括等效电阻组合和二极管。其中，二极管可以为一个，也可以为一个以上。
等效电阻组合的第一端与均衡控制芯片连接，等效电阻组合的第二端接地，等效电阻组合的第三端与二极管的负极连接。二极管的正极与工作信号提供端连接。
如图6所示，等效电阻组合可包括电阻R21和R22。二极管共有三个，分别为D1、D2和D3。二极管D1的正极、D2的正极和D3的正极分别与工作信号提供端Vw1、Vw2和Vw3连接。电阻R21的一端与均衡控制芯片连接，电阻R21的另一端与电阻R22的一端和二极管D1的负极、D2的负极和D3的负极连接。电阻R22的另一端接地。
若第三晶体管Q3未接收到高电平信号(即故障报告信号)，则工作信号提供端Vw1、Vw2和/或Vw3向均衡控制芯片提供高电平信号(即工 作信号)，使得均衡控制芯片正常工作。
需要说明的是，上述实施例中的第一电压提供端V1、第二电压提供端V2、第三电压提供端V3、第四电压提供端V4、第五电压提供端V5、第六电压提供端V6、第七电压提供端V7和第八电压提供端V8均提供高于0V的电压。第一电压提供端V1、第二电压提供端V2、第三电压提供端V3、第四电压提供端V4、第五电压提供端V5、第六电压提供端V6、第七电压提供端V7和第八电压提供端V8的电压可以相同，也可以不同，具体可以根据均衡保护电路的工作需求来进行调整。
本发明实施例还提供了一种电池均衡系统，该电池均衡系统包括上述实施例中的均衡保护电路。电池均衡系统还可以包括均衡控制芯片、电池模组或其他的功能芯片、功能模块，在此并不限定。
上述实施例中所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本发明的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本发明的技术方案而没有特定细节中的一个或更多，或者可以采用其它的元器件等。在其它情况下，不详细示出或描述公知结构、材料等以避免模糊本发明的主要技术创意。

Claims (11)

  1. 一种均衡保护电路，其特征在于，包括：
    欠压检测模块，所述欠压检测模块的输入端与均衡电压采样端和第一电压提供端连接，所述欠压检测模块的输出端与故障信号触发模块的输入端连接，所述欠压检测模块用于将所述第一电压提供端的电压转化为基准下限电压，若均衡电压采样端的均衡电压小于所述基准下限电压，则向所述故障信号触发模块输出欠压触发信号；
    过压检测模块，所述过压检测模块的输入端与所述均衡电压采样端和第二电压提供端连接，所述过压检测模块的输出端与所述故障信号触发模块的输入端连接，所述过压检测模块用于将所述第二电压提供端的电压转化为基准上限电压，若均衡电压采样端的均衡电压大于所述基准上限电压，则向所述故障信号触发模块输出过压触发信号；
    所述故障信号触发模块，所述故障信号触发模块的输出端与故障信号保持模块的输入端连接，所述故障信号触发模块用于接收所述欠压触发信号或所述过压触发信号，向所述故障信号保持模块输出故障触发信号；
    所述故障信号保持模块，所述故障信号保持模块的输出端与保护控制模块的输入端和外接信号输出端连接，所述故障信号保持模块用于接收所述故障触发信号，生成保持一段时间的故障报告信号，并向所述保护控制模块和所述外接信号输出端输出所述故障报告信号；以及
    所述保护控制模块，所述保护控制模块的输出端与均衡控制芯片连接，所述保护控制模块用于接收所述故障报告信号，向所述均衡控制芯片输出工作停止信号，控制所述均衡控制芯片停止工作。
  2. 根据权利要求1所述的均衡保护电路，其特征在于，还包括复位模块，所述复位模块的输入端与外接信号输入端连接，所述复位模块的输出端与所述故障信号保持模块的输入端连接，所述复位模块用于接收所述外接信号输入端的控制信号，向所述故障信号保持模块输出复位信号，控制所述故障信号保持模块复位。
  3. 根据权利要求1所述的均衡保护电路，其特征在于，所述欠压检 测模块包括第一电阻组合、第二电阻组合和第一比较器；
    其中，所述第一电阻组合的一端与第一电压提供端连接，所述第一电阻组合的另一端与所述第二电阻组合的一端连接，所述第二电阻组合的另一端接地；
    所述第一比较器的正相输入端与所述均衡电压采样端连接，所述第一比较器的反相输入端与所述第一电阻组合的另一端和所述第二电阻组合的一端均连接，所述第一比较器的输出端与所述故障信号触发模块连接。
  4. 根据权利要求1所述的均衡保护电路，其特征在于，所述过压检测模块包括第三电阻组合、第四电阻组合和第二比较器；
    其中，所述第三电阻组合的一端与第二电压提供端连接，所述第三电阻组合的另一端与所述第四电阻组合的一端连接，所述第四电阻组合的另一端接地；
    所述第二比较器的正相输入端与所述第三电阻组合的另一端和所述第四电阻组合的一端均连接，所述第二比较器的反相输入端与所述均衡电压采样端连接，所述第二比较器的输出端与所述故障信号触发模块连接。
  5. 根据权利要求1所述的均衡保护电路，其特征在于，所述故障信号触发模块包括第一光耦合器，所述第一光耦合器包括第一发光二极管和第一光敏半导体管；
    其中，所述第一发光二极管的正极与第三电压提供端连接，所述第一发光二极管的负极与所述欠压检测模块的输出端和所述过压检测模块的输出端均连接；
    所述第一光敏半导体管的一端与所述故障信号保持模块的输入端连接，所述第一光敏半导体管的另一端接地。
  6. 根据权利要求1所述的均衡保护电路，其特征在于，所述故障信号保持模块包括第一晶体管和第二晶体管；
    其中，所述第一晶体管的控制端与所述故障信号触发模块的输出端连接，所述第一晶体管的第一端与第四电压提供端连接，所述第一晶体管的第二端与所述外接信号输出端连接；
    所述第二晶体管的控制端与所述第一晶体管的第二端和所述保护控制 模块的输入端均连接，所述第二晶体管的第一端接地，所述第二晶体管的第二端与所述故障信号触发模块的输出端连接。
  7. 根据权利要求1所述的均衡保护电路，其特征在于，所述保护控制模块包括第三晶体管和第二光耦合器，所述第二光耦合器包括第二发光二极管和第二光敏半导体管；
    所述第三晶体管的控制端与所述故障信号保持模块的输出端连接，所述第三晶体管的第一端接地，所述第三晶体管的第二端与所述第二发光二极管的负极连接；
    所述第二发光二极管的正极与第五电压提供端连接；
    所述第二光敏半导体管的一端与所述均衡控制芯片连接，所述第二光敏半导体管的另一端接地。
  8. 根据权利要求2所述的均衡保护电路，其特征在于，所述复位模块包括第四晶体管；
    所述第四晶体管的控制端与所述外接信号输入端连接，所述第四晶体管的第一端与第六电压提供端连接，所述第四晶体管的第二端与所述故障信号保持模块的输入端连接。
  9. 根据权利要求1所述的均衡保护电路，其特征在于，还包括工作信号提供模块，所述工作信号提供模块的输入端与工作信号提供端连接，所述工作信号提供模块的输出端与所述均衡控制芯片连接，所述工作信号提供模块用于所述保护控制模块未接收所述故障报告信号时，为所述均衡控制芯片提供工作信号。
  10. 根据权利要求9所述的均衡保护电路，其特征在于，所述工作信号提供模块包括等效电阻组合和二极管；
    所述等效电阻组合的第一端与所述均衡控制芯片连接，所述等效电阻组合的第二端接地，所述等效电阻组合的第三端与所述二极管的负极连接；
    所述二极管的正极与所述工作信号提供端连接。
  11. 一种电池均衡系统，其特征在于，包括如权利要求1-10中任意一项所述的均衡保护电路。
PCT/CN2017/093373 2017-05-18 2017-07-18 均衡保护电路和电池均衡系统 Ceased WO2018209787A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201720554558.3 2017-05-18
CN201720554558.3U CN207039214U (zh) 2017-05-18 2017-05-18 均衡保护电路和电池均衡系统

Publications (1)

Publication Number Publication Date
WO2018209787A1 true WO2018209787A1 (zh) 2018-11-22

Family

ID=61479998

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/093373 Ceased WO2018209787A1 (zh) 2017-05-18 2017-07-18 均衡保护电路和电池均衡系统

Country Status (2)

Country Link
CN (1) CN207039214U (zh)
WO (1) WO2018209787A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115549034A (zh) * 2021-06-30 2022-12-30 星络社区云物联科技有限公司 一种电池及其欠压保护电路

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111196178A (zh) * 2018-11-16 2020-05-26 宁德时代新能源科技股份有限公司 转换电路、电池均衡系统及电池管理系统
CN111293747A (zh) * 2020-02-26 2020-06-16 北斗(天津)科学技术应用研究院(有限合伙) 一种用于分布式能源交换系统的流转电池

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386642A (zh) * 2010-08-31 2012-03-21 凹凸电子（武汉）有限公司 用于电池包的控制系统、通讯系统的自诊断以及重构方法
CN103812153A (zh) * 2012-11-12 2014-05-21 芜湖宏宇汽车电子有限责任公司 新能源汽车用主动平衡式bms控制模块及其控制方法
CN104167711A (zh) * 2014-09-02 2014-11-26 航天长峰朝阳电源有限公司 自复位式延时锁定保护装置
US20150222280A1 (en) * 2014-01-31 2015-08-06 Hittite Microwave Corporation Apparatus and methods for fast charge pump holdover on signal interruption
CN106183872A (zh) * 2016-08-15 2016-12-07 陕西赛雷博瑞新能源科技有限公司 一种电池组内组间均衡控制系统及其控制方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386642A (zh) * 2010-08-31 2012-03-21 凹凸电子（武汉）有限公司 用于电池包的控制系统、通讯系统的自诊断以及重构方法
CN103812153A (zh) * 2012-11-12 2014-05-21 芜湖宏宇汽车电子有限责任公司 新能源汽车用主动平衡式bms控制模块及其控制方法
US20150222280A1 (en) * 2014-01-31 2015-08-06 Hittite Microwave Corporation Apparatus and methods for fast charge pump holdover on signal interruption
CN104167711A (zh) * 2014-09-02 2014-11-26 航天长峰朝阳电源有限公司 自复位式延时锁定保护装置
CN106183872A (zh) * 2016-08-15 2016-12-07 陕西赛雷博瑞新能源科技有限公司 一种电池组内组间均衡控制系统及其控制方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115549034A (zh) * 2021-06-30 2022-12-30 星络社区云物联科技有限公司 一种电池及其欠压保护电路

Also Published As

Publication number Publication date
CN207039214U (zh) 2018-02-23

Similar Documents

Publication Publication Date Title
JP2021190412A (ja) 非常灯制御回路、非常灯制御装置および照明器具
CN111668904A (zh) 充电器检测电路、方法及电化学装置
WO2018209787A1 (zh) 均衡保护电路和电池均衡系统
CN206990730U (zh) 一种电动车电池正反接及未接检测电路
CN112186279B (zh) 一种具有休眠激活功能的电源管理系统
TWI450083B (zh) 電源管理裝置
WO2021036946A1 (zh) 一种电池充电控制电路及电子设备
CN106160071A (zh) 短路保护电路
CN210693428U (zh) 一种基于镜像电流源的过流保护电路
CN105591438B (zh) 微电源电池组、具有安全控制的微型光伏逆变器装置
CN111934668A (zh) 一种数字量输入电路及设备
JP4175567B2 (ja) 防爆用分離回路
CN103630842A (zh) 电池组充电检测系统
CN218383247U (zh) 一种熔丝熔断检测电路及电池管理系统
CN217425622U (zh) 一种电池模组的检测电路、电池管理系统及车辆
WO2009066908A2 (en) Portable charge/discharge apparatuses
US12038481B2 (en) Voltage sensing circuit, battery pack, and battery system
CN214337591U (zh) 报警驱动电路及掉电监测装置
CN210416442U (zh) 车载支架
CN202758054U (zh) 电池组充电检测系统
CN202886568U (zh) 电池组充电检测系统
CN209675928U (zh) 一种保护电路及设备
CN114513034B (zh) 充电检测电路及装置、电池管理系统、电池包和用电设备
WO2022161275A1 (zh) 一种电池充电保护电路以及机器人
CN110429687A (zh) 一种电池充电管理电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17909774

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17909774

Country of ref document: EP

Kind code of ref document: A1