WO2018208086A1 - Graphene-polycrystalline silicon composite, preparation method therefor, conductor, and substrate - Google Patents

Graphene-polycrystalline silicon composite, preparation method therefor, conductor, and substrate Download PDF

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WO2018208086A1
WO2018208086A1 PCT/KR2018/005346 KR2018005346W WO2018208086A1 WO 2018208086 A1 WO2018208086 A1 WO 2018208086A1 KR 2018005346 W KR2018005346 W KR 2018005346W WO 2018208086 A1 WO2018208086 A1 WO 2018208086A1
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graphene
polycrystalline silicon
composite
silicon composite
powder
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Korean (ko)
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임영수
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부경대학교 산학협력단
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K99/00Subject matter not provided for in other groups of this subclass
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01BNON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00Carbon; Compounds thereof
    • C01B32/15Nano-sized carbon materials
    • C01B32/182Graphene
    • C01B32/184Preparation
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01BNON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00Carbon; Compounds thereof
    • C01B32/15Nano-sized carbon materials
    • C01B32/182Graphene
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01BNON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B33/00Silicon; Compounds thereof
    • C01B33/02Silicon
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01BNON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B33/00Silicon; Compounds thereof
    • C01B33/02Silicon
    • C01B33/021Preparation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01BCABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H01B1/04Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of carbon-silicon compounds, carbon or silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material

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  • the present invention relates to a graphene-polycrystalline silicon composite, a method for manufacturing the same, a conductor, and a substrate, and more particularly, to a graphene-polycrystalline silicon composite, a method for manufacturing the same, a conductor, and the like, which improve charge transfer characteristics by controlling a polycrystalline silicon interface. It relates to a substrate.
  • silicon silicon
  • silicon is abundant in the earth, it is infinite in resources, environmentally friendly because it is non-toxic, and it is easy to control the electrical properties when doping impurities, which is a key material in the semiconductor material industry. It is widely used to.
  • an object of the present invention is to provide a graphene-polycrystalline silicon composite with improved charge transfer characteristics.
  • Another object of the present invention is to provide a method for producing the graphene-polycrystalline silicon composite.
  • Still another object of the present invention is to provide a conductor and a substrate including the graphene-polycrystalline silicon composite.
  • the graphene-polycrystalline silicon composite according to the present invention for the above object is an aggregate of a plurality of unit crystals formed by polycrystalline silicon, and has a structure in which graphene is disposed at grain boundaries between unit crystals.
  • a plurality of graphenes may be stacked on the grain boundary.
  • an n-type element may be doped into the unit crystals.
  • the electron mobility of the graphene-polycrystalline silicon composite shows a high value.
  • the graphene-free polycrystalline silicon under the same conditions includes polycrystalline silicon doped with n-type elements but no graphene is present at the grain boundaries of the polycrystalline silicon.
  • the p-type element may be doped into the unit crystals.
  • the hole mobility of the graphene-polycrystalline silicon composite exhibits a high value as compared with the graphene-free polycrystalline silicon under the same conditions.
  • the graphene-free polycrystalline silicon under the same conditions includes polycrystalline silicon doped with a p-type element but no graphene is present at the grain boundaries of the polycrystalline silicon.
  • the graphene disposed between the unit crystals may be graphene, reduced graphene oxide or graphene oxide.
  • Graphene has a structure arranged.
  • the preparing of the graphene-polycrystalline silicon composite may be performed by discharge plasma sintering.
  • the silicon powder used in the mixing step may be a silicon powder doped with a p-type element or n-type element.
  • Each of the conductor and the substrate according to the present invention for another object described above includes the graphene-polycrystalline silicon composite described above.
  • the graphene-polycrystalline silicon composite of the present invention described above, a method of manufacturing the same, a conductor, and a substrate, the graphene-polycrystalline silicon composite having excellent charge transfer characteristics can be obtained by positioning graphene at the grain boundaries of polycrystalline silicon. Since graphene is a material with a unique property that Fermi liquid spontaneously fills up or down the Dirac point under the influence of the Fermi level of the heterogeneous material in contact, In the case of forming an interface between silicon grain boundaries heavily doped with graphene, the effect of grain boundary scattering of charges may be reduced due to band alignment of silicon and graphene, thereby improving charge transfer characteristics of the composite.
  • the interface control effect of the polycrystalline silicon of graphene can be implemented in both n-type and p-type.
  • TEM 1 and 2 are transmission electron microscope (TEM) pictures of the silicon powder and the silicon-reduced graphene oxide composite powder used in the preparation of the composite 1 according to the present invention.
  • 3 to 6 are views for explaining the characteristics of the composite 2 according to the present invention.
  • FIG 7 to 10 are views for explaining the characteristics of the composite 3 according to the present invention.
  • FIG. 11 is a diagram illustrating a band alignment relationship between n-type and p-type silicon and graphene.
  • the graphene-polycrystalline silicon composite according to the present invention is a composite having a structure in which graphene is disposed at grain boundaries formed by polycrystalline silicon.
  • the complex is a collection of a plurality of unit crystals, each of the unit crystals are composed of polycrystalline silicon, the interface between the unit crystals corresponds to a grain boundary and has a structure in which graphene is disposed at this grain boundary.
  • the graphene disposed at the grain boundary may be graphene, graphene oxide, or reduced graphene oxide.
  • graphene-polycrystalline silicon composite may be prepared by reducing graphene oxide using graphene oxide.
  • Graphene has a unique property that the Fermi liquid spontaneously fills up or down the Dirac point due to the Fermi level of the polycrystalline silicon, which is in contact with the heterogeneous material.
  • the effect of grain boundary scattering of the charge may be reduced due to the band alignment of the polycrystalline silicon and the graphene, thereby improving charge transfer characteristics of the composite. That is, not only charges are conducted through the percolate graphene network but also through the band alignment of polycrystalline silicon and graphene, the effect of grain boundary scattering of charges is reduced, thereby improving charge transfer characteristics of polycrystalline silicon.
  • the interface control effect of the polycrystalline silicon of graphene can be implemented in both n-type and p-type.
  • Silicon is a material in which electrons and holes exist in the same number due to thermal equilibrium even when undoped, and electrical conduction by electrons and holes is possible at the same time. As possible substance.
  • silicon is fundamentally different from other oxide semiconductors in which an electronic band structure, which is an elemental semiconductor, mainly determines n-type electronic band structure. Therefore, the mechanism in which the electrical conductivity is improved by graphene disposed at grain boundaries of unit crystals is fundamentally different from that of other oxide semiconductors.
  • the unit crystals may be polycrystalline silicon doped with an n-type element.
  • the electron mobility of the graphene-polycrystalline silicon composite according to the present invention exhibits a high value as compared with pure polycrystalline silicon under the same conditions.
  • Arsenic (As) is mentioned as an n-type element.
  • polycrystalline silicon doped with n-type elements in unit crystals the mobility of electrons, that is, electron mobility, in the conduction band of silicon is improved by graphene disposed at grain boundaries of the unit crystals.
  • the unit crystals may be polycrystalline silicon doped with a p-type element.
  • the hole mobility of the graphene-polycrystalline silicon composite according to the present invention exhibits a high value as compared with pure polycrystalline silicon under the same conditions.
  • Aluminum, boron, gallium, indium etc. are mentioned as a p-type element.
  • the inventors of the present invention have unit crystals composed of polycrystalline silicon doped with p-type elements, and between these unit crystals. It was confirmed that the hole mobility of the graphene-polycrystalline silicon composite is increased due to the arrangement of graphene at the grain boundary of the composite, and thus the composite having the higher hole mobility may be invented.
  • a valence that is a charge carrier having a property opposite to that of electrons hole mobility of the band), that is, hole mobility is improved.
  • holes are charge transporters having opposite properties to electrons, there is no particular correlation between electron mobility and hole mobility, but the inventors of the present invention have found that the grain boundary between the unit crystals of graphene is composed of polycrystalline silicon doped with p-type element. It has been found that the hole mobility of the graphene-polycrystalline silicon composite can be improved by placing it in the.
  • the unit crystal is made of silicon, both n-type and p-type can be realized, and thus the composite including the unit crystal made of polycrystalline silicon doped with n-type elements has a high hole mobility.
  • the composite including unit crystals made of polycrystalline silicon doped with a p-type element is implemented to have high electron mobility.
  • the graphene-polycrystalline silicon composite according to the present invention may be prepared by first mixing a silicon powder and a graphene oxide powder, adding a reducing agent to synthesize a silicon-reduced graphene oxide composite powder, and then sintering it.
  • the silicon powder may be a silicon powder doped with a p-type or n-type element.
  • the impurity doped silicon powder is used, the polycrystalline silicon included in the graphene-polycrystalline silicon composite may be finally doped with impurities.
  • the silicon-reduced graphene oxide composite powder may be sintered by a discharge plasma sintering method to prepare a graphene-polycrystalline silicon composite.
  • the chemically / thermally reduced graphene oxide prepared as described above has electrical properties similar to graphene.
  • the powder was prepared by dispersing the silicon powder and graphene oxide pulverized to about 300 nm size in 200 ml of dimethylformamide using a specmill and then stirred for 5 minutes to prepare a mixed powder.
  • the silicon-reduced graphene oxide composite powder was prepared by adding hydrazine monohydrate to the mixed powder and reacting at 80 ° C. for 1 hour in a heating mantle to chemically reduce graphene oxide. The content of graphene oxide at this time was adjusted to 1% by weight.
  • the solution was aged at room temperature for 24 hours to stabilize the structure, followed by centrifugation at 10,000 rpm for 10 minutes, and then dried in a vacuum oven at 40 ° C for 24 hours to finally reduce the graphene oxide-silicon oxide composite powder.
  • the obtained reduced graphene oxide-silicon composite powder was sintered by the discharge plasma sintering method.
  • the temperature of the sintering process was 1,300 degreeC, the sintering time was 30 minutes, and the sintering pressure was 100 MPa.
  • the graphene oxide-polycrystalline silicon composite finally cooled by sintering was synthesized.
  • TEM 1 and 2 are transmission electron microscope (TEM) images of the silicon powder and the silicon-reduced graphene oxide composite powder used in the preparation of the composite 1 according to the present invention.
  • the silicon powder used as a raw material has a size of about 300 nm
  • the silicon powder in the silicon-reduced graphene oxide composite powder by reducing the graphene oxide using a reducing agent It can be seen that the reduced graphene oxide is coated on the surface. At this time, it can be confirmed through the TEM photograph that the reduced graphene oxide coated on the surface of the silicon powder is laminated in a plurality of layers.
  • FIGS. 3 to 6 are views for explaining the characteristics of the composite 2 according to the present invention.
  • the results of the composite 2 ( ⁇ ) and the comparative examples thereof are similar to those of the arsenic-doped n-type silicon wafer ( ⁇ ) and the arsenic-doped n-type polycrystalline silicon sintered body ( ⁇ ). Indicates.
  • FIG 3 is a graph showing the relationship between the carrier concentration (unit: cm -3 ) and the charge mobility (unit: cm 2 V -1 s -1 ) at room temperature, the carrier in the arsenic doped n-type single crystal silicon The values calculated using Masetti's formula showing charge mobility with concentration are shown as solid lines.
  • the n-type polycrystalline silicon sintered body ( ⁇ ) has a charge mobility (about 100 cm 2 V ⁇ 1 s ⁇ 1 ) of the single crystal silicon calculated by the Masseti formula due to grain boundary scattering. It appears to have a significantly lower charge mobility compared to (about 25 cm 2 V -1 s -1 level).
  • the charge mobility of the composite 2 ( ⁇ ) whose interface is controlled by the reduced graphene oxide shows about twice the charge mobility of the n-type polycrystalline silicon sintered body ( ⁇ ).
  • the charge mobility in the material is largely determined by the influence of grain boundary scattering, ionized impurity scattering, and phonon scattering according to the Masshiessen's rule.
  • the charge is scattered.
  • the charge mobility tends to increase with temperature.
  • the charge mobility of the complex 2 ( ⁇ ) shows an inverse relationship with the temperature.
  • FIG. 5 is a graph showing the change in charge mobility with temperature.
  • the carrier concentrations of the composite 2 ( ⁇ ), the n-type silicon wafer ( ⁇ ), and the n-type polycrystalline silicon sintered body ( ⁇ ) do not tend to be significantly different. It can be seen that indicates.
  • FIG. 6 is a graph showing the change in electrical conductivity (unit Scm -1 ) with temperature, and the electrical conductivity of the composite 2 ( ⁇ ) according to the present invention compared to the n-type polycrystalline silicon sintered body ( ⁇ ) through FIG. It can be seen that the overall value shows a high value according to the change in temperature.
  • Reduced graphene oxide doped with boron by carrying out substantially the same process as the preparation of the composite 1, except that boron was doped into the composite 1 by using a boron-doped silicon powder.
  • Composite 3 a polycrystalline silicon composite, was prepared.
  • FIG. 7 to 10 are views for explaining the characteristics of the composite 3 according to the present invention.
  • Figures 7 to 10 the results for the composite 3 ( ⁇ ) and, as a comparative example, the results for the boron-doped p-type silicon wafer ( ⁇ ) is shown together.
  • the temperature dependence of the charge mobility of the composite 3 ( ⁇ ) tends to decrease the mobility as the temperature increases, which is the effect of grain boundary scattering through the interface control using graphene It can be seen that this is reduced, and from this result, it can be seen that the improvement of charge transfer characteristics through interface control using graphene is applicable to not only n-type silicon but also p-type silicon. In addition, also in the other properties it can be seen that the properties of the composite 3 ( ⁇ ) appear similar to the properties of the composite 2 ( ⁇ ) shown in Figures 3 to 6.
  • FIG. 11 is a diagram illustrating a band alignment relationship between n-type and p-type silicon and graphene.
  • graphene is a material without a bandgap, and a Fermi liquid whose electron or hole concentration changes depending on the Fermi level of the material in contact with the graphene. It is a substance with properties. Therefore, when graphene is located at the interface between the heavily doped silicon grain boundaries, charges passing through the interface between silicon and graphene may be free from grain boundary scattering due to the band alignment of silicon and graphene. As a result, the effect of grain boundary scattering of charges is reduced, thereby improving charge transfer characteristics of the composite.

Abstract

In a graphene-polycrystalline silicon composite, a preparation method therefor, a conductor, and a substrate, the graphene-polycrystalline silicon composite is an aggregate of a plurality of unit crystals formed by polycrystalline silicon and has a structure in which graphene is disposed in the crystal grain boundary between the unit crystals.

Description

그래핀-다결정 실리콘 복합체, 이의 제조 방법, 전도체 및 기판Graphene-Polycrystalline Silicon Composites, Methods of Manufacturing the Same, Conductors and Substrates
본 발명은 그래핀-다결정 실리콘 복합체, 이의 제조 방법, 전도체 및 기판에 관한 것으로, 더욱 상세하게는 다결정 실리콘 계면을 제어함으로써 전하 이동 특성을 향상시킨 그래핀-다결정 실리콘 복합체, 이의 제조 방법, 전도체 및 기판에 관한 것이다.The present invention relates to a graphene-polycrystalline silicon composite, a method for manufacturing the same, a conductor, and a substrate, and more particularly, to a graphene-polycrystalline silicon composite, a method for manufacturing the same, a conductor, and the like, which improve charge transfer characteristics by controlling a polycrystalline silicon interface. It relates to a substrate.
실리콘(silicon, 규소)은 지구에 풍부하게 존재하기 때문에 자원이 무한하고, 독성이 없어 환경 친화적이며, 불순물을 도핑할 경우 전기적 특성을 쉽게 조절할 수 있어 반도체 소재 산업에서 핵심소재로서 일상생활에서 첨단산업에 이르기까지 널리 이용되고 있다.Since silicon (silicon) is abundant in the earth, it is infinite in resources, environmentally friendly because it is non-toxic, and it is easy to control the electrical properties when doping impurities, which is a key material in the semiconductor material industry. It is widely used to.
한편, 최근 환경오염과 화석에너지의 고갈 등의 문제로 인하여 차세대 친환경 에너지 기술 개발에 대한 관심이 고조되고 있다. 그중에서도 태양전지에 대한 연구가 활발하게 진행되고 있는데, 현재 태양전지 산업의 대부분은 실리콘 태양전지가 차지하고 있다. 태양전지의 발전을 위해 저가형 고효율 태양전지의 개발이 요구되지만, 단결정 실리콘 태양전지는 높은 효율은 가능하나 가격이 높다는 문제점이 있다. 반면, 다결정 실리콘 태양전지는 가격은 낮은 장점을 갖지만, 효율 증대에 한계가 있다는 문제점이 있다. 이에 따라 다결정 실리콘 태양전지의 효율 향상에 대한 요구가 계속되고 있다.Meanwhile, due to problems such as environmental pollution and depletion of fossil energy, interest in development of next-generation environmentally friendly energy technology is increasing. Among them, researches on solar cells are being actively conducted, and most of the solar cell industry is made up of silicon solar cells. Development of low-cost, high-efficiency solar cells is required for the development of solar cells, but single crystal silicon solar cells have high efficiency but high price. On the other hand, polycrystalline silicon solar cells have the advantage of low price, but there is a problem that there is a limit to increase the efficiency. Accordingly, there is a continuing demand for improved efficiency of polycrystalline silicon solar cells.
상기한 종래 기술의 문제를 해결하기 위한, 본 발명의 일 목적은 전하 이동 특성이 향상된 그래핀-다결정 실리콘 복합체을 제공하는 것이다.In order to solve the above problems of the prior art, an object of the present invention is to provide a graphene-polycrystalline silicon composite with improved charge transfer characteristics.
본 발명의 다른 목적은 상기 그래핀-다결정 실리콘 복합체의 제조 방법을 제공하는 것이다.Another object of the present invention is to provide a method for producing the graphene-polycrystalline silicon composite.
본 발명의 또 다른 목적은 상기 그래핀-다결정 실리콘 복합체를 포함하는 전도체 및 기판을 제공하는 것이다.Still another object of the present invention is to provide a conductor and a substrate including the graphene-polycrystalline silicon composite.
상기한 일 목적을 위한 본 발명에 따른 그래핀-다결정 실리콘 복합체는 다결정 실리콘이 형성하는 다수의 단위 결정체들의 집합체이고, 단위 결정체들 사이의 결정립계에 그래핀이 배치된 구조를 갖는다.The graphene-polycrystalline silicon composite according to the present invention for the above object is an aggregate of a plurality of unit crystals formed by polycrystalline silicon, and has a structure in which graphene is disposed at grain boundaries between unit crystals.
일 실시예에서, 상기 결정립계에는 다수의 그래핀들이 적층되어 배치될 수 있다.In one embodiment, a plurality of graphenes may be stacked on the grain boundary.
일 실시예에서, 상기 단위 결정체들에 n형 원소가 도핑될 수 있다. 이때, 동일 조건의 그래핀 미포함 다결정 실리콘과 대비하여, 상기 그래핀-다결정 실리콘 복합체의 전자 이동도(electron mobility)가 높은 값을 나타낸다. 동일 조건의 그래핀 미포함 다결정 실리콘은, n형 원소가 도핑된 다결정 실리콘을 포함하되 다결정 실리콘의 결정립계에는 그래핀이 존재하지 않은 경우를 의미한다.In an embodiment, an n-type element may be doped into the unit crystals. In this case, as compared with the graphene-free polycrystalline silicon under the same conditions, the electron mobility of the graphene-polycrystalline silicon composite shows a high value. The graphene-free polycrystalline silicon under the same conditions includes polycrystalline silicon doped with n-type elements but no graphene is present at the grain boundaries of the polycrystalline silicon.
일 실시예에서, 상기 단위 결정체들에 p형 원소가 도핑될 수 있다. 이때, 동일 조건의 그래핀 미포함 다결정 실리콘과 대비하여, 상기 그래핀-다결정 실리콘 복합체의 정공 이동도(hole mobility)가 높은 값을 나타낸다. 동일 조건의 그래핀 미포함 다결정 실리콘은, p형 원소가 도핑된 다결정 실리콘을 포함하되 다결정 실리콘의 결정립계에는 그래핀이 존재하지 않은 경우를 의미한다.In one embodiment, the p-type element may be doped into the unit crystals. In this case, the hole mobility of the graphene-polycrystalline silicon composite exhibits a high value as compared with the graphene-free polycrystalline silicon under the same conditions. The graphene-free polycrystalline silicon under the same conditions includes polycrystalline silicon doped with a p-type element but no graphene is present at the grain boundaries of the polycrystalline silicon.
일 실시예에서, 상기 단위 결정체들 사이에 배치된 그래핀은, 그래핀, 환원된 산화그래핀 또는 산화그래핀일 수 있다.In one embodiment, the graphene disposed between the unit crystals may be graphene, reduced graphene oxide or graphene oxide.
상기한 다른 목적을 위한 본 발명에 따른 그래핀-다결정 실리콘 복합체의 제조 방법은, 실리콘 분말과 산화그래핀 분말을 분산 용매에서 혼합시키는 단계; 혼합된 실리콘 분말과 산화그래핀 분말에 환원제를 첨가하여, 환원된 산화그래핀이 실리콘 분말의 표면에 코팅된 혼합 분말을 제조하는 단계; 및 상기 혼합 분말을 소결하여 그래핀-다결정 실리콘 복합체를 제조하는 단계를 포함하고, 상기 그래핀-다결정 실리콘 복합체는 다결정 실리콘이 형성하는 다수의 단위 결정체들의 집합체로서, 상기 단위 결정체들 사이의 결정립계에 그래핀이 배치된 구조를 갖는다.Graphene-polycrystalline silicon composite production method according to the present invention for another object described above comprises the steps of mixing the silicon powder and graphene oxide powder in a dispersion solvent; Adding a reducing agent to the mixed silicon powder and the graphene oxide powder to prepare a mixed powder in which the reduced graphene oxide is coated on the surface of the silicon powder; And sintering the mixed powder to produce a graphene-polycrystalline silicon composite, wherein the graphene-polycrystalline silicon composite is an aggregate of a plurality of unit crystals formed by polycrystalline silicon, and is located at grain boundaries between the unit crystals. Graphene has a structure arranged.
일 실시예에서, 상기 그래핀-다결정 실리콘 복합체를 제조하는 단계는 방전 플라즈마 소결법으로 수행할 수 있다.In an embodiment, the preparing of the graphene-polycrystalline silicon composite may be performed by discharge plasma sintering.
일 실시예에서, 상기 혼합시키는 단계에서 이용하는 실리콘 분말은 p형 원소 또는 n형 원소가 도핑된 실리콘 분말일 수 있다.In one embodiment, the silicon powder used in the mixing step may be a silicon powder doped with a p-type element or n-type element.
상기한 또 다른 목적을 위한 본 발명에 따른 전도체 및 기판 각각은 상기에서 설명한 그래핀-다결정 실리콘 복합체를 포함한다.Each of the conductor and the substrate according to the present invention for another object described above includes the graphene-polycrystalline silicon composite described above.
상기에서 설명한 본 발명의 그래핀-다결정 실리콘 복합체, 이의 제조 방법, 전도체 및 기판에 따르면, 다결정 실리콘의 결정립계에 그래핀이 위치함으로써 우수한 전하 이동 특성을 갖는 그래핀-다결정 실리콘 복합체를 얻을 수 있다. 그래핀은 접촉하고 있는 이종 물질의 페르미 레벨(Fermi level)에 영향을 받아 페르미 액체(Fermi liquid)가 디락 포인트(Dirac point)의 위 또는 아래로 자발적으로 채워지는 독특한 성질을 가지고 있는 물질이기 때문에, 그래핀으로 고농도로 도핑된 실리콘 결정립계 사이의 계면을 형성할 경우 실리콘과 그래핀의 밴드 정렬(band alignment)로 인해 전하의 결정립계 산란의 효과가 줄어들어 복합체의 전하 이동 특성을 향상시킬 수 있다. 이러한 그래핀의 다결정 실리콘의 계면 제어 효과는 n형 및 p형 모두에서 구현할 수 있다.According to the graphene-polycrystalline silicon composite of the present invention described above, a method of manufacturing the same, a conductor, and a substrate, the graphene-polycrystalline silicon composite having excellent charge transfer characteristics can be obtained by positioning graphene at the grain boundaries of polycrystalline silicon. Since graphene is a material with a unique property that Fermi liquid spontaneously fills up or down the Dirac point under the influence of the Fermi level of the heterogeneous material in contact, In the case of forming an interface between silicon grain boundaries heavily doped with graphene, the effect of grain boundary scattering of charges may be reduced due to band alignment of silicon and graphene, thereby improving charge transfer characteristics of the composite. The interface control effect of the polycrystalline silicon of graphene can be implemented in both n-type and p-type.
도 1 및 도 2는 본 발명에 따른 복합체 1의 제조에 이용한 실리콘 분말과 실리콘-환원된 산화그래핀 복합 분말의 투과전자현미경(TEM) 사진을 나타낸 도면들이다.1 and 2 are transmission electron microscope (TEM) pictures of the silicon powder and the silicon-reduced graphene oxide composite powder used in the preparation of the composite 1 according to the present invention.
도 3 내지 도 6은 본 발명에 따른 복합체 2의 특성을 설명하기 위한 도면들이다.3 to 6 are views for explaining the characteristics of the composite 2 according to the present invention.
도 7 내지 도 10은 본 발명에 따른 복합체 3의 특성을 설명하기 위한 도면들이다.7 to 10 are views for explaining the characteristics of the composite 3 according to the present invention.
도 11은 n형 및 p형 실리콘과 그래핀의 밴드 정렬(band alignment) 관계를 나타낸 도면이다.FIG. 11 is a diagram illustrating a band alignment relationship between n-type and p-type silicon and graphene. FIG.
본 발명은 다양한 변경을 가할 수 있고 여러 가지 형태를 가질 수 있는바, 특정 실시예들을 도면에 예시하고 본문에 상세하게 설명하고자 한다. 그러나 이는 본 발명을 특정한 개시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다. 각 도면을 설명하면서 유사한 참조부호를 유사한 구성요소에 대해 사용하였다. As the inventive concept allows for various changes and numerous modifications, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.
본 출원에서 사용한 용어는 단지 특정한 실시 예를 설명하기 위해 사용된 것으로서 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함한다. 본 출원에서, "포함하다" 또는 "가지다" 등의 용어는 명세서 상에 기재된 특징, 단계, 동작, 구성요소, 부분품 또는 이들을 조합한 것이 존재함을 지정하려는 것이지, 하나 또는 그 이상의 다른 특징들이나 단계, 동작, 구성요소, 부분품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다.The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprises" or "having" are intended to indicate that there is a feature, step, operation, component, part, or combination thereof described on the specification, and one or more other features or steps. It is to be understood that the present invention does not exclude, in advance, the possibility of the presence or addition of any operation, component, part, or combination thereof.
다르게 정의되지 않는 한, 기술적이거나 과학적인 용어를 포함해서 여기서 사용되는 모든 용어들은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미를 가지고 있다. 일반적으로 사용되는 사전에 정의되어 있는 것과 같은 용어들은 관련 기술의 문맥 상 가지는 의미와 일치하는 의미를 가지는 것으로 해석되어야 하며, 본 출원에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않는다.Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.
본 발명에 따른 그래핀-다결정 실리콘 복합체는 다결정 실리콘이 형성하는 결정립계에 그래핀이 배치된 구조를 갖는 복합화물이다.The graphene-polycrystalline silicon composite according to the present invention is a composite having a structure in which graphene is disposed at grain boundaries formed by polycrystalline silicon.
상기 복합체는 다수의 단위 결정체들의 집합체로서, 단위 결정체들 각각이 다결정 실리콘으로 구성되고, 단위 결정체들 사이의 계면이 결정립계에 해당하며 이때의 결정립계에 그래핀이 배치된 구조를 갖는다.The complex is a collection of a plurality of unit crystals, each of the unit crystals are composed of polycrystalline silicon, the interface between the unit crystals corresponds to a grain boundary and has a structure in which graphene is disposed at this grain boundary.
이때 상기 결정립계에 배치된 그래핀은 그래핀, 산화그래핀, 환원된 산화그래핀 일수 있으며, 일례로 산화그래핀을 이용하여 산화그래핀을 환원시킴으로써 그래핀-다결정 실리콘 복합체를 제조할 수 있다.In this case, the graphene disposed at the grain boundary may be graphene, graphene oxide, or reduced graphene oxide. For example, graphene-polycrystalline silicon composite may be prepared by reducing graphene oxide using graphene oxide.
그래핀은 접촉하고 있는 이종 물질인 다결정 실리콘의 페르미 레벨(Fermi level)에 영향을 받아 페르미 액체(Fermi liquid)가 디락 포인트(Dirac point)의 위 또는 아래로 자발적으로 채워지는 독특한 성질을 갖는다. 이에 의해, 그래핀이 다결정 실리콘 결정립계에 배치되는 경우 다결정 실리콘과 그래핀의 밴드 정렬(band alignment)로 인해 전하의 결정립계 산란의 효과가 줄어들어 복합체의 전하 이동 특성을 향상시킬 수 있다. 즉, 퍼컬레이트(percolate)된 그래핀 네트워크만을 통하여 전하가 전도되는 것이 아니라, 다결정 실리콘과 그래핀의 밴드 정렬을 통해서 나타나는 현상을 통해 전하의 결정립계 산란의 영향이 줄어들어 다결정 실리콘의 전하 이동 특성이 향상되는 특징을 가진다. 이러한 그래핀의 다결정 실리콘의 계면 제어 효과는 n형 및 p형 모두에서 구현할 수 있다.Graphene has a unique property that the Fermi liquid spontaneously fills up or down the Dirac point due to the Fermi level of the polycrystalline silicon, which is in contact with the heterogeneous material. As a result, when the graphene is disposed in the polycrystalline silicon grain boundary, the effect of grain boundary scattering of the charge may be reduced due to the band alignment of the polycrystalline silicon and the graphene, thereby improving charge transfer characteristics of the composite. That is, not only charges are conducted through the percolate graphene network but also through the band alignment of polycrystalline silicon and graphene, the effect of grain boundary scattering of charges is reduced, thereby improving charge transfer characteristics of polycrystalline silicon. Has the characteristic of being. The interface control effect of the polycrystalline silicon of graphene can be implemented in both n-type and p-type.
실리콘은 도핑되지 않은 경우에도 열적 평형에 의해서 전자와 정공이 동수로 존재하는 물질로서, 전자와 정공에 의한 전기전도가 동시에 가능하고, 이종원소가 도핑된 경우 n형이나 p형으로의 구현이 선택적으로 가능한 물질이다. 또한, 실리콘은 원소 반도체로서 전자 및 정공의 전기적 특성을 결정하는 전자 밴드 구조(electronic band structure)가 n형으로만 주로 존재하는 다른 산화물 반도체들과는 근본적으로 상이하다. 따라서, 단위 결정체들의 결정립계에 배치된 그래핀에 의해 전기전도 특성이 향상되는 메카니즘이 실리콘은 다른 산화물 반도체들과는 근본적으로 상이하다.Silicon is a material in which electrons and holes exist in the same number due to thermal equilibrium even when undoped, and electrical conduction by electrons and holes is possible at the same time. As possible substance. In addition, silicon is fundamentally different from other oxide semiconductors in which an electronic band structure, which is an elemental semiconductor, mainly determines n-type electronic band structure. Therefore, the mechanism in which the electrical conductivity is improved by graphene disposed at grain boundaries of unit crystals is fundamentally different from that of other oxide semiconductors.
일 실시예에서, 단위 결정체들은 n형 원소가 도핑된 다결정 실리콘일 수 있다. 이때, 본 발명에 따른 그래핀-다결정 실리콘 복합체의 전자 이동도(electron mobility)가 동일한 조건의 순수 다결정 실리콘과 대비하여 높은 값을 나타낸다. n형 원소로서는 비소(As)를 들 수 있다. 단위 결정체들이 n형 원소가 도핑된 다결정 실리콘에서는 단위 결정체들의 결정립계에 배치된 그래핀에 의해서 실리콘의 전도대의 전자의 이동도, 즉 전자 이동도가 향상되게 된다.In one embodiment, the unit crystals may be polycrystalline silicon doped with an n-type element. At this time, the electron mobility of the graphene-polycrystalline silicon composite according to the present invention exhibits a high value as compared with pure polycrystalline silicon under the same conditions. Arsenic (As) is mentioned as an n-type element. In polycrystalline silicon doped with n-type elements in unit crystals, the mobility of electrons, that is, electron mobility, in the conduction band of silicon is improved by graphene disposed at grain boundaries of the unit crystals.
다른 실시예에서, 단위 결정체들은 p형 원소가 도핑된 다결정 실리콘일 수 있다. 이때, 본 발명에 따른 그래핀-다결정 실리콘 복합체의 정공 이동도(hole mobility)가 동일한 조건의 순수 다결정 실리콘과 대비하여 높은 값을 나타낸다. p형 원소로서는 알루미늄, 붕소, 갈륨, 인듐 등을 들 수 있다. 결정립계에 배치된 그래핀에 의한 정공 이동도의 변화나 이의 상관관계에 대해서 전혀 알려진 바 없지만, 본 발명의 발명자들은 단위 결정체들이 p형 원소가 도핑된 다결정 실리콘에 의해서 구성되고, 이들 단위 결정체들 사이의 결정립계에 그래핀이 배치됨으로 인해 그래핀-다결정 실리콘 복합체의 정공 이동도가 높아지는 것을 확인하였으며, 이로부터 정공 이동도가 높아진 복합체를 발명할 수 있었다.In another embodiment, the unit crystals may be polycrystalline silicon doped with a p-type element. At this time, the hole mobility of the graphene-polycrystalline silicon composite according to the present invention exhibits a high value as compared with pure polycrystalline silicon under the same conditions. Aluminum, boron, gallium, indium etc. are mentioned as a p-type element. Although there is no known change in the hole mobility due to graphene disposed at the grain boundary or its correlation, the inventors of the present invention have unit crystals composed of polycrystalline silicon doped with p-type elements, and between these unit crystals. It was confirmed that the hole mobility of the graphene-polycrystalline silicon composite is increased due to the arrangement of graphene at the grain boundary of the composite, and thus the composite having the higher hole mobility may be invented.
특히, p형 원소가 도핑된 다결정 실리콘이 단위 결정체를 이루고, 단위 결정체들 사이의 결정립계에 그래핀이 배치된 본 발명에서는, 전자와 반대 성질을 갖는 전하 수송자(charge carrier)인 가전대(valence band)의 정공의 이동도, 즉 정공 이동도가 향상되게 된다. 정공은 전자와 반대 성질을 갖는 전하 수송자이기 때문에, 전자 이동도와 정공 이동도에는 특별한 상관관계가 없지만 본 발명의 발명자들은 그래핀을 p형 원소가 도핑된 다결정 실리콘으로 이루어진 단위 결정체들 사이의 결정립계에 배치시킴으로써 그래핀-다결정 실리콘 복합체의 정공 이동도를 향상시킬 수 있음을 발견한 것이다.In particular, in the present invention in which polycrystalline silicon doped with a p-type element forms a unit crystal and graphene is disposed at grain boundaries between the unit crystals, a valence that is a charge carrier having a property opposite to that of electrons hole mobility of the band), that is, hole mobility is improved. Because holes are charge transporters having opposite properties to electrons, there is no particular correlation between electron mobility and hole mobility, but the inventors of the present invention have found that the grain boundary between the unit crystals of graphene is composed of polycrystalline silicon doped with p-type element. It has been found that the hole mobility of the graphene-polycrystalline silicon composite can be improved by placing it in the.
즉, 본 발명에서는 단위 결정체가 실리콘으로 이루어져 있기 때문에 n형이나 p형을 모두 구현시킬 수 있고, 이에 따라 n형 원소가 도핑된 다결정 실리콘으로 이루어진 단위 결정체를 포함하는 복합체는 높은 정공 이동도를 가지고, p형 원소가 도핑된 다결정 실리콘으로 이루어진 단위 결정체를 포함하는 복합체는 높은 전자 이동도를 갖도록 구현된다.That is, in the present invention, since the unit crystal is made of silicon, both n-type and p-type can be realized, and thus the composite including the unit crystal made of polycrystalline silicon doped with n-type elements has a high hole mobility. The composite including unit crystals made of polycrystalline silicon doped with a p-type element is implemented to have high electron mobility.
본 발명에 따른 그래핀-다결정 실리콘 복합체는, 먼저 실리콘 분말과 산화그래핀 분말을 혼합하고 환원제를 첨가하여 실리콘-환원된 산화그래핀 복합 분말을 합성한 후, 이를 소결함으로써 제조할 수 있다. 상기 실리콘 분말은 p형 또는 n형 원소가 도핑된 실리콘 분말을 이용할 수 있다. 불순물이 도핑된 실리콘 분말을 이용하는 경우, 최종적으로 그래핀-다결정 실리콘 복합체에 포함된 다결정 실리콘에 불순물이 도핑된 형태가 될 수 있다.The graphene-polycrystalline silicon composite according to the present invention may be prepared by first mixing a silicon powder and a graphene oxide powder, adding a reducing agent to synthesize a silicon-reduced graphene oxide composite powder, and then sintering it. The silicon powder may be a silicon powder doped with a p-type or n-type element. In the case where the impurity doped silicon powder is used, the polycrystalline silicon included in the graphene-polycrystalline silicon composite may be finally doped with impurities.
소결 공정에서, 상기 실리콘-환원된 산화그래핀 복합 분말은 방전 플라즈마 소결법으로 소결됨으로써 그래핀-다결정 실리콘 복합체를 제조할 수 있다.In the sintering process, the silicon-reduced graphene oxide composite powder may be sintered by a discharge plasma sintering method to prepare a graphene-polycrystalline silicon composite.
상기 소결 공정은 고온과 진공 분위기 하에서 진행되기 때문에 소결체를 제조하는 것뿐만 아니라, 1차로 환원제를 이용하여 화학적 환원된 산화그래핀을 2차적으로 열적 환원시킬 수 있다. 이와 같이 제조된 화학적/열적 환원된 산화그래핀은 전기적으로 그래핀과 유사한 성질을 갖게 된다.Since the sintering process proceeds under a high temperature and vacuum atmosphere, not only to prepare a sintered body, but also to thermally reduce the chemically reduced graphene oxide secondarily using a reducing agent. The chemically / thermally reduced graphene oxide prepared as described above has electrical properties similar to graphene.
이하에서는, 구체적인 제조예 및 제조된 복합체의 특성 평가를 통해서 본 발명에 따른 복합체 및 이의 제조 방법에 대해서 보다 상세하게 설명하기로 한다.Hereinafter, the composite according to the present invention and a method for preparing the same will be described in more detail through evaluation of properties of specific preparation examples and the prepared composite.
제조예 1: 복합체 1의 제조Preparation Example 1 Preparation of Complex 1
스펙스밀을 이용하여 약 300 nm 크기로 분쇄된 실리콘 분말과 산화그래핀을 디메틸포름아미드 200 ml에 분산시킨 후 5분간 교반하여 혼합 분말을 준비하였다. 상기 혼합 분말에 히드라진 1수화물을 첨가하여 히팅 맨틀에서 80℃에서 1시간 동안 반응시켜 그래핀 산화물을 화학적 환원시킴으로써 실리콘-환원된 산화그래핀 복합 분말을 제조하였다. 이때의 산화그래핀의 함량은 1 중량%로 조절하였다. 반응이 끝난 용액은 구조 안정화를 위해 상온에서 24시간 동안 에이징 시킨 후 10,000 rpm에서 10 분간 원심분리 시켜준 후 40℃에서 24 시간 동안 진공 오븐에서 건조시켜 최종적으로 환원된 산화그래핀-실리콘 복합 분말을 얻었다. 얻어진 환원된 산화그래핀-실리콘 복합 분말을 방전 플라즈마 소결법으로 소결하였다. 소결 공정의 온도는 1,300℃이었고, 소결 시간은 30분, 소결 압력은 100 MPa이었다. 소결체에 대해서 로냉 시켜 최종적으로 환원된 산화그래핀-다결정 실리콘 복합체를 합성하였다.The powder was prepared by dispersing the silicon powder and graphene oxide pulverized to about 300 nm size in 200 ml of dimethylformamide using a specmill and then stirred for 5 minutes to prepare a mixed powder. The silicon-reduced graphene oxide composite powder was prepared by adding hydrazine monohydrate to the mixed powder and reacting at 80 ° C. for 1 hour in a heating mantle to chemically reduce graphene oxide. The content of graphene oxide at this time was adjusted to 1% by weight. After completion of the reaction, the solution was aged at room temperature for 24 hours to stabilize the structure, followed by centrifugation at 10,000 rpm for 10 minutes, and then dried in a vacuum oven at 40 ° C for 24 hours to finally reduce the graphene oxide-silicon oxide composite powder. Got it. The obtained reduced graphene oxide-silicon composite powder was sintered by the discharge plasma sintering method. The temperature of the sintering process was 1,300 degreeC, the sintering time was 30 minutes, and the sintering pressure was 100 MPa. The graphene oxide-polycrystalline silicon composite finally cooled by sintering was synthesized.
실리콘 분말과 복합 분말의 구조 확인: TEM 사진Check the structure of silicon powder and composite powder: TEM photo
복합체 1의 제조에 이용한 실리콘 분말과, 복합체 1이 생성되기 전의 중간 산물인 실리콘-환원된 산화그래핀 복합 분말 각각에 대해서 투과전자현미경 사진들을 촬영하였다. 그 결과를 도 1 및 도 2에 나타낸다.Transmission electron micrographs were taken for each of the silicon powder used for the preparation of the composite 1 and the silicon-reduced graphene oxide composite powder, which is an intermediate product before the formation of the composite 1. The results are shown in FIGS. 1 and 2.
도 1 및 도 2는 본 발명에 따른 복합체 1의 제조에 이용한 실리콘 분말과 실리콘-환원된 산화그래핀 복합 분말의 투과전자현미경(transmission electron microscope; TEM) 사진을 나타낸 도면들이다.1 and 2 are transmission electron microscope (TEM) images of the silicon powder and the silicon-reduced graphene oxide composite powder used in the preparation of the composite 1 according to the present invention.
도 1 및 도 2를 참조하면, 원료로 이용된 실리콘 분말이 약 300 nm의 크기를 가지는 것을 확인할 수 있고, 환원제를 이용하여 산화그래핀을 환원시킴으로써 실리콘-환원된 산화그래핀 복합 분말에서 실리콘 분말의 표면에 환원된 산화그래핀이 코팅되어 있는 것을 확인할 수 있다. 이때, 실리콘 분말의 표면에 코팅된 환원된 산화그래핀은 복수의 층으로 적층되어 있음을 TEM 사진을 통해서 확인할 수 있다.1 and 2, it can be seen that the silicon powder used as a raw material has a size of about 300 nm, the silicon powder in the silicon-reduced graphene oxide composite powder by reducing the graphene oxide using a reducing agent It can be seen that the reduced graphene oxide is coated on the surface. At this time, it can be confirmed through the TEM photograph that the reduced graphene oxide coated on the surface of the silicon powder is laminated in a plurality of layers.
제조예 2: 복합체 2의 제조Preparation Example 2 Preparation of Complex 2
비소가 도핑된 실리콘 분말을 이용함으로써 복합체 1에 n형 도핑 원소로서 비소가 도핑된 것을 제외하고는. 복합체 1을 제조하는 공정과 실질적으로 동일한 공정을 수행하여 비소가 도핑된 환원된 산화그래핀-다결정 실리콘 복합체인 복합체 2를 준비하였다.Except that arsenic was doped as n-type doping element in Composite 1 by using arsenic doped silicon powder. Substantially the same process as preparing the composite 1 was carried out to prepare a composite 2 which is a arsenic doped reduced graphene oxide-polycrystalline silicon composite.
복합체 2의 특성평가Characterization of Complex 2
상기와 같이 준비된 복합체 2에 대해서, 상온에서의 캐리어 농도와 전하 이동도(즉, 전자 이동도) 사이의 관계, 온도에 따른 전하 이동도의 변화, 온도에 따른 캐리어 농도의 변화 및 온도에 따른 전기 전도도의 변화를 각각 측정하였다. 그 결과를 도 3 내지 도 6에 나타낸다.For Composite 2 prepared as above, the relationship between the carrier concentration at room temperature and the charge mobility (i.e., electron mobility), the change in charge mobility with temperature, the change in carrier concentration with temperature, and the electricity with temperature Each change in conductivity was measured. The results are shown in FIGS. 3 to 6.
도 3 내지 도 6은 본 발명에 따른 복합체 2의 특성을 설명하기 위한 도면들이다. 도 3 내지 도 6 각각에서는 복합체 2(△)에 대한 결과와, 이의 비교예로서 비소가 도핑된 n형 실리콘 웨이퍼(□) 및 비소가 도핑된 n형 다결정 실리콘 소결체(○)에 대한 결과를 같이 나타낸다.3 to 6 are views for explaining the characteristics of the composite 2 according to the present invention. In each of FIGS. 3 to 6, the results of the composite 2 (Δ) and the comparative examples thereof are similar to those of the arsenic-doped n-type silicon wafer (□) and the arsenic-doped n-type polycrystalline silicon sintered body (○). Indicates.
도 3은 상온에서의 캐리어 농도(단위: cm-3)와 전하 이동도(단위: cm2V-1s-1) 사이의 관계를 나타낸 그래프로서, 비소가 도핑된 n형 단결정 실리콘에서의 캐리어 농도에 따른 전하 이동도를 나타내는 마세티 공식(Masetti's formula)을 이용하여 계산된 값을 실선으로 하여 함께 나타낸다.3 is a graph showing the relationship between the carrier concentration (unit: cm -3 ) and the charge mobility (unit: cm 2 V -1 s -1 ) at room temperature, the carrier in the arsenic doped n-type single crystal silicon The values calculated using Masetti's formula showing charge mobility with concentration are shown as solid lines.
도 3을 참조하면, 동일한 캐리어 농도 조건에 대해서, n형 다결정 실리콘 소결체(○)는 결정립계 산란으로 인해 마세티 공식으로 계산된 단결정 실리콘의 전하 이동도(약 100 cm2V-1s- 1)에 비해서 현저히 낮은 전하 이동도를 갖는 것으로 나타난다(약 25 cm2V-1s-1 수준). 반면, 환원된 산화그래핀으로 계면이 제어된 복합체 2(△)의 전하 이동도는 n형 다결정 실리콘 소결체(○)보다 2배 정도 높은 전하 이동도를 나타내는 것을 확인할 수 있다.Referring to FIG. 3, for the same carrier concentration condition, the n-type polycrystalline silicon sintered body (○) has a charge mobility (about 100 cm 2 V −1 s 1 ) of the single crystal silicon calculated by the Masseti formula due to grain boundary scattering. It appears to have a significantly lower charge mobility compared to (about 25 cm 2 V -1 s -1 level). On the other hand, it can be seen that the charge mobility of the composite 2 (Δ) whose interface is controlled by the reduced graphene oxide shows about twice the charge mobility of the n-type polycrystalline silicon sintered body (○).
도 4는 온도(단위: K)에 따른 전하 이동도 변화를 나타낸 그래프이다.4 is a graph showing the change in charge mobility with temperature (unit: K).
도 4를 참조하면, 물질 내에서의 전하 이동도는 매시슨의 규칙(Matthiessen's rule)에 의해서 크게 결정립계 산란, 이온화된 불순물 산란, 포논 산란의 영향으로 결정되는데, 일반적으로 다결정 재료에서는 결정립계에 의해 주로 전하가 산란된다. 그 결과 n형 다결정 실리콘 소결체(○)의 양상과 같이 온도에 따라서 전하 이동도가 증가하는 경향을 나타내는 것을 확인할 수 있다.Referring to FIG. 4, the charge mobility in the material is largely determined by the influence of grain boundary scattering, ionized impurity scattering, and phonon scattering according to the Masshiessen's rule. The charge is scattered. As a result, it can be seen that, as in the aspect of the n-type polycrystalline silicon sintered body (○), the charge mobility tends to increase with temperature.
하지만, 본 발명에 따른 복합체 2(△)에서는 실리콘과 그래핀의 밴드 정렬로 인해 전하의 결정립계 산란의 효과가 감소하여 전하 이동도가 증가하는 동시에 결정립계 산란 효과의 감소에 의해, n형 실리콘 웨이퍼(□)와 유사하게, 복합체 2(△)의 전하 이동도는 온도에 반비례하는 관계를 나타내는 것을 확인할 수 있다.However, in the composite 2 (△) according to the present invention, due to the band alignment of silicon and graphene, the effect of grain boundary scattering of the charge is reduced, thereby increasing charge mobility and decreasing grain boundary scattering effect, thereby reducing the n-type silicon wafer ( Similar to □), it can be seen that the charge mobility of the complex 2 (△) shows an inverse relationship with the temperature.
도 5는 온도에 따른 전하 이동도 변화를 나타낸 그래프로서, 도 5에서는 복합체 2(△), n형 실리콘 웨이퍼(□) 및 n형 다결정 실리콘 소결체(○) 모두 캐리어 농도는 크게 차이가 나지 않는 경향을 나타내는 것을 확인할 수 있다.5 is a graph showing the change in charge mobility with temperature. In FIG. 5, the carrier concentrations of the composite 2 (Δ), the n-type silicon wafer (□), and the n-type polycrystalline silicon sintered body (○) do not tend to be significantly different. It can be seen that indicates.
도 6은 온도에 따른 전기전도도(electrical conductivity, 단위 Scm-1) 변화를 나타낸 그래프로서, 도 6을 통해서 n형 다결정 실리콘 소결체(○)에 비해서 본 발명에 따른 복합체 2(△)의 전기전도도가 전체적으로 온도 변화에 따라서 높은 값을 나타내는 것을 확인할 수 있다.6 is a graph showing the change in electrical conductivity (unit Scm -1 ) with temperature, and the electrical conductivity of the composite 2 (△) according to the present invention compared to the n-type polycrystalline silicon sintered body (○) through FIG. It can be seen that the overall value shows a high value according to the change in temperature.
제조예 3: 복합체 3의 제조Preparation Example 3 Preparation of Complex 3
붕소가 도핑된 실리콘 분말을 이용함으로써 복합체 1에 p형 도핑 원소로서 붕소가 도핑된 것을 제외하고는, 복합체 1을 제조하는 공정과 실질적으로 동일한 공정을 수행하여 붕소가 도핑된 환원된 산화그래핀-다결정 실리콘 복합체인 복합체 3을 준비하였다.Reduced graphene oxide doped with boron by carrying out substantially the same process as the preparation of the composite 1, except that boron was doped into the composite 1 by using a boron-doped silicon powder. Composite 3, a polycrystalline silicon composite, was prepared.
복합체 3의 특성평가Characterization of Complex 3
상기와 같이 준비된 복합체 3에 대해서, 상온에서의 캐리어 농도와 전하 이동도(즉, 정공 이동도) 사이의 관계, 온도에 따른 전하 이동도의 변화, 온도에 따른 캐리어 농도의 변화 및 온도에 따른 전기 전도도의 변화를 각각 측정하였다. 그 결과를 도 7 내지 도 10에 나타낸다.For the composite 3 prepared as above, the relationship between the carrier concentration and the charge mobility (ie, hole mobility) at room temperature, the change in the charge mobility with temperature, the change in the carrier concentration with temperature, and the electricity with temperature Each change in conductivity was measured. The results are shown in FIGS. 7 to 10.
도 7 내지 도 10은 본 발명에 따른 복합체 3의 특성을 설명하기 위한 도면들이다. 도 7 내지 도 10에서, 복합체 3(◇)에 대한 결과와, 이의 비교예로서 붕소가 도핑된 p형 실리콘 웨이퍼(▽)에 대한 결과를 같이 나타낸다.7 to 10 are views for explaining the characteristics of the composite 3 according to the present invention. In Figures 7 to 10, the results for the composite 3 (◇) and, as a comparative example, the results for the boron-doped p-type silicon wafer (▽) is shown together.
도 7 내지 도 10을 참조하면, 복합체 3(◇)의 전하 이동도의 온도 의존성을 보면 온도가 증가함에 따라 이동도가 감소하는 경향을 보이는데, 이는 그래핀을 이용한 계면 제어를 통해 결정립계 산란의 영향이 줄어들었기 때문으로 볼 수 있으며, 이 결과를 통해 그래핀을 이용한 계면 제어를 통한 전하 이동 특성의 향상은 n형 실리콘뿐만 아니라 p형 실리콘에도 적용 가능함을 알 수 있다. 또한, 다른 특성들에 있어서도 복합체 3(◇)의 특성은 도 3 내지 도 6에서 살펴본 복합체 2(△)의 특성과 유사하게 나타나는 것을 확인할 수 있다.Referring to Figures 7 to 10, the temperature dependence of the charge mobility of the composite 3 (◇) tends to decrease the mobility as the temperature increases, which is the effect of grain boundary scattering through the interface control using graphene It can be seen that this is reduced, and from this result, it can be seen that the improvement of charge transfer characteristics through interface control using graphene is applicable to not only n-type silicon but also p-type silicon. In addition, also in the other properties it can be seen that the properties of the composite 3 (◇) appear similar to the properties of the composite 2 (△) shown in Figures 3 to 6.
도 11은 n형 및 p형 실리콘과 그래핀의 밴드 정렬(band alignment) 관계를 나타낸 도면이다.FIG. 11 is a diagram illustrating a band alignment relationship between n-type and p-type silicon and graphene. FIG.
도 3 내지 도 10을 도 11과 함께 참조하면, 그래핀은 밴드갭이 없는 물질로서, 접하고 있는 물질의 페르미 레벨(Fermi level)에 영향을 받아 전자 또는 홀 농도가 변화하는 페르미 액체(Fermi liquid)특성을 가지고 있는 물질이다. 따라서 도면가 같이 고농도로 도핑된 실리콘 결정립계 사이의 계면에 그래핀이 위치할 경우 실리콘과 그래핀의 밴드 정렬로 인해 실리콘과 그래핀의 계면을 지나는 전하는 결정립계 산란으로부터 자유로워질 수 있다. 결과적으로 전하의 결정립계 산란의 효과가 줄어들어 복합체의 전하 이동 특성을 향상시킬 수 있다.Referring to FIGS. 3 to 10 together with FIG. 11, graphene is a material without a bandgap, and a Fermi liquid whose electron or hole concentration changes depending on the Fermi level of the material in contact with the graphene. It is a substance with properties. Therefore, when graphene is located at the interface between the heavily doped silicon grain boundaries, charges passing through the interface between silicon and graphene may be free from grain boundary scattering due to the band alignment of silicon and graphene. As a result, the effect of grain boundary scattering of charges is reduced, thereby improving charge transfer characteristics of the composite.
이상에서, 본 발명의 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되는 것은 아니며, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능하다.In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. Modifications are possible.

Claims (12)

  1. 다결정 실리콘이 형성하는 다수의 단위 결정체들의 집합체이고,Is a collection of a number of unit crystals formed by polycrystalline silicon,
    단위 결정체들 사이의 결정립계에 그래핀이 배치된 구조를 갖는 것을 특징으로 하는,Characterized in that the graphene is arranged in the grain boundary between the unit crystals,
    그래핀-다결정 실리콘 복합체.Graphene-polycrystalline silicon composite.
  2. 제1항에 있어서,The method of claim 1,
    상기 결정립계에는 다수의 그래핀들이 적층되어 배치된 것을 특징으로 하는,Characterized in that a plurality of graphene is stacked and disposed in the grain boundary,
    그래핀-다결정 실리콘 복합체.Graphene-polycrystalline silicon composite.
  3. 제1항에 있어서,The method of claim 1,
    단위 결정체들에 n형 원소가 도핑된 것을 특징으로 하는, 그래핀-다결정 실리콘 복합체.Graphene-polycrystalline silicon composite, characterized in that the n-type element is doped in the unit crystals.
  4. 제3항에 있어서,The method of claim 3,
    동일 조건의 그래핀 미포함 다결정 실리콘과 대비하여, 전자 이동도(electron mobility)가 높은 값을 나타내는 것을 특징으로 하는,Compared to the graphene-free polycrystalline silicon of the same conditions, characterized in that the electron mobility (electron mobility) shows a high value,
    그래핀-다결정 실리콘 복합체.Graphene-polycrystalline silicon composite.
  5. 제1항에 있어서,The method of claim 1,
    단위 결정체들에 p형 원소가 도핑된 것을 특징으로 하는, 그래핀-다결정 실리콘 복합체.Graphene-polycrystalline silicon composite, characterized in that the unit crystals doped with a p-type element.
  6. 제5항에 있어서,The method of claim 5,
    동일 조건의 그래핀 미포함 다결정 실리콘과 대비하여, 정공 이동도(hole mobility)가 높은 값을 나타내는 것을 특징으로 하는,In comparison with the graphene-free polycrystalline silicon of the same conditions, it characterized in that the hole mobility (hole hole) shows a high value,
    그래핀-다결정 실리콘 복합체.Graphene-polycrystalline silicon composite.
  7. 제1항에 있어서,The method of claim 1,
    상기 단위 결정체들 사이에 배치된 그래핀은Graphene disposed between the unit crystals
    그래핀, 환원된 산화그래핀 또는 산화그래핀인 것을 특징으로 하는,It is characterized in that the graphene, reduced graphene oxide or graphene oxide,
    그래핀-다결정 실리콘 복합체.Graphene-polycrystalline silicon composite.
  8. 실리콘 분말과 산화그래핀 분말을 분산 용매에서 혼합시키는 단계;Mixing the silicon powder and the graphene oxide powder in a dispersion solvent;
    혼합된 실리콘 분말과 산화그래핀 분말에 환원제를 첨가하여, 환원된 산화그래핀이 실리콘 분말의 표면에 코팅된 혼합 분말을 제조하는 단계; 및Adding a reducing agent to the mixed silicon powder and the graphene oxide powder to prepare a mixed powder in which the reduced graphene oxide is coated on the surface of the silicon powder; And
    상기 혼합 분말을 소결하여 그래핀-다결정 실리콘 복합체를 제조하는 단계를 포함하고,Sintering the mixed powder to prepare a graphene-polycrystalline silicon composite,
    상기 그래핀-다결정 실리콘 복합체는 다결정 실리콘이 형성하는 다수의 단위 결정체들의 집합체로서, 상기 단위 결정체들 사이의 결정립계에 그래핀이 배치된 구조를 갖는 것을 특징으로 하는,The graphene-polycrystalline silicon composite is a collection of a plurality of unit crystals formed by polycrystalline silicon, characterized in that having a structure in which graphene is disposed at grain boundaries between the unit crystals,
    그래핀-다결정 실리콘 복합체의 제조 방법.Method for preparing graphene-polycrystalline silicon composite.
  9. 제8항에 있어서,The method of claim 8,
    상기 그래핀-다결정 실리콘 복합체를 제조하는 단계는 방전 플라즈마 소결법으로 수행하는 것을 특징으로 하는,The step of preparing the graphene-polycrystalline silicon composite, characterized in that performed by the discharge plasma sintering method,
    그래핀-다결정 실리콘 복합체의 제조 방법.Method for preparing graphene-polycrystalline silicon composite.
  10. 제8항에 있어서,The method of claim 8,
    상기 혼합시키는 단계에서 이용하는 실리콘 분말은 p형 원소 또는 n형 원소가 도핑된 실리콘 분말인 것을 특징으로 하는,The silicon powder used in the mixing step is characterized in that the silicon powder doped with p-type element or n-type element,
    그래핀-다결정 실리콘 복합체의 제조 방법.Method for preparing graphene-polycrystalline silicon composite.
  11. 제1항 내지 제7항 중 어느 한 항에 따른 그래핀-다결정 실리콘 복합체를 포함하는, 전도체.A conductor comprising the graphene-polycrystalline silicon composite according to any one of claims 1 to 7.
  12. 제1항 내지 제7항 중 어느 한 항에 따른 그래핀-다결정 실리콘 복합체로 형성된 기판.A substrate formed of the graphene-polycrystalline silicon composite according to any one of claims 1 to 7.
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