WO2018207359A1 - Wireless communication device, transmission method and reception method - Google Patents

Wireless communication device, transmission method and reception method Download PDF

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Publication number
WO2018207359A1
WO2018207359A1 PCT/JP2017/018066 JP2017018066W WO2018207359A1 WO 2018207359 A1 WO2018207359 A1 WO 2018207359A1 JP 2017018066 W JP2017018066 W JP 2017018066W WO 2018207359 A1 WO2018207359 A1 WO 2018207359A1
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signal
frequency
wireless communication
chirp signal
unit
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PCT/JP2017/018066
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French (fr)
Japanese (ja)
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石岡　和明
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三菱電機株式会社
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Priority to JP2019516857A priority Critical patent/JP6580289B2/en
Priority to PCT/JP2017/018066 priority patent/WO2018207359A1/en
Publication of WO2018207359A1 publication Critical patent/WO2018207359A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits

Definitions

  • the present invention relates to a radio communication apparatus, a transmission method, and a reception method that perform radio communication of signals using a ZC (Zadoff-Chu) sequence for a random access preamble.
  • ZC Zero-Chu
  • the ZC sequence defined on the time axis may be used for the uplink random access preamble, that is, the preamble of the random access channel.
  • a ZC sequence is a type of chirp signal obtained by discretizing a chirp signal that sweeps the frequency on the time-frequency axis.
  • the ZC sequence is a constant envelope and a CAZAC (Constant Amplitude Zero Auto-Correlation) sequence in which the autocorrelation with a shifted timing is zero.
  • the ZC sequence can improve the efficiency of the transmission amplifier because there is little amplitude fluctuation, and has excellent orthogonality on the time axis because the autocorrelation is zero. Due to this property, in LTE, a ZC sequence is used as a reference signal serving as a reference signal for random access preamble and synchronous detection.
  • Patent Document 1 discloses a technique for detecting the timing of a ZC sequence.
  • the wireless communication device includes a reference oscillator such as a crystal oscillator, and generates a radio frequency with a frequency synthesizer based on the reference oscillator.
  • the radio communication device on the transmission side up-converts the frequency of the signal using a frequency mixer and transmits it from the antenna, and the radio communication device on the reception side down-converts the frequency of the signal received by the antenna with the frequency mixer.
  • a frequency deviation occurs due to an error in the frequency of each reference oscillator included in the wireless communication device on the transmission side and the reception side.
  • the frequency deviation is larger than the allowable value, wireless communication between the wireless communication devices becomes difficult. Therefore, it is necessary to detect and correct the frequency deviation in the radio communication device on the receiving side.
  • a signal based on a chirp signal such as a ZC sequence has the property that the frequency deviation and the timing shift of the ZC sequence are equalized, and the timing of the ZC sequence is shifted.
  • the frequency deviation cannot be measured accurately. Therefore, it is necessary that the transmitting-side wireless communication apparatus transmits another signal for detecting the frequency deviation, and the receiving-side wireless communication apparatus receives another signal to detect the frequency deviation.
  • a circuit for transmitting another signal must be added in the wireless communication apparatus on the transmission side, and a circuit for receiving another signal must be added in the wireless communication apparatus on the reception side.
  • the present invention has been made in view of the above, and wirelessly transmits a signal capable of detecting a frequency deviation on the receiving side while including a data signal without transmitting another signal for detecting the frequency deviation.
  • An object is to obtain a communication device.
  • the wireless communication apparatus of the present invention includes an upstream chirp signal that sweeps the frequency from the lower side to the higher side and a downstream chirp signal that sweeps the frequency from the higher side to the lower side.
  • a transmitter that repeatedly generates alternately and transmits a multiplexed signal obtained by multiplexing an uplink chirp signal or a downlink chirp signal and a data signal, and an oscillation circuit that generates a frequency signal used when up-converting the multiplexed signal; It is characterized by providing.
  • the wireless communication device can transmit a signal that includes a data signal and can detect a frequency deviation on the receiving side without transmitting another signal for detecting the frequency deviation. Play.
  • wireless communications system Block diagram showing a configuration example of a transmitter of a wireless communication device
  • Block diagram showing a configuration example of a receiver of a wireless communication device Block diagram showing a configuration example of a frequency deviation detection unit of a wireless communication device
  • wireless communication apparatus Block diagram showing a configuration example of a delay detection unit of a wireless communication device
  • wireless communication apparatus receives a radio signal.
  • wireless communication apparatus detects a frequency deviation.
  • wireless communication apparatus with a processor and memory The figure which shows the example in the case of comprising the treatment circuit of a radio
  • FIG. 1 is a diagram illustrating a configuration example of a radio communication system 100 according to an embodiment of the present invention.
  • the wireless communication system 100 includes wireless communication devices 1 and 2.
  • the wireless communication devices 1 and 2 are devices that can transmit and receive wireless signals.
  • wireless signals are transmitted and received between the wireless communication device 1 and the wireless communication device 2.
  • the wireless communication apparatus 1 includes a transmitter 11, a receiver 12, a reference transmitter 13, a frequency synthesizer 14, a duplexer 15, and an antenna 16.
  • the transmitter 11 modulates transmission data, which is a data signal to be transmitted, and generates a multiplexed signal, that is, a radio signal, obtained by multiplexing the modulated transmission data and a chirp signal.
  • the receiver 12 separates the received multiplexed signal, that is, a radio signal into a chirp signal and a data signal, demodulates the data signal, and outputs received data that is the demodulated data signal.
  • the reference transmitter 13 generates a reference signal used in the wireless communication device 1.
  • the frequency synthesizer 14 uses the reference signal generated by the reference transmitter 13 to reduce the frequency signal used when up-converting the radio signal transmitted by the transmitter 11 and the radio signal received by the receiver 12. This is an oscillation circuit that generates a frequency signal used for conversion.
  • the duplexer 15 outputs the radio signal generated by the transmitter 11 to the antenna 16 and outputs the radio signal received by the antenna 16 to the receiver 12.
  • the antenna 16 acquires the radio signal generated by the transmitter 11 via the duplexer 15 and transmits it to the radio communication device 2.
  • the antenna 16 receives a radio signal transmitted from the radio communication device 2 and outputs it to the receiver 12 via the duplexer 15.
  • the wireless communication apparatus 2 includes a transmitter 21, a receiver 22, a reference transmitter 23, a frequency synthesizer 24, a duplexer 25, and an antenna 26.
  • the transmitter 21, the receiver 22, the reference transmitter 23, the frequency synthesizer 24, the duplexer 25, and the antenna 26 of the wireless communication device 2 are respectively the transmitter 11, the receiver 12, and the reference transmitter 13 of the wireless communication device 1. Since it is similar to the frequency synthesizer 14, the duplexer 15, and the antenna 16, detailed description thereof is omitted.
  • the wireless communication apparatus 2 receives the wireless signal and outputs reception data, that is, the wireless communication apparatus 1
  • the operation of the wireless communication devices 1 and 2 when the wireless communication device 2 is the receiving device and the wireless communication device 2 is the receiving device will be described.
  • FIG. 2 is a block diagram illustrating a configuration example of the transmitter 11 of the wireless communication device 1 according to the present embodiment.
  • the transmitter 11 includes a data modulation unit 31, a chirp signal generation unit 32, a multiplexing unit 33, an up-converter 34, and an amplifier 35.
  • the data modulator 31 modulates the transmission data by a modulation scheme such as QPSK (Quadrature Phase Shift Keying), 16QAM (Quadrature Amplitude Modulation), 64QAM.
  • the modulation method is not limited to these.
  • the chirp signal generation unit 32 generates a chirp signal. The configuration of the chirp signal generation unit 32 and the details of the chirp signal generated by the chirp signal generation unit 32 will be described later.
  • the multiplexing unit 33 multiplexes the data signal modulated by the data modulation unit 31 and the chirp signal generated by the chirp signal generation unit 32.
  • the signal multiplexing method in the multiplexing unit 33 includes time division multiplexing, frequency division multiplexing, a method using both multiplexing methods, and the like, but is not limited thereto.
  • the up-converter 34 mixes the multiplexed signal multiplexed by the multiplexing unit 33 and the frequency signal output from the frequency synthesizer 14 using a frequency mixer, and up-converts the frequency of the multiplexed signal to a radio frequency.
  • the amplifier 35 amplifies the upconverted signal output from the upconverter 34 to a prescribed transmission power, and outputs the amplified signal to the antenna 16 via the duplexer 15.
  • the transmitter 11 transmits a multiplexed signal, that is, a radio signal to the radio communication device 2 via the duplexer 15 and the antenna 16.
  • FIG. 3 is a diagram illustrating an example of a time-frequency waveform of the uplink chirp signal generated by the chirp signal generation unit 32 of the wireless communication apparatus 1 according to the present embodiment. Moreover, FIG.
  • the upstream chirp signal can be expressed as a signal whose frequency increases with time, and the downstream chirp signal can be expressed as a signal whose frequency decreases with time.
  • FIG. 5 is a diagram illustrating an example of an IQ waveform of the uplink chirp signal generated by the chirp signal generation unit 32 of the wireless communication apparatus 1 according to the present embodiment.
  • FIG. 6 is a figure which shows the example of IQ waveform of the downlink chirp signal which the chirp signal generation part 32 of the radio
  • the horizontal axis indicates the frequency band, and the vertical axis indicates the amplitude.
  • the upstream chirp signal and the downstream chirp signal have a complex conjugate relationship because they are signals with the frequency axis inverted. For this reason, the I waveform is the same between the upstream chirp signal and the downstream chirp signal, and the Q signal is inverted between the upstream chirp signal and the downstream chirp signal.
  • the chirp signal generation unit 32 repeatedly generates the upstream chirp signal shown in FIG. 3 and the downstream chirp signal shown in FIG. 4 alternately.
  • the chirp signal generation unit 32 performs ramp-up and ramp-down as shown in FIGS. 5 and 6 at the beginning and end of the upstream chirp signal and the downstream chirp signal in order to avoid unnecessary radiation outside the band. Append.
  • FIG. 7 is a block diagram illustrating a configuration example of the chirp signal generation unit 32 of the wireless communication device 1 according to the present embodiment.
  • the chirp signal generation unit 32 includes a memory 41, a counter 42, and a reading unit 43.
  • the memory 41 stores an upstream chirp signal and a downstream chirp signal.
  • the counter 42 generates a memory address of the memory 41.
  • the reading unit 43 alternately reads and outputs the upstream chirp signal and the downstream chirp signal from the memory 41.
  • FIG. 8 is a diagram illustrating an example of a memory map of the uplink chirp signal and the downlink chirp signal stored in the memory 41 of the wireless communication apparatus 1 according to the present embodiment.
  • n memory addresses are assigned to the upstream chirp signal and the downstream chirp signal.
  • n is an integer of 2 or more.
  • IQ waveform data shown in FIG. 5 is stored in the upstream chirp signal portion in the memory map
  • IQ waveform data shown in FIG. 6 is stored in the downstream chirp signal portion in the memory map. Has been.
  • the chirp signal generation unit 32 repeatedly generates an uplink chirp signal and a downlink chirp signal alternately. Therefore, the multiplexing unit 33 multiplexes the uplink chirp signal or the downlink chirp signal and the data signal modulated by the data modulation unit 31. Specifically, after multiplexing the upstream chirp signal and the data signal, the multiplexing unit 33 multiplexes the downstream chirp signal and the data signal, and repeats this operation.
  • the upstream chirp signal and the downstream chirp signal may be collectively referred to as a chirp signal.
  • FIG. 9 is a flowchart showing an operation in which the wireless communication apparatus 1 according to the present embodiment transmits a wireless signal.
  • the data modulation unit 31 of the transmitter 11 modulates transmission data (step S1).
  • the chirp signal generation unit 32 repeatedly generates an uplink chirp signal and a downlink chirp signal alternately (step S2).
  • the multiplexing unit 33 multiplexes the uplink chirp signal or the downlink chirp signal generated by the chirp signal generation unit 32 and the data signal modulated by the data modulation unit 31 (step S3).
  • the up-converter 34 up-converts the frequency of the multiplexed signal to a radio frequency (step S4).
  • the amplifier 35 amplifies the power of the signal after the up-conversion (Step S5).
  • the transmitter 11 transmits a radio signal to the radio communication device 2 via the duplexer 15 and the antenna 16 (step S6). In this way, the transmitter 11 repeatedly generates an uplink chirp signal and a downlink chirp signal alternately, and transmits a radio signal obtained by multiplexing the uplink chirp signal or the downlink chirp signal and the data signal.
  • FIG. 10 is a block diagram illustrating a configuration example of the receiver 22 of the wireless communication device 2 according to the present embodiment.
  • the receiver 22 includes an amplifier 51, a down converter 52, a separation unit 53, a frequency deviation detection unit 54, and a data demodulation unit 55.
  • the amplifier 51 amplifies the multiplex signal received through the duplexer 25 and the antenna 26, that is, a radio signal, to a prescribed power.
  • the down converter 52 uses a frequency mixer to mix the radio signal output from the amplifier 51 and the frequency signal output from the frequency synthesizer 24, and down-converts the frequency of the radio signal to the frequency of the baseband signal. .
  • the separation unit 53 separates the multiplexed signal received by the receiver 22 into a chirp signal and a data signal.
  • the multiplexed signal is a baseband signal output from the down converter 52, and is a signal using time division multiplexing, frequency division multiplexing, or both multiplexing methods.
  • the separation unit 53 outputs the chirp signal to the frequency deviation detection unit 54 and outputs the data signal to the data demodulation unit 55.
  • the frequency deviation detector 54 detects the frequency deviation of the frequency used in the wireless communication device 2 and the wireless communication device 1 using the chirp signal separated by the separation unit 53.
  • the frequency deviation detector 54 outputs the detected frequency deviation to the data demodulator 55.
  • the data demodulator 55 corrects the frequency deviation of the data signal using the frequency deviation detected by the frequency deviation detector 54, and demodulates the data signal separated by the separator 53, such as QPSK, 16QAM, 64QAM. Go and output the received data.
  • FIG. 11 is a block diagram illustrating a configuration example of the frequency deviation detection unit 54 of the wireless communication device 2 according to the present embodiment.
  • the frequency deviation detection unit 54 includes an FFT (Fast Fourier Transform) 61, a memory 62, a complex multiplication unit 63, a delay detection unit 64, a frequency axis inversion unit 65, a cyclic addition unit 66, an FFT 67, and a peak detection.
  • FFT Fast Fourier Transform
  • the FFT 61 performs N-point FFT, that is, fast Fourier transform, for each chirp signal transmitted from the wireless communication device 1 a plurality of times on the chirp signal output from the separation unit 53, and converts the chirp signal from the signal on the time axis. Convert to N signals on the frequency axis. N is a value determined by the sampling frequency at the time of FFT. That is, the FFT 61 converts the upstream chirp signal and the downstream chirp signal from a signal on the time axis to a signal on the frequency axis.
  • the FFT 61 is a first conversion unit.
  • the memory 62 stores a complex conjugate of data obtained by converting a chirp signal, which is a transmission waveform from the wireless communication device 1, into a signal on the frequency axis.
  • FIG. 12 is a diagram illustrating a signal flow in the frequency deviation detection unit 54 of the wireless communication device 2 according to the present embodiment.
  • the signal waveform shown in FIG. 12A is the channel estimation value obtained by the complex multiplier 63.
  • the delay detection unit 64 delay-detects the channel estimation value output from the complex multiplication unit 63 for each chirp signal, and obtains a delay detection result for each frequency. That is, the delay detection unit 64 performs delay detection for each frequency between successive upstream chirp signals and downstream chirp signals. As shown in FIG. 12B, the delay detection result for the channel estimation value is a delay detection result having a different delay time for each frequency.
  • FIG. 13 is a block diagram illustrating a configuration example of the delay detection unit 64 of the wireless communication apparatus 2 according to the present embodiment.
  • the delay detection unit 64 includes a delay unit 71, a complex conjugate unit 72, and a complex multiplication unit 73.
  • the delay unit 71 delays the channel estimation value, which is the output from the complex multiplication unit 63, in N frequency axis data units.
  • the complex conjugate unit 72 converts the data delayed by the delay unit 71 into a complex conjugate.
  • the complex multiplier 73 performs complex multiplication of the delayed reference signal output from the complex conjugate unit 72 and the non-delayed channel estimation value output from the complex multiplier 63 for each frequency.
  • the frequency axis inversion unit 65 converts the delay detection result for one of the chirp signals out of the delay detection results output from the delay detection unit 64, that is, the delay detection result when one of the upstream chirp signal and the downstream chirp signal is used as a reference.
  • the frequency axis is inverted in order to reverse the order of arrangement of signals for each frequency. As shown in FIG. 12 (b), in the case of delay detection with respect to the upstream chirp signal based on the downstream chirp signal and the case of delay detection with respect to the downstream chirp signal based on the upstream chirp signal, The delay time trend is different.
  • the frequency axis inversion unit 65 aligns the tendency of the delay time for each frequency. Therefore, when delay detection is performed based on the downstream chirp signal, the frequency axis inversion unit 65 arranges the signals for each frequency of the delay detection result. The order is reversed and the frequency axis is reversed.
  • the cyclic adder 66 improves the SNR by cyclically adding the delay detection results for each frequency because the delay detection results output from the frequency axis inversion unit 65 have the same delay time for each frequency.
  • the cyclic addition unit 66 includes a delay detection result in which the frequency axis is not inverted by the frequency axis inversion unit 65 among the delay detection results output from the delay detection unit 64, and a frequency axis in the frequency axis inversion unit 65.
  • the inverted delayed detection result is cyclically added.
  • FIG. 12D shows the signal after cyclic addition.
  • the cyclic addition unit 66 can improve the SNR by the frequency diversity effect even when the wireless transmission path is in a fading environment by cyclically adding the delay detection results of different frequencies.
  • FIG. 12D shows the signal after cyclic addition.
  • the cyclic addition unit 66 includes a complex addition unit 81 and a memory 82.
  • the complex adder 81 adds the previous cyclic addition result held in the memory 82 and the delayed detection result output from the frequency axis inversion unit 65 for each frequency, that is, cyclic addition.
  • the complex adder 81 stores and holds the addition result in the memory 82 and outputs the result to the FFT 67 via the memory 82.
  • the memory 82 holds the addition result by the complex adder 81.
  • the delayed detection result after cyclic addition output from the cyclic adder 66 is the result of delayed detection in which the delay time varies linearly for each frequency. For this reason, when there is a frequency deviation, the delayed detection result after cyclic addition output from the cyclic addition unit 66 is a signal that is linearly rotated in phase with a slope proportional to the frequency deviation.
  • the FFT 67 performs FFT on the delayed detection result after cyclic addition output from the cyclic adder 66 and converts the signal on the time axis into the signal on the frequency axis.
  • the FFT 67 is a second conversion unit.
  • the peak detecting unit 68 can detect the phase rotation amount proportional to the frequency deviation by detecting the peak where the amplitude of the signal output from the FFT 67 is maximized, that is, the peak detection position can be detected as the frequency deviation.
  • FIG. 12E shows the output from the FFT 67 having the maximum amplitude.
  • the peak detector 68 outputs the detected frequency deviation to the data demodulator 55.
  • FIG. 15 is a flowchart showing an operation in which the wireless communication device 2 according to the present embodiment receives a wireless signal.
  • the receiver 22 receives a wireless signal from the wireless communication device 1 via the antenna 26 and the duplexer 25 (step S11).
  • the amplifier 51 amplifies the power of the radio signal (step S12).
  • the down converter 52 down-converts the frequency of the radio signal to the frequency of the baseband signal (step S13).
  • the separation unit 53 separates the baseband signal output from the down converter 52 into a chirp signal and a data signal (step S14).
  • the frequency deviation detection unit 54 detects the frequency deviation using the chirp signal separated by the separation unit 53 (step S15).
  • the data demodulator 55 demodulates the data signal using the frequency deviation detected by the frequency deviation detector 54 (step S16).
  • the receiver 22 receives the radio signal transmitted from the radio communication device 1 and detects the frequency deviation of the frequency used in the radio communication devices 1 and 2 using the received radio signal.
  • FIG. 16 is a flowchart illustrating an operation in which the frequency deviation detection unit 54 of the wireless communication apparatus 2 according to the present embodiment detects a frequency deviation.
  • the FFT 61 performs FFT on the chirp signal output from the separator 53, and converts the signal on the time axis into the signal on the frequency axis (step S21).
  • the complex multiplier 63 calculates a channel estimation value on the frequency axis for each chirp signal (step S22).
  • the delay detection unit 64 performs delay detection for each frequency between the upstream chirp signal and the downstream chirp signal (step S23).
  • the frequency axis inversion unit 65 inverts the frequency axis of the delay detection result when one of the upstream chirp signal and the downstream chirp signal is used as a reference (step S24).
  • the cyclic addition unit 66 cyclically adds the delay detection results output from the delay detection unit 64 and the frequency axis inversion unit 65 (step S25).
  • the FFT 67 performs FFT on the delayed detection result after cyclic addition output from the cyclic adder 66, and converts the signal on the time axis into the signal on the frequency axis (step S26).
  • the peak detector 68 detects a frequency deviation based on the amplitude of the signal output from the FFT 67 (step S27).
  • the wireless communication device 2 modulates the transmission data. The same operation is performed when the wireless signal is transmitted and the wireless communication apparatus 1 receives the wireless signal and outputs the received data.
  • the configuration of the receiver 12 of the wireless communication device 1 is the same as the configuration of the receiver 22 of the wireless communication device 2.
  • the reference transmitter 13 is an oscillator such as a crystal oscillator.
  • the frequency synthesizer 14 is an oscillation circuit.
  • the duplexer 15 is a filter circuit.
  • the antenna 16 is an antenna element.
  • the amplifier 51 is an amplifier circuit.
  • the down converter 52 is a frequency conversion circuit.
  • the separation unit 53 is a separation circuit.
  • the data demodulator 55 is a demodulator.
  • the frequency deviation detector 54 is realized by a processing circuit.
  • the wireless communication device 1 includes a processing circuit for detecting a frequency deviation of frequencies used in the wireless communication device 2 of the own device and the communication partner.
  • the processing circuit may be a processor and a memory that execute a program stored in the memory, or may be dedicated hardware.
  • FIG. 17 is a diagram illustrating an example in which the processing circuit of the wireless communication apparatus 1 according to the present embodiment is configured by a processor and a memory.
  • the processing circuit includes the processor 91 and the memory 92
  • each function of the processing circuit of the wireless communication device 1 is realized by software, firmware, or a combination of software and firmware.
  • Software or firmware is described as a program and stored in the memory 92.
  • each function is realized by the processor 91 reading and executing the program stored in the memory 92. That is, in the wireless communication apparatus 1, the processing circuit includes a memory 92 for storing a program that results in detecting a frequency deviation. These programs can also be said to cause a computer to execute the procedure and method of the wireless communication apparatus 1.
  • the processor 91 may be a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor).
  • the memory 92 is nonvolatile or volatile, such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (registered trademark) (Electrically EPROM), and the like.
  • RAM Random Access Memory
  • ROM Read Only Memory
  • flash memory such as EPROM (Erasable Programmable ROM), EEPROM (registered trademark) (Electrically EPROM), and the like.
  • Such semiconductor memory, magnetic disk, flexible disk, optical disk, compact disk, mini disk, DVD (Digital Versatile Disc), and the like are applicable.
  • FIG. 18 is a diagram illustrating an example in which the treatment circuit of the wireless communication device 1 according to the present embodiment is configured with dedicated hardware.
  • the processing circuit is configured with dedicated hardware
  • the processing circuit 93 shown in FIG. 18 includes, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), An FPGA (Field Programmable Gate Array) or a combination of these is applicable.
  • Each function of the wireless communication apparatus 1 may be realized by the processing circuit 93 for each function, or each function may be realized by the processing circuit 93 collectively.
  • the data modulation unit 31 is a modulator.
  • the multiplexing unit 33 is a multiplexing circuit.
  • the up converter 34 is a frequency conversion circuit.
  • the amplifier 35 is an amplifier circuit.
  • the chirp signal generation unit 32 is realized by a processing circuit.
  • the processing circuit of the chirp signal generation unit 32 may have the configuration shown in FIG. 7 or the configuration shown in FIGS. 17 and 18.
  • each function of the wireless communication device 1 may be realized by dedicated hardware, and a part may be realized by software or firmware.
  • the processing circuit can realize the above-described functions by dedicated hardware, software, firmware, or a combination thereof.
  • radio communication apparatus 1 repeatedly generates uplink chirp signals and downlink chirp signals alternately, and multiplexes the uplink chirp signal or downlink chirp signal and the data signal.
  • the wireless communication device 2 receives the multiplexed signal and detects the frequency deviation of the frequency used in the wireless communication devices 1 and 2 using the upstream chirp signal and the downstream chirp signal separated from the multiplexed signal.
  • the wireless communication apparatus 2 is the result of the delay detection in which the delay time changes linearly for each frequency at the output stage from the cyclic adder 66 of the frequency deviation detector 54. Therefore, it is possible to accurately detect the frequency deviation without affecting the peak detection by the peak detector 68, that is, the detection of the frequency deviation.
  • the wireless communication device 1 transmits a signal that can be detected by the wireless communication device 2 on the receiving side while including the data signal. Thereby, it is not necessary for the wireless communication apparatuses 1 and 2 to add a circuit for transmitting and receiving another signal for detecting a frequency deviation.
  • the configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

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Abstract

A wireless communication device (1) is provided with: a transmitter (11) that alternately and repeatedly generates an up-chirp signal that sweeps from low frequency to high frequency and a down-chirp signal that sweeps from high frequency to low frequency, and transmits a multiple signal obtained by multiplexing the up-chirp signal or the down-chirp signal and a data signal; and a frequency synthesizer (14) that generates a frequency signal used when the multiple signal is up-converted.

Description

無線通信装置、送信方法および受信方法Wireless communication apparatus, transmission method, and reception method
　本発明は、ランダムアクセスプリアンブルにＺＣ（Zadoff－Chu）系列を使用した信号の無線通信を行う無線通信装置、送信方法および受信方法に関する。 The present invention relates to a radio communication apparatus, a transmission method, and a reception method that perform radio communication of signals using a ZC (Zadoff-Chu) sequence for a random access preamble.
　３ＧＰＰ（3rd　Generation　Partnership　Project）において標準化が行われているＬＴＥ（Long　Term　Evolution）の仕様では、上りランダムアクセスプリアンブルすなわちランダムアクセスチャネルのプリアンブルに、時間軸上で定義されるＺＣ系列を使用することが規定されている（非特許文献１）。 In the LTE (Long Term Evolution) specification standardized in 3GPP (3rd Generation Partnership Project), the ZC sequence defined on the time axis may be used for the uplink random access preamble, that is, the preamble of the random access channel. (Non-Patent Document 1).
　ＺＣ系列とは、周波数を掃引するチャープ信号を時間周波数軸上で離散化したチャープ信号の一種である。ＺＣ系列は、定包絡線、かつタイミングのずれた自己相関が０になるＣＡＺＡＣ（Constant　Amplitude　Zero　Auto－Correlation）系列である。ＺＣ系列は、振幅変動が少ないことから送信アンプの効率を改善でき、自己相関が０であることから優れた時間軸上の直交性を有する。この性質からＬＴＥでは、ランダムアクセスプリアンブル、および同期検波の基準信号となるリファレンスシグナルとしてＺＣ系列が使われている。特許文献１には、ＺＣ系列のタイミングを検出する技術が開示されている。 A ZC sequence is a type of chirp signal obtained by discretizing a chirp signal that sweeps the frequency on the time-frequency axis. The ZC sequence is a constant envelope and a CAZAC (Constant Amplitude Zero Auto-Correlation) sequence in which the autocorrelation with a shifted timing is zero. The ZC sequence can improve the efficiency of the transmission amplifier because there is little amplitude fluctuation, and has excellent orthogonality on the time axis because the autocorrelation is zero. Due to this property, in LTE, a ZC sequence is used as a reference signal serving as a reference signal for random access preamble and synchronous detection. Patent Document 1 discloses a technique for detecting the timing of a ZC sequence.
特開２０１１－１８２１２７号公報JP 2011-182127 A
　無線通信装置は、水晶発振器などの基準発振器を備え、この基準発振器を基準にして周波数シンセサイザで無線周波数を発生させている。送信側の無線通信装置は、周波数ミキサを用いて信号の周波数をアップコンバートしてアンテナから送信し、受信側の無線通信装置は、アンテナで受信した信号の周波数を周波数ミキサでダウンコンバートする。ここで、送信側および受信側の無線通信装置が備える各基準発振器の周波数の誤差によって、周波数偏差が発生する。周波数偏差が許容値より大きい場合、無線通信装置間の無線通信が困難となる。そのため、受信側の無線通信装置では、周波数偏差を検出して補正する必要がある。 The wireless communication device includes a reference oscillator such as a crystal oscillator, and generates a radio frequency with a frequency synthesizer based on the reference oscillator. The radio communication device on the transmission side up-converts the frequency of the signal using a frequency mixer and transmits it from the antenna, and the radio communication device on the reception side down-converts the frequency of the signal received by the antenna with the frequency mixer. Here, a frequency deviation occurs due to an error in the frequency of each reference oscillator included in the wireless communication device on the transmission side and the reception side. When the frequency deviation is larger than the allowable value, wireless communication between the wireless communication devices becomes difficult. Therefore, it is necessary to detect and correct the frequency deviation in the radio communication device on the receiving side.
　しかしながら、上記従来の技術によれば、ＺＣ系列の様なチャープ信号をベースとした信号は、周波数偏差とＺＣ系列のタイミングずれとが等化になる性質があり、ＺＣ系列のタイミングがずれた場合、周波数偏差を正確に測定することができない。そのため、送信側の無線通信装置は周波数偏差の検出のために別の信号を送信し、受信側の無線通信装置は別の信号を受信して周波数偏差を検出する必要がある。送信側の無線通信装置では別の信号を送信するための回路を追加し、受信側の無線通信装置では別の信号を受信するための回路を追加しなければならない、という問題があった。 However, according to the above-described conventional technique, a signal based on a chirp signal such as a ZC sequence has the property that the frequency deviation and the timing shift of the ZC sequence are equalized, and the timing of the ZC sequence is shifted. The frequency deviation cannot be measured accurately. Therefore, it is necessary that the transmitting-side wireless communication apparatus transmits another signal for detecting the frequency deviation, and the receiving-side wireless communication apparatus receives another signal to detect the frequency deviation. There is a problem that a circuit for transmitting another signal must be added in the wireless communication apparatus on the transmission side, and a circuit for receiving another signal must be added in the wireless communication apparatus on the reception side.
　本発明は、上記に鑑みてなされたものであって、周波数偏差を検出するための別の信号を送信することなく、データ信号を含みつつ受信側で周波数偏差を検出可能な信号を送信する無線通信装置を得ることを目的とする。 The present invention has been made in view of the above, and wirelessly transmits a signal capable of detecting a frequency deviation on the receiving side while including a data signal without transmitting another signal for detecting the frequency deviation. An object is to obtain a communication device.
　上述した課題を解決し、目的を達成するために、本発明の無線通信装置は、周波数を低い方から高い方へ掃引する上りチャープ信号および周波数を高い方から低い方へ掃引する下りチャープ信号を交互に繰り返し生成し、上りチャープ信号または下りチャープ信号と、データ信号とを多重した多重信号を送信する送信器と、多重信号のアップコンバートの際に使用される周波数信号を生成する発振回路と、を備えることを特徴とする。 In order to solve the above-described problems and achieve the object, the wireless communication apparatus of the present invention includes an upstream chirp signal that sweeps the frequency from the lower side to the higher side and a downstream chirp signal that sweeps the frequency from the higher side to the lower side. A transmitter that repeatedly generates alternately and transmits a multiplexed signal obtained by multiplexing an uplink chirp signal or a downlink chirp signal and a data signal, and an oscillation circuit that generates a frequency signal used when up-converting the multiplexed signal; It is characterized by providing.
　本発明にかかる無線通信装置は、周波数偏差を検出するための別の信号を送信することなく、データ信号を含みつつ受信側で周波数偏差を検出可能な信号を送信することができる、という効果を奏する。 The wireless communication device according to the present invention can transmit a signal that includes a data signal and can detect a frequency deviation on the receiving side without transmitting another signal for detecting the frequency deviation. Play.
無線通信システムの構成例を示す図The figure which shows the structural example of a radio | wireless communications system 無線通信装置の送信器の構成例を示すブロック図Block diagram showing a configuration example of a transmitter of a wireless communication device 無線通信装置のチャープ信号生成部が生成する上りチャープ信号の時間周波数波形の例を示す図The figure which shows the example of the time frequency waveform of the upstream chirp signal which the chirp signal generation part of a radio | wireless communication apparatus produces | generates 無線通信装置のチャープ信号生成部が生成する下りチャープ信号の時間周波数波形の例を示す図The figure which shows the example of the time frequency waveform of the downlink chirp signal which the chirp signal generation part of a radio | wireless communication apparatus produces | generates 無線通信装置のチャープ信号生成部が生成する上りチャープ信号のＩＱ波形の例を示す図The figure which shows the example of IQ waveform of the uplink chirp signal which the chirp signal generation part of a radio | wireless communication apparatus produces | generates 無線通信装置のチャープ信号生成部が生成する下りチャープ信号のＩＱ波形の例を示す図The figure which shows the example of IQ waveform of the downlink chirp signal which the chirp signal generation part of a radio | wireless communication apparatus produces | generates 無線通信装置のチャープ信号生成部の構成例を示すブロック図Block diagram showing a configuration example of a chirp signal generation unit of a wireless communication device 無線通信装置のメモリに記憶されている上りチャープ信号および下りチャープ信号のメモリマップの一例を示す図The figure which shows an example of the memory map of the upstream chirp signal and the downstream chirp signal which are memorize | stored in the memory of a radio | wireless communication apparatus 無線通信装置が無線信号を送信する動作を示すフローチャートThe flowchart which shows the operation | movement which a radio | wireless communication apparatus transmits a radio signal. 無線通信装置の受信器の構成例を示すブロック図Block diagram showing a configuration example of a receiver of a wireless communication device 無線通信装置の周波数偏差検出部の構成例を示すブロック図Block diagram showing a configuration example of a frequency deviation detection unit of a wireless communication device 無線通信装置の周波数偏差検出部内でのシグナルフローを示す図The figure which shows the signal flow in the frequency deviation detection part of a radio | wireless communication apparatus 無線通信装置の遅延検波部の構成例を示すブロック図Block diagram showing a configuration example of a delay detection unit of a wireless communication device 無線通信装置の巡回加算部の構成例を示すブロック図A block diagram showing a configuration example of a cyclic addition unit of a wireless communication device 無線通信装置が無線信号を受信する動作を示すフローチャートThe flowchart which shows the operation | movement which a radio | wireless communication apparatus receives a radio signal. 無線通信装置の周波数偏差検出部が周波数偏差を検出する動作を示すフローチャートThe flowchart which shows the operation | movement which the frequency deviation detection part of a radio | wireless communication apparatus detects a frequency deviation. 無線通信装置の処理回路をプロセッサおよびメモリで構成する場合の例を示す図The figure which shows the example in the case of comprising the processing circuit of a radio | wireless communication apparatus with a processor and memory 無線通信装置の処置回路を専用のハードウェアで構成する場合の例を示す図The figure which shows the example in the case of comprising the treatment circuit of a radio | wireless communication apparatus with exclusive hardware
　以下に、本発明の実施の形態にかかる無線通信装置、送信方法および受信方法を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。 Hereinafter, a wireless communication apparatus, a transmission method, and a reception method according to an embodiment of the present invention will be described in detail based on the drawings. Note that the present invention is not limited to the embodiments.
実施の形態．
　図１は、本発明の実施の形態にかかる無線通信システム１００の構成例を示す図である。無線通信システム１００は無線通信装置１，２を備える。無線通信装置１，２は、無線信号を送受信可能な装置である。無線通信システム１００では、無線通信装置１と無線通信装置２との間で無線信号を送受信する。 Embodiment.
FIG. 1 is a diagram illustrating a configuration example of a radio communication system 100 according to an embodiment of the present invention. The wireless communication system 100 includes wireless communication devices 1 and 2. The wireless communication devices 1 and 2 are devices that can transmit and receive wireless signals. In the wireless communication system 100, wireless signals are transmitted and received between the wireless communication device 1 and the wireless communication device 2.
　無線通信装置１は、送信器１１と、受信器１２と、基準発信器１３と、周波数シンセサイザ１４と、共用器１５と、アンテナ１６と、を備える。送信器１１は、送信されるデータ信号である送信データを変調し、変調後の送信データとチャープ信号とを多重した多重信号すなわち無線信号を生成する。受信器１２は、受信した多重信号すなわち無線信号をチャープ信号およびデータ信号に分離し、データ信号を復調し、復調されたデータ信号である受信データを出力する。 The wireless communication apparatus 1 includes a transmitter 11, a receiver 12, a reference transmitter 13, a frequency synthesizer 14, a duplexer 15, and an antenna 16. The transmitter 11 modulates transmission data, which is a data signal to be transmitted, and generates a multiplexed signal, that is, a radio signal, obtained by multiplexing the modulated transmission data and a chirp signal. The receiver 12 separates the received multiplexed signal, that is, a radio signal into a chirp signal and a data signal, demodulates the data signal, and outputs received data that is the demodulated data signal.
　基準発信器１３は、無線通信装置１で使用される基準信号を生成する。周波数シンセサイザ１４は、基準発信器１３で生成された基準信号を用いて、送信器１１で送信する無線信号のアップコンバートの際に使用される周波数信号、および受信器１２で受信した無線信号のダウンコンバートの際に使用される周波数信号を生成する発振回路である。 The reference transmitter 13 generates a reference signal used in the wireless communication device 1. The frequency synthesizer 14 uses the reference signal generated by the reference transmitter 13 to reduce the frequency signal used when up-converting the radio signal transmitted by the transmitter 11 and the radio signal received by the receiver 12. This is an oscillation circuit that generates a frequency signal used for conversion.
　共用器１５は、送信器１１で生成された無線信号をアンテナ１６へ出力し、アンテナ１６で受信された無線信号を受信器１２へ出力する。アンテナ１６は、共用器１５を介して送信器１１で生成された無線信号を取得し、無線通信装置２へ送信する。また、アンテナ１６は、無線通信装置２から送信された無線信号を受信し、共用器１５を介して受信器１２へ出力する。 The duplexer 15 outputs the radio signal generated by the transmitter 11 to the antenna 16 and outputs the radio signal received by the antenna 16 to the receiver 12. The antenna 16 acquires the radio signal generated by the transmitter 11 via the duplexer 15 and transmits it to the radio communication device 2. The antenna 16 receives a radio signal transmitted from the radio communication device 2 and outputs it to the receiver 12 via the duplexer 15.
　無線通信装置２は、送信器２１と、受信器２２と、基準発信器２３と、周波数シンセサイザ２４と、共用器２５と、アンテナ２６と、を備える。無線通信装置２の送信器２１、受信器２２、基準発信器２３、周波数シンセサイザ２４、共用器２５、およびアンテナ２６は、各々、無線通信装置１の送信器１１、受信器１２、基準発信器１３、周波数シンセサイザ１４、共用器１５、およびアンテナ１６と同様のため、詳細な説明については省略する。 The wireless communication apparatus 2 includes a transmitter 21, a receiver 22, a reference transmitter 23, a frequency synthesizer 24, a duplexer 25, and an antenna 26. The transmitter 21, the receiver 22, the reference transmitter 23, the frequency synthesizer 24, the duplexer 25, and the antenna 26 of the wireless communication device 2 are respectively the transmitter 11, the receiver 12, and the reference transmitter 13 of the wireless communication device 1. Since it is similar to the frequency synthesizer 14, the duplexer 15, and the antenna 16, detailed description thereof is omitted.
　無線通信システム１００において、具体的に、無線通信装置１から送信データを変調して無線信号を送信し、無線通信装置２が無線信号を受信して受信データを出力する場合、すなわち無線通信装置１を送信装置とし、無線通信装置２を受信装置とした場合の無線通信装置１，２の動作について説明する。 In the wireless communication system 100, specifically, when transmission data is modulated from the wireless communication apparatus 1 and a wireless signal is transmitted, and the wireless communication apparatus 2 receives the wireless signal and outputs reception data, that is, the wireless communication apparatus 1 The operation of the wireless communication devices 1 and 2 when the wireless communication device 2 is the receiving device and the wireless communication device 2 is the receiving device will be described.
　まず、無線信号を送信する無線通信装置１の送信器１１の構成について説明する。図２は、本実施の形態にかかる無線通信装置１の送信器１１の構成例を示すブロック図である。送信器１１は、データ変調部３１と、チャープ信号生成部３２と、多重部３３と、アップコンバータ３４と、増幅器３５と、を備える。 First, the configuration of the transmitter 11 of the wireless communication device 1 that transmits a wireless signal will be described. FIG. 2 is a block diagram illustrating a configuration example of the transmitter 11 of the wireless communication device 1 according to the present embodiment. The transmitter 11 includes a data modulation unit 31, a chirp signal generation unit 32, a multiplexing unit 33, an up-converter 34, and an amplifier 35.
　データ変調部３１は、送信データに対して、ＱＰＳＫ（Quadrature　Phase　Shift　Keying）、１６ＱＡＭ（Quadrature　Amplitude　Modulation）、６４ＱＡＭなどの変調方式による変調を施す。変調方式については、これらに限定されるものではない。チャープ信号生成部３２は、チャープ信号を生成する。チャープ信号生成部３２の構成、およびチャープ信号生成部３２で生成されるチャープ信号の詳細については後述する。多重部３３は、データ変調部３１で変調されたデータ信号と、チャープ信号生成部３２で生成されたチャープ信号とを多重する。多重部３３における信号の多重方式については、時分割多重、周波数分割多重、両方の多重方式を用いる方法などがあるが、これらに限定されるものではない。 The data modulator 31 modulates the transmission data by a modulation scheme such as QPSK (Quadrature Phase Shift Keying), 16QAM (Quadrature Amplitude Modulation), 64QAM. The modulation method is not limited to these. The chirp signal generation unit 32 generates a chirp signal. The configuration of the chirp signal generation unit 32 and the details of the chirp signal generated by the chirp signal generation unit 32 will be described later. The multiplexing unit 33 multiplexes the data signal modulated by the data modulation unit 31 and the chirp signal generated by the chirp signal generation unit 32. The signal multiplexing method in the multiplexing unit 33 includes time division multiplexing, frequency division multiplexing, a method using both multiplexing methods, and the like, but is not limited thereto.
　アップコンバータ３４は、周波数ミキサを用いて、多重部３３で多重された多重信号と、周波数シンセサイザ１４から出力された周波数信号とをミキシングして、多重信号の周波数を無線周波数にアップコンバートする。増幅器３５は、アップコンバータ３４から出力されたアップコンバート後の信号を規定された送信電力に増幅し、共用器１５を介してアンテナ１６へ出力する。送信器１１は、共用器１５およびアンテナ１６経由で、多重信号すなわち無線信号を無線通信装置２へ送信する。 The up-converter 34 mixes the multiplexed signal multiplexed by the multiplexing unit 33 and the frequency signal output from the frequency synthesizer 14 using a frequency mixer, and up-converts the frequency of the multiplexed signal to a radio frequency. The amplifier 35 amplifies the upconverted signal output from the upconverter 34 to a prescribed transmission power, and outputs the amplified signal to the antenna 16 via the duplexer 15. The transmitter 11 transmits a multiplexed signal, that is, a radio signal to the radio communication device 2 via the duplexer 15 and the antenna 16.
　ここで、チャープ信号生成部３２が生成するチャープ信号について説明する。本実施の形態において、チャープ信号生成部３２は、周波数を低い方から高い方へ掃引する上りチャープ信号、および周波数を高い方から低い方へ掃引する下りチャープ信号の２種のチャープ信号を交互に繰り返し生成する。図３は、本実施の形態にかかる無線通信装置１のチャープ信号生成部３２が生成する上りチャープ信号の時間周波数波形の例を示す図である。また、図４は、本実施の形態にかかる無線通信装置１のチャープ信号生成部３２が生成する下りチャープ信号の時間周波数波形の例を示す図である。横軸は時間を示し、縦軸は周波数を示す。上りチャープ信号は時間とともに周波数が増加する信号であり、下りチャープ信号は時間とともに周波数が減少する信号であると表現することもできる。 Here, the chirp signal generated by the chirp signal generation unit 32 will be described. In the present embodiment, the chirp signal generator 32 alternately performs two types of chirp signals, an upstream chirp signal that sweeps the frequency from the lower side to the higher side, and a downstream chirp signal that sweeps the frequency from the higher side to the lower side. Generate repeatedly. FIG. 3 is a diagram illustrating an example of a time-frequency waveform of the uplink chirp signal generated by the chirp signal generation unit 32 of the wireless communication apparatus 1 according to the present embodiment. Moreover, FIG. 4 is a figure which shows the example of the time frequency waveform of the downlink chirp signal which the chirp signal generation part 32 of the radio | wireless communication apparatus 1 concerning this Embodiment produces | generates. The horizontal axis indicates time, and the vertical axis indicates frequency. The upstream chirp signal can be expressed as a signal whose frequency increases with time, and the downstream chirp signal can be expressed as a signal whose frequency decreases with time.
　これらのチャープ信号の時間波形は複素数で表すことができ、実数軸をＩ、虚数軸をＱとすると、図５および図６のように表すことができる。図５は、本実施の形態にかかる無線通信装置１のチャープ信号生成部３２が生成する上りチャープ信号のＩＱ波形の例を示す図である。また、図６は、本実施の形態にかかる無線通信装置１のチャープ信号生成部３２が生成する下りチャープ信号のＩＱ波形の例を示す図である。横軸は周波数帯を示し、縦軸は振幅を示す。上りチャープ信号と下りチャープ信号とは、周波数軸を反転させた信号であるため複素共役の関係にある。このため、Ｉ波形は上りチャープ信号と下りチャープ信号とで同じであり、Ｑ信号は上りチャープ信号と下りチャープ信号とで正負が反転している。 The time waveforms of these chirp signals can be represented by complex numbers, and can be represented as shown in FIGS. 5 and 6, where I is the real axis and Q is the imaginary axis. FIG. 5 is a diagram illustrating an example of an IQ waveform of the uplink chirp signal generated by the chirp signal generation unit 32 of the wireless communication apparatus 1 according to the present embodiment. Moreover, FIG. 6 is a figure which shows the example of IQ waveform of the downlink chirp signal which the chirp signal generation part 32 of the radio | wireless communication apparatus 1 concerning this Embodiment produces | generates. The horizontal axis indicates the frequency band, and the vertical axis indicates the amplitude. The upstream chirp signal and the downstream chirp signal have a complex conjugate relationship because they are signals with the frequency axis inverted. For this reason, the I waveform is the same between the upstream chirp signal and the downstream chirp signal, and the Q signal is inverted between the upstream chirp signal and the downstream chirp signal.
　チャープ信号生成部３２は、図３に示す上りチャープ信号および図４に示す下りチャープ信号を交互に繰り返し生成する。なお、チャープ信号生成部３２は、帯域外への不要輻射を避けるため、上りチャープ信号および下りチャープ信号の初め部分と終わり部分には、図５および図６に示すようにランプアップおよびランプダウンを付加する。 The chirp signal generation unit 32 repeatedly generates the upstream chirp signal shown in FIG. 3 and the downstream chirp signal shown in FIG. 4 alternately. The chirp signal generation unit 32 performs ramp-up and ramp-down as shown in FIGS. 5 and 6 at the beginning and end of the upstream chirp signal and the downstream chirp signal in order to avoid unnecessary radiation outside the band. Append.
　図７は、本実施の形態にかかる無線通信装置１のチャープ信号生成部３２の構成例を示すブロック図である。チャープ信号生成部３２は、メモリ４１と、カウンタ４２と、読み出し部４３と、を備える。メモリ４１は、上りチャープ信号および下りチャープ信号を記憶している。カウンタ４２は、メモリ４１のメモリアドレスを生成する。読み出し部４３は、メモリ４１から上りチャープ信号および下りチャープ信号を交互に繰り返し読み出して出力する。図８は、本実施の形態にかかる無線通信装置１のメモリ４１に記憶されている上りチャープ信号および下りチャープ信号のメモリマップの一例を示す図である。ここでは、上りチャープ信号および下りチャープ信号に対してｎ個のメモリアドレスを割り当てている。ｎは２以上の整数である。メモリ４１において、メモリマップでの上りチャープ信号部分には、図５に示すＩＱ波形のデータが記憶されており、メモリマップでの下りチャープ信号部分には、図６に示すＩＱ波形のデータが記憶されている。 FIG. 7 is a block diagram illustrating a configuration example of the chirp signal generation unit 32 of the wireless communication device 1 according to the present embodiment. The chirp signal generation unit 32 includes a memory 41, a counter 42, and a reading unit 43. The memory 41 stores an upstream chirp signal and a downstream chirp signal. The counter 42 generates a memory address of the memory 41. The reading unit 43 alternately reads and outputs the upstream chirp signal and the downstream chirp signal from the memory 41. FIG. 8 is a diagram illustrating an example of a memory map of the uplink chirp signal and the downlink chirp signal stored in the memory 41 of the wireless communication apparatus 1 according to the present embodiment. Here, n memory addresses are assigned to the upstream chirp signal and the downstream chirp signal. n is an integer of 2 or more. In the memory 41, IQ waveform data shown in FIG. 5 is stored in the upstream chirp signal portion in the memory map, and IQ waveform data shown in FIG. 6 is stored in the downstream chirp signal portion in the memory map. Has been.
　このように、チャープ信号生成部３２は、上りチャープ信号および下りチャープ信号を交互に繰り返し生成する。そのため、多重部３３は、上りチャープ信号または下りチャープ信号と、データ変調部３１で変調されたデータ信号とを多重する。具体的に、多重部３３は、上りチャープ信号とデータ信号とを多重すると、つぎは下りチャープ信号とデータ信号とを多重することになり、この動作を繰り返し行う。以降の説明において、上りチャープ信号および下りチャープ信号の総称として、チャープ信号と称することがある。 In this way, the chirp signal generation unit 32 repeatedly generates an uplink chirp signal and a downlink chirp signal alternately. Therefore, the multiplexing unit 33 multiplexes the uplink chirp signal or the downlink chirp signal and the data signal modulated by the data modulation unit 31. Specifically, after multiplexing the upstream chirp signal and the data signal, the multiplexing unit 33 multiplexes the downstream chirp signal and the data signal, and repeats this operation. In the following description, the upstream chirp signal and the downstream chirp signal may be collectively referred to as a chirp signal.
　図９は、本実施の形態にかかる無線通信装置１が無線信号を送信する動作を示すフローチャートである。無線通信装置１において、送信器１１のデータ変調部３１は、送信データを変調する（ステップＳ１）。チャープ信号生成部３２は、上りチャープ信号および下りチャープ信号を交互に繰り返し生成する（ステップＳ２）。多重部３３は、チャープ信号生成部３２で生成された上りチャープ信号または下りチャープ信号と、データ変調部３１で変調されたデータ信号とを多重する（ステップＳ３）。アップコンバータ３４は、多重信号の周波数を無線周波数にアップコンバートする（ステップＳ４）。増幅器３５は、アップコンバート後の信号の電力を増幅する（ステップＳ５）。送信器１１は、共用器１５およびアンテナ１６経由で、無線信号を無線通信装置２へ送信する（ステップＳ６）。このように、送信器１１は、上りチャープ信号および下りチャープ信号を交互に繰り返し生成し、上りチャープ信号または下りチャープ信号と、データ信号とを多重した無線信号を送信する。 FIG. 9 is a flowchart showing an operation in which the wireless communication apparatus 1 according to the present embodiment transmits a wireless signal. In the wireless communication device 1, the data modulation unit 31 of the transmitter 11 modulates transmission data (step S1). The chirp signal generation unit 32 repeatedly generates an uplink chirp signal and a downlink chirp signal alternately (step S2). The multiplexing unit 33 multiplexes the uplink chirp signal or the downlink chirp signal generated by the chirp signal generation unit 32 and the data signal modulated by the data modulation unit 31 (step S3). The up-converter 34 up-converts the frequency of the multiplexed signal to a radio frequency (step S4). The amplifier 35 amplifies the power of the signal after the up-conversion (Step S5). The transmitter 11 transmits a radio signal to the radio communication device 2 via the duplexer 15 and the antenna 16 (step S6). In this way, the transmitter 11 repeatedly generates an uplink chirp signal and a downlink chirp signal alternately, and transmits a radio signal obtained by multiplexing the uplink chirp signal or the downlink chirp signal and the data signal.
　つぎに、無線通信装置１から送信された無線信号を受信する無線通信装置２の受信器２２の構成について説明する。図１０は、本実施の形態にかかる無線通信装置２の受信器２２の構成例を示すブロック図である。受信器２２は、増幅器５１と、ダウンコンバータ５２と、分離部５３と、周波数偏差検出部５４と、データ復調部５５と、を備える。 Next, the configuration of the receiver 22 of the wireless communication device 2 that receives the wireless signal transmitted from the wireless communication device 1 will be described. FIG. 10 is a block diagram illustrating a configuration example of the receiver 22 of the wireless communication device 2 according to the present embodiment. The receiver 22 includes an amplifier 51, a down converter 52, a separation unit 53, a frequency deviation detection unit 54, and a data demodulation unit 55.
　増幅器５１は、共用器２５およびアンテナ２６を介して受信された多重信号すなわち無線信号を規定された電力に増幅する。ダウンコンバータ５２は、周波数ミキサを用いて、増幅器５１から出力された無線信号と、周波数シンセサイザ２４から出力された周波数信号とをミキシングして、無線信号の周波数をベースバンド信号の周波数にダウンコンバートする。分離部５３は、受信器２２で受信した多重信号を、チャープ信号およびデータ信号に分離する。多重信号は、詳細には、ダウンコンバータ５２から出力されたベースバンド信号であって、時分割多重、周波数分割多重、または両方の多重方式が用いられた信号である。分離部５３は、チャープ信号を周波数偏差検出部５４に出力し、データ信号をデータ復調部５５に出力する。 The amplifier 51 amplifies the multiplex signal received through the duplexer 25 and the antenna 26, that is, a radio signal, to a prescribed power. The down converter 52 uses a frequency mixer to mix the radio signal output from the amplifier 51 and the frequency signal output from the frequency synthesizer 24, and down-converts the frequency of the radio signal to the frequency of the baseband signal. . The separation unit 53 separates the multiplexed signal received by the receiver 22 into a chirp signal and a data signal. Specifically, the multiplexed signal is a baseband signal output from the down converter 52, and is a signal using time division multiplexing, frequency division multiplexing, or both multiplexing methods. The separation unit 53 outputs the chirp signal to the frequency deviation detection unit 54 and outputs the data signal to the data demodulation unit 55.
　周波数偏差検出部５４は、分離部５３で分離されたチャープ信号を用いて、無線通信装置２および無線通信装置１で使用されている周波数の周波数偏差を検出する。周波数偏差検出部５４は、検出した周波数偏差をデータ復調部５５に出力する。周波数偏差検出部５４の詳細な構成および動作については後述する。データ復調部５５は、周波数偏差検出部５４で検出された周波数偏差を用いてデータ信号の周波数偏差を補正し、分離部５３で分離されたデータ信号に対してＱＰＳＫ、１６ＱＡＭ、６４ＱＡＭなどの復調を行って受信データを出力する。 The frequency deviation detector 54 detects the frequency deviation of the frequency used in the wireless communication device 2 and the wireless communication device 1 using the chirp signal separated by the separation unit 53. The frequency deviation detector 54 outputs the detected frequency deviation to the data demodulator 55. The detailed configuration and operation of the frequency deviation detector 54 will be described later. The data demodulator 55 corrects the frequency deviation of the data signal using the frequency deviation detected by the frequency deviation detector 54, and demodulates the data signal separated by the separator 53, such as QPSK, 16QAM, 64QAM. Go and output the received data.
　図１１は、本実施の形態にかかる無線通信装置２の周波数偏差検出部５４の構成例を示すブロック図である。周波数偏差検出部５４は、ＦＦＴ（Fast　Fourier　Transform）６１と、メモリ６２と、複素乗算部６３と、遅延検波部６４と、周波数軸反転部６５と、巡回加算部６６と、ＦＦＴ６７と、ピーク検出部６８と、を備える。 FIG. 11 is a block diagram illustrating a configuration example of the frequency deviation detection unit 54 of the wireless communication device 2 according to the present embodiment. The frequency deviation detection unit 54 includes an FFT (Fast Fourier Transform) 61, a memory 62, a complex multiplication unit 63, a delay detection unit 64, a frequency axis inversion unit 65, a cyclic addition unit 66, an FFT 67, and a peak detection. Unit 68.
　ＦＦＴ６１は、分離部５３から出力されたチャープ信号に対して、無線通信装置１から複数回送信されるチャープ信号毎にＮポイントのＦＦＴすなわち高速フーリエ変換を行い、チャープ信号を時間軸上の信号から周波数軸上のＮ個の信号に変換する。ＮはＦＦＴの際のサンプリング周波数によって決定される値である。すなわち、ＦＦＴ６１は、上りチャープ信号および下りチャープ信号を時間軸上の信号から周波数軸上の信号に変換する。ＦＦＴ６１は、第１の変換部である。 The FFT 61 performs N-point FFT, that is, fast Fourier transform, for each chirp signal transmitted from the wireless communication device 1 a plurality of times on the chirp signal output from the separation unit 53, and converts the chirp signal from the signal on the time axis. Convert to N signals on the frequency axis. N is a value determined by the sampling frequency at the time of FFT. That is, the FFT 61 converts the upstream chirp signal and the downstream chirp signal from a signal on the time axis to a signal on the frequency axis. The FFT 61 is a first conversion unit.
　メモリ６２は、無線通信装置１からの送信波形であるチャープ信号を周波数軸上の信号に変換したデータの複素共役を記憶している。 The memory 62 stores a complex conjugate of data obtained by converting a chirp signal, which is a transmission waveform from the wireless communication device 1, into a signal on the frequency axis.
　複素乗算部６３は、ＦＦＴ６１からの出力と、メモリ６２に記憶されている複素共役とを周波数毎に複素乗算し、周波数軸上のチャネル推定値をチャープ信号毎に算出する。図１２は、本実施の形態にかかる無線通信装置２の周波数偏差検出部５４内でのシグナルフローを示す図である。図１２（ａ）で示される信号波形が、複素乗算部６３で得られたチャネル推定値である。 The complex multiplier 63 complex-multiplies the output from the FFT 61 and the complex conjugate stored in the memory 62 for each frequency, and calculates a channel estimation value on the frequency axis for each chirp signal. FIG. 12 is a diagram illustrating a signal flow in the frequency deviation detection unit 54 of the wireless communication device 2 according to the present embodiment. The signal waveform shown in FIG. 12A is the channel estimation value obtained by the complex multiplier 63.
　遅延検波部６４は、複素乗算部６３から出力されたチャネル推定値をチャープ信号毎に遅延検波して、周波数毎の遅延検波結果を得る。すなわち、遅延検波部６４は、連続する上りチャープ信号と下りチャープ信号との間で周波数毎の遅延検波を行う。図１２（ｂ）に示すように、チャネル推定値に対する遅延検波結果は、周波数毎に遅延時間の異なる遅延検波結果となる。図１３は、本実施の形態にかかる無線通信装置２の遅延検波部６４の構成例を示すブロック図である。遅延検波部６４は、遅延部７１と、複素共役部７２と、複素乗算部７３と、を備える。遅延部７１は、複素乗算部６３からの出力であるチャネル推定値を、Ｎ個の周波数軸のデータ単位に遅延させる。複素共役部７２は、遅延部７１で遅延されたデータを複素共役に変換する。複素乗算部７３は、複素共役部７２からの出力である遅延した基準信号と、複素乗算部６３からの出力である遅延していないチャネル推定値との複素乗算を周波数毎に行う。 The delay detection unit 64 delay-detects the channel estimation value output from the complex multiplication unit 63 for each chirp signal, and obtains a delay detection result for each frequency. That is, the delay detection unit 64 performs delay detection for each frequency between successive upstream chirp signals and downstream chirp signals. As shown in FIG. 12B, the delay detection result for the channel estimation value is a delay detection result having a different delay time for each frequency. FIG. 13 is a block diagram illustrating a configuration example of the delay detection unit 64 of the wireless communication apparatus 2 according to the present embodiment. The delay detection unit 64 includes a delay unit 71, a complex conjugate unit 72, and a complex multiplication unit 73. The delay unit 71 delays the channel estimation value, which is the output from the complex multiplication unit 63, in N frequency axis data units. The complex conjugate unit 72 converts the data delayed by the delay unit 71 into a complex conjugate. The complex multiplier 73 performs complex multiplication of the delayed reference signal output from the complex conjugate unit 72 and the non-delayed channel estimation value output from the complex multiplier 63 for each frequency.
　周波数軸反転部６５は、遅延検波部６４から出力された遅延検波結果のうち、一方のチャープ信号に対する遅延検波結果、すなわち上りチャープ信号または下りチャープ信号の一方を基準にしたときの遅延検波結果に対して、周波数毎の信号の並び順を逆順とするため周波数軸を反転させる。図１２（ｂ）に示すように、上りチャープ信号に対して下りチャープ信号を基準に遅延検波した場合と、下りチャープ信号に対して上りチャープ信号を基準に遅延検波した場合とでは、周波数毎の遅延時間の傾向が異なる。この場合、巡回加算部６６でそのまま遅延検波結果を巡回加算しても、ＳＮＲ（Signal　to　Noise　Ratio）を改善させる効果は得られない。そのため、周波数軸反転部６５は、図１２（ｃ）の例では、周波数毎の遅延時間の傾向を揃えるため、下りチャープ信号を基準に遅延検波した場合は遅延検波結果の周波数毎の信号の並び順を逆順とし周波数軸を反転させる。 The frequency axis inversion unit 65 converts the delay detection result for one of the chirp signals out of the delay detection results output from the delay detection unit 64, that is, the delay detection result when one of the upstream chirp signal and the downstream chirp signal is used as a reference. On the other hand, the frequency axis is inverted in order to reverse the order of arrangement of signals for each frequency. As shown in FIG. 12 (b), in the case of delay detection with respect to the upstream chirp signal based on the downstream chirp signal and the case of delay detection with respect to the downstream chirp signal based on the upstream chirp signal, The delay time trend is different. In this case, even if the cyclic detection unit 66 cyclically adds the delay detection results as they are, the effect of improving the SNR (Signal to Noise Ratio) cannot be obtained. Therefore, in the example of FIG. 12C, the frequency axis inversion unit 65 aligns the tendency of the delay time for each frequency. Therefore, when delay detection is performed based on the downstream chirp signal, the frequency axis inversion unit 65 arranges the signals for each frequency of the delay detection result. The order is reversed and the frequency axis is reversed.
　巡回加算部６６は、周波数軸反転部６５から出力された遅延検波結果は周波数毎の遅延時間が揃っているため、遅延検波結果を周波数毎に巡回加算してＳＮＲを改善する。具体的に、巡回加算部６６は、遅延検波部６４から出力された遅延検波結果のうち周波数軸反転部６５で周波数軸が反転されていない遅延検波結果、および周波数軸反転部６５で周波数軸が反転された遅延検波結果を巡回加算する。図１２（ｄ）が巡回加算後の信号を示している。巡回加算部６６は、異なる周波数の遅延検波結果を巡回加算することによって、無線伝送路がフェージング環境にある場合においても、周波数ダイバーシチ効果によってＳＮＲを改善することができる。図１４は、本実施の形態にかかる無線通信装置２の巡回加算部６６の構成例を示すブロック図である。巡回加算部６６は、複素加算部８１と、メモリ８２と、を備える。複素加算部８１は、メモリ８２に保持されている前回までの巡回加算結果と周波数軸反転部６５から出力された遅延検波結果とを周波数毎に加算、すなわち巡回加算する。複素加算部８１は、加算結果をメモリ８２に記憶し保持させるとともに、メモリ８２を介してＦＦＴ６７に出力する。メモリ８２は、複素加算部８１による加算結果を保持する。 The cyclic adder 66 improves the SNR by cyclically adding the delay detection results for each frequency because the delay detection results output from the frequency axis inversion unit 65 have the same delay time for each frequency. Specifically, the cyclic addition unit 66 includes a delay detection result in which the frequency axis is not inverted by the frequency axis inversion unit 65 among the delay detection results output from the delay detection unit 64, and a frequency axis in the frequency axis inversion unit 65. The inverted delayed detection result is cyclically added. FIG. 12D shows the signal after cyclic addition. The cyclic addition unit 66 can improve the SNR by the frequency diversity effect even when the wireless transmission path is in a fading environment by cyclically adding the delay detection results of different frequencies. FIG. 14 is a block diagram illustrating a configuration example of the cyclic addition unit 66 of the wireless communication apparatus 2 according to the present embodiment. The cyclic addition unit 66 includes a complex addition unit 81 and a memory 82. The complex adder 81 adds the previous cyclic addition result held in the memory 82 and the delayed detection result output from the frequency axis inversion unit 65 for each frequency, that is, cyclic addition. The complex adder 81 stores and holds the addition result in the memory 82 and outputs the result to the FFT 67 via the memory 82. The memory 82 holds the addition result by the complex adder 81.
　巡回加算部６６から出力された巡回加算後の遅延検波結果は、周波数毎に遅延時間が直線的に変化した遅延検波の結果となる。そのため、巡回加算部６６から出力された巡回加算後の遅延検波結果は、周波数偏差がある場合、周波数偏差に比例した傾きで直線的に位相回転した信号となる。ＦＦＴ６７は、巡回加算部６６から出力された巡回加算後の遅延検波結果に対してＦＦＴを行い、時間軸上の信号から周波数軸上の信号に変換する。ＦＦＴ６７は、第２の変換部である。 The delayed detection result after cyclic addition output from the cyclic adder 66 is the result of delayed detection in which the delay time varies linearly for each frequency. For this reason, when there is a frequency deviation, the delayed detection result after cyclic addition output from the cyclic addition unit 66 is a signal that is linearly rotated in phase with a slope proportional to the frequency deviation. The FFT 67 performs FFT on the delayed detection result after cyclic addition output from the cyclic adder 66 and converts the signal on the time axis into the signal on the frequency axis. The FFT 67 is a second conversion unit.
　ピーク検出部６８は、ＦＦＴ６７から出力された信号の振幅が最大となるピークを検出することで、周波数偏差に比例した位相回転量を検出、すなわちピーク検出位置を周波数偏差として検出することができる。図１２（ｅ）はＦＦＴ６７からの出力のうち振幅が最大のものを示している。ピーク検出部６８は、検出した周波数偏差をデータ復調部５５に出力する。 The peak detecting unit 68 can detect the phase rotation amount proportional to the frequency deviation by detecting the peak where the amplitude of the signal output from the FFT 67 is maximized, that is, the peak detection position can be detected as the frequency deviation. FIG. 12E shows the output from the FFT 67 having the maximum amplitude. The peak detector 68 outputs the detected frequency deviation to the data demodulator 55.
　図１５は、本実施の形態にかかる無線通信装置２が無線信号を受信する動作を示すフローチャートである。無線通信装置２において、受信器２２は、アンテナ２６および共用器２５を経由して無線通信装置１から無線信号を受信する（ステップＳ１１）。増幅器５１は、無線信号の電力を増幅する（ステップＳ１２）。ダウンコンバータ５２は、無線信号の周波数をベースバンド信号の周波数にダウンコンバートする（ステップＳ１３）。分離部５３は、ダウンコンバータ５２から出力されたベースバンド信号を、チャープ信号およびデータ信号に分離する（ステップＳ１４）。周波数偏差検出部５４は、分離部５３で分離されたチャープ信号を用いて、周波数偏差を検出する（ステップＳ１５）。データ復調部５５は、周波数偏差検出部５４で検出された周波数偏差を用いて、データ信号を復調する（ステップＳ１６）。このように、受信器２２は、無線通信装置１から送信された無線信号を受信し、受信した無線信号を用いて、無線通信装置１，２で使用されている周波数の周波数偏差を検出する。 FIG. 15 is a flowchart showing an operation in which the wireless communication device 2 according to the present embodiment receives a wireless signal. In the wireless communication device 2, the receiver 22 receives a wireless signal from the wireless communication device 1 via the antenna 26 and the duplexer 25 (step S11). The amplifier 51 amplifies the power of the radio signal (step S12). The down converter 52 down-converts the frequency of the radio signal to the frequency of the baseband signal (step S13). The separation unit 53 separates the baseband signal output from the down converter 52 into a chirp signal and a data signal (step S14). The frequency deviation detection unit 54 detects the frequency deviation using the chirp signal separated by the separation unit 53 (step S15). The data demodulator 55 demodulates the data signal using the frequency deviation detected by the frequency deviation detector 54 (step S16). Thus, the receiver 22 receives the radio signal transmitted from the radio communication device 1 and detects the frequency deviation of the frequency used in the radio communication devices 1 and 2 using the received radio signal.
　周波数偏差検出部５４が周波数偏差を検出する前述のステップＳ１５の詳細な動作について説明する。図１６は、本実施の形態にかかる無線通信装置２の周波数偏差検出部５４が周波数偏差を検出する動作を示すフローチャートである。周波数偏差検出部５４において、ＦＦＴ６１は、分離部５３から出力されたチャープ信号に対してＦＦＴを行い、時間軸上の信号から周波数軸上の信号に変換する（ステップＳ２１）。複素乗算部６３は、周波数軸上のチャネル推定値をチャープ信号毎に算出する（ステップＳ２２）。遅延検波部６４は、上りチャープ信号と下りチャープ信号との間で周波数毎の遅延検波を行う（ステップＳ２３）。周波数軸反転部６５は、上りチャープ信号または下りチャープ信号の一方を基準にしたときの遅延検波結果の周波数軸を反転させる（ステップＳ２４）。巡回加算部６６は、遅延検波部６４および周波数軸反転部６５から出力された遅延検波結果を巡回加算する（ステップＳ２５）。ＦＦＴ６７は、巡回加算部６６から出力された巡回加算後の遅延検波結果に対してＦＦＴを行い、時間軸上の信号から周波数軸上の信号に変換する（ステップＳ２６）。ピーク検出部６８は、ＦＦＴ６７から出力された信号の振幅に基づいて、周波数偏差を検出する（ステップＳ２７）。 The detailed operation of the above-described step S15 in which the frequency deviation detecting unit 54 detects the frequency deviation will be described. FIG. 16 is a flowchart illustrating an operation in which the frequency deviation detection unit 54 of the wireless communication apparatus 2 according to the present embodiment detects a frequency deviation. In the frequency deviation detector 54, the FFT 61 performs FFT on the chirp signal output from the separator 53, and converts the signal on the time axis into the signal on the frequency axis (step S21). The complex multiplier 63 calculates a channel estimation value on the frequency axis for each chirp signal (step S22). The delay detection unit 64 performs delay detection for each frequency between the upstream chirp signal and the downstream chirp signal (step S23). The frequency axis inversion unit 65 inverts the frequency axis of the delay detection result when one of the upstream chirp signal and the downstream chirp signal is used as a reference (step S24). The cyclic addition unit 66 cyclically adds the delay detection results output from the delay detection unit 64 and the frequency axis inversion unit 65 (step S25). The FFT 67 performs FFT on the delayed detection result after cyclic addition output from the cyclic adder 66, and converts the signal on the time axis into the signal on the frequency axis (step S26). The peak detector 68 detects a frequency deviation based on the amplitude of the signal output from the FFT 67 (step S27).
　なお、無線通信装置１が送信データを変調して無線信号を送信し、無線通信装置２が無線信号を受信して受信データを出力する場合について説明したが、無線通信装置２が送信データを変調して無線信号を送信し、無線通信装置１が無線信号を受信して受信データを出力する場合も同様の動作となる。 Although the case where the wireless communication device 1 modulates transmission data and transmits a wireless signal and the wireless communication device 2 receives the wireless signal and outputs reception data has been described, the wireless communication device 2 modulates the transmission data. The same operation is performed when the wireless signal is transmitted and the wireless communication apparatus 1 receives the wireless signal and outputs the received data.
　つづいて、無線通信装置１，２のハードウェア構成について説明する。無線通信装置１，２は同様の構成のため、無線通信装置１を例にして説明する。なお、無線通信装置１の受信器１２の構成は、無線通信装置２の受信器２２の構成と同様とする。無線通信装置１において、基準発信器１３は水晶発振器などの発振器である。周波数シンセサイザ１４は発振回路である。共用器１５はフィルタ回路である。アンテナ１６はアンテナ素子である。受信器１２において、増幅器５１は増幅回路である。ダウンコンバータ５２は周波数変換回路である。分離部５３は分離回路である。データ復調部５５はデモジュレータである。周波数偏差検出部５４は処理回路により実現される。すなわち、無線通信装置１は、自装置および通信相手の無線通信装置２で使用されている周波数の周波数偏差を検出するための処理回路を備える。処理回路は、メモリに格納されるプログラムを実行するプロセッサおよびメモリであってもよいし、専用のハードウェアであってもよい。 Next, the hardware configuration of the wireless communication devices 1 and 2 will be described. Since the wireless communication apparatuses 1 and 2 have the same configuration, the wireless communication apparatus 1 will be described as an example. The configuration of the receiver 12 of the wireless communication device 1 is the same as the configuration of the receiver 22 of the wireless communication device 2. In the wireless communication device 1, the reference transmitter 13 is an oscillator such as a crystal oscillator. The frequency synthesizer 14 is an oscillation circuit. The duplexer 15 is a filter circuit. The antenna 16 is an antenna element. In the receiver 12, the amplifier 51 is an amplifier circuit. The down converter 52 is a frequency conversion circuit. The separation unit 53 is a separation circuit. The data demodulator 55 is a demodulator. The frequency deviation detector 54 is realized by a processing circuit. That is, the wireless communication device 1 includes a processing circuit for detecting a frequency deviation of frequencies used in the wireless communication device 2 of the own device and the communication partner. The processing circuit may be a processor and a memory that execute a program stored in the memory, or may be dedicated hardware.
　図１７は、本実施の形態にかかる無線通信装置１の処理回路をプロセッサおよびメモリで構成する場合の例を示す図である。処理回路がプロセッサ９１およびメモリ９２で構成される場合、無線通信装置１の処理回路の各機能は、ソフトウェア、ファームウェア、またはソフトウェアとファームウェアとの組み合わせにより実現される。ソフトウェアまたはファームウェアはプログラムとして記述され、メモリ９２に格納される。処理回路では、メモリ９２に記憶されたプログラムをプロセッサ９１が読み出して実行することにより、各機能を実現する。すなわち、無線通信装置１において、処理回路は、周波数偏差を検出することが結果的に実行されることになるプログラムを格納するためのメモリ９２を備える。また、これらのプログラムは、無線通信装置１の手順および方法をコンピュータに実行させるものであるともいえる。 FIG. 17 is a diagram illustrating an example in which the processing circuit of the wireless communication apparatus 1 according to the present embodiment is configured by a processor and a memory. When the processing circuit includes the processor 91 and the memory 92, each function of the processing circuit of the wireless communication device 1 is realized by software, firmware, or a combination of software and firmware. Software or firmware is described as a program and stored in the memory 92. In the processing circuit, each function is realized by the processor 91 reading and executing the program stored in the memory 92. That is, in the wireless communication apparatus 1, the processing circuit includes a memory 92 for storing a program that results in detecting a frequency deviation. These programs can also be said to cause a computer to execute the procedure and method of the wireless communication apparatus 1.
　ここで、プロセッサ９１は、ＣＰＵ（Central　Processing　Unit）、処理装置、演算装置、マイクロプロセッサ、マイクロコンピュータ、またはＤＳＰ（Digital　Signal　Processor）などであってもよい。また、メモリ９２には、例えば、ＲＡＭ（Random　Access　Memory）、ＲＯＭ（Read　Only　Memory）、フラッシュメモリ、ＥＰＲＯＭ（Erasable　Programmable　ＲＯＭ）、ＥＥＰＲＯＭ（登録商標）（Electrically　ＥＰＲＯＭ）などの、不揮発性または揮発性の半導体メモリ、磁気ディスク、フレキシブルディスク、光ディスク、コンパクトディスク、ミニディスク、またはＤＶＤ（Digital　Versatile　Disc）などが該当する。 Here, the processor 91 may be a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor). The memory 92 is nonvolatile or volatile, such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (registered trademark) (Electrically EPROM), and the like. Such semiconductor memory, magnetic disk, flexible disk, optical disk, compact disk, mini disk, DVD (Digital Versatile Disc), and the like are applicable.
　図１８は、本実施の形態にかかる無線通信装置１の処置回路を専用のハードウェアで構成する場合の例を示す図である。処理回路が専用のハードウェアで構成される場合、図１８に示す処理回路９３は、例えば、単一回路、複合回路、プログラム化したプロセッサ、並列プログラム化したプロセッサ、ＡＳＩＣ（Application　Specific　Integrated　Circuit）、ＦＰＧＡ（Field　Programmable　Gate　Array）、またはこれらを組み合わせたものが該当する。無線通信装置１の各機能を機能別に処理回路９３で実現してもよいし、各機能をまとめて処理回路９３で実現してもよい。 FIG. 18 is a diagram illustrating an example in which the treatment circuit of the wireless communication device 1 according to the present embodiment is configured with dedicated hardware. When the processing circuit is configured with dedicated hardware, the processing circuit 93 shown in FIG. 18 includes, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), An FPGA (Field Programmable Gate Array) or a combination of these is applicable. Each function of the wireless communication apparatus 1 may be realized by the processing circuit 93 for each function, or each function may be realized by the processing circuit 93 collectively.
　無線通信装置１の送信器１１において、データ変調部３１はモジュレータである。多重部３３は多重回路である。アップコンバータ３４は周波数変換回路である。増幅器３５は増幅回路である。チャープ信号生成部３２は処理回路により実現される。チャープ信号生成部３２の処理回路については、図７に示す構成であってもよいし、図１７および図１８の示す構成であってもよい。 In the transmitter 11 of the wireless communication apparatus 1, the data modulation unit 31 is a modulator. The multiplexing unit 33 is a multiplexing circuit. The up converter 34 is a frequency conversion circuit. The amplifier 35 is an amplifier circuit. The chirp signal generation unit 32 is realized by a processing circuit. The processing circuit of the chirp signal generation unit 32 may have the configuration shown in FIG. 7 or the configuration shown in FIGS. 17 and 18.
　なお、無線通信装置１の各機能について、一部を専用のハードウェアで実現し、一部をソフトウェアまたはファームウェアで実現するようにしてもよい。このように、処理回路は、専用のハードウェア、ソフトウェア、ファームウェア、またはこれらの組み合わせによって、上述の各機能を実現することができる。 Note that a part of each function of the wireless communication device 1 may be realized by dedicated hardware, and a part may be realized by software or firmware. As described above, the processing circuit can realize the above-described functions by dedicated hardware, software, firmware, or a combination thereof.
　以上説明したように、本実施の形態によれば、無線通信装置１は、上りチャープ信号および下りチャープ信号を交互に繰り返し生成し、上りチャープ信号または下りチャープ信号と、データ信号とを多重した多重信号を送信する。無線通信装置２は、多重信号を受信し、多重信号から分離した上りチャープ信号および下りチャープ信号を用いて、無線通信装置１，２で使用されている周波数の周波数偏差を検出することとした。無線通信装置２は、伝搬路変動などにより受信タイミングが変動した場合においても、周波数偏差検出部５４の巡回加算部６６からの出力段階では周波数毎に遅延時間が直線的に変化した遅延検波の結果となるため、ピーク検出部６８でのピーク検出すなわち周波数偏差の検出に影響を及ぼすことなく、正確な周波数偏差の検出が可能となる。 As described above, according to the present embodiment, radio communication apparatus 1 repeatedly generates uplink chirp signals and downlink chirp signals alternately, and multiplexes the uplink chirp signal or downlink chirp signal and the data signal. Send a signal. The wireless communication device 2 receives the multiplexed signal and detects the frequency deviation of the frequency used in the wireless communication devices 1 and 2 using the upstream chirp signal and the downstream chirp signal separated from the multiplexed signal. Even when the reception timing fluctuates due to propagation path fluctuation or the like, the wireless communication apparatus 2 is the result of the delay detection in which the delay time changes linearly for each frequency at the output stage from the cyclic adder 66 of the frequency deviation detector 54. Therefore, it is possible to accurately detect the frequency deviation without affecting the peak detection by the peak detector 68, that is, the detection of the frequency deviation.
　無線通信装置１は、データ信号を含みつつ受信側の無線通信装置２で周波数偏差を検出可能な信号を送信する。これにより、無線通信装置１，２では周波数偏差の検出のために別の信号を送受信するための回路を追加する必要は無い。 The wireless communication device 1 transmits a signal that can be detected by the wireless communication device 2 on the receiving side while including the data signal. Thereby, it is not necessary for the wireless communication apparatuses 1 and 2 to add a circuit for transmitting and receiving another signal for detecting a frequency deviation.
　以上の実施の形態に示した構成は、本発明の内容の一例を示すものであり、別の公知の技術と組み合わせることも可能であるし、本発明の要旨を逸脱しない範囲で、構成の一部を省略、変更することも可能である。 The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.
　１，２　無線通信装置、１１，２１　送信器、１２，２２　受信器、１３，２３　基準発信器、１４，２４　周波数シンセサイザ、１５，２５　共用器、１６，２６　アンテナ、３１　データ変調部、３２　チャープ信号生成部、３３　多重部、３４　アップコンバータ、３５，５１　増幅器、４１，６２，８２　メモリ、４２　カウンタ、４３　読み出し部、５２　ダウンコンバータ、５３　分離部、５４　周波数偏差検出部、５５　データ復調部、６１，６７　ＦＦＴ、６３，７３　複素乗算部、６４　遅延検波部、６５　周波数軸反転部、６６　巡回加算部、６８　ピーク検出部、７１　遅延部、７２　複素共役部、８１　複素加算部、１００　無線通信システム。 1, 2, wireless communication device, 11, 21 transmitter, 12, 22 receiver, 13, 23 reference transmitter, 14, 24 frequency synthesizer, 15, 25 duplexer, 16, 26 antenna, 31 data modulator, 32 chirp Signal generation unit, 33 multiplexing unit, 34 up converter, 35, 51 amplifier, 41, 62, 82 memory, 42 counter, 43 reading unit, 52 down converter, 53 separation unit, 54 frequency deviation detection unit, 55 data demodulation unit, 61, 67 FFT, 63, 73 complex multiplication unit, 64 delay detection unit, 65 frequency axis inversion unit, 66 cyclic addition unit, 68 peak detection unit, 71 delay unit, 72 complex conjugate unit, 81 complex addition unit, 100 wireless communication system.

Claims (8)

  1. 　周波数を低い方から高い方へ掃引する上りチャープ信号および周波数を高い方から低い方へ掃引する下りチャープ信号を交互に繰り返し生成し、前記上りチャープ信号または前記下りチャープ信号と、データ信号とを多重した多重信号を送信する送信器と、
    　前記多重信号のアップコンバートの際に使用される周波数信号を生成する発振回路と、
    　を備えることを特徴とする無線通信装置。     The uplink chirp signal that sweeps the frequency from low to high and the downlink chirp signal that sweeps the frequency from high to low are alternately generated repeatedly, and the uplink chirp signal or the downlink chirp signal and the data signal are multiplexed. A transmitter for transmitting the multiplexed signal,
    An oscillation circuit for generating a frequency signal used in up-conversion of the multiplexed signal;
    A wireless communication apparatus comprising:
  2. 　前記送信器は、
    　前記上りチャープ信号および前記下りチャープ信号を交互に繰り返し生成するチャープ信号生成部と、
    　前記上りチャープ信号または前記下りチャープ信号と、前記データ信号とを多重する多重部と、
    　を備えることを特徴とする請求項１に記載の無線通信装置。     The transmitter is
    A chirp signal generator for alternately and repeatedly generating the upstream chirp signal and the downstream chirp signal;
    A multiplexing unit that multiplexes the uplink chirp signal or the downlink chirp signal and the data signal;
    The wireless communication apparatus according to claim 1, further comprising:
  3. 　請求項１または２に記載の無線通信装置である他の無線通信装置から送信された多重信号を受信し、受信した多重信号を用いて、自装置および前記他の無線通信装置で使用されている周波数の周波数偏差を検出する受信器と、
    　受信した多重信号のダウンコンバートの際に使用される周波数信号を生成する発振回路と、
    　を備えることを特徴とする無線通信装置。     A multiplexed signal transmitted from another wireless communication device which is the wireless communication device according to claim 1 or 2 is received, and the received multiple signal is used by the own device and the other wireless communication device. A receiver that detects the frequency deviation of the frequency;
    An oscillation circuit that generates a frequency signal used when down-converting the received multiplexed signal;
    A wireless communication apparatus comprising:
  4. 　前記受信器は、
    　受信した多重信号を、前記上りチャープ信号および前記下りチャープ信号と、前記データ信号とに分離する分離部と、
    　前記分離部で分離された前記上りチャープ信号および前記下りチャープ信号を用いて、前記周波数偏差を検出する周波数偏差検出部と、
    　前記周波数偏差検出部で検出された前記周波数偏差を用いて、前記分離部で分離された前記データ信号を復調するデータ復調部と、
    　を備えることを特徴とする請求項３に記載の無線通信装置。     The receiver is
    A separator that separates the received multiplexed signal into the upstream chirp signal and the downstream chirp signal, and the data signal;
    A frequency deviation detection unit that detects the frequency deviation using the upstream chirp signal and the downstream chirp signal separated by the separation unit;
    A data demodulating unit that demodulates the data signal separated by the separating unit using the frequency deviation detected by the frequency deviation detecting unit;
    The wireless communication apparatus according to claim 3, further comprising:
  5. 　前記周波数偏差検出部は、
    　前記上りチャープ信号および前記下りチャープ信号を時間軸上の信号から周波数軸上の信号に変換する第１の変換部と、
    　連続する前記上りチャープ信号と前記下りチャープ信号との間で周波数毎の遅延検波を行う遅延検波部と、
    　前記遅延検波部から出力された遅延検波結果のうち、前記上りチャープ信号または前記下りチャープ信号の一方を基準にしたときの遅延検波結果の周波数軸を反転する周波数軸反転部と、
    　前記遅延検波部から出力された遅延検波結果のうち前記周波数軸反転部で周波数軸が反転されていない遅延検波結果、および前記周波数軸反転部で周波数軸が反転された遅延検波結果を巡回加算する巡回加算部と、
    　前記巡回加算部で巡回加算された遅延検波結果を時間軸上の信号から周波数軸上の信号に変換する第２の変換部と、
    　前記第２の変換部から出力された信号のピーク検出を行い、ピーク検出位置を前記周波数偏差として検出するピーク検出部と、
    　を備えることを特徴とする請求項４に記載の無線通信装置。     The frequency deviation detector is
    A first converter that converts the upstream chirp signal and the downstream chirp signal from a signal on a time axis to a signal on a frequency axis;
    A delay detection unit that performs delay detection for each frequency between the upstream chirp signal and the downstream chirp signal;
    Of the delay detection results output from the delay detection unit, a frequency axis inversion unit for inverting the frequency axis of the delay detection result when one of the uplink chirp signal or the downlink chirp signal is used as a reference;
    Of the delay detection results output from the delay detection unit, the delay detection result whose frequency axis is not inverted by the frequency axis inversion unit and the delay detection result whose frequency axis is inverted by the frequency axis inversion unit are cyclically added. A cyclic addition unit;
    A second conversion unit that converts the delay detection result cyclically added by the cyclic addition unit from a signal on the time axis to a signal on the frequency axis;
    A peak detection unit that detects a peak of the signal output from the second conversion unit and detects a peak detection position as the frequency deviation;
    The wireless communication apparatus according to claim 4, further comprising:
  6. 　請求項１または２に記載の無線通信装置の送信器、
    　を備えることを特徴とする請求項３から５のいずれか１つに記載の無線通信装置。     The transmitter of the wireless communication device according to claim 1 or 2,
    The wireless communication apparatus according to any one of claims 3 to 5, further comprising:
  7. 　無線通信装置の送信器が、周波数を低い方から高い方へ掃引する上りチャープ信号および周波数を高い方から低い方へ掃引する下りチャープ信号を交互に繰り返し生成する生成ステップと、
    　前記送信器が、前記上りチャープ信号または前記下りチャープ信号と、データ信号とを多重した多重信号を生成する多重ステップと、
    　前記送信器が、前記多重信号を送信する送信ステップと、
    　を含むことを特徴とする送信方法。     A generation step in which a transmitter of a wireless communication device alternately and repeatedly generates an upstream chirp signal that sweeps the frequency from the lower side to the higher side and a downstream chirp signal that sweeps the frequency from the higher side to the lower side;
    A multiplexing step in which the transmitter generates a multiplexed signal obtained by multiplexing the uplink chirp signal or the downlink chirp signal and a data signal;
    A transmitting step in which the transmitter transmits the multiplexed signal;
    The transmission method characterized by including.
  8. 　無線通信装置の受信器が、請求項７に記載の送信方法によって他の無線通信装置から送信された多重信号を受信し、受信した多重信号から、上りチャープ信号および下りチャープ信号と、データ信号とを分離する分離ステップと、
    　前記受信器が、分離された前記上りチャープ信号および前記下りチャープ信号を用いて、自装置および前記他の無線通信装置で使用されている周波数の周波数偏差を検出する検出ステップと、
    　前記受信器が、前記周波数偏差を用いて、分離された前記データ信号を復調する復調ステップと、
    　を含むことを特徴とする受信方法。     A receiver of a wireless communication device receives a multiplexed signal transmitted from another wireless communication device by the transmission method according to claim 7, and from the received multiplexed signal, an upstream chirp signal and a downstream chirp signal, a data signal, Separating steps,
    A detection step in which the receiver detects a frequency deviation of a frequency used in its own device and the other wireless communication device using the separated upstream chirp signal and the downstream chirp signal;
    A demodulation step in which the receiver demodulates the separated data signal using the frequency deviation;
    A receiving method comprising:
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