WO2018201694A1 - 在100g以上光传输芯片中控制ptp报文的方法及系统 - Google Patents

在100g以上光传输芯片中控制ptp报文的方法及系统 Download PDF

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WO2018201694A1
WO2018201694A1 PCT/CN2017/111855 CN2017111855W WO2018201694A1 WO 2018201694 A1 WO2018201694 A1 WO 2018201694A1 CN 2017111855 W CN2017111855 W CN 2017111855W WO 2018201694 A1 WO2018201694 A1 WO 2018201694A1
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ptp
cache
packet
message
ethernet service
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French (fr)
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方继通
梁元涛
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Fiberhome Telecommunication Technologies Co Ltd
Wuhan Fisilink Microelectronics Technology Co Ltd
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Fiberhome Telecommunication Technologies Co Ltd
Wuhan Fisilink Microelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/31—Flow control; Congestion control by tagging of packets, e.g. using discard eligibility [DE] bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools

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  • the present invention relates to the field of optical transmission chip supporting time synchronization technology, and in particular to a method and system for controlling PTP messages in an optical transmission chip of 100 G or more.
  • 100G (100GB/s) transmission is far ahead of 10G and 40G transmission in terms of capacity and cost per bit.
  • 100G is undoubtedly the main driving force for the growth of optical network equipment in the world, 100G.
  • Super 100G is becoming the focus of breakthroughs in high-speed transmission technology.
  • the IEEE 1588 V2 protocol also known as PTP (Precision Time Protocol) is a preferred solution for solving network time synchronization technology.
  • Supporting PTP packet control in a 100G Ethernet service interface of a 100G or super 100G optical transmission chip is a prerequisite for accurate network time synchronization.
  • the optical transmission chip in order to support the high-precision time synchronization function of the IEEE 1588 V2 of the 100G interface, it is necessary to complete the line rate resolution identification of the PTP message and the control function of the PTP message at the rate of the 100 G Ethernet interface.
  • the technical problem to be solved by the present invention is to implement the control of the PTP packet by the optical transmission chip, and increase the control efficiency and processing performance of the optical transmission chip above 100G for the PTP packet.
  • the optical transmission chip above 100G supports the design scale and cost of the IEEE1588V2 high-precision time synchronization function.
  • the method for controlling a PTP message in an optical transmission chip of 100 G or more provided by the present invention includes the following steps:
  • Step A When the Ethernet service channel packet is identified as a PTP packet, the PTP packet control flag is set at the end of the PTP packet, and the process proceeds to step B.
  • Step B Select a non-full PTP cache as the PTP write cache, the non-full PTP cache is defined as: at least one cache space in the PTP cache is empty, go to step C;
  • Step C Selecting an empty buffer space in the PTP write buffer, and writing an Ethernet service channel packet in the current cache space; if the PTP packet control flag of the currently written Ethernet service channel packet is valid, Determining that the currently written Ethernet service channel packet is a PTP packet, and writing the packet description information of the current PTP packet in the current buffer space, and proceeding to step D;
  • Step D The other PTP cache is written as a PTP write cache, and when the PTP write cache is not full, step C is re-executed;
  • Step E During the process from step B to step D, when there is a non-empty PTP cache, the PTP packet in the PTP cache is read; the non-empty PTP cache is defined as: at least one cache space in the PTP cache. It is not empty.
  • the system for controlling PTP messages in an optical transmission chip of 100 G or more which comprises the foregoing method, includes a PTP tag control module, a PTP parsing and recognition module, a PTP cache control module, and a PTP read module;
  • the PTP tag control module is used to: when the Ethernet service channel message is identified as PTP In the message, the PTP message control flag is set at the end of the PTP message, and the working signal is sent to the PTP buffer control module.
  • the PTP cache control module is configured to: after receiving the working signal, select a non-full PTP cache as the PTP write cache, and the non-full PTP cache is defined as: at least one cache space in the PTP cache is empty, and parsed into the PTP.
  • the identification module sends a PTP parsing identification signal; after receiving the PTP buffer control signal, the other PTP cache is used as a PTP write buffer, and when the PTP write buffer is not full, the PTP parsing and identifying module is again sent a PTP parsing identification signal;
  • the PTP parsing and identifying module is configured to: after receiving the PTP parsing and identifying signal, select one empty buffer space in the PTP write buffer, and write an Ethernet service channel packet in the current buffer space; if the currently written Ethernet service If the PTP packet control flag of the channel packet is valid, the packet that is currently written is marked as a PTP packet, and the packet description information of the current PTP packet is written in the current buffer space, and sent to the PTP cache control module.
  • PTP buffer control signal
  • the PTP reading module is configured to read PTP packets in the PTP cache when a non-empty PTP cache exists in the process of working in the PTP parsing and identifying module and the PTP cache control module; the non-empty PTP cache is defined as: At least one cache space in the PTP cache is non-empty.
  • the PTP packet control flag is set in the end of the identified PTP packet, so that the primary and secondary PTP buffers of the Ethernet channel can control the PTP packet.
  • a PTP packet with a full packet combined with the cache space for the primary and secondary PTP cache switching and one full packet can be written in each buffer space.
  • the present invention uses a complete write and rewrite write mechanism to control the target PTP message for both the primary and secondary PTP caches of the Ethernet channel.
  • Ethernet channel at the same time
  • the PTP packet timestamp and the entire packet description obtained in real time are controlled and transmitted along with the PTP packet, so that the PTP packet control is not affected by the BC and TC clock types in the prior art, thereby ensuring 100G or over 100G.
  • the IEEE1588V2 time synchronization function in the chip is more practical and efficient.
  • the present invention can not only effectively control the PTP packet control of the 100G and the super 100G optical transmission chip, but also is insensitive to the BC and TC clock types of the time synchronization application scenario when the PTP packet is efficiently controlled.
  • the present invention significantly improves the control efficiency and processing performance of the 100G or super 100G optical transmission chip for PTP messages, and reduces the chip design resources and design complexity of supporting the IEEE1588V2 high-precision time synchronization function, and is also a chip. Bringing advantages in design scale and design cost, it is very suitable for promotion.
  • FIG. 1 is a flowchart of a method for controlling a PTP message in an optical transmission chip of 100 G or more according to an embodiment of the present invention
  • FIG. 2 is a connection block diagram of a system for controlling PTP messages in an optical transmission chip of 100 G or more according to an embodiment of the present invention.
  • a method for controlling a PTP packet in an optical transmission chip of 100 G or more in the embodiment of the present invention includes the following steps:
  • All PTP caches in S2 include a primary PTP cache and a secondary PTP cache.
  • Each PTP cache is divided into 4 cache spaces, and each block buffer can write 1 full packet of PTP packets (the cache space supports 1518 bytes).
  • the length of the packet is defined as: PTP buffer is not full: at least one cache space in the PTP cache is empty; if the primary PTP cache and the secondary PTP cache are both non-full, the primary PTP cache is selected as the PTP write cache. .
  • the first time is to write to the main PTP buffer, and then to the non-full PTP buffer to which the write is switched according to the handover control indication.
  • S3 Selecting an empty buffer space in the PTP write buffer according to the switch control indication, and sequentially writing the received Ethernet service channel message at the second memory start address of the current cache space until writing to The end of the Ethernet service channel packet or the end of the current buffer space. The end of the packet or the end of the buffer space is written as the write-off condition, and goes to S4.
  • S4 determining whether the PTP packet control flag of the currently written Ethernet service channel packet is valid. If the condition is that the PTP packet control flag exists, the current Ethernet service channel packet is written in the buffer space. Go to S6, otherwise (for example, the PTP packet control flag does not exist, that is, the current Ethernet service channel packet is not written in the buffer space), and the process goes to S5.
  • S5 Generate a current buffer space rewrite indication, and re-execute S2 (that is, overwrite the next Ethernet service channel packet).
  • S6 Generate a current buffer space write completion indication, and write a packet description information of the current PTP packet at the first memory start address of the current cache space, where the package description information includes the received current PTP generated in S1.
  • the real time stamp of the message go to S7.
  • S7 Generate a buffer switching control indication, and write other PTP caches as PTP writes. Save and go to S8.
  • S8 Determine whether the PTP write buffer is not full. If yes, jump to S3, otherwise execute S8 again.
  • S9 Continuously detecting whether the PTP cache is non-empty, and the PTP cache is non-empty.
  • the definition is as follows: at least one cache space in the PTP cache is non-empty, and the null check is determined according to the whole package manner; if yes, read according to the polling manner.
  • the PTP packet in the PTP cache is taken until the PTP cache read operation is stopped when the primary and secondary PTP caches are empty. Otherwise, all PTP caches are empty. S9 is re-executed.
  • the following describes a method for controlling a PTP message in an optical transmission chip of 100 G or more in the embodiment of the present invention by using a 200 G OTN Framer chip as a specific embodiment.
  • Step 1 When the 200G OTN Framer chip is initialized, the register identifies all PTP packet marking patterns by default, and the default setting of the register is: Enable PTP in the tail for all PTP packets except the peer delay mechanism message class. The message control flag is valid and go to step 2.
  • Step 2 The primary and secondary PTP caches of the 100G Ethernet service channel of the 200G OTN Framer chip are detected to be non-full. Write the 100G Ethernet service channel packet to the empty cache space of the primary PTP cache and go to step 3.
  • Step 3 The currently written 100G Ethernet service channel packet is a Sync packet, and the PTP packet control flag of the packet is valid.
  • the current PTP packet is written at the first memory start address of the current buffer space. For the package description information, go to step four.
  • Step 4 In the current 100G Ethernet service channel, generate a buffer switching control indication, so that the current primary PTP cache write control right is switched to the secondary PTP cache; that is, the secondary PTP cache becomes the PTP write cache of the Ethernet service channel, and the PTP The write buffer (that is, the secondary PTP cache) is not full, and the Ethernet service is written in the PTP write cache according to the above steps. Channel message.
  • step 4 it is detected that the primary PTP cache of the current 100G Ethernet service channel is non-empty, and the Sync message is read out in the main PTP buffer by the whole packet.
  • the 200G OTN Framer chip includes two 100G Ethernet interface channels.
  • each 100G Ethernet service packet has been written and cached.
  • the PTP packet control flag is enabled for the PTP packet except the peer delay mechanism message type, the method for controlling the PTP packet is effectively implemented only for the target PTP packet.
  • the output from the primary or secondary PTP cache significantly improves the control efficiency and processing performance of the PTP message for the 100G or over 100G optical transmission chip.
  • each buffer space of the primary and secondary PTP caches of the 100G PTP cache control module supports a packet length of 1518 bytes, so that the 100G channel can be extended to support the control of larger custom PTP packets.
  • the control of the text is insensitive to the BC and TC clock types, and effectively increases the application range of the 100G and super 100G optical transmission chips in the time synchronization scenario.
  • the system for controlling PTP messages in an optical transmission chip of 100 G or more which includes the foregoing method, includes a timestamp generation module, an Ethernet service module, a PTP tag control module, and a PTP parsing and recognition module. , PTP cache control module, PTP read module and message processing module.
  • the timestamp generating module is configured to: when receiving the Ethernet service channel packet, send the real time stamp of the received packet to the Ethernet service module.
  • the Ethernet service module is used to associate the real-time timestamp with the received message in a packet description manner.
  • the PTP tag control module is used to: when the Ethernet service channel message is identified as PTP In the message, a PTP message control flag is set at the end of the PTP message, and a working signal is sent to the PTP buffer control module.
  • the PTP cache control module is configured to: after receiving the working signal, select a non-full PTP cache as the PTP write cache, and the non-full PTP cache is defined as: at least one cache space in the PTP cache is empty, and parsed into the PTP.
  • the identification module sends a PTP resolution identification signal. After receiving the PTP buffer control signal, the other PTP cache is used as the PTP write buffer. When the PTP write buffer is not full, the PTP parsing identification signal is sent to the PTP parsing and identifying module.
  • the PTP cache includes a primary PTP cache and a secondary PTP cache.
  • the PTP cache control module selects a non-full PTP cache as the PTP write cache.
  • the workflow includes: if the primary PTP cache and the secondary PTP cache are both non-full, select the primary PTP cache. As a PTP write cache.
  • the PTP parsing and identifying module is configured to: after receiving the PTP parsing and identifying signal, select one empty buffer space in the PTP write buffer, and write an Ethernet service channel packet in the current buffer space (the second in the current cache space) At the memory start address, the Ethernet service channel packet is written until it is written to the end of the Ethernet service channel packet or at the end of the current buffer space. If the PTP packet control flag of the currently written Ethernet service channel packet is valid, it is determined that the currently written Ethernet service channel packet is a PTP packet, and the packet description of the current PTP packet is written in the current buffer space.
  • the packet description information of the current PTP packet is written, that is, the real-time timestamp of the current PTP packet is received), and the PTP cache control signal is sent to the PTP cache control module.
  • the PTP reading module is configured to read PTP packets in the PTP cache when a non-empty PTP cache exists in the process of working in the PTP parsing and identifying module and the PTP cache control module; the non-empty PTP cache is defined as: At least one cache space in the PTP cache is non-empty.
  • the packet processing module is used to: complete the processing function of the packet.

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Abstract

本发明涉及光传输芯片支持时间同步技术领域，具体涉及一种在100G以上光传输芯片中控制PTP报文的方法及系统。该方法的步骤为：在PTP报文的尾部设置PTP报文控制标记；在选择的PTP写入缓存空间中，写入以太网业务通道报文；若当前写入的以太网业务通道报文的PTP报文控制标记有效，则在当前缓存空间中写入PTP报文的包描述信息；将其他PTP缓存作为PTP写入缓存再次写入报文；当存在非空的PTP缓存时，读取PTP缓存中的PTP报文。本发明能够实用高效的完成光传输芯片对PTP报文的控制，增加100G以上的光传输芯片对PTP报文的控制效率和处理性能，降低100G以上的光传输芯片支持IEEE1588V2高精度时间同步功能的设计规模和成本。

Description

在100G以上光传输芯片中控制PTP报文的方法及系统 技术领域
本发明涉及光传输芯片支持时间同步技术领域，具体涉及一种在100G以上光传输芯片中控制PTP报文的方法及系统。
背景技术
在光网络市场背景下，就传输在容量和每比特成本而言，100G(100GB/s)传输已经远远领先于10G和40G传输，100G毫无疑问成为全球光网络设备增长的主要动力，100G和超100G正成为高速传输技术领域突破的重点。
IEEE1588V2协议也称为PTP(Precision Time Protocol，精确时间协议)，是目前解决网络时间同步技术的较佳方案。在100G或超100G光传输芯片的100G以太网业务接口中支持PTP报文的控制是实现精确网络时间同步的前提。在光传输芯片中为了支持100G接口的IEEE1588V2的高精度时间同步功能，需要完成100G以太网接口速率下对PTP报文的线速解析识别和PTP报文的控制功能。
目前，为了使光传输芯片支持IEEE1588V2高精度时间同步功能，特别是对于100G以太网业务接口支持高精度时间同步功能中PTP报文的控制处理，往往伴随着庞大的报文缓存处理和复杂的电路控制；与此同时，在支持不同时钟类型的应用场景时，例如BC(边界时钟)及TC(透明时钟)，处理和控制机制更加复杂和繁琐，不仅占用了大量的业务报文带宽，而且耗费了较大的芯片设计资源，从而增加了100G及超100G光传输芯片的设计规模和成本。
发明内容
针对现有技术中存在的缺陷，本发明解决的技术问题为：实用高效的完成光传输芯片对PTP报文的控制，增加100G以上的光传输芯片对PTP报文的控制效率和处理性能，降低100G以上的光传输芯片支持IEEE1588V2高精度时间同步功能的设计规模和成本。
为达到以上目的，本发明提供的在100G以上光传输芯片中控制PTP报文的方法，包括以下步骤：
步骤A：当以太网业务通道报文被识别为PTP报文时，在PTP报文的尾部设置PTP报文控制标记，转到步骤B；
步骤B：选择1个非满的PTP缓存作为PTP写入缓存，非满的PTP缓存定义为：PTP缓存中至少有1块缓存空间为空，转到步骤C；
步骤C：在PTP写入缓存中选择1块空缓存空间，在当前缓存空间中写入以太网业务通道报文；若当前写入的以太网业务通道报文的PTP报文控制标记有效，则确定当前写入的以太网业务通道报文为PTP报文，在当前缓存空间中写入当前PTP报文的包描述信息，转到步骤D；
步骤D：将其他PTP缓存作为PTP写入缓存，当PTP写入缓存为非满时，重新执行步骤C；
步骤E：执行步骤B至步骤D的过程中，当存在非空的PTP缓存时，读取PTP缓存中的PTP报文；非空的PTP缓存的定义为：PTP缓存中至少有1块缓存空间为非空。
本发明提供的实现上述方法的在100G以上光传输芯片中控制PTP报文的系统，包括PTP标记控制模块、PTP解析识别模块、PTP缓存控制模块和PTP读取模块；
PTP标记控制模块用于：当以太网业务通道报文被识别为PTP 报文时，在PTP报文的尾部设置PTP报文控制标记，向PTP缓存控制模块发送工作信号；
PTP缓存控制模块用于：收到工作信号后，选择1个非满的PTP缓存作为PTP写入缓存，非满的PTP缓存定义为：PTP缓存中至少有1块缓存空间为空，向PTP解析识别模块发送PTP解析识别信号；收到PTP缓存控制信号后，将其他PTP缓存作为PTP写入缓存，当PTP写入缓存为非满时，重新向PTP解析识别模块发送PTP解析识别信号；
PTP解析识别模块用于：收到PTP解析识别信号后，在PTP写入缓存中选择1块空缓存空间，在当前缓存空间中写入以太网业务通道报文；若当前写入的以太网业务通道报文的PTP报文控制标记有效，则确定当前写入的以太网业务通道报文为PTP报文，在当前缓存空间中写入当前PTP报文的包描述信息，向PTP缓存控制模块发送PTP缓存控制信号；
PTP读取模块用于：在PTP解析识别模块和PTP缓存控制模块工作的过程中，当存在非空的PTP缓存时，读取PTP缓存中的PTP报文；非空的PTP缓存的定义为：PTP缓存中至少有1块缓存空间为非空。
与现有技术相比，本发明的优点在于：
本发明将PTP报文控制标记设置于识别出的PTP报文尾，便于以太网通道的主、辅PTP缓存对PTP报文进行控制。为了在以太网业务通道中支持线速控制PTP报文，采用了以整包结合缓存空间存储的主、辅PTP缓存切换形式、并且每个缓存空间均可写入1个整包的PTP报文。本发明对以太网通道的主、辅PTP缓存均采用完成写入和重新覆盖写入机制来控制目标PTP报文。同时将以太网通道 实时获取的PTP报文时间戳和整个包描述，伴随PTP报文进行控制和传递，进而使得PTP报文控制不受现有技术中的BC和TC时钟类型的影响，从而保证在100G或超100G芯片中支持IEEE1588V2时间同步功能更加实用高效。
有鉴于此，本发明不仅能够高效的实现100G及超100G光传输芯片对PTP报文的控制，而且对PTP报文高效控制时，对时间同步应用场景的BC及TC时钟类型不敏感。与此同时，本发明显著的提高了100G或超100G光传输芯片对PTP报文的控制效率和处理性能，降低了支持IEEE1588V2高精度时间同步功能的芯片设计资源和设计复杂度，进而也为芯片在设计规模和设计成本上带来优势，非常适于推广。
附图说明
图1为本发明实施例中在100G以上光传输芯片中控制PTP报文的方法的流程图；
图2为本发明实施例中在100G以上光传输芯片中控制PTP报文的系统的连接框图。
具体实施方式
以下结合附图及实施例对本发明作进一步详细说明。
参见图1所示，本发明实施例中的在100G以上光传输芯片中控制PTP报文的方法，包括以下步骤：
S1：当收到以太网业务通道报文时，产生收到报文的实时时间戳，当以太网业务通道报文被识别为PTP报文时，根据默认寄存器或自定义配置，在PTP报文的尾部设置PTP报文控制标记，转到S2。
S2：分别判断以太网业务通道的每个PTP缓存是否为非满，若 是，选择1个非满的PTP缓存作为PTP写入缓存，转到S3，否则重新执行S2。
S2中的所有PTP缓存包括主PTP缓存和辅PTP缓存，每个PTP缓存均划分为4块缓存空间，每块缓存空间均可写入1个整包的PTP报文(缓存空间支持1518字节的报文长度)；PTP缓存为非满的定义为：PTP缓存中至少有1块缓存空间为空；若主PTP缓存和辅PTP缓存均为非满，则选择主PTP缓存作为PTP写入缓存。在第一次时是写入主PTP缓存，在接下来就是根据切换控制指示写入被切换到的非满PTP缓存中。
S3：根据切换控制指示在PTP写入缓存中选择1块空的缓存空间，在当前缓存空间的第2个内存起始地址处，顺序写入收到的以太网业务通道报文，直至写至以太网业务通道报文尾、或者当前缓存空间尾为止，其中报文尾或缓冲空间尾以先写到的为写截止条件，转到S4。
S4：判断当前写入的以太网业务通道报文的PTP报文控制标记是否有效，若是(先决条件为PTP报文控制标记存在，即当前以太网业务通道报文在缓冲空间内写完)，转到S6，否则(例如PTP报文控制标记不存在，即当前以太网业务通道报文在缓冲空间内未写完)转到S5。
S5：产生当前缓存空间重新写入指示，重新执行S2(即覆盖写入下一条以太网业务通道报文)。
S6：产生当前缓存空间写入完成指示，在当前缓存空间的第1个内存起始地址处，写入当前PTP报文的包描述信息，包描述信息包括已在S1中产生的收到当前PTP报文的实时时间戳，转到S7。
S7：产生缓存切换控制指示，将其他PTP缓存作为PTP写入缓 存，转到S8。
S8：判断PTP写入缓存是否为非满，若是，跳转至S3，否则重新执行S8。
在执行S2至S8的过程中，还包括以下步骤：
S9：持续检测是否有PTP缓存为非空，PTP缓存为非空的定义为：PTP缓存中至少有1块缓存空间为非空，空检测按整包方式判定；若是，按照轮询的方式读取PTP缓存中的PTP报文，直至主辅PTP缓存均为空时停止PTP缓存读操作；否则(所有PTP缓存均为空)重新执行S9。
下面以200G OTN Framer芯片作为具体实施例，来说明本发明实施例中的在100G以上光传输芯片中控制PTP报文的方法。
步骤一：200G OTN Framer芯片初始化时，寄存器默认识别所有PTP报文标记图样，且寄存器默认设定为：对除了peer延时机制消息类报文之外的所有PTP报文，在尾部使能PTP报文控制标记有效，转到步骤二。
步骤二：检测到200G OTN Framer芯片100G以太网业务通道的主、辅PTP缓存均为非满。将100G以太网业务通道报文写入主PTP缓存的空缓存空间中，转到步骤三。
步骤三：当前写入的100G以太网业务通道报文为Sync报文，该报文的PTP报文控制标记有效，在当前缓存空间的第1个内存起始地址处，写入当前PTP报文的包描述信息，转到步骤四。
步骤四：在当前100G以太网业务通道下，产生缓存切换控制指示，使当前主PTP缓存写控制权切换至辅PTP缓存；即辅PTP缓存成为本以太网业务通道的PTP写入缓存，该PTP写入缓存(即辅PTP缓存)为非满，在该PTP写入缓存中按照上述步骤写入以太网业务 通道报文。
在执行步骤四的过程中，检测到当前100G以太网业务通道的主PTP缓存为非空，在主PTP缓存中按整包的方式读出Sync报文。
上述具体实施例中200G OTN Framer芯片包括2路100G以太网接口通道，在开启PTP模式工作时，每路100G以太网业务报文在写入缓存时已经完成了具体的PTP报文识别、标记控制和包描述信息关联。当对除了peer延时机制消息类报文之外的所有PTP报文，在尾部使能PTP报文控制标记有效时，通过本发明控制PTP报文的方法，高效实现了仅对目标PTP报文从主或辅PTP缓存进行输出，显著提高了100G或超100G光传输芯片对PTP报文的控制效率和处理性能。
与此同时100G PTP缓存控制模块的主、辅PTP缓存的每块缓存空间各支持一个1518字节的报文长度，使得100G通道可扩展支持较大的自定义PTP报文的控制；此外PTP报文的控制对BC及TC时钟类型不敏感，也有效的增加了100G及超100G光传输芯片在时间同步场景下的应用范围。
参见图2所示，本发明实施例提供的实现上述方法的在100G以上光传输芯片中控制PTP报文的系统，包括时间戳生成模块、以太网业务模块、PTP标记控制模块、PTP解析识别模块、PTP缓存控制模块、PTP读取模块和报文处理模块。
时间戳生成模块用于：当收到以太网业务通道报文时，将收到报文的实时时间戳发送至以太网业务模块。
以太网业务模块用于：将实时时间戳以包描述的方式和收到的报文相关联。
PTP标记控制模块用于：当以太网业务通道报文被识别为PTP 报文时，在PTP报文的尾部设置PTP报文控制标记，向PTP缓存控制模块发送工作信号。
PTP缓存控制模块用于：收到工作信号后，选择1个非满的PTP缓存作为PTP写入缓存，非满的PTP缓存定义为：PTP缓存中至少有1块缓存空间为空，向PTP解析识别模块发送PTP解析识别信号。收到PTP缓存控制信号后，将其他PTP缓存作为PTP写入缓存，当PTP写入缓存为非满时，重新向PTP解析识别模块发送PTP解析识别信号。
PTP缓存包括主PTP缓存和辅PTP缓存，PTP缓存控制模块选择1个非满的PTP缓存作为PTP写入缓存的工作流程包括：若主PTP缓存和辅PTP缓存均为非满，选择主PTP缓存作为PTP写入缓存。
PTP解析识别模块用于：收到PTP解析识别信号后，在PTP写入缓存中选择1块空缓存空间，在当前缓存空间中写入以太网业务通道报文(在当前缓存空间的第2个内存起始地址处，写入以太网业务通道报文，直至写至以太网业务通道报文尾、或者当前缓存空间尾为止)。若当前写入的以太网业务通道报文的PTP报文控制标记有效，则确定当前写入的以太网业务通道报文为PTP报文，在当前缓存空间中写入当前PTP报文的包描述信息(在当前缓存空间的第1个内存起始地址处，写入当前PTP报文的包描述信息，即收到当前PTP报文的实时时间戳)，向PTP缓存控制模块发送PTP缓存控制信号。
PTP读取模块用于：在PTP解析识别模块和PTP缓存控制模块工作的过程中，当存在非空的PTP缓存时，读取PTP缓存中的PTP报文；非空的PTP缓存的定义为：PTP缓存中至少有1块缓存空间为非空。
报文处理模块用于：完成报文的处理功能。
进一步，本发明不局限于上述实施方式，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围之内。本说明书中未作详细描述的内容属于本领域专业技术人员公知的现有技术。

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  1. 一种在100G以上光传输芯片中控制PTP报文的方法，其特征在于，该方法包括以下步骤：
    步骤A：当以太网业务通道报文被识别为PTP报文时，在PTP报文的尾部设置PTP报文控制标记，转到步骤B；
    步骤B：选择1个非满的PTP缓存作为PTP写入缓存，非满的PTP缓存定义为：PTP缓存中至少有1块缓存空间为空，转到步骤C；
    步骤C：在PTP写入缓存中选择1块空缓存空间，在当前缓存空间中写入以太网业务通道报文；若当前写入的以太网业务通道报文的PTP报文控制标记有效，则确定当前写入的以太网业务通道报文为PTP报文，在当前缓存空间中写入当前PTP报文的包描述信息，转到步骤D；
    步骤D：将其他PTP缓存作为PTP写入缓存，当PTP写入缓存为非满时，重新执行步骤C；
    步骤E：执行步骤B至步骤D的过程中，当存在非空的PTP缓存时，读取PTP缓存中的PTP报文；非空的PTP缓存的定义为：PTP缓存中至少有1块缓存空间为非空。
  2. 如权利要求1所述的在100G以上光传输芯片中控制PTP报文的方法，其特征在于：步骤C中所述在当前缓存空间中写入以太网业务通道报文包括以下流程：在当前缓存空间的第2个内存起始地址处，写入以太网业务通道报文，直至写至以太网业务通道报文尾、或者当前缓存空间尾为止。
  3. 如权利要求2所述的在100G以上光传输芯片中控制PTP报文的方法，其特征在于：步骤C中所述在当前缓存空间中写入当前PTP报文的包描述信息的流程为：在当前缓存空间的第1个内存起始 地址处，写入当前PTP报文的包描述信息。
  4. 如权利要求1所述的在100G以上光传输芯片中控制PTP报文的方法，其特征在于：步骤B中所述PTP缓存包括主PTP缓存和辅PTP缓存，所述选择1个非满的PTP缓存作为PTP写入缓存包括以下流程：若主PTP缓存和辅PTP缓存均为非满，选择主PTP缓存作为PTP写入缓存。
  5. 如权利要求1至4任一项所述的在100G以上光传输芯片中控制PTP报文的方法，其特征在于：步骤A还包括以下步骤：当收到以太网业务通道报文时，产生收到报文的实时时间戳；步骤C中所述包描述信息包括收到当前PTP报文的实时时间戳。
  6. 一种实现权利要求1至5任一项所述方法的在100G以上光传输芯片中控制PTP报文的系统，其特征在于：该系统包括PTP标记控制模块、PTP解析识别模块、PTP缓存控制模块和PTP读取模块；
    PTP标记控制模块用于：当以太网业务通道报文被识别为PTP报文时，在PTP报文的尾部设置PTP报文控制标记，向PTP缓存控制模块发送工作信号；
    PTP缓存控制模块用于：收到工作信号后，选择1个非满的PTP缓存作为PTP写入缓存，非满的PTP缓存定义为：PTP缓存中至少有1块缓存空间为空，向PTP解析识别模块发送PTP解析识别信号；收到PTP缓存控制信号后，将其他PTP缓存作为PTP写入缓存，当PTP写入缓存为非满时，重新向PTP解析识别模块发送PTP解析识别信号；
    PTP解析识别模块用于：收到PTP解析识别信号后，在PTP写入缓存中选择1块空缓存空间，在当前缓存空间中写入以太网业务通 道报文；若当前写入的以太网业务通道报文的PTP报文控制标记有效，则确定当前写入的以太网业务通道报文为PTP报文，在当前缓存空间中写入当前PTP报文的包描述信息，向PTP缓存控制模块发送PTP缓存控制信号；
    PTP读取模块用于：在PTP解析识别模块和PTP缓存控制模块工作的过程中，当存在非空的PTP缓存时，读取PTP缓存中的PTP报文；非空的PTP缓存的定义为：PTP缓存中至少有1块缓存空间为非空。
  7. 如权利要求6所述的在100G以上光传输芯片中控制PTP报文的系统，其特征在于：所述PTP解析识别模块在当前缓存空间中写入以太网业务通道报文的工作流程为：在当前缓存空间的第2个内存起始地址处，写入以太网业务通道报文，直至写至以太网业务通道报文尾、或者当前缓存空间尾为止。
  8. 如权利要求6所述的在100G以上光传输芯片中控制PTP报文的系统，其特征在于：所述PTP解析识别模块在当前缓存空间中写入当前PTP报文的包描述信息的流程为：在当前缓存空间的第1个内存起始地址处，写入当前PTP报文的包描述信息。
  9. 如权利要求6所述的在100G以上光传输芯片中控制PTP报文的系统，其特征在于：所述PTP缓存控制模块中的PTP缓存包括主PTP缓存和辅PTP缓存，PTP缓存控制模块选择1个非满的PTP缓存作为PTP写入缓存的工作流程包括：若主PTP缓存和辅PTP缓存均为非满，选择主PTP缓存作为PTP写入缓存。
  10. 如权利要求6至9任一项所述的在100G以上光传输芯片中控制PTP报文的系统，其特征在于：该系统还包括时间戳生成模块和以太网业务模块；
    时间戳生成模块用于：当收到以太网业务通道报文时，将收到报文的实时时间戳发送至以太网业务模块；
    以太网业务模块用于：将实时时间戳与收到的报文相关联；
    所述PTP解析识别模块中的描述信息包括收到当前PTP报文的实时时间戳。
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CN106982103A (zh) 2017-07-25
CN106982103B (zh) 2019-01-18

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