WO2018194544A1 - Multi-bit ferroelectric memory - Google Patents

Multi-bit ferroelectric memory Download PDF

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Publication number
WO2018194544A1
WO2018194544A1 PCT/US2017/027939 US2017027939W WO2018194544A1 WO 2018194544 A1 WO2018194544 A1 WO 2018194544A1 US 2017027939 W US2017027939 W US 2017027939W WO 2018194544 A1 WO2018194544 A1 WO 2018194544A1
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Prior art keywords
ferroelectric material
material portion
ferroelectric
memory
polarization
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PCT/US2017/027939
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French (fr)
Inventor
Daniel H. MORRIS
Uygar E. Avci
Ian A. Young
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Intel Corporation
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Priority to PCT/US2017/027939 priority Critical patent/WO2018194544A1/en
Publication of WO2018194544A1 publication Critical patent/WO2018194544A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • Embodiments described herein generally relate to the field of electronic devices and, more particularly, multi-bit ferroelectric memory.
  • the density of embedded memory can be an important factor in the ability to further scale microelectronics.
  • dense embedded memory that does not include a requirement for large capacitors and low signal sensing voltage are needed for scaled technology generations.
  • Ferroelectric memories are one approach to future dense memories.
  • ferroelectric memory is still limited in that, as with most memory architectures, the memory is limited to a single bit per unit cell. Having the capacity to store more than 1 bit per unit cell would improve memory density significantly, increasing performance and lowering cost of the chips.
  • Figure 1 is an illustration of a memory element including ferroelectric polarization utilizing one transistor and one ferroelectric capacitor according to an embodiment
  • Figure 2 is an illustration of a memory element including ferroelectric polarization utilizing one ferroelectric transistor according to an embodiment
  • Figure 3 is an illustration of characteristics of a multiple bit ferroelectric memory material construction according to an embodiment
  • Figure 4 illustrates ferroelectric material for a memory unit cell including ferroelectric materials having differing polarization characteristics according to an embodiment
  • Figure 5 illustrates ferroelectric material for a memory unit cell including a ferroelectric material with multiple different thicknesses according to an embodiment
  • Figure 6 illustrates ferroelectric material for a memory unit cell including ferroelectric material capacitors with different thicknesses according to an embodiment
  • Figure 7 is an illustration of a process for read and write operations for a multi-bit ferroelectric memory according to an embodiment
  • Figure 8 is an illustration of a system on chip including a multi-bit ferroelectric memory according to an embodiment.
  • Embodiments described herein are generally directed to multi-bit ferroelectric memory.
  • Fluoroelectric material or “FE material” refers to a material that provides a high level of electric polarization, wherein the polarization may be reversed by the application of a sufficient external electric field.
  • Cross electric field refers an electric field required to begin switching the polarization of a particular ferroelectric material.
  • Critical voltage refers to a voltage required to begin switching the polarization of a particular ferroelectric material.
  • Polarization voltage refers to a voltage required to fully switch the polarization of a particular ferroelectric material to a desired polarization level.
  • a polarization voltage associated with a low polarization state should be higher than the critical voltage of a low polarization state but lower than the critical voltage of a higher polarization state.
  • a multi-bit ferroelectric memory is implemented using multiple- voltage write characteristics through application of differing FE materials, FE material architecture, of both to provide a high density computer memory, including high density eDRAM (embedded Dynamic Random Access Memory).
  • FE materials including high density eDRAM (embedded Dynamic Random Access Memory).
  • eDRAM embedded Dynamic Random Access Memory
  • FE memories may be expected to have a density that is three times denser than a standard SRAM cell, and be comparable to a 1T+1C (one-transistor one-capacitor) DRAM cell.
  • a multi-bit FE memory architecture improves upon conventional FE memories by increasing the memory density through a capability of storing multiple bits per unit cell.
  • the multi-bit FE memory includes multiple polarization levels, wherein additional polarization levels allow for a storage of additional bits of memory.
  • two polarization levels (as in a conventional memory) may enable one bit of memory; four polarization levels enable two bits of memory; and eight polarization may enable three bits of memory.
  • the density of the memory utilizing an embodiment of multi-bit ferroelectric architecture may be a multiple of the density of ferroelectric memory having a conventional architecture.
  • the resulting FE memory may be addressed using different voltage levels during a write cycle, thereby allowing for storage of multiple bits of data in a single unit cell.
  • a multi-bit FE memory cell may store a non-integer number of bits.
  • a multi-bit FE memory cell may store greater than two polarization levels but fewer than four. Thus, this memory cell stores greater than one bit of data but fewer than two bits of data.
  • the figures and descriptions herein generally refer to four polarization levels in a memory unit cell, thereby allowing for storage of 2 bits of data in each memory unit cell.
  • embodiments are not limited to such an implementation, and may for example include storage of more than 2 bits of data in a memory unit cell through
  • embodiments are not limited to a memory device having a consistent memory ferroelectric material type or architecture in each memory cell.
  • a first memory cell allows for storage of a single bit of data and a second memory cell allows for storage of multiple bits of data.
  • a multi-bit ferroelectric memory may include, for example, one or more of the following ferroelectric materials:
  • SBTO Tin Bismuth Tantalate
  • Figure 1 is an illustration of a memory element including ferroelectric polarization utilizing one transistor and one ferroelectric capacitor according to an embodiment.
  • a memory element 100 includes a transistor, shown as a field effect transistor
  • the memory element is structured as a transistor plus FE capacitor (IT + 1FE-CAP) memory, memory element 100 further including a ferroelectric trench capacitor 150 coupled to source or drain 120, the ferroelectric capacitor 150 including ferroelectric material 155 as a dielectric material between a first plate 160 (such as a heavily doped region in a hole formed for the trench capacitor to form a buried plate) and a second plate 165 (such as material deposited fill the interior of the capacitor).
  • the ferroelectric capacitor 150 is to polarize at a particular voltage, thus enabling the storage of a bit in the memory element.
  • FIG. 2 is an illustration of a memory element including ferroelectric polarization utilizing one ferroelectric transistor according to an embodiment.
  • a memory element 200 is structured as a transistor plus FE material (1 FE-FET) memory, the memory element 200 including a transistor 200, shown as a field effect transistor with a source or drain terminal 215 and a source or drain terminal 220, together with a gate terminal 225 (shown as gate metal) on a ferroelectric material layer 255, the ferroelectric material being coupled to or integrated with the gate terminal, the ferroelectric material layer being between the gate terminal 225 and an oxide layer 230 above the semiconductor material 235.
  • the ferroelectric material layer 255 is to polarize at a particular voltage, thus enabling the storage of a bit in the memory element.
  • the memory elements illustrated in Figures 1 and 2 are structured as multi-bit memory cells through the implementation of multiple polarization voltages.
  • the multiple polarization voltages are provided by ferroelectric material with differing polarization characteristics, material architectures, or fabrication processes, or a combination of such factors. For example, adjustment of polarization voltage may be adjusted by one or more of the following factors:
  • Figure 3 is an illustration of characteristics of a multiple bit ferroelectric memory material construction according to an embodiment.
  • the ferroelectric material is constructed as illustrated in, for example, Figures 4 through 6 to provide multiple polarization levels. In this illustration, four polarization levels are shown. As illustrated in
  • a first ferroelectric material portion may switch polarization at a lower voltage, shown as +Vwl and -Vwl, and a second ferroelectric material portion may switch polarization at a second, higher voltage, shown as +Vw2 and -Vw2.
  • the multi-level polarization allows for the storage of two bits per memory unit cell, thereby potentially doubling the density of a memory device.
  • processes for writing bits to a multi-bit memory include one or more of applying a first polarization voltage to set a first bit to a first value; applying a second polarization voltage to set the first and second bits to the first value; applying an inverse of the first polarization voltage to set the first bit to a second value; or applying an inverse of the second polarization voltage to set the first and second bits to the second value.
  • a FE memory includes more than one bit per cell. By enabling more than 1 bit per cell, the density of the FE cells may be multiplied. To provide for multiple bits per cells, a clear differentiation between different memory states is provided.
  • the differentiation between memory states includes portions of FE materials having differing polarization voltages, such as a first FE material portion to polarize at a first write voltage and a second FE material portion to polarize at a second write voltage, wherein the first write voltage is greater than the second write voltage, thereby creating multiple memory states in a single memory cell.
  • the differing polarization voltages of the FE material portions being created by differing polarization characteristics, material
  • Figure 4 illustrates ferroelectric material for a memory unit cell including ferroelectric materials having differing polarization characteristics according to an embodiment.
  • an FE material structure 400 for a memory cell includes multiple FE material portions, including at least a first FE material portion 455 and a second FE material portion 457, which are illustrated as being between a first material 425, such as first terminal or other material, and a second material 427, such as a second terminal or other material.
  • the FE memory cell 400 includes the first FE material portion 455 including a first FE layer composed of a first FE material having a first critical field (Ec) value
  • the memory cell includes two separate types of FE materials with different critical fields so that such FE materials are polarized at different write voltages.
  • Figure 4 illustrates the first FE layer and second FE layer arranged in series, i.e., as a series connection of the FE material elements.
  • first FE layer and second FE layer are arranged side by side to provide a parallel connection through the FE material portions.
  • the FE layers are illustrated as being of similar thicknesses, but embodiments are not limited to any particular thickness of the differing FE materials.
  • Figure 5 illustrates ferroelectric material for a memory unit cell including a ferroelectric material with multiple different thicknesses according to an embodiment.
  • an FE material structure 500 for a memory cell includes a first FE material portion 550 including a first FE layer having a first thickness and a second FE material portion 557 including a second FE layer having a second thickness, the first thickness being greater than the second thickness.
  • the first FE material portion 550 is illustrated as being between a first material 525, such as a first terminal or other material, and a second material 527, such as a second terminal or other material
  • the second FE material portion 557 is illustrated as being between a first material 530, such as a first terminal or other material, and a second material 532, such as a second terminal or other material.
  • the first and second material portions 550-557 may be composed of the same type of FE material.
  • the critical voltage of the layers will be different from each other although the layers are fabricated using the same FE material.
  • FE elements 550 and 557 provide different critical voltages due to different material composition or processing conditions.
  • material 550 may be annealed at a first temperature (e.g. 500° C) and a second material 557 may be annealed at a second temperature (600° C).
  • FE elements 550 and 557 although illustrated in Figure 5 as having differing thicknesses, may instead have similar or equal thicknesses.
  • Figure 6 illustrates ferroelectric material for a memory unit cell including ferroelectric material capacitors with different thicknesses according to an embodiment.
  • a memory cell may include an FE capacitor structure 600 over a bit line, the FE capacitor structure including multiple capacitors with differing FE material thicknesses.
  • a memory cell may be such as illustrated in Figure 1, wherein the FE capacitor structure is coupled with a terminal of the transistor being coupled with the multiple capacitors.
  • the FE capacitor structure 600 includes a first FE material portion 655 composed of an FE material with a first thickness (forming a first trench capacitor) and a second FE material portion 657 composed of the FE material with a second thickness (forming a second trench capacitor), wherein the first thickness is thinner than the second thickness.
  • the first FE material portion has a polarization voltage that is lower than the polarization voltage of the second FE material portion. Also illustrated is a first plate 660 surrounding the first FE material portion 655 (the thin FE material) and the second FE material portion (the thick FE material) and a second plate 665 filling the interior of the capacitor.
  • the first capacitor formed with the first FE material portion 655 and the second capacitor formed with the second FE material portion 657 are connected in parallel, thereby forming a device providing two different polarization voltage magnitudes.
  • the first ferroelectric material portion 655 and the second ferroelectric material portion 657 include FE material providing different polarization voltages due to differences in material composition or processing conditions.
  • FE elements 655 and 657 although illustrated in Figure 6 as having differing thicknesses, may instead have similar or equal thicknesses.
  • Figure 7 is an illustration of a process for read and write operations for a multi-bit ferroelectric memory according to an embodiment.
  • a memory cell of the multi- bit ferroelectric memory includes a first FE material portion with a first polarization voltage and a second FE material portion with a second polarization voltage, the memory cell allowing for storage of two bits of data in a single memory unit cell.
  • a process for operation of a multi-bit ferroelectric memory 700 includes the following: 705: Receive a write command for a multi-bit ferroelectric memory.
  • the memory may include ferroelectric material with differing polarization characteristics, material architectures, or fabrication processes, or a combination of such factors, such as illustrated in Figures 4 through 6.
  • the memory may be structured as a transistor plus FE capacitor (IT + 1FE-CAP, such as generally illustrated in Figure 1) or as a transistor with FE material (1FE-FET, such as generally illustrated in Figure 2).
  • reading the bits of data stored in the memory unit cell may include comparing a detected voltage value (V) to certain voltage threshold values (VI, V2, and V3 in this example, wherein VI ⁇ V2 ⁇ V3).
  • V detected voltage value
  • VI V2
  • V3 certain voltage threshold values
  • the data values may be determined as:
  • Figure 8 is an illustration of a system on chip including a multi-bit ferroelectric memory according to an embodiment.
  • a system on chip (SoC) 800 includes:
  • CPU central processing unit
  • other processing element 810 for the processing of data.
  • a graphics processing unit (GPU) 820 to create images for output to a display.
  • a memory 830 may include random access memory (RAM) or other dynamic storage device or element as a main memory for storing information and instructions to be executed by a CPU 810 and GPU 820.
  • Main memory may include, but is not limited to, dynamic random access memory (DRAM).
  • memory 830 includes a multi-bit FE memory 835.
  • the multi-bit FE memory 835 may include ferroelectric material with differing polarization characteristics, material architectures, or fabrication processes, or a combination of such factors, such as illustrated in Figures 4 through 6.
  • the memory may be structured as a transistor plus FE capacitor (IT + 1FE-CAP, such as generally illustrated in Figure 1) or as a transistor with FE material (1FE-FET, such as generally illustrated in Figure 2).
  • Memory 830 may further include a non-volatile memory, such as flash memory, and a read only memory (ROM) or other static storage device for storing static information and instructions for the CPU 810 and GPU 820.
  • ROM read only memory
  • a Northbridge 840 to handle communications between the CPU 810 and other component of the SoC.
  • the SoC 800 may further include a Southbridge 850 to handle I/O functions.
  • Wireless communication includes, but is not limited to, Wi-Fi, BluetoothTM, near field communication, and other wireless communication standards.
  • the one or more antennas include one or more dipole, monopole, or other antennas.
  • a multi-bit memory device includes a transistor element; and a plurality of ferroelectric material portions coupled to or integrated with a terminal of the transistor element, the ferroelectric material portions including at least: a first ferroelectric material portion having a first polarization voltage, and a second ferroelectric material portion having a second polarization voltage, the second polarization voltage being different than the first polarization voltage.
  • the plurality of ferroelectric material portions are coupled to a source or drain of the transistor element to form a lT+lFE-CAP (transistor plus ferroelectric capacitor) memory.
  • the plurality of ferroelectric material portions are coupled to or integrated with a gate terminal of the transistor element to form a 1FE-FET (transistor plus ferroelectric material) memory.
  • the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following: polarization characteristics; material architectures; or fabrication processes.
  • the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following: ferroelectric material type; ferroelectric material doping type and doping amount; ferroelectric material thickness; annealing temperature, time, or both between the deposition of the first ferroelectric material portion and the second ferroelectric material portion; underlayer oxide type and thickness; or stress induced by top and bottom metal contact materials.
  • the first ferroelectric material portion includes a first type of ferroelectric material and the second ferroelectric material portion includes a second type of ferroelectric material, a critical voltage value of the first type of ferroelectric material being different than a critical voltage value of the second type of ferroelectric material.
  • the first ferroelectric material portion and the second ferroelectric material portion are connected in series.
  • the first ferroelectric material portion and the second ferroelectric material portion are connected in parallel.
  • the first ferroelectric material portion includes a first layer of ferroelectric material and the second ferroelectric material portion includes a second layer of ferroelectric material.
  • the first ferroelectric material portion and second ferroelectric material portion include a same first type of ferroelectric material, wherein the first ferroelectric material portion includes a first thickness of the first type of ferroelectric material and the second ferroelectric material portion includes a second thickness of the first type of ferroelectric material, the first thickness and the second thickness being different.
  • the first ferroelectric material portion and the second ferroelectric material portion are connected in parallel.
  • the first ferroelectric material portion is a first layer of ferroelectric material and the second ferroelectric material portion is a second layer of ferroelectric material.
  • the first ferroelectric material portion includes a first ferroelectric capacitor and the second ferroelectric material portion includes a second ferroelectric capacitor.
  • the first ferroelectric material portion and the second ferroelectric material portion include one or more of the following ferroelectric materials: PZTO (Lead Zirconium Titanate); SBTO (Strontium Bismuth Tantalate); SBO (Strontium Boron Oxide); BTO (Barium Titanate); BFO (Bismuth Ferrite); Hf(x)Zr(l-x)0 (Halfnium Zirconium Oxide); Hf (Hafnium) doped with silicon; or Hf doped with Al (aluminum).
  • a method includes: receiving a write command for a multi-bit ferroelectric memory, the multi-bit ferroelectric memory including a first ferroelectric material portion with a first polarization voltage and a second ferroelectric material portion with a second polarization voltage, the first polarization voltage being smaller than the second polarization voltage; writing at least first and second bits of write data to a memory unit cell of the multi-bit ferroelectric using the first and second voltage polarization voltages to activate polarization of the first and second ferroelectric material portions as required for the write data; receiving a read command to retrieve data from the multi-bit ferroelectric memory; and reading the memory unit cell, wherein reading the memory unit cell includes comparing a voltage to certain voltage states produced by the multi-bit ferroelectric memory based on a polarization state of the first ferroelectric material portion and a polarization state of the second ferroelectric material portion.
  • writing the first and second bits of data to the memory unit cell includes one or more of: applying the first polarization voltage to set a first bit to a first value; applying the second polarization voltage to set the first and second bits to the first value;
  • the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following: polarization characteristics; material architectures; or fabrication processes.
  • a system on chip includes: a processor for processing of data; a memory for storage of data, the memory including dynamic random access memory (DRAM) and non-volatile flash memory; and a transmitter or receiver for transmission or reception of data.
  • the memory includes a plurality of ferroelectric material portions, the plurality of ferroelectric material portions including at least: a first ferroelectric material portion having a first polarization voltage, and a second ferroelectric material portion having a second polarization voltage, the second polarization voltage being different than the first polarization voltage.
  • the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following: polarization characteristics; material architectures; or fabrication processes.
  • the first ferroelectric material portion includes a first type of ferroelectric material and the second ferroelectric material portion includes a second type of ferroelectric material, a critical voltage value of the first type of ferroelectric material being different than a critical voltage value of the second type of ferroelectric material.
  • the first ferroelectric material portion and the second ferroelectric material portion are connected in series.
  • the first ferroelectric material portion and the second ferroelectric material portion are connected in parallel.
  • the first ferroelectric material portion includes a first layer of ferroelectric material and the second ferroelectric material portion includes a second layer of ferroelectric material.
  • the first ferroelectric material portion and second ferroelectric material portion include a same first type of ferroelectric material, wherein the first ferroelectric material portion includes a first thickness of the first type of ferroelectric material and the second ferroelectric material portion includes a second thickness of the first type of ferroelectric material, the first thickness and the second thickness being different.
  • the first ferroelectric material portion and the second ferroelectric material portion are connected in parallel.
  • the first ferroelectric material portion is a first layer of ferroelectric material and the second ferroelectric material portion is a second layer of ferroelectric material.
  • the first ferroelectric material portion includes a first ferroelectric capacitor and the second ferroelectric material portion includes a second ferroelectric capacitor.
  • Various embodiments may include various processes. These processes may be performed by hardware components or may be embodied in computer program or machine- executable instructions, which may be used to cause a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the processes.
  • the processes may be performed by a combination of hardware and software.
  • Portions of various embodiments may be provided as a computer program product, which may include a computer-readable medium having stored thereon computer program instructions, which may be used to program a computer (or other electronic devices) for execution by one or more processors to perform a process according to certain embodiments.
  • the computer-readable medium may include, but is not limited to, magnetic disks, optical disks, read-only memory
  • ROM read only memory
  • RAM random access memory
  • EPROM erasable programmable read-only memory
  • EEPROM electrically-erasable programmable read-only memory
  • magnetic or optical cards flash memory, or other type of computer-readable medium suitable for storing electronic instructions.
  • embodiments may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer to a requesting computer.
  • Many of the methods are described in their most basic form, but processes can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present embodiments. It will be apparent to those skilled in the art that many further modifications and adaptations can be made.
  • the particular embodiments are not provided to limit the concept but to illustrate it. The scope of the embodiments is not to be determined by the specific examples provided above but only by the claims below.
  • element A may be directly coupled to element B or be indirectly coupled through, for example, element C.
  • a component, feature, structure, process, or characteristic A “causes” a component, feature, structure, process, or characteristic B, it means that "A” is at least a partial cause of "B” but that there may also be at least one other component, feature, structure, process, or characteristic that assists in causing "B.”
  • the specification indicates that a component, feature, structure, process, or characteristic "may”, “might”, or “could” be included, that particular component, feature, structure, process, or characteristic is not required to be included. If the specification or claim refers to "a” or “an” element, this does not mean there is only one of the described elements.
  • An embodiment is an implementation or example.
  • Reference in the specification to "an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments.
  • the various appearances of "an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. It should be appreciated that in the foregoing description of exemplary embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various novel aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed

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Abstract

Embodiments are generally directed to a multi-bit ferroelectric memory. An embodiment of a multi-bit memory device includes a transistor element; and multiple ferroelectric material portions coupled to or integrated with a terminal of the transistor element, the ferroelectric material portions including at least a first ferroelectric material portion having a first polarization voltage, and a second ferroelectric material portion having a second polarization voltage, the second polarization voltage being different than the first polarization voltage.

Description

MULTI-BIT FERROELECTRIC MEMORY
TECHNICAL FIELD
Embodiments described herein generally relate to the field of electronic devices and, more particularly, multi-bit ferroelectric memory.
BACKGROUND
In microelectronic devices, the density of embedded memory can be an important factor in the ability to further scale microelectronics.
In particular, dense embedded memory that does not include a requirement for large capacitors and low signal sensing voltage are needed for scaled technology generations.
Ferroelectric memories are one approach to future dense memories.
However, ferroelectric memory is still limited in that, as with most memory architectures, the memory is limited to a single bit per unit cell. Having the capacity to store more than 1 bit per unit cell would improve memory density significantly, increasing performance and lowering cost of the chips.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments described here are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
Figure 1 is an illustration of a memory element including ferroelectric polarization utilizing one transistor and one ferroelectric capacitor according to an embodiment;
Figure 2 is an illustration of a memory element including ferroelectric polarization utilizing one ferroelectric transistor according to an embodiment;
Figure 3 is an illustration of characteristics of a multiple bit ferroelectric memory material construction according to an embodiment;
Figure 4 illustrates ferroelectric material for a memory unit cell including ferroelectric materials having differing polarization characteristics according to an embodiment;
Figure 5 illustrates ferroelectric material for a memory unit cell including a ferroelectric material with multiple different thicknesses according to an embodiment;
Figure 6 illustrates ferroelectric material for a memory unit cell including ferroelectric material capacitors with different thicknesses according to an embodiment;
Figure 7 is an illustration of a process for read and write operations for a multi-bit ferroelectric memory according to an embodiment; and Figure 8 is an illustration of a system on chip including a multi-bit ferroelectric memory according to an embodiment.
DETAILED DESCRIPTION
Embodiments described herein are generally directed to multi-bit ferroelectric memory.
For the purposes of this description:
"Ferroelectric material" or "FE material" refers to a material that provides a high level of electric polarization, wherein the polarization may be reversed by the application of a sufficient external electric field.
"Critical electric field" refers an electric field required to begin switching the polarization of a particular ferroelectric material.
"Critical voltage" refers to a voltage required to begin switching the polarization of a particular ferroelectric material.
"Polarization voltage" refers to a voltage required to fully switch the polarization of a particular ferroelectric material to a desired polarization level. As used herein, a polarization voltage associated with a low polarization state should be higher than the critical voltage of a low polarization state but lower than the critical voltage of a higher polarization state.
In some embodiments, a multi-bit ferroelectric memory is implemented using multiple- voltage write characteristics through application of differing FE materials, FE material architecture, of both to provide a high density computer memory, including high density eDRAM (embedded Dynamic Random Access Memory).
To continue the pace of improvements in microelectronic performance, computer memory needs to be scalable to smaller sizes. Ferroelectric memories, particularly memory architectures using new thin FE materials, provide a promising memory option for the future. In a particular configuration, FE memories may be expected to have a density that is three times denser than a standard SRAM cell, and be comparable to a 1T+1C (one-transistor one-capacitor) DRAM cell.
However, density of individual memory cells remains a critical parameter, and conventional concepts of ferroelectric memory continue to be limited to a single bit of data in each memory cell. There are great potential advantages connected with an increase in the number of bits that may be stored in each memory unit cell. The cost of memory may be essentially cut in half if it is possible to double the density of the memory.
In some embodiments, a multi-bit FE memory architecture improves upon conventional FE memories by increasing the memory density through a capability of storing multiple bits per unit cell. In some embodiments, the multi-bit FE memory includes multiple polarization levels, wherein additional polarization levels allow for a storage of additional bits of memory. In general, two polarization levels (as in a conventional memory) may enable one bit of memory; four polarization levels enable two bits of memory; and eight polarization may enable three bits of memory. However, other embodiments utilizing different numbers of polarization levels are possible. In this manner, the density of the memory utilizing an embodiment of multi-bit ferroelectric architecture may be a multiple of the density of ferroelectric memory having a conventional architecture.
In some embodiments, by implementing one or more ferroelectric material portions such that there are clear multiple polarization levels, the resulting FE memory may be addressed using different voltage levels during a write cycle, thereby allowing for storage of multiple bits of data in a single unit cell.
In some embodiments, a multi-bit FE memory cell may store a non-integer number of bits. For example, in some embodiments, a multi-bit FE memory cell may store greater than two polarization levels but fewer than four. Thus, this memory cell stores greater than one bit of data but fewer than two bits of data.
The figures and descriptions herein generally refer to four polarization levels in a memory unit cell, thereby allowing for storage of 2 bits of data in each memory unit cell.
However, it is noted that embodiments are not limited to such an implementation, and may for example include storage of more than 2 bits of data in a memory unit cell through
implementation of more than 2 ferroelectric material portions in the unit cell.
Further, embodiments are not limited to a memory device having a consistent memory ferroelectric material type or architecture in each memory cell. For example, in some embodiments a first memory cell allows for storage of a single bit of data and a second memory cell allows for storage of multiple bits of data.
In some embodiments, a multi-bit ferroelectric memory may include, for example, one or more of the following ferroelectric materials:
(a) PZTO (Lead Zirconium Titanate);
(b) SBTO (Strontium Bismuth Tantalate);
(c) SBO (Strontium Boron Oxide);
(d) BTO (Barium Titanate);
(e) BFO (Bismuth Ferrite);
(f) Hf(x)Zr(l-x)0 (Halfnium Zirconium Oxide);
(g) Hf (Hafnium) doped with silicon; or
(h) Hf doped with Al (aluminum)
There are multiple approaches that may be utilized to use ferroelectric polarization to implement a memory device. Two of such approaches are shown in Figures 1 and 2. Figure 1 is an illustration of a memory element including ferroelectric polarization utilizing one transistor and one ferroelectric capacitor according to an embodiment. In some embodiments, a memory element 100 includes a transistor, shown as a field effect transistor
(FET) 110 with a source or drain terminal 115, a source or drain terminal 120, and a gate terminal 125 on an oxide layer 130 above semiconductor material 135. In some embodiments, the memory element is structured as a transistor plus FE capacitor (IT + 1FE-CAP) memory, memory element 100 further including a ferroelectric trench capacitor 150 coupled to source or drain 120, the ferroelectric capacitor 150 including ferroelectric material 155 as a dielectric material between a first plate 160 (such as a heavily doped region in a hole formed for the trench capacitor to form a buried plate) and a second plate 165 (such as material deposited fill the interior of the capacitor). The ferroelectric capacitor 150 is to polarize at a particular voltage, thus enabling the storage of a bit in the memory element.
Figure 2 is an illustration of a memory element including ferroelectric polarization utilizing one ferroelectric transistor according to an embodiment. In some embodiments, a memory element 200 is structured as a transistor plus FE material (1 FE-FET) memory, the memory element 200 including a transistor 200, shown as a field effect transistor with a source or drain terminal 215 and a source or drain terminal 220, together with a gate terminal 225 (shown as gate metal) on a ferroelectric material layer 255, the ferroelectric material being coupled to or integrated with the gate terminal, the ferroelectric material layer being between the gate terminal 225 and an oxide layer 230 above the semiconductor material 235. The ferroelectric material layer 255 is to polarize at a particular voltage, thus enabling the storage of a bit in the memory element.
In some embodiments, the memory elements illustrated in Figures 1 and 2 are structured as multi-bit memory cells through the implementation of multiple polarization voltages. In some embodiments, the multiple polarization voltages are provided by ferroelectric material with differing polarization characteristics, material architectures, or fabrication processes, or a combination of such factors. For example, adjustment of polarization voltage may be adjusted by one or more of the following factors:
(a) FE material type;
(b) FE material doping type and doping amount;
(c) FE material thickness;
(d) Annealing temperature/time difference between the deposition of a first FE material portion and a second ferroelectric material portion;
(e) Underlayer oxide type and thickness, wherein the underlayer is below the ferroelectric layers; or (f) Stress induced by changing the top and bottom metal contact materials.
Figure 3 is an illustration of characteristics of a multiple bit ferroelectric memory material construction according to an embodiment. In some embodiments, the ferroelectric material is constructed as illustrated in, for example, Figures 4 through 6 to provide multiple polarization levels. In this illustration, four polarization levels are shown. As illustrated in
Figure 3, a first ferroelectric material portion may switch polarization at a lower voltage, shown as +Vwl and -Vwl, and a second ferroelectric material portion may switch polarization at a second, higher voltage, shown as +Vw2 and -Vw2. In some embodiments, the multi-level polarization allows for the storage of two bits per memory unit cell, thereby potentially doubling the density of a memory device.
In some embodiments, processes for writing bits to a multi-bit memory include one or more of applying a first polarization voltage to set a first bit to a first value; applying a second polarization voltage to set the first and second bits to the first value; applying an inverse of the first polarization voltage to set the first bit to a second value; or applying an inverse of the second polarization voltage to set the first and second bits to the second value.
For example, utilizing the polarization voltages illustrated in Figure 3 assuming a first data value of '00', application of +Vwl transitions a memory unit cell to Ό ; application of +Vw2 transitions the memory unit cell to ' 11 '; application of application of -Vwl (after application of +Vw2) transitions the memory unit cell to ΊΟ', thus allowing a full two bits of data to be stored in the unit cell; and application of -Vw2 transitions the memory unit cell to '00'.
In some embodiments, a FE memory includes more than one bit per cell. By enabling more than 1 bit per cell, the density of the FE cells may be multiplied. To provide for multiple bits per cells, a clear differentiation between different memory states is provided. In some embodiments, the differentiation between memory states includes portions of FE materials having differing polarization voltages, such as a first FE material portion to polarize at a first write voltage and a second FE material portion to polarize at a second write voltage, wherein the first write voltage is greater than the second write voltage, thereby creating multiple memory states in a single memory cell. In some embodiments, the differing polarization voltages of the FE material portions being created by differing polarization characteristics, material
architectures, or fabrication processes, or a combination of such factors. In some embodiments, the differentiation between memory states may be implemented as illustrated in Figures 4 through 6. In some embodiments, parallel connection of two FE layers with a same FE material with different thicknesses or use of different FE materials with different critical electric-field values may be utilized to enable multi-bit operation. Figure 4 illustrates ferroelectric material for a memory unit cell including ferroelectric materials having differing polarization characteristics according to an embodiment. In some embodiments, an FE material structure 400 for a memory cell includes multiple FE material portions, including at least a first FE material portion 455 and a second FE material portion 457, which are illustrated as being between a first material 425, such as first terminal or other material, and a second material 427, such as a second terminal or other material.
In some embodiments, the FE memory cell 400 includes the first FE material portion 455 including a first FE layer composed of a first FE material having a first critical field (Ec) value
(the polarization characteristic), and the second FE material portion 457 including a second FE layer composed of a second FE material having a second critical field value, wherein the second critical field value is higher than the first critical field value. In some embodiments, the memory cell includes two separate types of FE materials with different critical fields so that such FE materials are polarized at different write voltages.
Figure 4 illustrates the first FE layer and second FE layer arranged in series, i.e., as a series connection of the FE material elements. However, embodiments are not limited to this structure. In an alternative embodiment, the first FE layer and second FE layer are arranged side by side to provide a parallel connection through the FE material portions. Further, for ease of illustration the FE layers are illustrated as being of similar thicknesses, but embodiments are not limited to any particular thickness of the differing FE materials.
Figure 5 illustrates ferroelectric material for a memory unit cell including a ferroelectric material with multiple different thicknesses according to an embodiment. In some embodiments, an FE material structure 500 for a memory cell includes a first FE material portion 550 including a first FE layer having a first thickness and a second FE material portion 557 including a second FE layer having a second thickness, the first thickness being greater than the second thickness. The first FE material portion 550 is illustrated as being between a first material 525, such as a first terminal or other material, and a second material 527, such as a second terminal or other material, and the second FE material portion 557 is illustrated as being between a first material 530, such as a first terminal or other material, and a second material 532, such as a second terminal or other material.
In some embodiments, the first and second material portions 550-557 may be composed of the same type of FE material. By using two different thicknesses in parallel (i.e., aligned next to each other to provide parallel connections through the two FE material portions), as illustrated in Figure 5, the critical voltage of the layers will be different from each other although the layers are fabricated using the same FE material. In some embodiments, FE elements 550 and 557 provide different critical voltages due to different material composition or processing conditions. For example, material 550 may be annealed at a first temperature (e.g. 500° C) and a second material 557 may be annealed at a second temperature (600° C). In some embodiments, FE elements 550 and 557, although illustrated in Figure 5 as having differing thicknesses, may instead have similar or equal thicknesses.
Figure 6 illustrates ferroelectric material for a memory unit cell including ferroelectric material capacitors with different thicknesses according to an embodiment. In some
embodiments, a memory cell may include an FE capacitor structure 600 over a bit line, the FE capacitor structure including multiple capacitors with differing FE material thicknesses. In some embodiments, a memory cell may be such as illustrated in Figure 1, wherein the FE capacitor structure is coupled with a terminal of the transistor being coupled with the multiple capacitors. In some embodiments, the FE capacitor structure 600 includes a first FE material portion 655 composed of an FE material with a first thickness (forming a first trench capacitor) and a second FE material portion 657 composed of the FE material with a second thickness (forming a second trench capacitor), wherein the first thickness is thinner than the second thickness. In this manner, the first FE material portion has a polarization voltage that is lower than the polarization voltage of the second FE material portion. Also illustrated is a first plate 660 surrounding the first FE material portion 655 (the thin FE material) and the second FE material portion (the thick FE material) and a second plate 665 filling the interior of the capacitor.
As illustrated in Figure 6, the first capacitor formed with the first FE material portion 655 and the second capacitor formed with the second FE material portion 657 are connected in parallel, thereby forming a device providing two different polarization voltage magnitudes.
In some embodiments, the first ferroelectric material portion 655 and the second ferroelectric material portion 657 include FE material providing different polarization voltages due to differences in material composition or processing conditions. In some embodiments, FE elements 655 and 657, although illustrated in Figure 6 as having differing thicknesses, may instead have similar or equal thicknesses.
Figure 7 is an illustration of a process for read and write operations for a multi-bit ferroelectric memory according to an embodiment. In this example, a memory cell of the multi- bit ferroelectric memory includes a first FE material portion with a first polarization voltage and a second FE material portion with a second polarization voltage, the memory cell allowing for storage of two bits of data in a single memory unit cell. In some embodiments, a process for operation of a multi-bit ferroelectric memory 700 includes the following: 705: Receive a write command for a multi-bit ferroelectric memory. In some
embodiments, the memory may include ferroelectric material with differing polarization characteristics, material architectures, or fabrication processes, or a combination of such factors, such as illustrated in Figures 4 through 6. In some embodiments, the memory may be structured as a transistor plus FE capacitor (IT + 1FE-CAP, such as generally illustrated in Figure 1) or as a transistor with FE material (1FE-FET, such as generally illustrated in Figure 2).
710: Write first and second bits of write data to a memory cell using first and second voltage levels to activate polarization of the first and second FE material portions as required for the write data.
715: Receive a read command to retrieve data from the multi-bit ferroelectric memory.
720: Read the memory unit cell utilizing multiple voltage levels produced by the memory because of the polarization states of the first and second FE material portions.
For example, in a particular implementation of a memory device, reading the bits of data stored in the memory unit cell may include comparing a detected voltage value (V) to certain voltage threshold values (VI, V2, and V3 in this example, wherein VI < V2 < V3). In this example, the data values may be determined as:
730: Upon determining 0 < V < VI, the data bits = '00' (735).
740: Upon determining Vl < V < V2, the data bits = '01 ' (745).
750: Upon determining V2 < V < V3, the data bits = ' 10' (755).
760: Upon determining V3 < V, the data bits = ' 11 ' (765).
Figure 8 is an illustration of a system on chip including a multi-bit ferroelectric memory according to an embodiment. In some embodiments, a system on chip (SoC) 800 includes:
(a) A central processing unit (CPU) or other processing element 810 for the processing of data.
(b) A graphics processing unit (GPU) 820 to create images for output to a display.
(c) A memory 830, where memory 830 may include random access memory (RAM) or other dynamic storage device or element as a main memory for storing information and instructions to be executed by a CPU 810 and GPU 820. Main memory may include, but is not limited to, dynamic random access memory (DRAM).
In some embodiments, memory 830 includes a multi-bit FE memory 835. In some embodiments, the multi-bit FE memory 835 may include ferroelectric material with differing polarization characteristics, material architectures, or fabrication processes, or a combination of such factors, such as illustrated in Figures 4 through 6. In some embodiments, the memory may be structured as a transistor plus FE capacitor (IT + 1FE-CAP, such as generally illustrated in Figure 1) or as a transistor with FE material (1FE-FET, such as generally illustrated in Figure 2). Memory 830 may further include a non-volatile memory, such as flash memory, and a read only memory (ROM) or other static storage device for storing static information and instructions for the CPU 810 and GPU 820.
(d) A Northbridge 840 to handle communications between the CPU 810 and other component of the SoC. In some embodiments, the SoC 800 may further include a Southbridge 850 to handle I/O functions.
(e) A transmitter, receiver, or both 860 for transmission and reception of data via wireless communications, and one or more antennas for transmission or reception of wireless communication. Wireless communication includes, but is not limited to, Wi-Fi, Bluetooth™, near field communication, and other wireless communication standards. The one or more antennas include one or more dipole, monopole, or other antennas.
(f) One or more interfaces 870, including USB (Universal Serial Bus), Firewire, Ethernet, or other interfaces. In some embodiments, a multi-bit memory device includes a transistor element; and a plurality of ferroelectric material portions coupled to or integrated with a terminal of the transistor element, the ferroelectric material portions including at least: a first ferroelectric material portion having a first polarization voltage, and a second ferroelectric material portion having a second polarization voltage, the second polarization voltage being different than the first polarization voltage.
In some embodiments, the plurality of ferroelectric material portions are coupled to a source or drain of the transistor element to form a lT+lFE-CAP (transistor plus ferroelectric capacitor) memory.
In some embodiments, the plurality of ferroelectric material portions are coupled to or integrated with a gate terminal of the transistor element to form a 1FE-FET (transistor plus ferroelectric material) memory.
In some embodiments, the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following: polarization characteristics; material architectures; or fabrication processes.
In some embodiments, the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following: ferroelectric material type; ferroelectric material doping type and doping amount; ferroelectric material thickness; annealing temperature, time, or both between the deposition of the first ferroelectric material portion and the second ferroelectric material portion; underlayer oxide type and thickness; or stress induced by top and bottom metal contact materials. In some embodiments, the first ferroelectric material portion includes a first type of ferroelectric material and the second ferroelectric material portion includes a second type of ferroelectric material, a critical voltage value of the first type of ferroelectric material being different than a critical voltage value of the second type of ferroelectric material.
In some embodiments, the first ferroelectric material portion and the second ferroelectric material portion are connected in series.
In some embodiments, the first ferroelectric material portion and the second ferroelectric material portion are connected in parallel.
In some embodiments, the first ferroelectric material portion includes a first layer of ferroelectric material and the second ferroelectric material portion includes a second layer of ferroelectric material.
In some embodiments, the first ferroelectric material portion and second ferroelectric material portion include a same first type of ferroelectric material, wherein the first ferroelectric material portion includes a first thickness of the first type of ferroelectric material and the second ferroelectric material portion includes a second thickness of the first type of ferroelectric material, the first thickness and the second thickness being different.
In some embodiments, the first ferroelectric material portion and the second ferroelectric material portion are connected in parallel.
In some embodiments, the first ferroelectric material portion is a first layer of ferroelectric material and the second ferroelectric material portion is a second layer of ferroelectric material.
In some embodiments, the first ferroelectric material portion includes a first ferroelectric capacitor and the second ferroelectric material portion includes a second ferroelectric capacitor.
In some embodiments, the first ferroelectric material portion and the second ferroelectric material portion include one or more of the following ferroelectric materials: PZTO (Lead Zirconium Titanate); SBTO (Strontium Bismuth Tantalate); SBO (Strontium Boron Oxide); BTO (Barium Titanate); BFO (Bismuth Ferrite); Hf(x)Zr(l-x)0 (Halfnium Zirconium Oxide); Hf (Hafnium) doped with silicon; or Hf doped with Al (aluminum).
In some embodiments, a method includes: receiving a write command for a multi-bit ferroelectric memory, the multi-bit ferroelectric memory including a first ferroelectric material portion with a first polarization voltage and a second ferroelectric material portion with a second polarization voltage, the first polarization voltage being smaller than the second polarization voltage; writing at least first and second bits of write data to a memory unit cell of the multi-bit ferroelectric using the first and second voltage polarization voltages to activate polarization of the first and second ferroelectric material portions as required for the write data; receiving a read command to retrieve data from the multi-bit ferroelectric memory; and reading the memory unit cell, wherein reading the memory unit cell includes comparing a voltage to certain voltage states produced by the multi-bit ferroelectric memory based on a polarization state of the first ferroelectric material portion and a polarization state of the second ferroelectric material portion.
In some embodiments, writing the first and second bits of data to the memory unit cell includes one or more of: applying the first polarization voltage to set a first bit to a first value; applying the second polarization voltage to set the first and second bits to the first value;
applying an inverse of the first polarization voltage to set the first bit to a second value; and applying an inverse of the second polarization voltage to set the first and second bits to the second value.
In some embodiments, the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following: polarization characteristics; material architectures; or fabrication processes.
In some embodiments, a system on chip includes: a processor for processing of data; a memory for storage of data, the memory including dynamic random access memory (DRAM) and non-volatile flash memory; and a transmitter or receiver for transmission or reception of data. In some embodiments, the memory includes a plurality of ferroelectric material portions, the plurality of ferroelectric material portions including at least: a first ferroelectric material portion having a first polarization voltage, and a second ferroelectric material portion having a second polarization voltage, the second polarization voltage being different than the first polarization voltage.
In some embodiments, the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following: polarization characteristics; material architectures; or fabrication processes.
In some embodiments, the first ferroelectric material portion includes a first type of ferroelectric material and the second ferroelectric material portion includes a second type of ferroelectric material, a critical voltage value of the first type of ferroelectric material being different than a critical voltage value of the second type of ferroelectric material.
In some embodiments, the first ferroelectric material portion and the second ferroelectric material portion are connected in series.
In some embodiments, the first ferroelectric material portion and the second ferroelectric material portion are connected in parallel.
In some embodiments, the first ferroelectric material portion includes a first layer of ferroelectric material and the second ferroelectric material portion includes a second layer of ferroelectric material. In some embodiments, the first ferroelectric material portion and second ferroelectric material portion include a same first type of ferroelectric material, wherein the first ferroelectric material portion includes a first thickness of the first type of ferroelectric material and the second ferroelectric material portion includes a second thickness of the first type of ferroelectric material, the first thickness and the second thickness being different.
In some embodiments, the first ferroelectric material portion and the second ferroelectric material portion are connected in parallel.
In some embodiments, the first ferroelectric material portion is a first layer of ferroelectric material and the second ferroelectric material portion is a second layer of ferroelectric material.
In some embodiments, the first ferroelectric material portion includes a first ferroelectric capacitor and the second ferroelectric material portion includes a second ferroelectric capacitor.
In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the described embodiments. It will be apparent, however, to one skilled in the art that embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form. There may be intermediate structure between illustrated components. The components described or illustrated herein may have additional inputs or outputs that are not illustrated or described.
Various embodiments may include various processes. These processes may be performed by hardware components or may be embodied in computer program or machine- executable instructions, which may be used to cause a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the processes.
Alternatively, the processes may be performed by a combination of hardware and software.
Portions of various embodiments may be provided as a computer program product, which may include a computer-readable medium having stored thereon computer program instructions, which may be used to program a computer (or other electronic devices) for execution by one or more processors to perform a process according to certain embodiments. The computer-readable medium may include, but is not limited to, magnetic disks, optical disks, read-only memory
(ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically-erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or other type of computer-readable medium suitable for storing electronic instructions. Moreover, embodiments may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer to a requesting computer. Many of the methods are described in their most basic form, but processes can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present embodiments. It will be apparent to those skilled in the art that many further modifications and adaptations can be made. The particular embodiments are not provided to limit the concept but to illustrate it. The scope of the embodiments is not to be determined by the specific examples provided above but only by the claims below.
If it is said that an element "A" is coupled to or with element "B," element A may be directly coupled to element B or be indirectly coupled through, for example, element C. When the specification or claims state that a component, feature, structure, process, or characteristic A "causes" a component, feature, structure, process, or characteristic B, it means that "A" is at least a partial cause of "B" but that there may also be at least one other component, feature, structure, process, or characteristic that assists in causing "B." If the specification indicates that a component, feature, structure, process, or characteristic "may", "might", or "could" be included, that particular component, feature, structure, process, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, this does not mean there is only one of the described elements.
An embodiment is an implementation or example. Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. It should be appreciated that in the foregoing description of exemplary embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various novel aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed
embodiments requires more features than are expressly recited in each claim. Rather, as the following claims reflect, novel aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims are hereby expressly incorporated into this description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS What is claimed is:
1. A multi-bit memory device comprising:
a transistor element; and
a plurality of ferroelectric material portions coupled to or integrated with a terminal of the transistor element, the ferroelectric material portions including at least:
a first ferroelectric material portion having a first polarization voltage, and a second ferroelectric material portion having a second polarization voltage, the second polarization voltage being different than the first polarization voltage.
2. The multi-bit memory device of claim 1, wherein the plurality of ferroelectric material portions are coupled to a source or drain of the transistor element to form a 1T+1FE-CAP (transistor plus ferroelectric capacitor) memory.
3. The multi-bit memory device of claim 1, wherein the plurality of ferroelectric material portions are coupled to or integrated with a gate terminal of the transistor element to form a 1FE- FET (transistor plus ferroelectric material) memory.
4. The multi-bit memory device of claim 1, wherein the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following: polarization characteristics;
material architectures; or
fabrication processes.
5. The multi-bit memory device of claim 4, wherein the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following: ferroelectric material type;
ferroelectric material doping type and doping amount;
ferroelectric material thickness;
annealing temperature, time, or both between the deposition of the first ferroelectric material portion and the second ferroelectric material portion;
underlayer oxide type and thickness; or
stress induced by top and bottom metal contact materials.
6. The multi-bit memory device of claim 1, wherein the first ferroelectric material portion includes a first type of ferroelectric material and the second ferroelectric material portion includes a second type of ferroelectric material, a critical voltage value of the first type of ferroelectric material being different than a critical voltage value of the second type of ferroelectric material.
7. The multi-bit memory device of claim 6, wherein the first ferroelectric material portion and the second ferroelectric material portion are connected in series.
8. The multi-bit memory device of claim 6, wherein the first ferroelectric material portion and the second ferroelectric material portion are connected in parallel.
9. The multi-bit memory device of claim 6, wherein the first ferroelectric material portion includes a first layer of ferroelectric material and the second ferroelectric material portion includes a second layer of ferroelectric material.
10. The multi-bit memory device of claim 1, wherein the first ferroelectric material portion and second ferroelectric material portion include a same first type of ferroelectric material, wherein the first ferroelectric material portion includes a first thickness of the first type of ferroelectric material and the second ferroelectric material portion includes a second thickness of the first type of ferroelectric material, the first thickness and the second thickness being different.
11. The multi-bit memory device of claim 10, wherein the first ferroelectric material portion and the second ferroelectric material portion are connected in parallel.
12. The multi-bit memory device of claim 10, wherein the first ferroelectric material portion is a first layer of ferroelectric material and the second ferroelectric material portion is a second layer of ferroelectric material.
13. The multi-bit memory device of claim 10, wherein the first ferroelectric material portion includes a first ferroelectric capacitor and the second ferroelectric material portion includes a second ferroelectric capacitor.
14. The multi-bit memory device of claim 1, wherein the first ferroelectric material portion and the second ferroelectric material portion include one or more of the following ferroelectric materials:
PZTO (Lead Zirconium Titanate);
SBTO (Strontium Bismuth Tantalate);
SBO (Strontium Boron Oxide);
BTO (Barium Titanate); BFO (Bismuth Ferrite);
Hf(x)Zr(l-x)0 (Halfnium Zirconium Oxide);
Hf (Hafnium) doped with silicon; or
Hf doped with Al (aluminum).
15. A method comprising:
receiving a write command for a multi-bit ferroelectric memory, the multi-bit ferroelectric memory including a first ferroelectric material portion with a first polarization voltage and a second ferroelectric material portion with a second polarization voltage, the first polarization voltage being smaller than the second polarization voltage;
writing at least first and second bits of write data to a memory unit cell of the multi-bit ferroelectric memory using the first and second voltage polarization voltages to activate polarization of the first and second ferroelectric material portions as required for the write data; receiving a read command to retrieve data from the multi-bit ferroelectric memory; and reading the memory unit cell, wherein reading the memory unit cell includes comparing a voltage to certain voltage states produced by the multi-bit ferroelectric memory based on a polarization state of the first ferroelectric material portion and a polarization state of the second ferroelectric material portion.
16. The method of claim 15, wherein writing the first and second bits of data to the memory unit cell includes one or more of:
applying the first polarization voltage to set a first bit to a first value;
applying the second polarization voltage to set the first and second bits to the first value; applying an inverse of the first polarization voltage to set the first bit to a second value; and
applying an inverse of the second polarization voltage to set the first and second bits to the second value.
17. The method of claim 15, wherein the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following:
polarization characteristics;
material architectures; or
fabrication processes.
18. A system on chip comprising:
a processor for processing of data; a memory for storage of data, the memory including dynamic random access memory
(DRAM) and non-volatile flash memory; and
a transmitter or receiver for transmission or reception of data;
wherein the memory includes a plurality of ferroelectric material portions, the plurality of ferroelectric material portions including at least:
a first ferroelectric material portion having a first polarization voltage, and a second ferroelectric material portion having a second polarization voltage, the second polarization voltage being different than the first polarization voltage.
19. The system on chip of claim 18, wherein the first ferroelectric material portion and the second ferroelectric material portion include differences in one or more of the following:
polarization characteristics;
material architectures; or
fabrication processes.
20. The system on chip of claim 18, wherein the first ferroelectric material portion includes a first type of ferroelectric material and the second ferroelectric material portion includes a second type of ferroelectric material, a critical voltage value of the first type of ferroelectric material being different than a critical voltage value of the second type of ferroelectric material.
21. The system on chip of claim 20, wherein the first ferroelectric material portion includes a first layer of ferroelectric material and the second ferroelectric material portion includes a second layer of ferroelectric material.
22. The system on chip of claim 18, wherein the first ferroelectric material portion and second ferroelectric material portion include a same first type of ferroelectric material, wherein the first ferroelectric material portion includes a first thickness of the first type of ferroelectric material and the second ferroelectric material portion includes a second thickness of the first type of ferroelectric material, the first thickness and the second thickness being different.
23. The system on chip of claim 22, wherein the first ferroelectric material portion is a first layer of ferroelectric material and the second ferroelectric material portion is a second layer of ferroelectric material.
24. The system on chip of claim 22, wherein the first ferroelectric material portion includes a first ferroelectric capacitor and the second ferroelectric material portion includes a second ferroelectric capacitor.
PCT/US2017/027939 2017-04-17 2017-04-17 Multi-bit ferroelectric memory WO2018194544A1 (en)

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