WO2018191967A1

WO2018191967A1 - Non-linear distortion mitigation for power amplifier

Info

Publication number: WO2018191967A1
Application number: PCT/CN2017/081478
Authority: WO
Inventors: Zhancang WANG
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2017-04-21
Filing date: 2017-04-21
Publication date: 2018-10-25

Abstract

Embodiments of the present disclosure relate to a radio frequency (RF) power amplifier (PA) and a corresponding method, device and computer readable storage medium. In example embodiments, an envelope control circuit is arranged in a modulator of a RF PA. The envelope control circuit senses an operating parameter associated with the RF PA. The operating parameter is related to at least one of a supply current, a supply voltage, an output voltage, and a load impedance associated with the RF PA. The envelope control circuit generates a first signal based on the sensed operating parameter and then generates a second signal for adjusting a bias or gain associated with the RF PA based on the first signal. Accordingly, a power transistor in the RF PA uses the second signal to generate an amplified RF signal. In this way, the memory effect distortions of the RF PA may be reduced.

Description

NON-LINEAR DISTORTION MITIGATION FOR POWER AMPLIFIER

TECHNICAL FIELD

Embodiments of the present disclosure generally relate to the field of telecommunication， and in particular， to nonlinear distortion mitigation for a radio frequency (RF) power amplifier (PA) and a corresponding RF PA， method， device， and computer readable storage medium.

BACKGROUND

Efficiency of a radio frequency (RF) power amplifier (PA) is a concern of designs for the RF PA， which may be generally defined as a ratio between a desired transmitting radio power of the RF PA and a total supply power for the RF PA. In wireless communications， in particular， in future wideband wireless communications， it is noted that even a little improvement in the efficiency of the PA may bring substantial profits to a wireless communication system， network device， or terminal.

Extensive efforts have been made for enhancing the efficiency of the RF PA in wireless communication infrastructure industries. Dynamic modulation， such as supply modulation and load modulation， has been developed for the RF PA. As example supply modulation techniques， Envelope Elimination and Restoration (EER) and Envelope tracking (ET) have been proposed for enhancement of the efficiency of the RF PA for the fifth generation (5G) . In addition， dynamic load modulation (DLM) has been proposed as a load modulation technique to provide high peak to average power ratio (PAPR) for the RF PA.

With the ET technique， an ET PA is generally more efficient. For example， a supply power applied to the ET PA may be constantly adjusted to ensure that the ET PA is operating at peak efficiency over an output power range. However， due to difficulties of implementations of the ET technique， an ET PA is not widely used for base station (BS) or user equipment (UE) in the wireless communications. Furthermore， the ET PA may typically be subject to severe memory effect distortions， which may bring great difficulties in designing linearization schemes for the ET PA. For example， such severe memory effect distortions may cause a PA behavioral model used in a conventional linearization scheme， such as digital pre-distortion (DPD) ， to be not precise enough for analyzing linearization compensations for the ET PA. As a result， the conventional model of the DPD may be unable to correctly model the ET PA.

In addition， a DLM PA employs a passive impedance tuner to dynamically control amplitude of an output signal of the PA. Compared with the ET PA， the DLM PA nearly does not consume a direct current (DC) power. Therefore， the DLM PA does not suffer from bandwidth versus efficiency limitations of the ET PA. Furthermore， circuit complexity of the DLM PA is relatively low because a matching network within the DLM PA is an integral part of an amplifier circuit. However， the DLM PA may be also subject to the severe memory effect distortions. Such severe memory effect distortions in both the ET and DLM PAs may significantly degrade the efficiency of the PA and further deteriorate performance of a PA system.

SUMMARY

In general， example embodiments of the present disclosure provide a RF PA and a corresponding method， device， and computer readable storage medium.

In a first aspect， a RF PA is provided. The RF PA includes a modulator. The modulator includes an envelope control circuit which is configured to： sense an operating parameter related to at least one of a supply current， a supply voltage， an output voltage， and a load impedance associated with the RF PA， generate a first signal based on the sensed operating parameter， and generate a second signal for adjusting a bias or gain associated with the RF PA based on the first signal. The RF PA also includes a power transistor configured to generate an amplified radio frequency signal based on the second signal.

In some embodiments， the modulator may be a supply modulator The envelope control circuit may be arranged between an output and an input of the power transistor The operating parameter may include a supply current of the power transistor， and the bias or gain associated with the radio frequency power amplifier may include an input bias of the power transistor

In some embodiments， the envelope control circuit may include： a current sensor configured to sense the supply current for the power transistor and generate the first signal having a first voltage level based on the sensed supply current； a level follower configured to convert the first signal into a third signal having a second voltage level， the first voltage level being greater than the second voltage level； a peak rectifier configured to detect a peak voltage level of the third signal； an attenuator configured to generate a biasing level based on the detected peak voltage level； and an actuator configured to generate the second signal for adjusting the input bias of the power transistor based on the biasing level.

In some embodiments， the RF PA may further include： an embedded controller configured to generate a fourth signal for digital proportion integral derivative， DPID， controlling of the radio frequency power amplifier based on the first signal.

In some embodiments， the first and fourth signals may be both analog signals. The embedded controller may include： an analog to digital converter configured to convert the first signal into a digital signal； a DPID block configured to generate a digital control signal for the DPID controlling based on the digital signal； and a digital to analog converter configured to convert the digital control signal into the fourth signal.

In some embodiments， the RF PA may further include： a junction node configured to combine the second and fourth signals.

In some embodiments， the modulator may further include a driver amplifier. The envelope control circuit may be arranged between an output and an input of the driver amplifier. The bias or gain associated with the radio frequency power amplifier may include a gain of the driver amplifier.

In some embodiments， the modulator may be a supply modulator. The operating parameter may include a supply current outputted by the driver amplifier， and the gain of the driver amplifier may include a current gain of the driver amplifier.

In some embodiments， the envelope control circuit may include： a current sensor configured to sense the supply current outputted by the driver amplifier and generate the first signal having a first voltage level based on the sensed supply current； a level follower configured to convert the first signal into a third signal having a second voltage level， the first voltage level being greater than the second voltage level； a peak rectifier configured to detect a peak voltage level of the third signal； an attenuator configured to generate a biasing level based on the detected peak voltage level； and an actuator configured to generate the second signal for adjusting the current gain of the driver amplifier based on the biasing level.

In some embodiments， the modulator may be a load modulator. The operating parameter may include an output voltage of the driver amplifier， and the gain of the driver amplifier may include a voltage gain of the driver amplifier. The load modulator may further include： a load impedance tuner configured to tune a load impedance of the power transistor based on the adjusted voltage gain of the driver amplifier.

In some embodiments， the envelope control circuit may include： a level follower configured to sense the output voltage of the driver amplifier， generate the first signal having a first voltage level， and convert the first signal into a third signal having a second voltage level， the first voltage level being greater than the second voltage level； a peak rectifier configured to detect a peak voltage level of the third signal； an attenuator configured to generate a biasing level based on the detected peak voltage level； and an actuator configured to generate the second signal for adjusting the voltage gain of the driver amplifier based on the biasing level.

In a second aspect， a method implemented in a RF PA is provided. The method comprises： sensing an operating parameter related to at least one of a supply current， a supply voltage， an output voltage， and a load impedance associated with the radio frequency power amplifier； generating a first signal based on the sensed operating parameter； generating a second signal for adjusting a bias or gain associated with the radio frequency power amplifier based on the first signal； and generating an amplified radio frequency signal based on the second signal.

In a third aspect， there is provided a device. The device comprises a processor and a memory. The memory contains instructions executable by the processor， whereby the device is operative to perform the method according to the second aspect.

In a fourth aspect， there is provided a computer readable storage medium tangibly storing a computer program. The computer program includes instructions which， when executed on at least one processor， cause the at least one processor to carry out the method according to the second aspect.

Through the following description， it would be appreciated that according to embodiments of the present disclosure， the envelope control circuit is provided to sense an operating parameter associated with the RF PA， to generate a signal based on the sensed operating parameter， and to generate a further signal for adjusting a bias or gain associated with the RF PA based on the first signal. Accordingly， the power transistor in the RF PA uses the second signal to generate an amplified RF signal. In this way， the memory effect distortions of the ET or DLM PA may be greatly reduced.

It is to be understood that the summary section is not intended to identify key or essential features of embodiments of the present disclosure， nor is it intended to be used to limit the scope of the present disclosure. Other features of the present disclosure will become easily comprehensible through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

Through the more detailed description of some embodiments of the present disclosure in the accompanying drawings， the above and other objects， features and advantages of the present disclosure will become more apparent， wherein：

Fig. 1 shows a diagrams of a circuit of an EER PA；

Fig. 2 shows a diagrams of a circuit of an ET PA；

Fig. 3 shows a diagram of a circuit of a DLM PA；

Fig. 4 shows inherent memory effects in the ET PA by observing the efficiency scattering effects；

Figs. 5 (a) and 5 (b) show linearization performance limitations of the DPD on its inherent memory effects in the ET PA；

Fig. 6 shows a block diagram of a RF PA in accordance with some embodiments of the present disclosure；

Fig. 7 shows a block diagram of a RF PA in accordance with some other embodiments of the present disclosure；

Fig. 8 shows a block diagram of the RF PA in accordance with yet other embodiments of the present disclosure；

Figs. 9 (a) -9 (d) show simulation results of the envelope control circuit in accordance with some embodiments of the present disclosure；

Fig. 10 shows example implementations of the envelope control circuit in accordance with some embodiments of the present disclosure；

Fig. 11 shows a flowchart of a method in accordance with some embodiments of the present disclosure；

Fig. 12 shows a flowchart of a method in accordance with some other embodiments of the present disclosure；

Fig. 13 shows a block diagram of an apparatus in accordance with some embodiments of the present disclosure； and

Fig. 14 shows a simplified block diagram of a device that is suitable for implementing embodiments of the present disclosure.

Throughout the drawings， the same or similar reference numerals represent the same or similar element.

DETAILED DESCRIPTION

Hereinafter， principle and spirit of the present disclosure will now be described with reference to some example embodiments. It is to be understood that these embodiments are described only for the purpose of illustration and help those skilled in the art to understand and implement the present disclosure， without suggesting any limitations as to the scope of the disclosure. The disclosure described herein can be implemented in various manners other than the ones described below. For example， features illustrated or described as a part of one embodiment may be used with another embodiment to yield still a further embodiment. In the interest of clarity， not all features of an actual implementation are described in this specification.

References in the specification to “one embodiment” ， “an embodiment” ， “example embodiment” ， and the like indicate that the embodiment described may include a particular feature， structure， or characteristic， but it is not necessary that every embodiment includes the particular feature， structure， or characteristic. Moreover， such phrases are not necessarily referring to the same embodiment. Further， when a particular feature， structure， or characteristic is described in connection with an embodiment， it is submitted that it is within the knowledge of one skilled in the art to affect such feature， structure， or characteristic in connection with other embodiments whether or not explicitly described.

It shall be understood that although the terms “first” and “second” and the like may be used herein to describe various elements， these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example， a first element could be termed a second element， and similarly， a second element could be termed a first element， without departing from the scope of example embodiments. As used herein， the term “and/or” includes any and all combinations of one or more of the associated listed terms.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be liming of example embodiments. As used herein， the singular forms “a” ， “an” and “the” are intended to include the plural forms as well， unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” ， “comprising” ， “has” ， “having” ， “includes” and/or “including” ， when used herein， specify the presence of stated features， elements， and/or components and the like， but do not preclude the presence or addition of one or more other features， elements， components and/or combinations thereof.

In the following description and claims， unless defined otherwise， all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skills in the art to which this disclosure belongs.

As used herein， the term “communication device” refers to any device capable of transmitting and receiving radio signal in a wireless communication network. Examples of the communication device may include a network device， a terminal device， and the like.

The term “network device” refers to a device in a wireless communication network via which a terminal device accesses the network and receives services. The network device refers a base station (BS) ， an access point (AP) ， a gateway， a server， a controller or any other suitable device in the wireless communication network. The BS may be， for example， a node B (NodeB or NB) ， an evolved NodeB (eNodeB or eNB) ， a gNB， a Remote Radio Unit (RRU) ， a radio header (RH) ， a remote radio head (RRH) ， a relay， a low power node such as a femto， a pico， and the like， depending on the applied terminology and technology.

Yet further examples of the network device include multi-standard radio (MSR) radio equipment such as MSR BSs， network controllers such as radio network controllers (RNCs) or base station controllers (BSCs) ， base transceiver stations (BTSs) ， transmission points， transmission nodes， Multi-cell/Multicast Coordination Entities (MCEs) ， core network nodes， such as Mobile Management Entities (MMEs) and Mobile Switching Centers (MSCs) ， Operation and Maintenance (O&M) nodes， Operation Support System (OSS) nodes， Self-Organizing Network (SON) nodes， positioning nodes， such as Enhanced Serving Mobile Location Centers (E-SMLCs) ， and/or Mobile Data Terminals (MDTs) . More generally， however， the network device may represent any suitable device (or group of devices) capable， configured， arranged， and/or operable to enable and/or provide an access to the wireless communication network for the terminal device or to provide some services to the terminal device that has accessed the wireless communication network.

As used herein， “terminal device” refers to a device capable， configured， arranged and/or operable to communicate wirelessly with the network device and/or another terminal device. Wireless communications may involve transmission and/or reception of wireless signals such as electromagnetic signals， radio waves， infrared signals， and/or other types of signals suitable for conveying information through air. In particular embodiments， the terminal device may be configured to transmit and/or receive information without direct human interaction. For instance， the terminal device may be designed to transmit information to the network on a predetermined schedule， when triggered by an internal or external event， or in response to requests from the network. Generally， the terminal device may represent any device capable of， configured for， arranged for， and/or operable for wireless communication with， for example， the network device. Examples of the terminal device include， but are not limited to， user equipment (UE) such as a mobile phone， a cellular phone， a smart phone， a voice over IP (VoIP) phone， a wireless local loop phone， a tablet， a mobile station， an image capture terminal device such as digital camera， a wireless camera， a wireless-enabled tablet computer， a personal digital assistant (PDA) ， a portable computer， a desktop computer， a laptop-embedded equipment (LEE) ， a laptop-mounted equipment (LME) ， a Universal Serial Bus (USB) dongle， wireless customer-premises equipment (CPE) ， a vehicle-mounted wireless terminal device， a wearable device， a gaming terminal device， a music storage and playback appliance， a wearable terminal device， a wireless endpoint， smart devices and the like. In the following description， the terms “terminal device” ， “terminal” ， “user equipment” and “UE” may be used interchangeably.

As used herein， the term “user equipment” or “UE” may not necessarily have a “user” in the sense of a human user who owns and/or operates the relevant device. Instead， the UE may represent a device that is intended for sale to， or operation by， a human user but that may not initially be associated with a specific human user. In some embodiments， a terminal device may be configured to transmit and/or receive information without direct human interaction. For instance， a terminal device may be designed to transmit information to a network on a predetermined schedule， when triggered by an internal or external event， or in response to requests from the wireless communication network.

As one specific example， the terminal device may represent a UE configured for communication in accordance with one or more communication standards promulgated by the 3rd Generation Partnership Project (3GPP) ， such as 3GPP’s Global System for Mobile (GSM) ， Universal Mobile Telecommunications System (UMTS) ， Long Term Evolution (LTE) ， and/or the fifth generation (5G) standards. The terminal device may also enable device-to-device (D2D) communications， for example by implementing a 3GPP standard for sidelink communications. In this case， the terminal device may be referred to as a D2D communication device.

As yet another specific example， in an Internet of Things (IOT) scenario， the terminal device may represent a machine or other devices that perform monitoring and/or measurements and transmit the results of the monitoring and/or measurements to another terminal device and/or the network device. The terminal device may in this case be a machine-to-machine (M2M) device， which， in a 3GPP context， may be referred to as a machine-type communication (MTC) device. As one particular example， the terminal device may be a UE implementing the 3GPP narrow band internet of things (NB-IoT) standard. Particular examples of such machines or devices are sensors， metering devices such as power meters， industrial machinery， or home or personal appliances such as refrigerators and televisions， personal wearable computing devices such as watches， and the like. In other scenarios， the terminal device may represent a vehicle or other apparatuses that are capable of monitoring and/or reporting its operational status or other functions associated with its operations.

The terminal device as described above may represent the endpoint of a wireless connection and thus may be referred to as a wireless terminal. Furthermore， the terminal device as described above may be mobile， and it may also be referred to as a mobile device or a mobile terminal， accordingly.

As used herein， the term “wireless communication network” refers to a network following any suitable communication standards and may represent any type of communication， telecommunication， data， cellular， and/or radio network or other types of systems. Furthermore， the communications between the terminal device and the network device in the wireless communication network may be implemented in accordance with one or more communication technologies and corresponding communication standards promulgated by the 3GPP， the Internet Engineering Task Force (IETF) ， or other standardization organizations， such as GSM， UMTS， Code Division Multiple Access (CDMA) ， Wideband Code Division Multiple Access (WCDMA) ， High-Speed Packet Access (HSPA) ， LTE， LTE-Advanced (LTE-A) ， Orthogonal Frequency Division Multiplexing (OFDM) ， D2D communications， 5G standards， wireless local area network (WLAN) ， Worldwide Interoperability for Microwave Access (WiMAX) ， Bluetooth， ZigBee， and/or any other technologies either currently known or to be developed in the future.

As described above， the EER， ET and DLM techniques have been proposed to enhance the efficiency of RF PAs. Figs. 1-3 show diagrams of example circuits of an EER PA 100， an ET PA 200， and a DLM PA 300， respectively. As shown， the EER PA 100 has one output 110 and two inputs including a RF input 120 and an envelope input 130. Likewise， the ET PA 200 has one output 210 and two

inputs

220 and 230， and the DLM PA 300 has one output 310 and two

inputs

320 and 330. The

envelope inputs

130， 230， and 330 may cause non-linear memory effect distortions of the RF PAs due to signal mismatching.

For example， when the supply power for the RF PA is changed from a low level to a high level instantaneously and dynamically or vice-versa， an operating point of the RF PA changes dramatically， for example， at a drain of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) that is utilized in the RF PA. Accordingly， significant memory effect distortions may be caused. Fig. 4 shows example memory effects in the ET PA. Scattering of efficiency points versus output power in Fig. 4 reflects the memory effects， and a contour presents a probability distribution of the measured efficiency points.

Such memory effect distortions are quite difficult to be linearized and mitigated， as described above. For example， it may be difficult to use the DPD to linearize these memory effect distortions. Figs. 5 (a) and 5 (b) show an example impact of the DPD on the memory effects in the ET PA where Fig. 5 (a) shows measured phase shift before the DPD and Fig. 5 (b) shows measured phase shift after the DPD. As shown， after the DPD， the scattering points reflecting the memory effects may not be completely linearized.

In general， the memory effects of the RF PA may be categorized into long term memory effects and short term memory effects. For example， the ET PA with GaN high electron mobility transistors (HEMTs) often exhibits significant long term memory effects due to trapping phenomena. The ET PA may also suffer from the short term memory effects. Both the long term and short term memory effects may become severe due to a dynamic output bias of the ET PA.

Such severe memory effect distortions may significantly degrade the performance of the PA. For example， these distortions may increase an adjacent channel power ratio (ACPR) of a wireless communication system， such as a long term evolution (LTE) system and a wideband code division multiple access (WCDMA) system. Efforts have been made in the designs of the linearization schemes for the ET PA. However， the linearization compensations of these memory effects require completely different modeling for dynamic ET PA behaviors. If the conventional model of the DPD is used to address these memory effects， great hardware computing resources may be consumed， which is ineffective and inefficient. Furthermore， relatively precise modeling for the dynamic ET PA is quite challenging.

Therefore， the memory effect distortions of the ET PA need to be decreased or mitigated so that an acceptable linearization level of the ET PA may be achieved effectively and efficiently by means of the conventional linearization scheme， such as the DPD. For example， less base band computing resources and less digital circuitry complexity may be required to achieve the acceptable linearization level.

In addition， several envelope shaping functions are employed in the ET PA， which include voltage envelope shaping functions and current envelope shaping functions， for example. With voltage envelope shaping such as de-trough， an envelope current will not be shaped. In this case， a varying resistance at a drain of the RF PA may cause serious memory effects. Therefore， the voltage envelope shaping is not effective for the efficiency enhancement of the RF PA.

Current envelope shaping may be more effective compared with the voltage envelope shaping. However， in the case that a class-B biased PA is employed， an oversupplied current is not utilized in any way and goes to the ground， which is a severe power waste. Such a sinking current becomes an efficiency reduction factor. If this current may be properly utilized， the overall efficiency through the current shaping may be enhanced.

In order to at least in part solve the above and other potential problems， embodiments of the present disclosure provide an envelope control circuit which is arranged in a modulator of a RF PA. The envelope control circuit senses an operating parameter associated with the RF PA. The operating parameter is related to at least one of a supply current， a supply voltage， an output voltage， and a load impedance associated with the RF PA. The envelope control circuit generates a signal (referred to as a “first signal” ) based on the sensed operating parameter and then generates a further signal (referred to as a “second signal” ) for adjusting a bias or gain associated with the RF PA based on the first signal. Accordingly， a power transistor in the RF PA uses the second signal to generate an amplified RF signal. By means of the envelope control circuit， the memory effect distortions of the ET or DLM PA may be greatly reduced. Principles and implementations of the present disclosure will be described in detail below with reference to Figs. 6-10.

Fig. 6 shows a block diagram of an example RF PA 600 in accordance with some embodiments of the present disclosure. In the RF PA 600， two modulators are arranged which include a supply modulator 605 and a load modulator 610. The supply modulator 605 includes a driver amplifier 615， and the load modulator 610 includes a load impedance tuner 620 and a driver amplifier 622. It is to be understood that the number and the types of modulators in the RF PA 600 are only for the purpose of illustration， without any suggestion of limitations. The RF PA 600 may include any suitable type and number of modulators.

As shown， three envelope control circuits 625-1， 625-2， and 625-3 (correctively referred to as an “envelope control circuit 625” ) are arranged in the

modulators

605 and 610. According to embodiments of the present disclosure， the envelope control circuit 625 senses the operating parameter related to at least one of a supply current， a supply voltage， an output voltage， and a load impedance associated with the RF PA 600， generates the first signal based on the sensed operating parameter， and generates the second signal for adjusting a bias or gain associated with the RF PA 600 based on the first signal. The operating parameter sensed by the envelope control circuit 625 and the bias or gain adjusted by the envelope control circuit 625 depend on specific arrangements of the envelope control circuit 625 within the RF PA 600. Detailed implementations， arrangements， and operations of the envelope control circuit 625 will be described in the following paragraphs with reference to Figs. 7-10.

The RF PA 600 also includes a power transistor 630 that generates an amplified RF signal based on the second signal generated by the envelope control circuit 625. By utilizing the envelope control circuit 625， the bias or gain associated with the RF PA 600 may be adjusted， and thus the non-linear memory effect distortions for example due to signal mismatching， may be reduced or even eliminated.

Fig. 7 shows a block diagram of the RF PA 600 in accordance with some other embodiments of the present disclosure. In this example， the RF PA 600 includes an input matching network， an input bias network， an output bias network， and an output matching network related to the power transistor 630.

In the input matching network of the RF PA 600， the supply modulator 605 includes a pre-driver 705， a driver amplifier 710 and a power stage 715. The driver amplifier 710 and a power stage 715 constitute a two-stage driver amplifier acting as the driver amplifier 615 in Fig. 6. It is to be understood that the structure composing of the pre-driver 705， the driver amplifier 710 and the power stage 715 is only an example implementation of the driver amplifier 615. Other structures may be possible for the driver amplifier 615.

The pre-driver 705， the driver amplifier 710， and the power stage 715 constitute a linear amplifier part of the supply modulator 605. The linear amplifier part amplifies an envelope signal from an envelope input 720 linearly， which offers a minor part of the supply power for the RF PA 600， but occupies most of a required bandwidth. The supply modulator 605 also includes a DC-DC converter 725 which acts as a switcher part with a relative high switching speed of about 10MHz， for example. The switcher part provides most of the power required by the RF PA 600 with a narrower bandwidth. The outputs of the linear amplifier and switcher parts may be synchronized and summed together at a junction node 730 so as to achieve efficient and broadband power conversion.

In the linear amplifier part， the pre-driver 705 amplifies the envelope signal from the envelope input 720 which has low distortion and noise and high gain. The driver amplifier 710 provides both a sufficient gain and a current to drive the final power stage 715 to operate in a broad band. The final power stage 715 may draw a sufficiently large current from the DC-DC converter 725 to provide a highly dynamic broadband current and voltage to a collector 735 of the power transistor 630. The power transistor 630 may be implemented in any suitable form. In some embodiments， the power transistor 630 may be implemented as a MOSFET. In these embodiments， the power stage 715 provides the current and voltage to a drain of the MOSFET.

As shown， a junction node 740 is placed between an output of the pre-driver 705 and an input of the driver amplifier 710. In this example， the junction node 740 is a feeding point for the envelope control circuit 625-1 which is arranged between the junction node 740 and a further junction node 745. The envelope control circuit 625-1 may sense a supply current from the power stage 715 and automatically control a current gain of the two-stage driver amplifier based on the sensed supply current. The automatic control may be implemented by the envelope control circuit 625-1 in any suitable way. Embodiments in this regard will be described in the following paragraphs with reference to Fig. 8.

In this way， the gain of the supply modulator 605， in particular， the current gain of the driver amplifier 710 and the power stage 715 may be adjusted automatically so that an appropriate current may be supplied to the collector (or drain) 735 of the power transistor 630 to eliminate current supply and demand mismatch and reduce total harmonic distortions (THD) if an improper large signal is applied at the envelope input 720 of the supply modulator 605. Accordingly， the envelope control circuit 625-1 provides a control loop 750 for mitigating short term (fast) memory effects in the RF PA 600.

An output signal of the supply modulator 605 is split at the junction node 745 into three portions. As shown， two of these portions are injected into the envelope control circuit 625-1 and 625-2， respectively. The other of the portions is injected into an embedded controller 755 which will be detailed in the following paragraphs.

As described above， the envelope control circuit 625-1 may form a source current control branch between the

junction nodes

740 and 745 for the RF PA 600. The envelope control circuit 625-2 as a part of the input bias network of the RF PA 600 may form a sink current control branch between the junction node 745 and another junction node 760. For example， based on the supply current outputted from the power stage 715， the envelope control circuit 625-2 may adjust an input bias at a base 760 of the power transistor 630， or at a gate in the embodiments where the power transistor 630 is implemented as the MOSFET. In this way， a redundant supply current may be sunk by the power transistor 630. Accordingly， the envelope control circuit 625-2 provides a control loop 765 for mitigating short term memory effects in the RF PA 600.

The embedded controller 755 receiving one portion of the output signal of the supply modulator 605 is also included in the input bias network of the RF PA 600. The embedded controller 755 includes an analog to digital converter (ADC) 770， a digital proportion integral derivative (DPID) block 775， and a digital to analog converter (DAC) 780. The embedded controller 755 may form a control loop 785 for long term (slow) behavior compensation for the RF PA 600， such as compensation of long term memory effects， temperature， and the like. Embodiments of the embedded controller 755 will be detailed in the following paragraphs with reference to Fig. 8.

In the output network of the RF PA 600， in addition to the load impedance tuner 615 and the driver amplifier 622， the load modulator 610 includes a pre-driver 790， as shown. The driver amplifier 622 may be implemented in any suitable way. As an example， a varactor driver may be employed as the driver amplifier 622.

As shown， the envelope control circuit 625-3 as a part of the output network of the RF PA 600 is arranged between an output and an input of the driver amplifier 622 so that an automatic gain control may be implemented for the load impedance tuner 620 to avoid operations of the driver amplifier 622 (for example， a varactor driver) in a nonlinear region. Accordingly， the envelope control circuit 625-3 forms a control loop 795 for short term nonlinear reactance compensation for the RF PA 600.

Fig. 8 shows a block diagram of the RF PA 600 in accordance with yet other embodiments of the present disclosure. In this example， as shown， the envelope control circuit 625-1， 625-2， or 625-3 includes a level follower 805-1， 805-2， or 805-3 (collectively referred to as a “level follower 805” ) ， a peak rectifier 810-1， 810-2， or 810-3 (collectively referred to as a “peak rectifier 810” ) ， an attenuator 815-1， 815-2， or 815-3 (collectively referred to as an “attenuator 815” ) ， an actuator 820-1， 820-2， or 820-3 (collectively referred to as an “actuator 820” ) . Depending on the specific arrangements and functions， the envelope control circuit 625 may optionally include a current sensor 825.

For example， the envelope control circuit 625-2 arranged between the output (for example， the collector 735) and the input (for example， the base 760) of the power transistor 630 includes the current sensor 825 coupled between the power stage 715 and the collector (or drain) 735 of the power transistor 630. The current sensor 825 may sense the supply current of the power transistor 630， or a collector (or drain) current supplied to the power transistor 630. The current sensor 825 may generate a signal having a voltage level based on the sensed supply current. For example， the sensed drain current may be converted into the voltage level by signal processing. In this way， the voltage difference between the two terminals of the current sensor may be sensed and amplified to a proper level. The current sensor may be effective in a broad band so that high dynamic current behaviors may be captured.

The level follower 805-2 may receive the signal generated by the current sensor 825 and convert it into a further signal having a lower voltage level. In this way， a DC level outputted by the power stage 715 may be reduced into a proper level， and the following components， such as the peak rectifier 810-2， the attenuator 815-2， and the actuator 820-2 in the envelope control circuit 625-2， may be isolated from the higher power output of the power stage 715.

Upon the reception of the signal converted by the level follower 805-2， the peak rectifier 810-2 detects a peak voltage level of the converted signal. The output of the peak rectifier 810-2 may represent an error between the supply current for the power transistor 630 and the sinking current of the power transistor 630. The attenuator 815-2 generates a biasing level based on the detected peak voltage level so that amplitude of the output voltage of the peak rectifier 810-2 may be scaled down into a proper biasing level to guarantee a proper biasing level for biasing the following actuator 820-2. The actuator 820-2 then generates a control signal for adjusting the input bias of the power transistor 630 based on the biasing level. In this way， a bias voltage dynamically fed back from the collector (or drain) 735 may be used for adjusting the bias input at the base (or gate) 760 of the power transistor 630 so as to eliminate the current supply and demand mismatch.

In this example， the bias input of the power transistor 630 may be adjusted dynamically between a bias level VGG1 and a further bias level VGG2. Thus， the current sinking capability and linearity of the RF PA 600 may be controlled. The envelope control circuit 625-2 may detect the output level of the power stage 715 quickly and determine whether the output level exceeds a predetermined range. The predetermined range may be selected so that acceptable memory effects may be produced by the RF PA 600.

The efficiency of the RF PA 600 may be boosted by utilizing a time-varying base (or gate) biasing scheme to enable envelope current shaping based on a collector (or drain) bias. The consistency of an envelope current and an envelope voltage may reduce a wasted power in the conventional design of the RF PA with a fixed DC gate bias. Furthermore， the serious memory effect distortions due to mismatching between the envelope current and voltage during ET operations.

Figs. 9 (a) -9 (d) show simulation results of the envelope control circuit 625-2 according to some embodiments of the present disclosure. A very large input signal (exceeding an appropriate range of usage) is applied at the envelope input 720. As shown in Fig. 9 (a) ， the output signal of the power stage 715 is highly clipped and distorted， which emulates distortions related to improper “current supply and demand” effects and other memory effects. Then， the level follower 805-2 isolates and copies the signal into the input of the peak rectifier 810-2， as shown in Fig. 9 (b) . The peak rectifier 810-2 extracts a control signal as shown in Fig. 9 (c) . Finally， the actuated input signal is adjusted autonomously by the attenuator 815-2 and the actuator 820-2 as shown in Fig. 9 (d) ， which is constrained to a predetermined range.

Still with reference to Fig. 8， as shown， one portion of the signal outputted by the current sensor 825 is injected at the junction node 745 into the embedded controller 755. In this example， this signal is an analog signal which is therefore inputted into the analog to digital converter， ADC， 770 of the embedded controller 755 where the signal is converted into a digital signal. The DPID block 775 generates a digital control signal for the DPID controlling based on the digital signal. Then， the digital to analog converter， DAC， 780 converts the digital control signal into an analog control signal. Thus， the embedded controller 755 may use a digital PID controller loop to adjust the bias voltage of the base 760 of the power transistor 630 based on the current of the collector (or drain) 735 when a dynamic supply current is provided to the power transistor630. The controlled bias DC level is outputted by the DAC 780 and injected into the base (or gate) 760 of the power transistor 630.

In this way， the embedded controller 755 may form the control loop (for example， the control loop 785 as shown in Fig. 7 for bias compensation for the RF PA 600 in a digital domain. The benefit of this closed loop control is to get rid of manual alignment or burn-in of the RF PA 600 and to compensate for long term drift due to memory effects， temperatures， and the like. In this example， the junction node 760 combines the outputs of the DAC 780 and the actuator 820-2 to provide both the slow and fast control of the base (or gate) input bias of the power transistor 630.

As shown in Fig. 8， the signal outputted by the current sensor 825 is also inputted into the level follower 805-1 in the envelope control circuit 625-1. Similar to the corresponding components of the envelope control circuit 625-2， the level follower 805-1 converts the signal into a signal having a lower voltage level. The peak rectifier 810-1 detects a peak voltage level of the converted signal. Then， the attenuator 815-1 generates a biasing level based on the detected peak voltage level. Accordingly， the actuator 820-1 may generate a control signal for adjusting the current gain of the driver amplifier 710 and the power stage 715 based on the biasing level.

In addition， the envelope control circuit 625-3 arranged between the output and input of the driver amplifier 622 operates a process similar to that of the envelope control circuit 625-1. For example， the level follower 805-3 detects an output voltage of the driver amplifier 622 and scales down this voltage and generates a signal having a lower voltage. The peak rectifier 810-1 detects a peak voltage level of the generated signal. The attenuator 815-1 generates a biasing level based on the detected peak voltage level. Then， the actuator 820-1 may generate a control signal for adjusting a voltage gain of the driver amplifier 622 based on the biasing level. Accordingly， the load impedance tuner 620 may tune a load impedance of the power transistor 630 based on the adjusted voltage gain of the driver amplifier 622.

Detailed example implementations of the envelope control circuit 625 will be described below with reference to Fig. 10. In these implementations， the level follower 805-1， 805-2， and 805-3 are implemented to include NPN bipolar junction transistor (BJT) transistors T1， T1’， and T1”and current regulating diodes S1， S1’， or S1”， respectively. A resistor R1 (or R1’or R1”) on the base of the transistor T1 (or T1’or T1”) is used to limit the base current. A capacitor C1 (or C1’or C1”) provides a DC block function for the generation of a control signal. The peak rectifier is composed of two Schottky diodes D1 and D2. The Schottky diodes are employed due to their high speed characteristics. As a specific example， the diodes based on GaN material may be utilized. Capacitors C2， C2’， and C2”function as the attenuator 815-1， 815-2， and 815-3， respectively. The capacitance value of the capacitor C2 (or C2’or C2”) may be selected so that the proper base (or gate) bias for a further NPN BJT transistor T2 (or T2’or T2”) may be obtained. The transistor T2， T2’， and T2”) functions as the actuator 820-1， 820-2， and 820-3， respectively.

As shown， the transistor T2 is coupled into the base (or gate) bias path of the power transistor 630 and provides a dynamic bias together with the bias outputted by the DAC 780 of the embedded controller 755. The transistor T2 is an analog switch with a bias level shifted between the voltages VGG1 and VGG2. The bias level may be predefined so that a bias range of the RF PA 600 may be optimized for sinking current capability of the power transistor 630. The ET supply and DLM load modulator autonomous control share the similar circuitry and play similar roles to reduce total harmonic distortions (THDs) and nonlinearity caused by related components.

It is to be understood that the implementations of the envelope control circuit 625 as shown in Fig 10 are only for the purpose of illustrations， without suggesting any limitations. Other implementations are also possible.

According to some embodiments of the present disclosure， a dynamic drain-to-gate or drain-supply-modulator coupling circuit is provided to assist in stabilizing the related operating points/parameters of the RF PA and thus reduce memory effects of the RF PA caused by inconsistent envelope voltage shaping in both long term and short term. Compared with a conventional fixed direct current， DC， supply for the RF PA， embodiments of the present disclosure present better efficiency distribution and scattering， and therefore the memory effects may be greatly reduced. In addition， according to other embodiments of the present disclosure， the nonlinear effects caused by non-linear varactors used in load impedance tuner of the dynamic load modulator may also be reduced.

Fig. 11 shows a flowchart of an example method 1100 in accordance with some embodiments of the present disclosure. The method 1100 can be implemented at the RF PA 600 as described above with reference to Figs. 6-10.

At block 1105， an operating parameter related to at least one of a supply current， a supply voltage， an output voltage， and a load impedance associated with the radio frequency power amplifier is sensed. At block 1110， the first signal is generated based on the sensed operating parameter. At block 1115， the second signal is generated based on the first signal for adjusting a bias or gain associated with the radio frequency power amplifier. At block 1120， an amplified radio frequency signal is generated based on the second signal.

In some embodiments， the radio frequency power amplifier includes a power transistor. In these embodiments， the supply current for the power transistor may be sensed as the operating parameter associated with the RF PA.

In some embodiments， the first signal has a voltage level (referred to as a “first voltage level” ) . In this case， the first signal may be converted into a further signal (referred to as a “third signal” ) having a further voltage level (referred to as a “second voltage level” ) . The first voltage level is greater than the second voltage level. Then， a peak voltage level of the third signal may be detected， and a biasing level may be generated based on the detected peak voltage level. Further， the second signal may be generated based on the biasing level for adjusting an input bias of the power transistor.

In some embodiments， the method 1100 may further comprise generating a signal (referred to as a “fourth signal” ) for digital proportion integral derivative， DPID， controlling of the radio frequency power amplifier based on the first signal.

In some embodiments， the first and fourth signals are both analog signals. In these embodiments， the first signal may be converted into a digital signal， and a digital control signal for the DPID controlling is generated based on the digital signal. Then， the digital control signal is converted into the fourth signal. In some embodiments， the second and fourth signals may be combined.

In some embodiments， the radio frequency power amplifier may include a modulator which includes a driver amplifier. In these embodiments， the second signal may be generated for adjusting a gain of the driver amplifier.

In some embodiments， the modulator may be a supply modulator. In this example， a supply current outputted by the driver amplifier may be sensed as the operating parameter associated with the RF PA. In some embodiments， the second signal may be generated for adjusting the gain of the driver amplifier comprises：

In some embodiments， the first signal may have a first voltage level. In these embodiments， the first signal may be converted into the third signal having the second voltage level lower than the first voltage level. Then， a peak voltage level of the third signal may be detected. Further， a biasing level may be generated based on the detected peak voltage level， and the second signal may be generated based on the biasing level for adjusting the current gain of the driver amplifier.

In some embodiments， the modulator may be a load modulator. In this example， an output voltage of the driver amplifier may be sensed as the operating parameter associated with the RF PA. In some embodiments， the second signal may be generated for adjusting a voltage gain of the driver amplifier.

In some embodiments， the radio frequency power amplifier may further include a power transistor. In these embodiments， the method 1100 may further comprise： tuning a load impedance of the power transistor based on the adjusted voltage gain of the driver amplifier.

In the embodiments where the first signal has a first voltage level， the first signal may be converted into the third signal having a second voltage level， the first voltage level being greater than the second voltage level. A peak voltage level of the third signal may be detected. Then， a biasing level may be generated based on the detected peak voltage level， and the second signal may be generated based on the biasing level for adjusting the voltage gain of the driver amplifier.

Fig. 12 shows a flow chart of a method 1200 in accordance with some other embodiments of the present disclosure. The method 1200 can be implemented at the RF PA 600 as described above with reference to Figs. 6-10 and may be considered as an example implementation of the method 1100.

At block 1205， the current of the feeding line between the power stage and the power transistor is sensed. At block 1210， a signal having a voltage level corresponding to the sensed current is generated. At block 1215， the generated signal is split into several portions， and at least one of the portions is fed through the level follower to the peak rectifier. At block 1220， the output of the peak rectifier is adjusted into an appropriate level to bias the actuator.

At block 1225， it is determined whether a mismatched current is generated. The determination is implemented based on a predetermined current threshold for autonomous control obtained at block 1230. If it is determined that the mismatched current is generated at block 1225， the method 1200 proceeds to block 1235 where the turn-on actuator reduces the gain or increases the quiescent current. Then， at block 1240， the feeding line current is reduced or current sinking capability of the RF PA is increased. Accordingly， the current supply and demand mismatch is mitigated.

If it is determined that the mismatched current is not generated at block 1225， the method 1200 proceeds to block 1245 where the almost turn-off actuator draws a little current. At block 1250， the feeding line current is almost not influenced. Likewise， the current supply and demand mismatch is mitigated， accordingly.

It is to be understood that all operations and features related to the RF PA 600 described above with reference to Figs. 6-10 are likewise applicable to the

methods

1100 and 1200 and have similar effects. For the purpose of simplification， the details will be omitted.

Fig. 13 shows a block diagram of an apparatus 1300 in accordance with some embodiments of the present disclosure. The apparatus 1300 can be considered as an example implementation of the RF PA 600 as described above with reference to Figs. 6-12.

As shown， the apparatus 1300 comprises： a sensing unit 1305 configured to sense an operating parameter related to at least one of a supply current， a supply voltage， an output voltage， and a load impedance associated with the radio frequency power amplifier； a first generating unit 1310 configured to generate a first signal based on the sensed operating parameter； a second generating unit 1315 configured to generate a second signal for adjusting a bias or gain associated with the radio frequency power amplifier based on the first signal； and a third generating unit 1320 configured to generate an amplified radio frequency signal based on the second signal.

It should be appreciated that units included in the apparatus 1300 correspond to the blocks of the method 1100. Therefore， all operations and features described above with reference to Figs. 6-12 are likewise applicable to the units included in the apparatus 1300 and have similar effects. For the purpose of simplification， the details will be omitted.

The units included in the apparatus 1300 may be implemented in various manners， including software， hardware， firmware， or any combination thereof. In one embodiment， one or more units may be implemented using software and/or firmware， for example， machine-executable instructions stored on the storage medium. In addition to or instead of machine-executable instructions， parts or all of the units in the terminal device 500 may be implemented， at least in part， by one or more hardware logic components. For example， and without limitation， illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs) ， Application-specific Integrated Circuits (ASICs) ， Application-specific Standard Products (ASSPs) ， System-on-a-chip systems (SOCs) ， Complex Programmable Logic Devices (CPLDs) ， and the like.

Fig. 14 is a simplified block diagram of a device 1400 that is suitable for implementing embodiments of the present disclosure. The device 1400 can be implemented at or as at least a part of a communication device which enables the functions or operations of the RF PA 600 as described above with reference to Figs. 6-13.

As shown， the device 1400 includes a processor 1410， a memory 1420 coupled to the processor 1410， a suitable transmitter (TX) and receiver (RX) 1440 coupled to the processor 1410， and a communication interface coupled to the TX/RX 1440. The memory 1410 stores at least a part of a program 1430. The TX/RX 1440 is for bidirectional communications. The TX/RX 1440 has at least one antenna to facilitate communication. The communication interface may represent any interface that is necessary for communication with other network elements， such as X2 interface for bidirectional communications between eNBs， S1 interface for communication between a Mobility Management Entity (MME) /Serving Gateway (S-GW) and the eNB， Un interface for communication between the eNB and a relay node (RN) ， or Uu interface for communication between the eNB and a communication device.

The program 1430 is assumed to include program instructions that， when executed by the associated processor 1410， enable the device 1400 to operate in accordance with the embodiments of the present disclosure， as discussed herein with reference to Figs. 1 to 7. The embodiments herein may be implemented by computer software executable by the processor 1410 of the device 1400， or by hardware， or by a combination of software and hardware. The processor 1410 may be configured to implement various embodiments of the present disclosure. Furthermore， a combination of the processor 1410 and memory 1410 may form processing means 1450 adapted to implement various embodiments of the present disclosure.

The memory 1410 may be of any type suitable to the local technical network and may be implemented using any suitable data storage technology， such as a non-transitory computer readable storage medium， semiconductor based memory devices， magnetic memory devices and systems， optical memory devices and systems， fixed memory and removable memory， as non-limiting examples. While only one memory 1410 is shown in the device 1400， there may be several physically distinct memory modules in the device 1400. The processor 1410 may be of any type suitable to the local technical network， and may include one or more of general purpose computers， special purpose computers， microprocessors， digital signal processors (DSPs) and processors based on multicore processor architecture， as non-limiting examples. The device 1400 may have multiple processors， such as an application specific integrated circuit chip that is slaved in time to a clock which synchronizes the main processor.

Generally， various embodiments of the present disclosure may be implemented in hardware or special purpose circuits， software， logic or any combination thereof. Some aspects may be implemented in hardware， while other aspects may be implemented in firmware or software which may be executed by a controller， microprocessor or other computing device. While various aspects of embodiments of the present disclosure are illustrated and described as block diagrams， flowcharts， or using some other pictorial representation， it will be appreciated that the blocks， apparatus， systems， techniques or methods described herein may be implemented in， as non-limiting examples， hardware， software， firmware， special purpose circuits or logic， general purpose hardware or controller or other computing devices， or some combination thereof.

The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer readable storage medium. The computer program product includes computer-executable instructions， such as those included in program modules， being executed in a device on a target real or virtual processor， to carry out the

methods

1100 and 1200 as described above with reference to any of Figs. 11 and 12. Generally， program modules include routines， programs， libraries， objects， classes， components， data structures， or the like that perform particular tasks or implement particular abstract data types. The functionality of the program modules may be combined or split between program modules as desired in various embodiments. Machine-executable instructions for program modules may be executed within a local or distributed device. In a distributed device， program modules may be located in both local and remote storage media.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer， special purpose computer， or other programmable data processing apparatus， such that the program codes， when executed by the processor or controller， cause the functions/operations specified in the flowcharts and/or block diagrams to be implemented. The program code may execute entirely on a machine， partly on the machine， as a stand-alone software package， partly on the machine and partly on a remote machine or entirely on the remote machine or server.

The above program code may be embodied on a machine readable medium， which may be any tangible medium that may contain， or store a program for use by or in connection with an instruction execution system， apparatus， or device. The machine readable medium may be a machine readable signal medium or a machine readable storage medium. A machine readable medium may include but not limited to an electronic， magnetic， optical， electromagnetic， infrared， or semiconductor system， apparatus， or device， or any suitable combination of the foregoing. More specific examples of the machine readable storage medium would include an electrical connection having one or more wires， a portable computer diskette， a hard disk， a random access memory (RAM) ， a read-only memory (ROM) ， an erasable programmable read-only memory (EPROM or Flash memory) ， an optical fiber， a portable compact disc read-only memory (CD-ROM) ， an optical storage device， a magnetic storage device， or any suitable combination of the foregoing.

Further， while operations are depicted in a particular order， this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order， or that all illustrated operations be performed， to achieve desirable results. In certain circumstances， multitasking and parallel processing may be advantageous. Likewise， while several specific implementation details are contained in the above discussions， these should not be construed as limitations on the scope of the present disclosure， but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely， various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination.

Although the present disclosure has been described in language specific to structural features and/or methodological acts， it is to be understood that the present disclosure defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather， the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

A radio frequency power amplifier (600) ， comprising：

a modulator (605， 610) including an envelope control circuit (625) configured to：

sense an operating parameter related to at least one of a supply current， a supply voltage， an output voltage， and a load impedance associated with the radio frequency power amplifier (600) ，

generate a first signal based on the sensed operating parameter， and

generate a second signal for adjusting a bias or gain associated with the radio frequency power amplifier (600) based on the first signal； and

a power transistor (630) configured to generate an amplified radio frequency signal based on the second signal.
The radio frequency power amplifier (600) of claim 1， wherein：

the modulator (605， 610) is a supply modulator (605) ，

the envelope control circuit (625-2) is arranged between an output and an input of the power transistor (630) ，

the operating parameter includes a supply current of the power transistor (630) ， and

the bias or gain associated with the radio frequency power amplifier (600) includes an input bias of the power transistor (630) .
The radio frequency power amplifier (600) of claim 2， wherein the envelope control circuit (625) includes：

a current sensor (825) configured to sense the supply current for the power transistor (630) and generate the first signal having a first voltage level based on the sensed supply current；

a level follower (805-2) configured to convert the first signal into a third signal having a second voltage level， the first voltage level being greater than the second voltage level；

a peak rectifier (810-2) configured to detect a peak voltage level of the third signal；

an attenuator (815-2) configured to generate a biasing level based on the detected peak voltage level； and

an actuator (820-2) configured to generate the second signal for adjusting the input bias of the power transistor (630) based on the biasing level.
The radio frequency power amplifier (600) of claim 3， further comprising：

an embedded controller (755) configured to generate a fourth signal for digital proportion integral derivative， DPID， controlling of the radio frequency power amplifier (600) based on the first signal.
The radio frequency power amplifier (600) of claim 4， wherein the first and fourth signals are both analog signals， and the embedded controller comprises：

an analog to digital converter (770) configured to convert the first signal into a digital signal；

a DPID block (775) configured to generate a digital control signal for the DPID controlling based on the digital signal； and

a digital to analog converter (780) configured to convert the digital control signal into the fourth signal.
The radio frequency power amplifier (600) of claim 4 or 5， further comprising：

a junction node (760) configured to combine the second and fourth signals.
The radio frequency power amplifier (600) of claim 1， wherein：

the modulator (605， 610) further includes a driver amplifier (615， 622) ，

the envelope control circuit (625) is arrange between an output and an input of the driver amplifier (615， 622) ， and

the bias or gain associated with the radio frequency power amplifier (600) includes a gain of the driver amplifier (615， 622) .
The radio frequency power amplifier (600) of claim 7， wherein：

the modulator (605， 610) is a supply modulator (605) ，

the operating parameter includes a supply current outputted by the driver amplifier (615) ， and

the gain of the driver amplifier (615， 622) includes a current gain of the driver amplifier (615) .
The radio frequency power amplifier (600) of claim 8， wherein the envelope control circuit (625) comprises：

a current sensor (825) configured to sense the supply current outputted by the driver amplifier (615) and generate the first signal having a first voltage level based on the sensed supply current；

a level follower (805-1) configured to convert the first signal into a third signal having a second voltage level， the first voltage level being greater than the second voltage level；

a peak rectifier (810-1) configured to detect a peak voltage level of the third signal；

an attenuator (815-1) configured to generate a biasing level based on the detected peak voltage level； and

an actuator (820-1) configured to generate the second signal for adjusting the current gain of the driver amplifier (615) based on the biasing level.
The radio frequency power amplifier (600) of claim 7， wherein the modulator (605， 610) is a load modulator (610) ， the operating parameter includes an output voltage of the driver amplifier (622) ， the gain of the driver amplifier (615， 622) includes a voltage gain of the driver amplifier (622) ， and the load modulator (610) further comprises：

a load impedance tuner (620) configured to tune a load impedance of the power transistor (630) based on the adjusted voltage gain of the driver amplifier (622) .
The radio frequency power amplifier (600) of claim 10， wherein the envelope control circuit (625) comprises：

a level follower (805-3) configured to sense the output voltage of the driver amplifier (622) ， generate the first signal having a first voltage level， and convert the first signal into a third signal having a second voltage level， the first voltage level being greater than the second voltage level；

a peak rectifier (810-3) configured to detect a peak voltage level of the third signal；

an attenuator (815-3) configured to generate a biasing level based on the detected peak voltage level； and

an actuator (820-3) configured to generate the second signal for adjusting the voltage gain of the driver amplifier (622) based on the biasing level.
A method (1100) implemented in a radio frequency power amplifier (600) ， comprising：

sensing (1105) an operating parameter related to at least one of a supply current， a supply voltage， an output voltage， and a load impedance associated with the radio frequency power amplifier (600) ；

generating (1110) a first signal based on the sensed operating parameter；

generating (1115) a second signal for adjusting a bias or gain associated with the radio frequency power amplifier (600) based on the first signal； and

generating (1120) an amplified radio frequency signal based on the second signal.
The method of claim 12， wherein the radio frequency power amplifier (600) includes a power transistor (630) ， and sensing (1105) the operating parameter comprises：

sensing the supply current for the power transistor (630) .
The method of claim 13， wherein the first signal has a first voltage level， and generating (1115) the second signal for adjusting the bias or gain associated with the radio frequency power amplifier (600) comprises：

converting the first signal into a third signal having a second voltage level， the first voltage level being greater than the second voltage level；

detecting a peak voltage level of the third signal；

generating a biasing level based on the detected peak voltage level； and

generating the second signal for adjusting an input bias of the power transistor (630) based on the biasing level.
The method of claim 14， further comprising：

generating a fourth signal for digital proportion integral derivative， DPID， controlling of the radio frequency power amplifier (600) based on the first signal.
The method of claim 15， wherein the first and fourth signals are both analog signals， and generating the fourth signal comprises：

converting the first signal into a digital signal；

generating a digital control signal for the DPID controlling based on the digital signal； and

converting the digital control signal into the fourth signal.
The method of claim 15 or 16， further comprising：

combining the second and fourth signals.
The method of claim 12， wherein the radio frequency power amplifier (600) includes a modulator (605， 610) including a driver amplifier (615， 622) ， and generating (1115) the second signal for adjusting the bias or gain associated with the radio frequency power amplifier (600) comprises：

generating the second signal for adjusting a gain of the driver amplifier (615， 622) .
The method of claim 18， wherein the modulator is a supply modulator (605) ， and sensing (1105) the operating parameter comprises：

sensing a supply current outputted by the driver amplifier (615) .
The method of claim 19， wherein generating (1115) the second signal for adjusting the gain of the driver amplifier comprises：

generating the second signal for adjusting a current gain of the driver amplifier (615) .
The method of claim 20， wherein the first signal has a first voltage level， and generating the second signal for adjusting the current gain of the driver amplifier (615) comprises：

converting the first signal into a third signal having a second voltage level， the first voltage level being greater than the second voltage level；

detecting a peak voltage level of the third signal；

generating a biasing level based on the detected peak voltage level； and

generating the second signal for adjusting the current gain of the driver amplifier (615) based on the biasing level.
The method of claim 18， wherein the modulator (605， 610) is a load modulator (610) ， and sensing (11105) the operating parameter comprises：

sensing an output voltage of the driver amplifier (622) .
The method of claim 22， wherein generating (1115) the second signal for adjusting the gain of the driver amplifier (615， 622) comprises：

generating the second signal for adjusting a voltage gain of the driver amplifier (622) .
The method of claim 23， wherein the radio frequency power amplifier (600) further includes a power transistor (630) ， and the method further comprises：

tuning a load impedance of the power transistor (630) based on the adjusted voltage gain of the driver amplifier (622) .
The method of claim 24， wherein the first signal has a first voltage level， and generating the second signal for adjusting the voltage gain of the driver amplifier (622) comprises：

converting the first signal into a third signal having a second voltage level， the first voltage level being greater than the second voltage level；

detecting a peak voltage level of the third signal；

generating a biasing level based on the detected peak voltage level； and

generating the second signal for adjusting the voltage gain of the driver amplifier (622) based on the biasing level.
A device (1400) ， comprising：

a processor (1410) and a memory (1420) ， the memory (1420) containing instructions executable by the processor (1410) whereby the device (1400) is operative to perform the method (1100) according to any of claims 12 to 25.
A computer readable storage medium tangibly storing a computer program， the computer program including instructions which， when executed on at least one processor， cause the at least one processor to carry out the method (1100) according to any of claims 12 to 25.