WO2018182633A1

WO2018182633A1 - Interlayers in selective area growth of gallium nitride (gan) based structures

Info

Publication number: WO2018182633A1
Application number: PCT/US2017/025095
Authority: WO
Inventors: Sansaptak DASGUPTA; Han Wui Then; Marko Radosavljevic; Paul B. Fischer
Original assignee: Intel Corporation
Priority date: 2017-03-30
Filing date: 2017-03-30
Publication date: 2018-10-04

Abstract

A computing device and integrated circuit die having GaN transistors on GaN-based structures a method of fabricating the GaN transistors on GaN-based structures is disclosed. The integrated circuit die includes a semiconductor substrate. The integrated circuit die includes a Gallium Nitride (GaN) transistor disposed above the semiconductor substrate. The GaN transistor includes a portion of a GaN-based structure. The integrated circuit die includes an interlayer of the GaN-based structure. The GaN-based structure disposed above an outer surface of the interlayer, the interlayer having polar orientation and semi-polar orientation.

Description

INTERLAYERS IN SELECTIVE AREA GROWTH OF GALLIUM

NITRIDE (GAN) BASED STRUCTURES

Background

[0001] Integrated circuits (IC) have continued to develop to address new and different performance demands. Semiconductor manufacturing processes are continually developed and employed to enable the manufacture of integrated circuits that meet the changing performance demands.

Brief Description of the Drawings

[0002] The present disclosure described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, features illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some features may be exaggerated relative to other features for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

[0003] Figures 1-12 illustrate an integrated circuit (IC) structure subsequent to various operations of a fabrication process, according to implementations.

[0004] Figure 13 is a diagram illustrating a multi-stack interlayer in a GaN-based structure, in accordance with implementations

[0005] Figure 14 illustrates a flow diagram of a fabrication process for forming GaN transistors having GaN-based structures with various interlayers, according to an implementation.

[0006] Figure 15 illustrates an interposer, according to implementations.

[0007] Figure 16 is a computing device built in accordance with implementation of the present disclosure.

Detailed Description

[0008] In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations .

[0009] III-Nitride (N) devices, such as Gallium Nitride (GaN) transistors, made from III-N materials have become ubiquitous in modern integrated circuits and computing devices. For example, integrated circuits with GaN transistors are often used in power electronics and communication circuits. GaN transistors are found in radio frequency (RF) power amplifiers, voltage regulators, and low-level logic devices, among others. Some III-Nitride (N) devices, such as GaN transistors, provide a wide band gap and high electron mobility, which are characteristics that have particular applicability in high-voltage applications, power electronics, and RF devices.

[0010] In some examples, GaN transistors may be formed above GaN-based structures. The lattice mismatch between the semiconductor substrate (e.g., Silicon substrate) and the GaN material layers above the semiconductor substrate may be considerable and promote defects, such as cracks in the GaN-based structures during the fabrication process. The defects in the GaN-based structures may render the above GaN transistors faulty and reduce yield. As wafer size increases and the size of GaN-based structures increase, defects become more probable.

[0011] Aspects of the present disclosure address the above-mentioned and other deficiencies by forming GaN transistors having GaN-based structures with various interlayers, in accordance with some implementations. In one example, an integrated circuit or computing device may include a semiconductor substrate. The integrated circuit or computing device may include a first GaN transistor disposed above the semiconductor substrate. The GaN transistor may include a first portion of a first GaN-based structure. The integrated circuit or computing device also includes a first interlayer of the first GaN-based structure. The first GaN-based structure surrounds an outer surface of the first interlayer having polar orientation and semi-polar orientation.

[0012] In another example, the integrated circuit or computing device include a second GaN transistor disposed above the semiconductor substrate. The second GaN transistor includes a second portion of a second GaN-based structure. The first GaN-based structure and the second GaN-based structure are a trapezoidal shape and physically separate (e.g., GaN island).

[0013] In another example, the integrated circuit die or computing device includes a multi-stack interlayer disposed above the semiconductor substrate. The multi-stack interlayer includes the first interlayer and a second interlayer disposed below the first interlayer. The first interlayer and the second interlayer include GaN. The first interlayer includes a higher ratio of GaN than the second interlayer. In one implementation, the first interlayer and the second interlayer of the multi- stack interlayer are Aluminum GaN (AlGaN). [0014] In examples, the integrated circuit die or computing device includes a third interlayer of the first GaN-based structure disposed above the first interlayer and within the first GaN-based structure. The first GaN-based structure surrounds an outer surface and an inner surface of the third interlayer having the polar orientation and the semi-polar orientation. In implementations, the first interlayer is Aluminum Nitride (A1N).

[0015] In another example, the first interlayer includes a top portion having the polar orientation. The first interlayer includes sidewalls having semi-polar orientation. The material characteristics of the top portion are different than material characteristics of the sidewalls. In implementations, the top portion of the first interlayer is thicker than the sidewalls of the first interlayer. In an example, a ratio of thickness between the sidewalls and top portion is less than or equal to 0.3. In implementations, the top portion of the interlayer is a polycrystalline structure and the sidewalls are crystalline structure. In some examples, a defect in the GaN-based structure terminates at an inner surface of the first interlayer. In some examples, the semiconductor substrate is Silicon (111). In some examples, the first GaN-based structure covers an area of 500 microns (um) or greater.

[0016] In some examples, a method of fabricating an integrated circuit includes growing a first segment of a Gallium Nitride (GaN) based structure above a semiconductor substrate. The method includes growing a first interlayer above the first segment of the GaN-based structure. The method also includes growing a second segment of the GaN-based structure above the first interlayer The second segment of the GaN-based structure surrounds an outer surface of the first interlayer having polar orientation and semi-polar orientation.

[0017] In an example, the method includes forming a multi- stack interlayer above the

semiconductor substrate. The multi-stack interlayer includes a second interlayer and a third interlayer disposed above the second interlayer. The first interlayer is disposed above the second and the third interlayer. The second interlayer and the third interlayer comprise GaN. The third interlayer includes a higher ratio of GaN than the second interlayer.

[0018] In an example, the method includes forming a first GaN transistor above the

semiconductor substrate. The first GaN transistor includes a first portion of the first GaN-based structure. In an example, the method also includes forming a second GaN transistor above the semiconductor substrate. The second GaN transistor includes a second portion of the first GaN- based structure.

[0019] In an example, growing the first interlayer above the first segment of the GaN-based structure, the method includes growing a top portion and sidewalls of the first interlayer responsive to an interlayer process. The top portion has the polar orientation and the sidewalls have the semi-polar orientation. The material characteristics of the top portion are different than material characteristics of the sidewalls.

[0020] In an example, the first interlay er is Aluminum Nitride (A1N) formed at a process temperature at or below 900 degrees Celsius. In another example, a defect in the GaN-based structure terminates at an inner surface of the first interlayer.

[0021] It may be noted that for purposes of illustration, rather than limitation, that aspects of the present disclosure describe processes and features for fabricating GaN transistors having GaN- based structures with various interlayers. It may be noted that aspects of the present disclosure may be applied to features, components, layers, etc. of an IC other than described herein. For example, processes described herein may be applied to form other transistor types such as bipolar junction transistors (BJT), Fin field effect transistors (FET), multiple-gate FET (MuFET) etc. In other examples, the processes described herein may be applied to different devices such as diodes, light-emitting diodes (LED), or memory cells, among others. In still other examples, the processes described herein may be used on the various layers of an IC or interconnects and vias between layers. It may be noted that GaN is used for purposes of illustration rather than limitation. In other implementations, the description and processes described herein may be applied to any other Ill-Nitride (N) material. For example, the fabrication processes herein may be used to form III-N transistors having III-N structures.

[0022] Figures 1-12 illustrate an integrated circuit structure, such as an integrated circuit with GaN transistors having GaN-based structures with various interlayers, according to

implementations. Fabrication processes 100 through 1200 include an integrated circuit die of a wafer at various stages of the fabrication process, according to one implementation. It may be noted that fabrication processes 100-1200 are shown for purposes of illustration, rather than limitation. Fabrication processes 100-1200 may be performed in any order, include any number of processes, and include additional, the same, or fewer processes. It may also be noted that for purposes of illustration, rather than limitation, materials are described for the various layers or structures illustrated in fabrication processes 100-1200. Other materials, other than or in addition to the materials described with respect to Figures 1-12, may also be used in other

implementations. It may be noted that for purposes of illustration, rather than limitation, the integrated circuit die may be diced from a wafer or be part of a wafer. It may also be noted that a layer (e.g., nucleation layer 114A, etc.), described herein, may include one or more layers. It may be noted that the number or quantity of elements (e.g., shallow trench isolation (STI) element 112A, STI element 112B, STI element 112C, etc.) are shown for purposes of illustrations, rather than limitation. In implementations, the elements described herein may be any number and depend on for example, the design of the integrated circuit.

[0023] Figure 1 illustrates an integrated circuit structure subsequent to forming STI elements, in accordance with some implementations. In Figure 1, process 100 shows STI elements 112A-C above substrate 110. In implementations, substrate 110 may be a semiconductor substrate.

Nucleation layers 114A and 114B are formed in trenches between adjacent STI elements 112A- C. In implementations, the substrate 110 may be a variety of materials, including, but not limited to, Silicon, Gallium Nitride (GaN), Germanium, Sapphire, or Silicon Carbide such as 3C-Silicon Carbide (3C-SiC). In implementations, the substrate 110 may be silicon on insulator (SOI). In implementations, the crystallographic orientation of a substantially monocrystalline substrate may be any of (100), (111), or (110). Other crystallographic orientations are also possible. In implementations, the crystallographic orientations of the substrate 110 may be offcut. In one implementation, the substrate 110 is (100) silicon with crystalline substrate surface region having cubic crystallinity. In another implementation, for a (100) silicon substrate, the semiconductor surface may be miscut, or offcut, for example 2-10° toward [110]. In another implementation, substrate 110 is (111) silicon with crystalline substrate surface region having hexagonal crystallinity. In one implementation, substrate 110 of silicon (111) may be used to grow GaN- based structures, as described herein. In one implementation, the wafer size used may be 300 millimeters (mm). In other implementations, the wafer size may be other than 300 mm.

[0024] It may be noted that elements herein may be described using a number and letter.

Elements that are described with a number and letter may be collectively described using a number without a letter. For example, nucleation layer(s) 114 may refer to nucleation layer 114A and/or nucleation layer 114B, while reference to nucleation layer 114 A may refer to only nucleation layer 114A, unless otherwise specified.

[0025] In implementations, a layer of STI material may be deposited above substrate 110. A photoresist material may be patterned to define one or more trenches (e.g., area between adjacent STI elements 112) within the layer of STI material. The photoresist material may form a pattern over the layer of STI material that may in turn, be used to form a pattern within the STI material for the opening of trenches to form STI elements 112, as illustrated in Figure 1. In

implementations, the STI material may be formed using lithography (e.g., 193 nanometer (nm) or extreme ultraviolet lithography (EUV)). Removal of remaining resist or an anti-reflection layer may be performed using ash or wet cleans, for example. In implementations, STI material may include one or more dielectric materials. Representative dielectric materials may include, but are not limited to, various Oxides, Nitrides and Carbides, for example, Silicon Oxide, Titanium Oxide, Hafnium Oxide, Aluminum Oxide, Oxynitride, Zirconium Oxide, Hafnium Silicate, Lanthanum Oxide, Silicon Nitride, Boron Nitride, Amorphous Carbon, Silicon Carbide,

Amorphous Silicon, or other similar dielectric materials. In implementations, STI elements 112 may be used to electrically isolate devices of an integrated circuit from one another. For example, STI elements 112 may be implemented to reduce or prevent current leakage between transistors.

[0026] In implementations, subsequent to forming the trenches by removing some of the STI layer, nucleation layer 114 may be grown in the trenches. In implementations, the nucleation layer 114 may promote growth and quality of additional layers above substrate 110, such as the growth of GaN. In implementations, STI elements 112 may have a (vertical) thickness of 50 nanometers (nm) to 500 nm. It may be noted that STI elements 112 may be any thickness and may vary depending on the implementation, application, aspect ratio, etc.

[0027] Figure 2 illustrates an integrated circuit structure subsequent to forming GaN-based structure segments, in accordance with some implementations. In Figure 2, process 200 shows the formation of GaN-based structure segments 216 (also referred to as "base GaN-based structure segments" or "GaN structure segments" herein) of GaN-based structures above nucleation layer 114, in accordance with implementations. GaN-based structure segments may also be referred to as "GaN segments" herein. It may be noted that a GaN-based structure may include one or more GaN segments 216. In implementations, the GaN segments 216 may be grown as part of part of a selective area growth (SAG) process. SAG may be a growth process on specific regions of a substrate 110 or wafer (rather than blanket growth) selective to other areas of substrate 110 or wafer where the growth of the material does not occur. For example, the GaN-based structure segments 216 (and GaN-based structures) may be discrete and physically separate from one another. In implementations, the GaN-based structure segments 216 are grown selectively, rather than etched from a blanked film. The GaN segments 216 may be grown in a trapezoidal shape where the top portion (c-plane) is wider than a base portion of the trapezoid. In implementations, the GaN segments 216 may be grown at a temperature of greater than or equal to 1000 degrees Celsius. In implementations, GaN segments 216 may be grown using metal organic vapor phase epitaxy (MOVPE) or metal organic chemical vapor deposition (MOCVD) growth techniques, among other processes. In implementations, GaN-based structure segments 216 may have a (vertical) thickness of 1 micrometer (um) to 5 um. It may be noted that GaN- based structure segments 216 may be any thickness and may vary depending on the

implementation, application, aspect ratio, etc.

[0028] Figure 3 illustrates an integrated circuit structure subsequent to forming interlayers, in accordance with some implementations. In Figure 3, process 300 shows the growth of an interlayers 318 (also referred to as "low-temperature (LT) interlayers" herein) above GaN-based structure segments 216, in accordance with implementations. In implementations, interlayers 318 may encapsulate the exposed or outer surface of GaN-based structure segments 216. In implementations, interlayers 318 have an inner surface 324 and an outer surface 326. In implementations, the interlayers 318 may conform to the trapezoidal shape of the GaN-based structure segments 216 and have sidewalls 320 and top portion 322. It may be noted that the GaN-based structure segments 216 (and GaN-based structures) may also have corresponding sidewalls and top portion. In implementations, the growth of interlayers 318 may be performed in an interlayer process.

[0029] In implementations, a GaN segment grown above the interlayers 318 may be

compressively strained, and help counterbalance tensile strain during a cool down phase post growth, for example. In other implementations, interlayers 318 may be used to decrease or control defects in the GaN-based structure segments 216 or GaN-based structures. For example, cracks in the vertical direction and in the GaN-based structure segments 216 may terminate or be partially terminated at or near the inner surface 324 of interlayers 318. In other examples, cracks in the GaN-based structure segments 216 may be caused to bend toward the inner surface 324 of the sidewalls 320 of the interlayers 318. In implementations, cracks may be especially prevalent in large area GaN-based structures. In some implementations, interlayers 318 may be used in large GaN-based structures, such as GaN-based structures with an area of 500 microns (um) or larger. It may be noted that interlayers 318 may be used in any size GaN-based structures. For example, interlayers 318 may be used in GaN-based structures with an area of 5um or larger.

[0030] In implementations, different portions of the interlayers 318 may have different material characteristics even though the different portions of interlayers 318 are grown in the same interlayer process. In implementations, at least part of the top portions 322 of interlayers 318 have different material characteristics than at least part of the sidewalls 320 of interlayers 318. In implementations, the top portions 322 of interlayers 318 have a polar orientation 328, such as along the c-plane. In implementations, the sidewalls 320 of interlayers 318 have a semi-polar orientation 330. The top portion 322 of interlayers 318 may be thicker than the sidewalls 320 of interlayers 318. In implementations, the ratio of thickness between the sidewalls 320 (any one of) and the top portion 322 of interlayers 318 is less than or equal to 0.3. For example, the top portion 322 may be 10 nm thick and the sidewalls 320 may be 2 nm thick. In implementations, the sidewalls 320 may be a crystalline structure and the top portion 322 may be a polycrystalline structure. In implementations, the top portion 322 of interlayers 318 may induce mobile or trap charges at the interface responsive to polarization differences between interlayers 318 and the underlying material. The amount of charge induced in the sidewall 320 of interlayers 318 may be reduced (e.g., relative to the top portion 322) responsive to the lower polarization properties.

[0031] In implementations, the interlayers 318 are a Nitride material, such as Aluminum Nitride (A1N). In implementations, interlayers 318 may be any other materials such as AlInN, AlGaN, SiNx, or other materials. In some implementations, interlayers 318 may be formed in a low- temperature interlayer process. In implementations, interlayers 318 may be formed in a low- temperature A1N process that is performed at 900 degrees Celsius or below. In implementations, the interlayer process may be a CVD process, such as MOCVD, or other process. In

implementations, a low-temperature interlayer process may help with a "relaxed" film growth to grow interlayers 318 having the different material characteristics as described above, for example. In implementations, the (vertical) thickness of interlayers 318 may be 2 nanometers (nm) to 15 nm. It may be noted that the thickness of interlayers 318 may be any thickness and may vary depending on the implementation, application, aspect ratio, etc.

[0032] In implementations, polar orientation 328 and semi-polar orientation 330 are schematic perspective views of various crystal planes in a portion of a GaN or Indium GaN (InGaN) material. As shown, the GaN/InGaN material has a wurtzite crystal structure with various lattice planes or facets as represented by corresponding Miller indices. In implementations, polar orientation 328 may refer to one or more crystal planes in a crystal structure that contain only one type of atoms. For example, the polar plane denoted as the "c-plane" in the wurtzite crystal structure with a Miller index of (0001) contains only Ga atoms. Similarly, other polar planes in the wurtzite crystal structure may contain only N atoms and/or other suitable type of atoms.

[0033] In implementations, non-polar orientation may refer to one or more crystal planes in a crystal structure that are generally perpendicular to a polar plane (e.g., to the c-plane). For example, a non-polar plane, such as the "a-plane" in the wurtzite crystal structure may have a Miller index of (11 20). In another example, a non-polar plane, such as the "m-plane" in the wurtzite crystal structure may have a Miller index of (10 10). Both the a-plane and the m-plane are generally perpendicular to the c-plane.

[0034] In implementations, semi-polar orientation 330 may refer to one or more crystal planes in a crystal structure that are canted relative to a polar plane (e.g., to the c-plane) without being perpendicular to the polar plane. For example, the semi-polar planes in the wurtzite crystal structure may have Miller indices of (10 13), (10 11), and (11 22) and form an angle with the c- plane. In implementations, the angle is greater than 0 degrees (°) but less than 90°. It may be noted that each of the polar, non-polar, or semi-polar planes can also include other crystal planes not shown. [0035] Figure 4 illustrates an integrated circuit structure subsequent to forming GaN-based structure segments, in accordance with some implementations. In Figure 4, process 400 illustrates the growth of additional GaN-based structure segments 416 above the interlayers 318, in accordance with implementations. The GaN-based structure segments 416 may be similar to GaN-based structure segments 216 as described with respect to Figure 2, unless otherwise noted. For example, GaN-based structure segments 416 may be grown in a similar manner as described with respect to GaN-based structure segments 216 of Figure 2. In implementations, GaN-based structure segments 416 that are between two interlayers may have a (vertical) thickness that is less than the base GaN-based structure segments 216. In implementations, the thickness of GaN- based structure segments 416 range from 50 nm to 250 nm. It may be noted that the thickness of GaN-based structure segments 416 may be any thickness and may vary depending on the implementation, application, aspect ratio, etc.

[0036] Figure 5 illustrates an integrated circuit structure subsequent to forming interlayers, in accordance with some implementations. In Figure 5, process 500 illustrates the growth of interlayers 518 above GaN-based structure segments 461, in accordance with implementations. The interlayers 518 may be similar to interlayers 318 as described with respect to Figure 3, unless otherwise noted. In implementations, any number of interlayers (e.g., 0 to 50), such as interlayers 318 or 518, may be used. It may be noted that interlayers, such as interlayers 318 or 518, may be combined with other implementations or aspects of the disclosure, and may vary depending on the implementation, application, aspect ratio, size of GaN-based structure, etc. In implementations, one or more defects, such as cracks that are not terminated at interlayers 318, may be terminated to the inner surfaces of interlayers 518, or any subsequent interlayers according to implementations. In implementations, interlayers 318 and 518 are both A1N interlayers grown using a low-temperature A1N interlayer process. In implementations, the distance between two adjacent interlayers, such as interlayers 318 and 518, may be the thickness of the intervening GaN-based structure segments 416 (e.g., 50 nm to 250 nm).

[0037] In other implementations, a super lattice may be formed within a GaN-based structure. In a super lattice, the layering of interlayers and GaN segments (as described above) may be repeated multiple times (e.g., 15 to 75 times) where the GaN segments have a thickness of 3 nm to 20 nm. The interlayers of the super lattice may be similar to interlayers 318 and 518, as described herein. In implementations, a super lattice may be used in lieu of non-super lattice implementations as described herein (e.g., a 1-8 interlayers with spacing in the range of 50 nm to 250 nm). In other implementations, a super lattice may be used in conjunction with non-super lattice implementations. For example, a super lattice may be formed above the substrate 110. Above the super lattice, one or more additional interlayers may be formed that have larger spacing (e.g., 50 nm to 250 nm) between adjacent interlayers.

[0038] Figure 6 illustrates an integrated circuit structure subsequent to forming GaN-based structure segments, in accordance with some implementations. In Figure 6, process 600 illustrates the growth of GaN-based structure segments 616, according to implementations. The GaN-based structure segments 616 (also referred to as "buffer layer" herein) may be similar to GaN-based structure segments 216 or GaN-based structure segments 416 as described with respect to Figure 2 or Figure 4, respectively, unless otherwise described. In implementations, where GaN-based structure segments 616 are above the upper most interlayers, such as interlayers 518, GaN-based structure segments 216 may have a thickness ranging from 100 nm to 2 um. It may be noted that the thickness of GaN-based structure segments 616 may be any thickness and may vary depending on the implementation, application, aspect ratio, etc.

[0039] Figure 7 illustrates an integrated circuit structure subsequent to forming film layers, in accordance with some implementations. In Figure 7, process 700 illustrates the growth of film layer 732. In implementations, film layer 732 in conjunction with GaN-based structure segments 616 may help induce a channel in a two-dimensional electrode gas, where the channel may be part of a GaN transistor. In implementations, film layer 732 may be grown above GaN-based structure segments 616 using a CVD process, a MOCVD process, or other process. In implementations, film layer 732 may be a Nitride -based film layer, such as Aluminum Indium Nitride (AlInN), Aluminum GaN (AlGaN), or AIN, for example. The (vertical thickness) of film layer 732 may range from 10 nm to 50 nm, in some implementations. It may be noted that the thickness of film layer 732 may be any thickness and may vary depending on the

implementation, application, aspect ratio, etc.

[0040] In implementations, GaN-based structures 734 may include the various GaN-based structure segments, such as GaN-based structure segments 216, GaN-based structure segments 416, and GaN-based structure segments 616, and the various interlayers, such as interlayers 318 and interlayers 518, and film layer 732. It may be noted that GaN-based structures 734 may include more, fewer, or different elements. For example, GaN-based structures 734 may include all the layers above the nucleation layer 114A and below film layer 732A. GaN-based structures may also be referred to as "GaN islands" or "GaN discrete structures" herein. In

implementations, the width 760 of GaN-based structures 734 may be the width of the nucleation layers 114 or the distance between two adjacent STI elements, such as STI element 112B and STI element 112C. In implementations, the depth (Z) of GaN-based structures 734 may be in the direction extending into the plane of the drawing. In implementations, width 760 of GaN-based structures 734 may range from 0.1 um to 30 um, and the depth (Z) of GaN-based structures 734 may range from 50 um to 200 um. It may be noted that the width 760 and depth of GaN-based structures 734 may be any size and may vary depending on the implementation, application, aspect ratio, etc. In implementations, the area of the GaN-based structure 734 may be measured using width 760 and depth (Z).

[0041] Figure 8 illustrates an integrated circuit structure subsequent to the deposition of fill material, in accordance with some implementations. In Figure 8, process 800 illustrates the deposition of fill material 836 is areas between the GaN-based structures 734, and on the sides of the various GaN-based structures 734. The fill material 836 may be deposited and planarized to expose the film layers 732. The fill material 836 may be a dielectric material, as described herein. In one implementation, the fill material 836 is an oxide, such as Silicon Oxide.

[0042] Figure 9 illustrates an integrated circuit structure subsequent to forming trenches, in accordance with some implementations. In Figure 9, process 900 illustrates an etch process to form trenches 938. In some implementations, the trenches 938A and 938B may etch some of the sidewall of the GaN-based structure 734A, for example. In other implementations, trench 938D may split up GaN-based structure 734B into multiple fin-like features, for example. In

implementations, the etch process may be a GaN-based structure isolation etch using Chlorine (C12) chemistry. In implementations, the trenches 938 may etch at least some of the bottom most interlay ers 318.

[0043] Figure 10 illustrates an integrated circuit structure subsequent to the deposition of isolation material, in accordance with some implementations. In Figure 10, process 1000 illustrates the deposition of isolation material in trenches 938 to form isolation regions around the GaN-based structures 734. The isolation material may include a dielectric material, as described herein, and may include Silicon Nitride or Silicon Oxynitride, for example.

[0044] Figure 11 illustrates an integrated circuit structure subsequent to the deposition of source and drains of GaN transistors, in accordance with some implementations. In Figure 11, process 1100 illustrates the deposition of sources 1142 and drains 1144 of GaN transistors 1146. It may be noted that in implementations, the location of the sources 1142 and drains 1144 may be reversed. In implementations, the sources 1142 and drains 1144 may be doped (e.g., n+) InGaN or GaN material. In implementations, the sources 1142 and drains 1144 may be raised sources and drains. In other implementations, sources 1142 and drains 1144 may be other than raised sources and drains. In implementations, replacement gate 1148 may be a sacrificial gate and be a hardmask material, such as Poly Silicon. In implementations, replacement gate 1148 may be a dielectric material, as described herein. [0045] Figure 12 illustrates an integrated circuit structure subsequent to the formation of contacts, in accordance with some implementations. In Figure 12, process 1200 illustrates the formation of source contact 1250, gate contact 1254, and drain contact 1252 of GaN transistor 1146A. It may be noted that similar contacts are formed for GaN transistors 1146B and 1146B. In implementations, gate contact 1254 may be formed using removable metal gate (RMG) techniques (e.g., remove replacement gate 1148). In implementations, source contact 1250, gate contact 1254, and drain contact 1252 may be a conductive material formed to electrically contact the underlying structure. In implementations, source contact 1250, gate contact 1254, and drain contact 1252 may be metal contacts.

[0046] In implementations, a GaN-based structure, such as GaN-based structure 734A (see

Figure 7) may have a single GaN transistor 1146A. In implementations, the GaN transistor 1146A may include a portion of GaN-based structure 734A, where the portion may include active areas of the GaN-based structure 734A (e.g., channel area including film layer 732A and GaN-based structure segment 616A). In implementations, the portion of GaN-based structure 734A of GaN transistor 1146A may be all or part of GaN-based structure 734A.

[0047] In implementations, a GaN-based structure, such as GaN-based structure 734B may have multiple GaN transistors, such as GaN transistor 1146B and 1146C. In implementations, the GaN transistor 1146B and 1146C may include a different portion of GaN-based structure 734B, where a first portion may include an active area of the GaN-based structure 734B associated with GaN transistor 1146B and a second portion may include an active area of GaN-based structure 734B associated with GaN transistor 1146C (e.g., channel areas of each GaN transistor 1146B and 1146C including film layer 732B and GaN-based structure segment 616B). In implementations, the portion of GaN-based structure 734B included in GaN transistors 1146B and 1146C may include additional parts of GaN-based structure 734B. In implementations, process 1200 shows all or part of integrated circuit 1280.

[0048] Figure 13 is a diagram illustrating a multi-stack interlayer 1354 in a GaN-based structure 1334, in accordance with implementations. For the purposes of clarity, rather than limitation, interlayers of the multi-stack interlayer 1354 may be referred to as an interlayer(s) of the multi- stack interlayer 1354, and interlayers, such as interlayers 318 or 518 as described with respect to Figure 3 and 5, may be referred to as low-temperature (LT) interlayers, hereinafter unless otherwise described. In implementations, interlayers of the multi-stack interlayer 1354 may be formed using a different material than the LT interlayers. For example, the interlayers of multi- stack interlayer 1354 may be formed using Aluminum GaN and the LT interlayers may be formed using A1N. It may be noted that GaN-based structure 1334 may be used in a similar manner as other GaN-based structures described herein,

[0049] In implementations, multi-stack interlayer 1354 may include one or more interlayers of the multi-stack interlayer 1354, such interlayers 1356, 1358, and 1360 of multi-stack interlayer 1354. GaN-based structure segment 1362 may be grown above multi-stack interlayer 1354 similar to GaN-based structure segment 616 of Figure 6. In some implementations, a film layer may be grown above GaN-based structure segment 1362.

[0050] In implementations, interlayers 1356, 1358, and 1360 of multi-stack interlayer 1354 may have varying ratios of GaN. For example, from the direction of the substrate 110 each successive interlayer 1356, 1358, and 1360 of multi-stack interlayer 1354 may have an increasing ratio of GaN. For example, interlayers 1356, 1358, and 1360 of multi-stack interlayer 1354 may be AlGaN where the ratio of GaN to total material progressively increases from 20 percent, 50 percent, and 80 percent, respectively.

[0051] In implementations, the first interlayer 1356 of multi-stack interlayer 1354 may be grown above nucleation layer 114A. In implementations, the GaN of the multi-stack interlayer 1354 may be compressively strained and help counterbalance tensile strain of the GaN-based structure 1334 during cool down, for example. In implementations, interlayers 1356, 1358, and 1360 of multi-stack interlayer 1354 may be a trapezoidal shape. In implementations, interlayers 1356, 1358, and 1360 of multi-stack interlayer 1354 may range from 100 nm to 500 in (vertical) thickness. It may be noted that any number of interlayers of multi-stack interlayer 1354 may be implemented.

[0052] In implementations, the top portion (polar plane) and sidewalls (semi-polar planes) of the interlayers of multi-stack interlayer 1354 may have different material characteristics. In implementations, the top portion of the interlayers 1360, 1358, or 1356 of multi-stack interlayer 1354 may be thicker than the sidewalls of the respective interlayers responsive to the higher growth rate in the <0001> direction. In some implementations, the top portion (e.g., the polar part) of the interlayers 1360, 1358, or 1356 of multi-stack interlayer 1354 may also enable the defect termination and bending of defects towards the so that the final top part of the device is of relatively lower density (e.g., similar to the defects and defect termination described with respect to interlayers 318 of Figure 3).

[0053] In implementations, the multi-stack interlayer 1354 may be used without LT interlayers, such as interlayers 318 and 518. In other implementations, multi-stack interlayer 1354 may be used in combination with one or more LT interlayers. For example, a large area structure of 2500 um or larger may use both a multi-stack interlayer 1354 and one or more LT interlayers. In other implementations, multi-stack interlayer 1354 may be used in conjunction with one or more interlayers 318 or 518, and/or in conjunction with a super lattice, as described herein. In implementations, process 1300 shows all or part of integrated circuit 1380.

[0054] Figures 14 illustrate a flow diagram of a fabrication process for forming GaN transistors having GaN-based structures with various interlayers, according to an implementation. It may be noted that elements of Figures 1-13 may be described below to help illustrate method 1400. Method 1400 may be performed as one or more operations. It may be noted that method 1400 may be performed in any order and may include the same, more, or fewer operations. It may be noted that method 1400 may be performed by one or more pieces of semiconductor fabrication equipment or fabrication tools.

[0055] Method 1400 begins at operation 1405 by growing a multi-stack interlayer 1354 above the substrate. In implementations, the multi-stack interlayer 1354 may be grown directly above nucleation layer 114. In implementations, the interlayers of multi-stack interlayer 1354 may be AlGaN with varying ratios of GaN. In other implementations, a multi-stack interlayer 1354 may not be used in a GaN-based structure. At operation 1410, a first segment of a GaN-based structure is grown above the substrate 110. In implementations using multi-stack interlayer 1354, the first segment of the GaN-based structure may be grown above the multi- stack interlayer 1354. At operation 1415, the first interlayer (e.g., LT interlayer) is grown above the first segment of the GaN-based structure. In implementations, the first interlayer is A1N.

[0056] At operation 1420, a second segment of the GaN-based structure is grown above the first interlayer. At operation 1425, another interlayer (e.g., LT interlayer) is grown above the second segment of the GaN-based structure. In an implementation, the second interlayer is A1N. At operation 1430, a third segment of the GaN-based structure is grown above the second interlayer. At operation 1435, a film layer is grown above the third segment of the GaN-based structure. At operation 1440, a first GaN transistor is formed above the substrate 110, where the first GaN transistor includes at least a portion of the GaN-based structure.

[0057] Figure 15 illustrates an interposer, according to implementations. The interposer 1500 may be an intervening substrate used to bridge a first substrate 1502 to a second substrate 1504. The first substrate 1502 may be, for instance, an integrated circuit die, including integrated circuit 1280 or 1380. The second substrate 1504 may be, for instance, a memory module, a computer motherboard, backplane, or another integrated circuit die. In one implementation, first substrate 1502 may be an integrated circuit die described with respect to Figures 1-13.

Generally, the purpose of an interposer 1500 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1500 may couple an integrated circuit die to a ball grid array (BGA) 1506 that can subsequently be coupled to the second substrate 1504. In some implementations, the first and second substrates 1502/1504 are attached to opposing sides of the interposer 1500. In other implementations, the first and second substrates 1502/1504 are attached to the same side of the interposer 1500. In further

implementations, three or more substrates are interconnected by way of the interposer 1500.

[0058] The interposer 1500 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[0059] The interposer may include metal interconnects 1508 and vias 1510, including but not limited to through- silicon vias (TSVs) 1512. The interposer 1500 may further include embedded devices 1514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, or MEMS devices, may also be formed on the interposer 1500. In accordance with one or more implementations, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1500.

[0060] Figure 16 is a computing device built in accordance with implementations of the present disclosure. The computing device 1600 may include a number of components. In one

implementation, the components are attached to one or more motherboards. In an alternate implementation, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices. In implementations, the components in the computing device 1600 include, but are not limited to, an integrated circuit 1280 or 1380 and at least one communications logic unit 1608. In some implementations the communications logic unit 1608 is fabricated within the integrated circuit die 1602 while in other implementations the communications logic unit 1608 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1602. The integrated circuit die 1602 may include a CPU 1604 as well as on-die memory 1606, often used as cache memory that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM). It may be noted that in implementations integrated circuit die 1602 may include fewer elements (e.g., without processor 1604 and/or on-die memory 1606) or additional elements other than processor 1604 and on-die memory 1606. In one example, integrated circuit die 1602 may include an integrated circuit 1280 or 1380 as described herein. In another example, integrated circuit die 1602 may include some or all the elements described herein, as well as include additional elements.

[0061] Computing device 1600 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1610 (e.g., DRAM), non-volatile memory 1612 (e.g., ROM or flash memory), a graphics processing unit 1614 (GPU), a digital signal processor 1616, a crypto processor 1642 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1620, at least one antenna 1622 (in some implementations two or more antenna may be used), a display or a touchscreen display 1624 (e.g., that may include integrated circuit die 1602) , a touchscreen controller 1626, a battery 1628 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1627, a compass (not shown), a motion coprocessor or sensors 1632 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 1634, a camera 1636, user input devices 1638 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1640 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 1600 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 1600 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 1600 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and

radiating electromagnetic waves in air or space.

[0062] The communications logic unit 1608 enables wireless communications for the transfer of data to and from the computing device 1600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some implementations they might not. The communications logic unit 1608 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1600 may include a multitude of communications logic units 1608. For instance, a first

communications logic unit 1608 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 1608 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0063] The processor 1604 (also referred to "processing device" herein) of the computing device 1600 includes one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure. The term "processor" or "processing device" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Processor 1604 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processor 1604 may be complex instruction set computing (CISC)

microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLrW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor 1604 may also be one or more special- purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like.

[0064] The communications logic unit 1608 may also include one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.

[0065] In further implementations, another component housed within the computing device 1600 may contain one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.

[0066] In various implementations, the computing device 1600 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an

entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1600 may be any other electronic device that processes data. [0067] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0068] Various operations are described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

[0069] The terms "over", "above", "under", "between", "adjacent", and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed above or over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0070] Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to Germanium, Indium Antimonide, Lead Telluride, Indium Arsenide, Indium Phosphide, Gallium Arsenide, Indium Gallium Arsenide, Gallium Antimonide, or other combinations of group III- V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.

[0071] A multitude of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.

[0072] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si0₂) and/or a high-k dielectric material. The high-k dielectric material may include elements such as Hafnium, Silicon, Oxygen, Titanium, Tantalum, Lanthanum, Aluminum, Zirconium, Barium, Strontium, Yttrium, Lead, Scandium, Niobium, and Zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, Hafnium Oxide, Hafnium Silicon Oxide, Lanthanum Oxide, Lanthanum Aluminum Oxide, Zirconium Oxide, Zirconium Silicon Oxide, Tantalum Oxide, Titanium Oxide, Barium Strontium Titanium Oxide, Barium Titanium Oxide, Strontium Titanium Oxide, Yttrium Oxide, Aluminum Oxide, Lead Scandium Tantalum Oxide, and Lead Zinc Niobate. In some implementations, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0073] The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

[0074] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, Ruthenium, Palladium, Platinum, Cobalt, Nickel, and conductive metal oxides, e.g., Ruthenium Oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, Hafnium, Zirconium, Titanium, Tantalum, Aluminum, alloys of these metals, and carbides of these metals such as Hafnium Carbide, Zirconium Carbide, Titanium Carbide, Tantalum Carbide, and Aluminum Carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0075] In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0076] In some implementations of the disclosure, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as Silicon Nitride, Silicon Oxide, Silicon Carbide, Silicon Nitride doped with Carbon, and Silicon Oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a multitude of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0077] In implementations, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions may be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as Boron, Aluminum, Antimony, Phosphorous, or Arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion

implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a Silicon alloy such as Silicon Germanium or Silicon Carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as Boron, Arsenic, or Phosphorous. In further implementations, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further implementations, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0078] In other implementations, one or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, Silicon Dioxide (Si0₂), Carbon doped oxide (CDO), Silicon Nitride, organic polymers such as Perfluorocyclobutane or Polytetrafluoroethylene, Fluorosilicate glass (FSG), and organosilicates such as Silsesquioxane, Siloxane, or Organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[0079] The words "example" or "exemplary" are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example' or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs.

Rather, use of the words "example" or "exemplary" is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless specified otherwise, or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims may generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term "an

implementation" or "one implementation" or "an implementation" or "one implementation" throughout is not intended to mean the same implementation or implementation unless described as such. The terms "first," "second," "third," "fourth," etc. as used herein are meant as labels to distinguish among different elements and may not necessarily have an ordinal meaning according to their numerical designation.

Claims

CLAIMS What is claimed is:

1. An integrated circuit die comprising:

a semiconductor substrate;

a Gallium Nitride (GaN) transistor disposed above the semiconductor substrate and comprising a portion of a GaN-based structure; and

an interlayer of the GaN-based structure, wherein the GaN-based structure is disposed above an outer surface of the interlayer, the interlayer having polar orientation and semi-polar orientation.

2. The integrated circuit die of claim 1, wherein the GaN transistor is a first GaN transistor and the GaN-based structure is a first GaN-based structure, the integrated circuit further comprising:

a second GaN transistor disposed above the semiconductor substrate and comprising a portion of a second GaN-based structure, wherein the first GaN-based structure and the second GaN-based structure have a trapezoidal shape and are physically separate.

3. The integrated circuit die of claim 1 or 2, wherein the interlayer is a first interlayer, the integrated circuit die further comprising:

a multi-stack interlayer disposed above the semiconductor substrate, the multi-stack interlayer comprising the first interlayer and a second interlayer disposed below the first interlayer, wherein the first interlayer and the second interlayer comprise GaN, wherein first interlayer comprises a higher ratio of GaN than the second interlayer.

4. The integrated circuit die of claim 3, wherein the first interlayer and the second interlayer comprise Aluminum GaN (AlGaN).

5. The integrated circuit of claim 1, wherein the interlayer is a first interlayer, the integrated circuit die further comprising:

a third interlayer of the GaN-based structure disposed above the first interlayer and within the GaN-based structure, wherein the GaN-based structure is disposed above an outer surface and below an inner surface of the third interlayer, the third interlayer having the polar orientation and the semi-polar orientation.

6. The integrated circuit die of claim 1, wherein the interlayer comprises Aluminum Nitride (A1N).

7. The integrated circuit die of claim 1, wherein the interlayer comprises:

a top portion of the interlayer having the polar orientation; and

sidewalls of the interlayer having semi-polar orientation, wherein material characteristics of the top portion are different than material characteristics of the sidewalls.

8. The integrated circuit die of claim 7, wherein the top portion of the interlayer is thicker than the sidewalls of the interlayer.

9. The integrated circuit die of claim 8, wherein a ratio of thickness between the sidewalls and top portion is less than or equal to 0.3.

10. The integrated circuit die of claim 7, wherein top portion comprises a polycrystalline structure and the sidewalls comprise a crystalline structure.

11. The integrated circuit die of claim 1, wherein a defect in the GaN-based structure terminates at an inner surface of the interlayer.

12. The integrated circuit die of claim 1, wherein the semiconductor substrate comprises Silicon (111).

13. The integrated circuit die of claim 1, wherein the GaN-based structure covers an area of 500 microns (um) or greater.

14. A computing device, comprising:

a memory; and

an integrated circuit, operatively coupled to the memory, the integrated circuit comprising:

a semiconductor substrate;

a Gallium Nitride (GaN) transistor disposed above the semiconductor substrate and comprising a portion of a GaN-based structure; and an interlayer of the GaN-based structure, wherein the GaN-based structure is disposed above an outer surface of the interlayer, the interlayer having polar orientation and semi-polar orientation.

15. The computing device of claim 14, wherein the GaN transistor is a first GaN transistor and the GaN structure is a first GaN structure, the computing device further comprising:

16. The computing device of claim 14 or 15, wherein the interlayer is a first interlayer, the computing device further comprising:

17. The computing device of claim 14, wherein the interlayer is a first interlayer, the computing device further comprising:

18. A method of fabricating an integrated circuit, comprising:

growing a first segment of a Gallium Nitride (GaN) based structure above a

semiconductor substrate;

growing an interlayer above the first segment of the GaN-based structure; and

growing a second segment of the GaN-based structure above the interlayer, wherein the second segment of the GaN-based structure is disposed above an outer surface of the interlayer, the interlayer having polar orientation and semi-polar orientation.

19. The method of fabricating the integrated circuit of claim 18, wherein the interlayer is a first interlayer, the method further comprising: forming a multi-stack interlayer above the semiconductor substrate, the multi-stack interlayer comprising a second interlayer and a third interlayer disposed above the second interlayer, wherein the first interlayer is disposed above the second and the third interlayer, and wherein the second interlayer and the third interlayer comprise GaN, wherein the third interlayer comprises a higher ratio of GaN than the second interlayer.

20. The method of fabricating the integrated circuit of claim 18, further comprising:

forming a first GaN transistor above the semiconductor substrate, wherein the first GaN transistor comprises a first portion of the GaN-based structure.

21. The method of fabricating the integrated circuit of claim 20, further comprising:

forming a second GaN transistor above the semiconductor substrate, wherein the second

GaN transistor comprises a second portion of the GaN-based structure.

22. The method of fabricating the integrated circuit of claim 18, wherein the interlayer is a first interlayer, the method further comprising:

growing a fourth interlayer above the second segment of the GaN-based structure; and growing a third segment of the GaN-based structure above the fourth interlayer, wherein the third segment of the GaN-based structure disposed above an outer surface of the fourth interlayer, the fourth interlayer having the polar and the semi-polar orientation.

23. The method of fabricating the integrated circuit of claim 18, wherein growing the interlayer above the first segment of the GaN-based structure comprises:

growing a top portion and sidewalls of the interlayer responsive to an interlayer process, wherein the top portion has the polar orientation and the sidewalls have the semi-polar orientation, and wherein material characteristics of the top portion are different than material characteristics of the sidewalls.

24. The method of fabricating the integrated circuit of claim 18, wherein the interlayer comprises Aluminum Nitride (AIN) formed at a process temperature at or below 900 degrees Celsius.

25. The method of fabricating the integrated circuit of claim 18, wherein a defect in the GaN- based structure terminates at an inner surface of the interlayer.