WO2018175059A1 - Système et procédé d'exécution spéculative de commandes à l'aide du tampon de mémoire de dispositif de commande - Google Patents

Système et procédé d'exécution spéculative de commandes à l'aide du tampon de mémoire de dispositif de commande Download PDF

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Publication number
WO2018175059A1
WO2018175059A1 PCT/US2018/019905 US2018019905W WO2018175059A1 WO 2018175059 A1 WO2018175059 A1 WO 2018175059A1 US 2018019905 W US2018019905 W US 2018019905W WO 2018175059 A1 WO2018175059 A1 WO 2018175059A1
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Prior art keywords
command
memory
memory device
host device
submission queue
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PCT/US2018/019905
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English (en)
Inventor
Shay Benisty
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Western Digital Technologies, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/468,620 external-priority patent/US10466903B2/en
Priority claimed from US15/585,827 external-priority patent/US10725835B2/en
Application filed by Western Digital Technologies, Inc. filed Critical Western Digital Technologies, Inc.
Priority to DE112018000230.6T priority Critical patent/DE112018000230T5/de
Priority to CN201880005085.9A priority patent/CN110073323B/zh
Publication of WO2018175059A1 publication Critical patent/WO2018175059A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/067—Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]

Definitions

  • NVM Express is a standard for accessing non-volatile storage media attached via PCI Express (PCIe) bus. NVMe may be used with a variety of non-volatile storage media, such as solid state drives (SSDs).
  • SSDs solid state drives
  • One focus of NVMe relates to I/O communication between a host device (which may access and/or write to the non-volatile storage media) and a memory device (which includes the non-volatile storage media).
  • NVMe implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. Completions are placed onto the associated completion queue by the memory device controller.
  • FIG. 1 A is a block diagram of an exemplary non-volatile memory system.
  • FIG. IB is a block diagram of a storage module that includes a plurality of non- volatile memory systems and a host.
  • FIG. 1C is a block diagram of a hierarchical storage system.
  • FIG. 2A is a block diagram of exemplary components of a controller of the non-volatile memory system of FIG. 1A.
  • FIG. 2B is a block diagram of exemplary components of a non-volatile memory die of the nonvolatile memory system of FIG. 1A.
  • FIG. 3 is a block diagram of the host device and NVMe controller illustrating a sequence for a host device and a memory device to request and process an NVMe command.
  • FIG. 4 is a block diagram of other exemplary components of a host device and a memory device.
  • FIG. 5 is a flow chart for speculative execution of a command in the submission queue.
  • FIG. 6 is a flow chart for speculative execution of a read command in the submission queue.
  • NVMe is based on a paired submission queue (SQ) and completion queue (CQ).
  • the host device using host software, places commands into a respective submission queue.
  • the memory device via the memory device controller, places entries on the associated completion queue, with the entries indicative of completed execution of commands.
  • submission queues and completion queues are allocated in the host device memory, such as in a host memory buffer.
  • the allocation for the queues in the host memory buffer may be physically located contiguously or non-contiguously.
  • the memory device controller performs a PCI Express (PCle) read from host memory in order to fetch the queue entries.
  • PCle PCI Express
  • the submission queues and completion queues may be stored in the memory device.
  • the Controller Memory Buffer enables the host device to place the submission queues and completion queues in controller memory.
  • a controller memory based queue is used in the same manner as a host memory based queue, with the difference being that the memory address used is located within the memory device (e.g., within the memory device controller's own memory rather than in the host memory).
  • the Admin and/or I/O Queues may be placed in the CMB, as discussed in more detail below.
  • all memory associated with the particular queue resides entirely in either the CMB or in host memory.
  • submission queues in controller memory enable the host software to directly write the entire submission queue entry to the memory device controller's internal memory space, thereby avoiding one read from the memory device controller to the host device.
  • Example types of queues include admin queues and I/O queues.
  • the admin queue such as the admin submission and completion queues, is an administrative submission queue, which includes administrative commands to the memory device.
  • Example administrative commands include, but are not limited to: Get Log Page (e.g., retrieves an NVMe log page from an NVMe device and provides the retuned structure); Identify (e.g., returns a data buffer that describes information about the NVMe subsystem, the controller or the namespaces), Get Features (e.g., retrieves the attributes of the Feature specified)/ and Set Features (e.g., specifies the attributes of the Feature indicated).
  • the administrative commands listed are merely for illustration purposes.
  • the I/O queues may relate to data transfer, such as read commands (e.g., reading data from the flash memory) and write commands (e.g., writing data to the flash memory).
  • the host device first writes commands to the submission queue, and thereafter notifies the memory device by updating the submission queue tail doorbell register, as discussed in more detail below.
  • the memory device controller begins to process the command.
  • the memory write request to the submission queue tail doorbell register shall not have the relaxed ordering bit set, to ensure that it arrives at the memory device controller after all writes to the CMB.
  • the memory device controller begins to process a command prior to notification by the host device of the command on the submission queue (e.g., prior to notification via the submission queue tail doorbell register). For example, the memory device may determine whether the host device has written a command to the submission queue. This may be performed in one of several ways. In one way, the memory device may monitor the NVMe submission queues physically located in the controller memory buffer, thereby enabling the memory device to begin speculative execution of the commands even before receiving the corresponding notification from the host device (e.g., the doorbell write transactions).
  • the memory device may monitor a communication interface between the host device and the memory device (e.g., the ingress of the PCle bus) to determine whether the host device has sent any communications indicative of writing a command to a submission queue.
  • the memory device may parse the command(s), and responsive to determining that one or more new commands are on the submission queue, may begin the execution of the one or more new commands in a speculative manner.
  • Various commands may be subject to speculative execution.
  • a read command may be subject to speculative read command execution, triggering a Read Look Ahead (RLA) algorithm.
  • the relevant data subject to the read command may be fetched from the flash memory to a temporal buffer.
  • the host device notifies the memory device of the command (e.g., queues the relevant command in by issuing a write transaction to the corresponding submission queue doorbell register)
  • the data may be fetched immediately from the temporal buffer and provided to the host device.
  • the RLA hit may result in better flash memory latency (e.g., sense and transfer time) and thereby result in better performance.
  • a write command may be subject to speculative write command execution. For example, one or more steps for performing the write command, such as fetching the flash translation layer (FTL) table, may be performed prior to the host device queuing the command.
  • FTL flash translation layer
  • the memory device selectively performs speculative execution of commands.
  • the memory device may analyze the command, and based on the type of command, may determine whether to speculatively begin execution of the command prior to notification of the host device, via the doorbell register, of placement of the command on the submission queue.
  • commands such as read commands, write commands, and the like.
  • the read command includes a pointer to a PRP list, with the PRP list indicating the sections in host memory where the memory device is to write the data that was read from flash memory.
  • the write command includes a pointer to a PRP list that indicates the sections in host memory where the data to write to flash is located (i.e., the memory device uses the PRP list to read host memory locations for data, with the read data being written to flash memory).
  • the memory device may analyze at least one aspect of the command, such as the priority of the command, may determine whether (or when) to speculatively begin execution of the command prior to notification of the host device, via the doorbell register, of placement of the command on the submission queue.
  • the priority of the command may determine whether (or when) to speculatively begin execution of the command prior to notification of the host device, via the doorbell register, of placement of the command on the submission queue.
  • the memory device may determine priority for a command (or for performing one or more phases) based on one or more criteria including any one, any combination or all of the following: (1) priority of the respective command; (2) internals of the memory device (e.g., the state of the die or the processing capability of the memory device, as discussed below); (3) power consumption; (4) state of the communication interface between the host device and the memory device (e.g., the status of the ingress and/or egress path); and (5) the phases of the commands subject to execution. Depending on the priority associated with the command, the memory device may determine whether a command is subject to speculative execution.
  • the memory device determines the priority of a first command and a second command, the priority associated with the first command being higher than the priority associated with the second command. Based on the determined priorities, the memory device performs speculative execution of the first command prior to, or instead of, speculative execution of the second command. Alternatively, in the event that the memory device is performing speculative execution of the second command, the memory device may halt performing speculative execution of the second command and begin speculative execution of the first command in response to determining that the host device has placed the first command on the submission queue and in response to determining that the priority associated with the first command being higher than the priority associated with the second command.
  • the memory device performs the speculative execution only on processes internal to the memory device, but not to processes that involve the host device (e.g., that are external to or involve communication with the host device).
  • any process involving the host device such as a reading a PRP list on the host device, is not speculatively performed.
  • an internal process such as reading from flash memory, performing error correction or encryption/decryption, may be speculatively performed.
  • the memory device may perform speculative execution of a read command, but not perform speculative execution of a write command.
  • the memory device prior to receiving the doorbell notice from the host device, the memory device speculatively performs certain processes in executing the read command, such as performing the read from the flash memory, performing error correction and encryption, but does not perform other processes related to communication with the host device, such as reading of the PRP list that is resident on the host device.
  • NVMe command execution performance is the time between the host device issuing a doorbell write to a submission queue and the memory device posting a completion message to a completion queue. Using the speculative execution, this time may be reduced. In this regard, speculative execution may improve performance for certain commands, such as read and write command, particularly in low queue depths. Further, command execution latency, which may be measured on the PCIe bus, may be improved for various command types (e.g., read, write, and Admin commands). Finally, the speculative execution may be implemented in either hardware or firmware, thereby simplifying implementation within the memory device.
  • the host device will notify the memory device of the command (e.g., the command will eventually be queued-in by the host device writing to the relevant tail doorbell register). Atypically, the host device may write a command to the submission queue, and thereafter override the command with a different command and then queue the different command. Regardless, the speculative execution may account for this atypical situation.
  • FIG. 1A is a block diagram illustrating a non-volatile memory device 100.
  • the non-volatile memory device 100 may include a controller 102 and non-volatile memory that may be made up of one or more non-volatile memory dies 104.
  • the term die refers to the set of non-volatile memory cells, and associated circuitry for managing the physical operation of those non-volatile memory cells, that are formed on a single semiconductor substrate.
  • the controller 102 may interface with a host device or a host system and transmit command sequences for read, program, and erase operations to the non-volatile memory die(s) 104.
  • the commands may include logical and/or physical addresses.
  • the controller 102 (which may be a flash memory controller) can take the form of processing circuitry, a microprocessor or processor, and a computer-readable medium that stores computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example.
  • the controller 102 can be configured with hardware and/or firmware to perform the various functions described below and shown in the flow diagrams. Also, some of the components shown as being internal to the controller can also be stored external to the controller, and other components can be used. Additionally, the phrase "operatively in communication with” could mean directly in communication with or indirectly (wired or wireless) in communication with through one or more components, which may or may not be shown or described herein.
  • a flash memory controller is a device that manages data stored on flash memory and communicates with a host, such as a computer or electronic device.
  • a flash memory controller can have various functionality in addition to the specific functionality described herein.
  • the flash memory controller can format the flash memory to ensure the memory is operating properly, map out bad flash memory cells, and allocate spare cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the flash memory controller and implement other features.
  • the firmware is a flash translation layer. In operation, when a host device needs to read data from or write data to the flash memory, it will communicate with the flash memory controller.
  • the flash memory controller can convert the logical address received from the host to a physical address in the flash memory.
  • the flash memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused).
  • the interface between the controller 102 and the non-volatile memory die(s) 104 may be any suitable flash interface, such as Toggle Mode 200, 400, or 800.
  • the memory device 100 may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card.
  • the system 100 may be part of an embedded memory device.
  • the non- volatile memory device 100 may include a single channel between the controller 102 and the non-volatile memory die(s) 104
  • the subject matter described herein is not limited to having a single memory channel.
  • 2, 4, 8 or more NAND channels may exist between the controller and the NAND memory die(s) 104, depending on controller capabilities.
  • more than a single channel may exist between the controller and the memory die(s) 104, even if a single channel is shown in the drawings.
  • FIG. IB illustrates a storage module 200 that includes plural non-volatile memory devices 100.
  • the storage module 200 may include a storage controller 202 that interfaces with a host 220 and with a storage system 204, which includes a plurality of non-volatile memory devices 100.
  • the interface between the storage controller 202 and non- volatile memory devices 100 may be a bus interface, such as a serial advanced technology attachment (SATA), a peripheral component interface express (PCle) interface, an embedded MultiMediaCard (eMMC) interface, a SD interface, or a Universal Serial Bus (USB) interface, as examples.
  • the storage system 200 in one embodiment, may be a solid state drive (SSD), such as found in portable computing devices, such as laptop computers and tablet computers, and mobile phones.
  • SSD solid state drive
  • FIG. 1C is a block diagram illustrating a hierarchical storage system 250.
  • the hierarchical storage system 250 may include a plurality of storage controllers 202, each of which control a respective storage system 204.
  • Host systems 252 may access memories within the hierarchical storage system 250 via a bus interface.
  • Example bus interfaces may include a non-volatile memory express (NVMe), a fiber channel over Ethernet (FCoE) interface, an SD interface, a USB interface, a SATA interface, a PCle interface, or an eMMC interface as examples.
  • the hierarchical storage system 250 illustrated in FIG. 1C may be a rack mountable mass storage system that is accessible by multiple host computers, such as would be found in a data center or other location where mass storage is needed.
  • host systems 252 may include the functionality described in host 220.
  • FIG. 2A is a block diagram illustrating exemplary components of the controller 102 in more detail.
  • the controller 102 may include a front end module 108 that interfaces with a host, a back end module 110 that interfaces with the non-volatile memory die(s) 104, and various other modules that perform various functions of the non-volatile memory device 100.
  • a module may be hardware or a combination of hardware and software.
  • each module may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof.
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • each module may include memory hardware that comprises instructions executable with a processor or processor circuitry to implement one or more of the features of the module.
  • the module may or may not include the processor.
  • each module may just be the portion of the memory that comprises instructions executable with the processor to implement the features of the corresponding module without the module including any other hardware. Because each module includes at least some hardware even when the included hardware comprises software, each module may be
  • a hardware module interchangeably referred to as a hardware module.
  • the controller 102 may include a buffer manager/bus control module 114 that manages buffers in random access memory (RAM) 116 and controls the internal bus arbitration for communication on an internal communications bus 117 of the controller 102.
  • a read only memory (ROM) 118 may store and/or access system boot code.
  • FIG. 2A illustrated in FIG. 2A as located separately from the controller 102, in other embodiments one or both of the RAM 116 and the ROM 118 may be located within the controller 102. In yet other embodiments, portions of RAM 116 and ROM 118 may be located both within the controller 102 and outside the controller 102. Further, in some implementations, the controller 102, the RAM 116, and the ROM 118 may be located on separate semiconductor dies. As discussed below, in one implementation, the submission queues and the completion queues may be stored in the Controller Memory Buffer, which may be housed in RAM 116.
  • the front end module 108 may include a host interface 120 and a physical layer interface (PHY) 122 that provide the electrical interface with the host or next level storage controller.
  • PHY physical layer interface
  • the choice of the type of the host interface 120 can depend on the type of memory being used. Examples types of the host interface 120 may include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe.
  • the host interface 120 may typically facilitate transfer for data, control signals, and timing signals.
  • the back end module 110 may include an error correction controller (ECC) engine 124 that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the nonvolatile memory die(s) 104.
  • ECC error correction controller
  • the ECC engine may be tunable, such as to generate different amounts of ECC data based on the mode (e.g., generate normal mode ECC data in normal programming mode and generate burst mode ECC data in burst programming mode, with the burst mode ECC data being greater than the normal mode ECC data).
  • the back end module 110 may also include a command sequencer 126 that generates command sequences, such as program, read, and erase command sequences, to be transmitted to the non-volatile memory die(s) 104. Additionally, the back end module 110 may include a RAID (Redundant Array of Independent Drives) module 128 that manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the non-volatile memory device 100. In some cases, the RAID module 128 may be a part of the ECC engine 124.
  • a memory interface 130 provides the command sequences to the non-volatile memory die(s) 104 and receives status information from the non-volatile memory die(s) 104.
  • the memory interface 130 may be a double data rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface.
  • DDR double data rate
  • a flash control layer 132 may control the overall operation of back end module 110.
  • the controller 102 may include one or more management tables for managing operations of storage system 100.
  • One type of management table includes logical-to-physical address mapping table.
  • the size of logical-to-physical address mapping table may grow with memory size.
  • the logical-to- physical address mapping table for high capacity storage device e.g., greater than 32G
  • the logical-to- physical address mapping table for high capacity storage device may be too large to store in SRAM, are may be stored in non-volatile memory 104 along with user and host data. Therefore, accesses to non-volatile memory 104 may first require reading the logical-to-physical address mapping table from non-volatile memory 104.
  • Additional modules of the non-volatile memory device 100 illustrated in FIG. 2A may include a media management layer 138, which performs wear leveling of memory cells of the non-volatile memory die 104.
  • the non-volatile memory device 100 may also include other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with controller 102.
  • one or more of the RAID module 128, media management layer 138 and buffer management/bus controller 114 are optional components that may not be necessary in the controller 102.
  • modules of the non-volatile memory device 100 illustrated in FIG. 2A may include host command written module 111, speculative command execution module 112, and host overwrite determination module 113. These modules are shown as separate from the other modules of the non-volatile memory device 100, although in other configurations, one or more of them may be part of any of the other modules.
  • the memory device may determine whether the host device has written to the submission queue prior to the host device formally notifying the memory device using the host command written module 111. Further, in response to the memory device determining that the host has written a command to the submission queue, the speculative command execution module 112 may begin to execute the command prior to formal notice from the host device. In addition, the host overwrite determination module 113 may determine whether the host device has overwritten the command that is subject to the speculative execution, as discussed in more detail below.
  • FIG. 2B is a block diagram illustrating exemplary components of a non- volatile memory die 104 in more detail.
  • the non-volatile memory die 104 may include a non-volatile memory array 142.
  • the nonvolatile memory array 142 may include a plurality of non-volatile memory elements or cells, each configured to store one or more bits of data.
  • the non-volatile memory elements or cells may be any suitable non-volatile memory cells, including NAND flash memory cells and/or NOR flash memory cells in a two dimensional and/or three dimensional configuration.
  • the memory cells may take the form of solid-state (e.g., flash) memory cells and can be one-time programmable, few-time programmable, or many-time programmable.
  • the memory elements or cells may be configured as single-level cells (SLCs) that store a single bit of data per cell, multi-level cells (MLCs) that store multiple bits of data per cell, or combinations thereof.
  • the multi-level cells (MLCs) may include triple-level cells (TLCs) that store three bits of data per cell.
  • a flash memory cell may include in the array 142 a floating gate transistor (FGT) that has a floating gate and a control gate.
  • the floating gate is surrounded by an insulator or insulating material that helps retain charge in the floating gate.
  • the presence or absence of charges inside the floating gate may cause a shift in a threshold voltage of the FGT, which is used to distinguish logic levels. That is, each FGT's threshold voltage may be indicative of the data stored in the memory cell.
  • FGT floating gate transistor
  • memory element and memory cell may be used interchangeably to refer to the same physical entity.
  • the memory cells may be disposed in the memory array 142 in accordance with a matrix-like structure of rows and columns of memory cells. At the intersection of a row and a column is a FGT (or memory cell).
  • a column of FGTs may be referred to as a string. FGTs in a string or column may be electrically connected in series.
  • a row of FGTs may be referred to as a page. Control gates of FGTs in a page or row may be electrically connected together.
  • the memory array 142 may also include wordlines and bitlines connected to the FGTs. Each page of FGTs is coupled to a wordline. In particular, each wordline may be coupled to the control gates of FGTs in a page. In addition, each string of FGTs may be coupled to a bitline. Further, a single string may span across multiple wordlines, and the number of FGTs in a string may be equal to the number of pages in a block.
  • the non-volatile memory die 104 may further include a page buffer or data cache 144 that caches data that is sensed from and/or that is to be programmed to the memory array 142.
  • the non-volatile memory die 104 may also include a row address decoder 146 and a column address decoder 148.
  • the row address decoder 146 may decode a row address and select a particular wordline in the memory array 142 when reading or writing data to/from the memory cells in the memory array 142.
  • the column address decoder 148 may decode a column address to select a particular group of bitlines in the memory array 142 to be electrically coupled to the data cache 144.
  • the non-volatile memory die 104 may include peripheral circuitry 150.
  • the peripheral circuitry 150 may include a state machine 151 that provides status information to the controller 102. Other functionality of the state machine 151 is described in further detail below.
  • FIG. 3 illustrates a sequence of steps for executing a command via the NVMe standard.
  • the host device 300 includes host memory 302, and the memory device includes a controller, such as an NVMe controller 310.
  • the host memory 302 includes a submission queue 304 and a completion queue 306.
  • the host device 300 creates one or more submission queues and one or more corresponding completion queues.
  • the submission queues and completion queues may have a 1 : 1 correlation, and in another implementation, the submission queues and completion queues do not have a 1 : 1 correlation.
  • the host device 300 may notify the memory device of the submission queue(s) and completion queue(s) by sending information, such as the base address for each queue to the memory device.
  • each submission queue has a corresponding completion queue.
  • the host device sends information to the memory device in order for the memory device to determine the locations of the submission queue and the completion queue in the host device.
  • the host device sends a command indicating the creation of the submission queue and the completion queue.
  • the command may include a PRP1 pointer, which is a pointer to a list on the host device of the locations of the specific submission queue or the specific completion queue.
  • the memory device sends a TLP read request using the PRP1 in order to obtain the PRP list, and stores the PRP list in the memory device to determine the memory locations within the host device for use in future commands to read from the specific submission queue or write to the specific completion queue.
  • the host device 300 may instruct the memory device to create the submission queue(s) and corresponding completion queue(s) in a memory resident in the memory device, such as a controller memory buffer.
  • the submission queue 304 may be based on a ring buffer, such as shown in FIG. 3, with a head pointer and a tail pointer.
  • the host device 300 may write a command (or several commands) to the submission queue. This is indicated in FIG. 3 as step 1, labeled "Queue Command". In particular, FIG. 3 illustrates that four commands were written to the submission queue.
  • the memory device is unaware that the host device 300 has updated the submission queue 304 with four commands, since the host device 300 updated its own host memory 302.
  • the memory device may monitor a communication interface between the host device 300 and the memory device for particular communications, such as writing to the submission queue(s) resident on the memory device.
  • the memory device can monitor the transport layer packets (TLPs) on the PCI Express bus to determine whether the host device 300 has sent a TLP that results in an update to the submission queue resident in the controller memory buffer.
  • TLPs transport layer packets
  • the memory device may identify one or more entries being written to the submission queue(s).
  • step 2 the host device 300 writes to a submission queue tail doorbell register 312 in the memory device.
  • This writing to the submission queue tail doorbell register 312 signifies to the memory device that the host device queued one or more commands in this specific submission queue 304 (e.g., 4 commands as illustrated in FIG. 3).
  • the writing to the submission queue tail doorbell register 312 may take one of several forms. In one way, the host device 300 indicates a new tail for the submission queue 304, thereby indicating the number of commands written to the submission queue 304. Thus, since the memory device is aware of the base address for the submission queue 304, the memory device only needs to know the tail address to indicate the number of new commands written to the submission queue 304.
  • each submission queue 304 has a corresponding submission queue tail doorbell register in the memory device, so that when the host device 300 updates a particular doorbell register (correlated to a particular submission queue 304), the memory device can determine, based on the doorbell register, which particular submission queue 304 has been updated.
  • step 2 (whereby the memory device is notified of command(s) on the submission queue 304) and before step 3 (whereby the memory device fetches the command(s)), the memory device is aware that there are command(s) pending in the submission queue 304. In the general case, there may be several submission queues (with potentially many pending commands in the several submission queues). Thus, before performing step 3, the memory device controller may arbitrate between the various submission queues to select the particular submission queue from which to fetch the command(s).
  • the memory device fetches the command(s) from the particular submission queue 304.
  • the memory device may access the base address of the particular submission queue 304 plus the pointer on the current head pointer implemented in the host device 300.
  • the submission queue or completion queue may be assigned an area of memory (such as in the host device or in the controller memory buffer in the memory device).
  • the submission queue and completion queues may include multiple entries, each associated with a specific command.
  • the size of each entry may be a predetermined size, such as 64Kb.
  • entries within the submission queue may be determined using the base address for the submission queue, and by offsetting the base address with the number of entries multiplied by the size of each entry (e.g., 64Kb).
  • the memory device is aware of the tail pointer, having been notified via step 2. Thus, the memory device can obtain all of the new commands from the submission queue 304.
  • the memory device may send a TLP request to obtain the command(s) from the submission queue 304. Responsive to receipt of the TLP request, the host device 300 sends a completion TLP message with the commands in the submission queue 304. In this regard, at end of step 3, the memory device receives the command(s) from the submission queue 304.
  • the memory device processes the command.
  • the memory device parses the commands, and determines the steps to execute the commands (e.g., read/write/etc. ).
  • the command may comprise a read command. Responsive to receipt of the read command, the memory device parses the read command, implements the address translation, and accesses the flash to receive the data. After receiving the data, the memory device causes the data to be stored on the host device based on information in the command (e.g., the PRP 1 discussed below).
  • the command may comprise a write command. Responsive to receipt of the write command, the memory device parses the write command, determines the location of the data on the host device subject to the write, reads the data from the location on the host device, and writes the data to flash memory.
  • the memory device may receive a read command or write command with a PRPl pointer.
  • a read command in which the host device requests the memory device to read from the flash memory, includes a PRPl pointer, which points to a PRP list.
  • the memory device obtains the PRP list in order to determine the memory locations within the host device to write the data that was read from the flash memory.
  • a write command in which the host device requests the memory device to write data to the flash memory, includes a PRPl pointer, which points to a PRP list.
  • the memory device obtains the PRP list in order to determine the memory locations within the host device to read the data from (and thereafter save the read data to the flash memory).
  • Each entry in the PRP list may be associated with a certain section in the host device memory, and may be a predetermined size, such as 4Kb. Thus, in a 1Mb transfer, there may be 250 references in the PRP list, each 4Kb in size.
  • the memory device may retrieve data out of sequence. This may be due to the data subject to retrieval being on several flash dies, with the dies being available for data retrieval at different times. For example, the memory device may retrieve the data corresponding to 100-200Kb of the 1Mb transfer before retrieving the data corresponding to 0-100Kb of the 1Mb transfer.
  • the memory device may transfer the data corresponding to 100-200Kb of the 1Mb transfer without having first retrieved the data corresponding to 0-100Kb of the 1Mb transfer.
  • NVMe there may be a multitude of PCIe TLPs to transfer the data from the memory device to the host device 300.
  • the transferred data is stored in the host memory 302 of the host device 300 based on an indication in the command (e.g., the command may include an address at which to store the requested data).
  • the memory device controller sends a completion message to the relevant completion queue 306.
  • the host device 300 associates submission queues with completion queues. So that, the host device 300 is aware of commands that are completed in the submission queue based on which completion queue the memory device writes to.
  • the completion message may contain information as to the processing of the command(s), such as whether the command was completed successfully or whether there was an error when executing the command.
  • step 5 the host device 300 is unaware that the memory device posted to the completion queue 306. This is due to the memory device causing data to be written to the completion queue 306.
  • step 6 the memory device notifies the host device 300 that there has been an update to the completion queue 306.
  • the memory device posts an interrupt to the host device 300 (e.g., in NVMe, the host device 300 may use an MSIe interrupt).
  • the host device 300 determines that there are one or more completion entries pending for the host device 300 in this completion queue 306. At step 7, the host device 300 then processes the entries in the completion queue 306.
  • the host device 300 After the host processes the entries from the completion queue 306, at step 8, the host device 300 notifies the memory device of the entries that the host device 300 processed from the completion queue 306. This may be performed by updating a completion queue head doorbell register 314 indicative to the memory device that the host device 300 processed one or more entries from the completion queue 306. Responsive to updating the completion queue head doorbell register 314, the memory device updates the head of the completion queue 306. Given the new head, the memory device is aware as to which entries in the completion queue 306 have already been processed by the host device 300 and may be overwritten.
  • FIG. 4 is a block diagram of other exemplary components of a host device 400 and a memory device 420.
  • the host device 400 includes host memory 402, which may comprise Physical Region Page (PRP) 404, data buffers 406, and other memory 408.
  • PRP Physical Region Page
  • FIG. 4 further illustrates a communication interface between the host device 400 and the memory device 420.
  • the communication interface between the host device and the memory device is simplex, with communications to and communications from the memory device on the same path.
  • the communication interface between the host device 400 and the memory device 420 is duplex, with a separate ingress path and a separate egress path.
  • the ingress path, from the perspective of the memory device 420 includes incoming requests from the host device 400 to the memory device 420.
  • the egress path from the perspective of the memory device 420, includes outgoing requests from the memory device 420 to the host device 400.
  • the incoming requests may be segmented in different ways, such as incoming read requests and incoming write requests.
  • the host device 400 may send, via the ingress path, a read request to read a section of memory in the memory device 420 or a write request to write to a section of memory in the memory device 420.
  • the memory device 420 may send, via the egress path, a read request to a section of memory in the host device 400 or a write request to write to a section of memory in the host device 400.
  • NVMe In practice using NVMe, there may be a series of read requests (a request by the host device to read a data resident on the memory device, and vice-versa) and a series of write requests (a request by the host device to write data to a location resident on the memory device, and vice-versa).
  • the memory device and the host device communicate with one another using transaction layer packet (TLP) requests, such as TLP read requests to perform a read on the other device, or TLP write requests to perform a write on the other device.
  • TLP transaction layer packet
  • the memory device responsive to a TLP write request (sent via the ingress path) by the host device to the doorbell register on the memory device (with the write to the doorbell register indicating that there is a command on the SQ), uses a TLP read request (sent via the egress path) to fetch the write command from the SQ (which is resident on the host device).
  • the write command is a request for the memory device to write data to the non-volatile memory.
  • the memory device parses the write command for information, such as an indication of a PRP pointer (e.g., PRP1) to a PRP list.
  • PRP pointer e.g., PRP1
  • the PRP list is a series of information, such as pointers or addresses, that indicates the location of the data in the host device.
  • the memory device then uses another TLP read request to read data from the pointers or address in the PRP list. Thereafter, the memory device performs the write by storing the data in non-volatile memory (e.g., flash memory) on the memory device. After storing the data, the memory device uses a TLP write request to write an entry to the CQ (indicating that the write command has been completed). Finally, the memory device uses a TLP write request to generate an interrupt to the host device, with the interrupt signaling to the host device that there is an entry on the CQ. Responsive to the interrupt, the host device reads the entry on the CQ, and then issues a TLP write request to CQ Doorbell Write register indicating that the host device has reviewed the entry on the CQ.
  • non-volatile memory e.g., flash memory
  • the memory device responsive to a TLP write request by the host to the doorbell register on the memory device (with the write to the doorbell register indicating that there is a command on the SQ), uses a TLP read request to fetch the read command from the SQ (which is resident on the host device).
  • the read command is a request for the memory device to read data from the non-volatile memory and to send the read data to the host device.
  • the memory device then reads the non-volatile memory (e.g., flash memory) to read the data.
  • the memory device can perform a series of operations on the data, such as error correction, encryption/decryption, etc., with storage buffers interspersed between each of the serial operation.
  • the memory device may then parse the read command for information, such as an indication of a PRP pointer (e.g., PRP1) to a PRP list.
  • PRP pointer e.g., PRP1
  • the PRP list is a series of information, such as pointers or addresses, that indicates the location in the host device to store the data that was read from non-volatile memory (and optionally error corrected, encrypted, etc.).
  • the memory device uses a TLP read request to read data from the pointers or address in the PRP list. Thereafter, the memory device uses a TLP write request to write the data that was read from non-volatile memory.
  • the memory device After writing the data to the host device, the memory device uses a TLP write request to write an entry to the CQ (indicating that the read command has been completed). Finally, the memory device uses a TLP write request to generate an interrupt to the host device, with the interrupt signaling to the host device that there is an entry on the CQ. Responsive to the interrupt, the host device reads the entry on the CQ, and then issues a TLP write request to CQ Doorbell Write register indicating that the host device has reviewed the entry on the CQ.
  • the CQ and SQ may be resident in the memory device, such as in the Controller Memory Buffer (CMB).
  • the host device may send a TLP write request (sent via the ingress path) to the memory device to write to the SQ.
  • the memory device may send a TLP write request (sent via the egress path) to generate an interrupt to the host device.
  • Memory device 420 includes the memory device controller 422 and memory arrays 446. Memory arrays 446 may be segmented in various ways, such as in 10 sections as illustrated in FIG. 4.
  • the memory device controller 422 may incorporate one or all of a PCle MAC and PHY interface 424.
  • the memory device controller 422 may also include one or more processors 450.
  • the memory device controller 422 further includes the Controller Memory Buffer (CMB) 426 which is allocated for the host device 400.
  • CMB Controller Memory Buffer
  • the various queues including the submission queues and completion queues, may be resident in the host device or in the memory device. As shown in FIG. 4, the queues are resident in CMB 426 in memory device 420, such as the submission queues 428. In addition, CMB 426 may include other data 430.
  • Command parser 432 is configured to monitor one or more internal buses, such as the bus from PCle MAC and PHY interface 424 to CMB 426. Command parser 432 is further configured to parse the NVMe commands written by the host device 400 in real-time (or as the commands are transmitted internally within memory device 420) and to select the commands that are candidates for a speculative execution.
  • Command parser 432 may queue those commands in the speculative command executer 434, which may be implemented either in hardware or firmware. As discussed in more detail below, based on resources internal to memory device 420, speculative command executer 434 may start the execution phase of those commands even before formal notice of the commands from host device 400.
  • Flash interface module 440 is configured to control and access the memory arrays 446.
  • flash interface module 440 may interact with the memory arrays 446 mainly for read and write operations.
  • Scheduler 440 is configured to control the data transfer while activating the control path 436 for fetching PRPs, posting completion (e.g., step 5 in FIG. 3) and interrupts (e.g., step 6 in FIG. 3), and activating the DMAs 438 for the actual data transfer between host device 400 and memory device 420.
  • the error correction engine 442 is configured to correct the data fetched from the memory arrays 446.
  • speculative command execution does not speculatively post any related transaction to the host device 400. Rather, the posting completion may be performed only after command queuing, which may be performed by a write to the relevant doorbell register (see step 3 in FIG. 3).
  • FIG. 4 includes the queues, such as submission queue 428, in CMB 426 resident in memory device 420, speculative execution may be performed when the queues, such as the sequential queues are resident in the host device 400.
  • sequential queues may be stored in Host DRAM.
  • the memory device holds internally the previous commands which were queued in the past by the host device 400 in the same slots.
  • FIG. 5 is a flow chart 500 for speculative execution of a command in the submission queue.
  • the host device 400 writes a command to the submission queue 428 located in CMB 426.
  • the command parser 432 parses the command in real-time while the command is written to CMB 426.
  • the command parser 432 determines whether to speculatively execute the command or not.
  • the command parser 432 may analyze one or more aspects in order to determine whether to perform speculative execution.
  • the command parser 432 analyzes the command itself (e.g., the type of the command) to determine whether to perform speculative execution.
  • the memory device may access the memory array 446 and pre-fetch some (or all) of the data responsive to the read command, prepare to enter a special state or prepare a database.
  • the command parser 432 analyzes the available internal resources of the memory device 420 to determine whether to perform speculative execution. As one example, in response to the command parser 432 determining that the memory device 420 has sufficient internal resources to perform the speculative execution, the command parser 432 determines to perform speculative execution. Conversely, if at a certain point, there are no available resources in the memory device required for execution of the command, the command may be executed later, and even after host command queuing. In still another implementation, the command parser 432 analyzes both the command and the internal resources of the memory device in determining whether to perform speculative execution. Thus, if there are available resources and if the command is a candidate for a speculative execution, the memory device will start the speculative execution phase.
  • the memory device 400 determines whether the host device 400 has overwritten the commands before queuing it. If so, at 514, speculative execution of the overwritten command is canceled. Otherwise, at 516, it is determined whether the host device 400 has queued the command by writing to the relevant doorbell register (e.g., step 2 of FIG. 3). If not, flow chart 500 loops back to 512 and waits to determine if an overwrite occurred. If so, at 518, the memory device 420 may continue the execution of the command normally while taking advantage of the speculative execution. As one example, speculative execution of a read command may comprise reading data from the memory arrays 446 and storing the read data into temporary memory buffers, as discussed with regard to FIG. 6.
  • FIG. 6 is a flow chart 600 for speculative execution of a read command in the submission queue.
  • the read operation may start at this point in a speculative way (e.g., a Read Look Ahead).
  • a speculative way e.g., a Read Look Ahead
  • memory device controller 422 may access the memory arrays 446, at 606, read the relevant pages and, at 608, store the read relevant pages in a temporal buffer.
  • data read from the memory arrays 446 may be subject to post-read processing, such as error correction and/or encryption/decryption.
  • the read data may first be analyzed for errors and, using ECC controller 124, correct for errors in the read data.
  • the error-corrected data may then be subject to encryption or decryption, and then stored in the temporal buffer.
  • the memory device controller 422 determines whether the host device 400 has queued the command. When the host device 400 queues the command in, at 612, it is determined whether the command has been overwritten. If not, at 614, the data can be retrieved from the temporal buffer rather than fetching it from the flash memory arrays. In this regard, in one implementation, the data stored in the temporal buffer is transmitted to the host only after the host device 400 queues the command in. In a more specific
  • the memory device may retrieve error-corrected decrypted data from the temporal buffer for transmission to the host device.
  • the memory device can perform the functions of retrieval, error correction, and encryption or decryption prior to the host device queuing the command (e.g., the host device performing step 2 in FIG. 3).
  • the host device 400 may have overwritten the command.
  • the new data is provided for the relevant read command.
  • the memory device may access the temporary memory buffers to transfer the read data to the host device. This is in contrast to conventional execution of the command, which reads the data from the memory arrays in response to the queuing of the command.
  • the speculative execution may be quicker since reading the data from the temporary buffers is quicker than reading the data from the memory arrays 446. The benefit in this case might be significant since the read performance of low queue depths can be easily increased.
  • Commands may be candidates for speculative execution.
  • write commands may be speculatively executed.
  • the speculative execution may comprise fetching the flash translation layer (FTL) table used for address translations (e.g., logical block to physical block translation table).
  • FTL flash translation layer
  • power management commands may be speculatively executed.
  • the host device 400 may request the memory device to enter a specific NVMe power state using the Set Features command.
  • the speculative execution in this case may include flushing all internal caches to the flash memory array and other preparation related to this special state.
  • flush commands may be speculatively executed.
  • the host device 400 may send flush commands.
  • the memory device 420 flushes its temporal buffers to the media and then posts a completion to the host device 400.
  • the memory device 420 may start the flush operation as usual.
  • the host device may overwrite the command (e.g., will not queue the command). Nevertheless, even if the memory device 420 performs the flush operation, the memory device 420 has not violated any rule.
  • any suitable type of memory can be used.
  • Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information.
  • volatile memory devices such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices
  • non-volatile memory devices such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information.
  • ReRAM resistive random access memory
  • the memory devices can be formed from passive and/or active elements, in any combinations.
  • passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc.
  • active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.
  • Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible.
  • flash memory devices in a NAND configuration typically contain memory elements connected in series.
  • a NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group.
  • memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array.
  • NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.
  • the semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.
  • the semiconductor memory elements are arranged in a single plane or a single memory device level.
  • memory elements are arranged in a plane ⁇ e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements.
  • the substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed.
  • the substrate may include a semiconductor such as silicon.
  • the memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations.
  • the memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
  • a three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).
  • a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels.
  • a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column.
  • the columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes.
  • Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.
  • the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels.
  • the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels.
  • Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels.
  • Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
  • a monolithic three dimensional memory array typically, one or more memory device levels are formed above a single substrate.
  • the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate.
  • the substrate may include a semiconductor such as silicon.
  • the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array.
  • layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.
  • two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory.
  • non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays.
  • multiple two dimensional memory arrays or three dimensional memory arrays may be formed on separate chips and then packaged together to form a stacked-chip memory device.
  • Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements.
  • memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading.
  • This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate.
  • a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.

Abstract

L'invention concerne des systèmes et des procédés d'exécution spéculative de commandes à l'aide du tampon de mémoire de dispositif de commande. Une NVM Express (NVMe) met en œuvre une file d'attente de soumission et un mécanisme de file d'attente d'achèvement appariés, un logiciel hôte sur le dispositif hôte plaçant des commandes dans la file d'attente de soumission, puis notifiant au dispositif de mémoire des commandes sur la file d'attente de soumission. La file d'attente de soumission peut être résidente dans le dispositif de mémoire, par exemple dans une mémoire tampon de dispositif de commande. Avant la notification par le dispositif hôte, le dispositif de mémoire peut déterminer que les commandes sont placées dans la file d'attente de soumission et peut exécuter de manière spéculative les commandes.
PCT/US2018/019905 2017-03-24 2018-02-27 Système et procédé d'exécution spéculative de commandes à l'aide du tampon de mémoire de dispositif de commande WO2018175059A1 (fr)

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CN201880005085.9A CN110073323B (zh) 2017-03-24 2018-02-27 使用控制器存储器缓冲区进行推测性执行命令的系统和方法

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