WO2018173196A1 - Single-ended ad converter, ad conversion circuit, and image sensor - Google Patents

Single-ended ad converter, ad conversion circuit, and image sensor Download PDF

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Publication number
WO2018173196A1
WO2018173196A1 PCT/JP2017/011727 JP2017011727W WO2018173196A1 WO 2018173196 A1 WO2018173196 A1 WO 2018173196A1 JP 2017011727 W JP2017011727 W JP 2017011727W WO 2018173196 A1 WO2018173196 A1 WO 2018173196A1
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Prior art keywords
converter
signal
input
node
pixels
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PCT/JP2017/011727
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French (fr)
Japanese (ja)
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雅人 大澤
靖也 原田
修三 平出
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オリンパス株式会社
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Priority to PCT/JP2017/011727 priority Critical patent/WO2018173196A1/en
Publication of WO2018173196A1 publication Critical patent/WO2018173196A1/en

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  • the present invention relates to a single-ended AD converter, an AD converter circuit, and an image sensor.
  • FIG. 15 shows the configuration of a conventional single-ended SAR ADC (Successive Approximation Register Analog to Digital Converter) disclosed in Patent Document 1.
  • the single-ended SAR ADC has a DAC (Digital to Analog Converter) 12, a comparator 13, a successive approximation logic circuit 14, and capacitors C1 to Cn.
  • the first input terminal of the comparator 13 is connected to the ground level, and the second input terminal of the comparator 13 is connected to the top plate side of the capacitors C1 to Cn.
  • the bottom plate sides of the capacitors C1 to Cn are connected to any one of the ground level and the reference voltage Vref.
  • the connection node on the bottom plate side of the capacitors C1 to Cn is determined by the result of the determination by the comparator 13 and the algorithm of the process executed by the successive approximation logic circuit 14.
  • the dynamic comparator when the dynamic comparator is applied to the conventional single-ended SAR ADC, an error occurs in the AD conversion result due to kickback noise caused by the reset operation performed by the dynamic comparator for each comparison operation.
  • the first input terminal of the comparator 13 is connected to the ground level, ie to the low impedance node. Therefore, the first input terminal of the comparator 13 is not affected by the kickback noise.
  • the second input terminal of the comparator 13 connected to the high impedance node is affected to some extent by kickback noise. This is the reason why an error occurs in the AD conversion result.
  • An object of the present invention is to provide a single-ended AD converter, an AD converter circuit, and an image sensor capable of obtaining highly accurate AD conversion results.
  • a single-ended AD converter includes a DAC circuit, a fixed capacitance, a dynamic comparator, and a control circuit.
  • the DAC circuit has a plurality of capacitances whose capacitance values are weighted.
  • the plurality of capacitors hold analog voltage signals input from the outside of the single-ended AD converter.
  • the fixed capacitance holds a reference voltage signal input from the outside of the single-ended AD converter.
  • the dynamic comparator compares the voltage of the analog voltage signal held by the DAC circuit with the voltage of the reference voltage signal held by the fixed capacitor.
  • the control circuit controls the DAC circuit in accordance with the comparison result of the dynamic comparator.
  • the sum of the capacitance values of the plurality of capacitors included in the DAC circuit is substantially equal to the capacitance value of the fixed capacitor.
  • the AD converter includes: a first input node to which the analog voltage signal is input; and a second input to which the reference voltage signal is input. It may have a node.
  • Each of the plurality of capacitors and the fixed capacitor may have a first electrode and a second electrode facing each other.
  • the dynamic comparator may have a first input terminal and a second input terminal.
  • the first electrodes of the plurality of capacitors may be connected to the first input node and the first input terminal.
  • the second electrodes of the plurality of capacitors may be connected to ground or a predetermined reference voltage.
  • the first electrode of the fixed capacitance may be connected to the second input node and the second input terminal.
  • the second electrode of the fixed capacitance may be connected to ground.
  • an AD conversion circuit includes a first AD converter and a second AD converter which are the single-ended AD converter.
  • the first AD converter and the second AD converter share the fixed capacity.
  • the first AD converter performs a first operation in parallel with a second operation by the second AD converter, and the second AD converter performs the first operation by the first AD converter.
  • the first operation is performed in parallel with the second operation.
  • the analog voltage signal is sampled into the DAC circuit.
  • AD conversion is sequentially performed based on each of the analog voltage signal and the reference voltage signal sampled by the first operation.
  • the first AD converter and the second AD converter alternately perform the first operation and the second operation.
  • the first AD converter and the second AD converter perform the first operation and the second operation while switching the first operation and the second operation.
  • a third operation of resetting the reference voltage signal sampled to the fixed capacitance is performed in a period shorter than the period.
  • an image sensor includes the AD conversion circuit.
  • the image sensor may have a plurality of pixels and a plurality of column circuits.
  • the plurality of pixels are arranged in a matrix.
  • the plurality of column circuits are arranged for each column of the plurality of pixels.
  • the signal output from the column circuit arranged in the odd-numbered column of the plurality of pixels may be input to any one of the first AD converter and the second AD converter.
  • the signal output from the column circuit arranged in the even column of the plurality of pixels is output from the column circuit arranged in the even column of the first AD converter and the second AD converter.
  • the input signal may be input to an AD converter different from the input AD converter.
  • the image sensor may have a plurality of pixels arranged in a matrix.
  • the plurality of pixels may include a plurality of first pixels and a plurality of second pixels.
  • the first pixel may have a color filter of a first color.
  • the second pixel may have a color filter of a second color different from the first color.
  • the plurality of first pixels and the plurality of second pixels may be periodically arranged.
  • the signal output from the first pixel may be input to any one of the first AD converter and the second AD converter.
  • the signal output from the second pixel is an AD different from the AD converter to which the signal output from the first pixel of the first AD converter and the second AD converter is input. It may be input to the converter.
  • the single-ended AD converter, the AD conversion circuit, and the image sensor can obtain highly accurate AD conversion results.
  • FIG. 1 shows the configuration of an AD converter ADC according to a first embodiment of the present invention.
  • the schematic configuration of the AD converter ADC will be described.
  • the AD converter ADC is a single-ended AD converter.
  • the AD converter ADC at least includes a DAC circuit CDACO, capacitors C1C to C6C, a comparator CMPO, and a control circuit SARLOGICO.
  • the DAC circuit CDACO has a plurality of capacitances C1O to C6O whose capacitance values are weighted.
  • the plurality of capacitors C1O to C6O hold an analog voltage signal input from the outside of the AD converter ADC, that is, a video signal VSIG1.
  • the plurality of capacitances C1C to C6C are fixed capacitances.
  • the plurality of capacitors C1C to C6C hold a reference voltage signal input from the outside of the AD converter ADC, that is, a reference signal VCM.
  • the comparator CMPO is a dynamic comparator.
  • the comparator CMPO compares the voltage of the video signal VSIG1 held in the DAC circuit CDACO with the voltage of the reference signal VCM held in the plurality of capacitors C1C to C6C.
  • the control circuit SARLOGICO is a successive approximation circuit.
  • the control circuit SARLOGICO controls the DAC circuit CDACO according to the comparison result of the comparator CMPO.
  • the sum of the capacitance values of the plurality of capacitors C1O to C6O of the DAC circuit CDACO and the sum of the capacitance values of the plurality of capacitors C1C to C6C are substantially the same.
  • the AD converter ADC also includes a node VIO (first input node) to which an analog voltage signal, that is, the video signal VSIG1 is input, and a node VIC (second input node) to which a reference voltage signal, that is, a reference signal VCM is input. And.
  • Each of the plurality of capacitors C1O to C6O and the plurality of capacitors C1C to C6C has a first electrode and a second electrode facing each other.
  • the comparator CMPO has a first input terminal and a second input terminal. The first electrodes of the plurality of capacitors C1O to C6O are connected to the node VIO and a first input terminal of the comparator CMPO.
  • the second electrodes of the plurality of capacitors C1O to C6O are connected to the ground GND or a predetermined reference voltage (reference voltage VREF).
  • the first electrodes of the plurality of capacitors C1C to C6C are connected to the node VIC and the second input terminal of the comparator CMPO.
  • the second electrode of the comparator CMPO is connected to the ground GND.
  • the AD converter ADC has an odd AD converter ADCO and a capacitance array CDACC.
  • the odd AD converter ADCO has a DAC circuit CDACO, a comparator CMPO, and a control circuit SARLOGICO.
  • the DAC circuit CDACO has capacitors C1O to C6O, switches SW1O to SW6O, and a sample switch SWSMPLO.
  • the capacitance array CDACC has capacitances C1C to C6C and a sample switch SWSMPLC.
  • the sample switch SWSMPLO has a first terminal and a second terminal.
  • the first terminal of the sample switch SWSMPLO is connected to the signal source SIG_ODD.
  • the second terminal of the sample switch SWSMPLO is connected to the node VIO.
  • the state of the sample switch SWSMPLO switches between on and off.
  • the sample switch SWSMPLO is on, the first terminal and the second terminal of the sample switch SWSMPLO are electrically connected.
  • the video signal VSIG1 from the signal source SIG_ODD is input to the node VIO.
  • the sample switch SWSMPLO is off, the first and second terminals of the sample switch SWSMPLO are in a high impedance state.
  • the state of the sample switch SWSMPLO is controlled by the control signal SMPLO.
  • the sample switch SWSMPLO When the control signal SMPLO is “H (High)”, the sample switch SWSMPLO is on. When the control signal SMPLO is “L (Low)”, the sample switch SWSMPLO is off. The sample switch SWSMPLO samples the video signal VSIG1 from the signal source SIG_ODD.
  • the switches SW1O to SW6O have a first terminal S1, a second terminal S2, and a third terminal D.
  • the first terminals S1 of the switches SW1O to SW6O are connected to the reference voltage VREF.
  • the second terminals S2 of the switches SW1O to SW6O are connected to the ground GND.
  • the third terminals D of the switches SW1O to SW6O are connected to the second electrodes of the capacitors C1O to C6O.
  • the states of the switches SW1O to SW6O switch between the first state and the second state. When the switches SW1O to SW6O are in the first state, the first terminals S1 of the switches SW1O to SW6O are electrically connected to the third terminals D of the switches SW1O to SW6O.
  • the capacitors C1O to C6O are connected to the reference voltage VREF.
  • the switches SW1O to SW6O are in the second state, the second terminals S2 of the switches SW1O to SW6O and the third terminals D of the switches SW1O to SW6O are electrically connected.
  • the capacitors C1O to C6O are connected to the ground GND.
  • the states of the switches SW1O to SW6O are controlled by bits DO1 to DO6 of the AD conversion result.
  • the bits DO1 to DO6 are "H”
  • the switches SW1O to SW6O are in the first state.
  • the bits DO1 to DO6 are "L”
  • the switches SW1O to SW6O are in the second state.
  • the capacitors C1O to C6O have a first electrode and a second electrode.
  • the first electrodes of the capacitors C1O to C6O are connected to the node VIO.
  • the second electrodes of the capacitors C1O to C6O are connected to the third terminal D of the switches SW1P to SW6P.
  • the capacitors C1O to C6O hold the video signal VSIG1 sampled by the sample switch SWSMPLO.
  • the sample switch SWSMPLC has a first terminal and a second terminal.
  • the first terminal of the sample switch SWSMPLC is connected to the reference signal source VCM_G.
  • the second terminal of the sample switch SWSMPLC is connected to the node VIC.
  • the state of the sample switch SWSMPLC switches between on and off.
  • the sample switch SWSMPLC is on, the first terminal and the second terminal of the sample switch SWSMPLC are electrically connected.
  • the reference signal VCM from the reference signal source VCM_G is input to the node VIC.
  • the sample switch SWSMPLC is off, the first and second terminals of the sample switch SWSMPLC are in a high impedance state.
  • the state of the sample switch SWSMPLC is controlled by the control signal SMPLC.
  • the control signal SMPLC is “H”, the sample switch SWSMPLC is on.
  • the control signal SMPLC is “L”, the sample switch SWSMPLC is off.
  • the capacitors C1C to C6C have a first electrode and a second electrode.
  • the first electrodes of the capacitors C1C to C6C are connected to the node VIC.
  • the second electrodes of the capacitors C1C to C6C are connected to the ground GND.
  • the capacitors C1C to C6C hold the reference signal VCM sampled by the sample switch SWSMPLC.
  • the capacitance values of the capacitors C1O to C6O and the capacitors C1C to C6C are weighted.
  • the capacitance value of each capacitance is represented by the sign of each capacitance.
  • the capacitance value of each capacitance is shown by equation (1).
  • the capacitance C1O and the capacitance C1C are capacitances having properties as dummy capacitances.
  • the capacitance C1O and the capacitance C1C are necessary to make the total value C of capacitances in each of the DAC circuit CDACO and the capacitance array CDACC into 25 Cu as in equation (2).
  • C Cu + 2 0 Cu + 2 1 Cu + 2 2 Cu + ⁇ ⁇ ⁇ 2 4 Cu (2)
  • the capacitance C1O and the capacitance C1C having a nature as a dummy capacitance are not essential requirements for the configuration of the AD converter ADC.
  • the capacitances C1O and C1C are necessary elements to simplify the description to be described later and to realize a high accuracy AD converter in an actual design. Therefore, in each embodiment of the present invention, the capacitance C1O and the capacitance C1C are described purposefully.
  • the DAC circuit CDACO is connected to the signal source SIG_ODD.
  • the capacitance array CDACC is connected to the reference signal source VCM_G.
  • the video signal VSIG1 generated by the signal source SIG_ODD is supplied to the node VIO.
  • the reference signal VCM generated by the reference signal source VCM_G is supplied to the node VIC.
  • the node VIO which is a charge summing node is connected to the second terminal of the sample switch SWSMPLO, the first electrodes of the capacitors C1O to C6O, and the first input terminal of the comparator CMPO.
  • the node VIO is an arbitrary position on the signal line electrically connected to them.
  • the node VIC which is a charge summing node, is connected to the second terminal of the sample switch SWSMPLC, the first electrodes of the capacitors C1C to C6C, and the second input terminal of the comparator CMPO.
  • the node VIC is an arbitrary position on a signal line electrically connected to them.
  • the comparator CMPO has a first input terminal (non-inverted input terminal), a second input terminal (inverted input terminal), a first output terminal (inverted output terminal), and a second output terminal (non-inverted And an output terminal).
  • the first input terminal of the comparator CMPO is connected to the node VIO.
  • a voltage based on the video signal VSIG1 is input to a first input terminal of the comparator CMPO.
  • the second input terminal of the comparator CMPO is connected to the node VIC.
  • a voltage based on the reference signal VCM is input to a second input terminal of the comparator CMPO.
  • the first output terminal and the second output terminal of the comparator CMPO are connected to the control circuit SARLOGICO.
  • the comparator CMPO compares the voltage of the node VIO with the voltage of the node VIC.
  • the comparator CMPO outputs a signal VONO based on the comparison result from the first output terminal, and outputs a signal VOPO based on the comparison result from the second output terminal.
  • the control circuit SARLOGICO has a first input terminal, a second input terminal, and an output terminal.
  • a first input of the control circuit SARLOGICO is connected to a first output of the comparator CMPO.
  • the second input terminal of the control circuit SARLOGICO is connected to the second output terminal of the comparator CMPO.
  • the signal VONO is input to a first input terminal of the control circuit SARLOGICO, and the signal VOPO is input to a second input terminal of the control circuit SARLOGICO.
  • the control circuit SARLOGICO generates the digital signal DO [6: 1] of the AD conversion result based on the signal VOPO and the signal VONO from the comparator CMPO, and outputs the digital signal DO [6: 1] from the output terminal.
  • the AD converter ADC is a 6-bit output AD converter, but is not limited to this example. The number of output bits of the AD converter ADC can be set arbitrarily.
  • the bits DO1 to DO6 constituting the digital signal DO [6: 1] are output to the switches SW1O to SW6O of the DAC circuit CDACO.
  • the control circuit SARLOGICO controls the DAC circuit CDACO by outputting the bits DO1 to DO6 to the switches SW1O to SW6O.
  • the sum of the capacitance values of the plurality of capacitors C1O to C6O of the DAC circuit CDACO be equal to the sum of the capacitance values of the plurality of capacitors C1C to C6C.
  • the capacitance value varies.
  • the variation of the absolute value of the capacitance value is 10% to 30% of the nominal value.
  • the sum of the capacitance values of the capacitances C1O to C6O and the sum of the capacitance values of the capacitances C1C to C6C are within the range of 0.9 Co to 1.1 Co It is.
  • FIG. 2 shows the configuration of the comparator CMPO.
  • the comparator CMPO has a differential amplifier circuit A1 and a latch circuit L1.
  • the differential amplifier circuit A1 includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, and a transistor M5.
  • the transistor M1, the transistor M2, and the transistor M5 are N-channel field effect transistors.
  • the transistor M3 and the transistor M4 are P-channel field effect transistors. Under the condition that the amplification function of the differential amplifier circuit A1 can be obtained, the types of the transistors constituting the differential amplifier circuit A1 can be arbitrarily selected.
  • the gate terminal of the transistor M1 is connected to the first input terminal.
  • the gate terminal of the transistor M2 is connected to the second input terminal.
  • the signal VIO is input from the DAC circuit CDACO to the gate terminal of the transistor M1 via the first input terminal.
  • Signal VIO is a signal corresponding to the voltage of node VIO.
  • the signal VIC is input from the capacitance array CDACC to the gate terminal of the transistor M2 via the second input terminal.
  • Signal VIC is a signal according to the voltage of node VIC.
  • the source terminal of the transistor M3 is connected to the power supply that outputs the power supply voltage VDD.
  • the drain terminal of the transistor M3 is connected to the drain terminal of the transistor M1.
  • the source terminal of the transistor M4 is connected to the power supply that outputs the power supply voltage VDD.
  • the drain terminal of the transistor M4 is connected to the drain terminal of the transistor M2.
  • the gate terminal of the transistor M4 is connected to the gate terminal of the transistor M3.
  • the internal clock signal BIT_CLK is input to the gate terminal of the transistor M3 and the gate terminal of the transistor M4.
  • the source terminal of the transistor M5 is connected to the ground GND.
  • the ground GND provides the lowest voltage.
  • the drain terminal of the transistor M5 is connected to the source terminal of the transistor M1 and the source terminal of the transistor M2.
  • the internal clock signal BIT_CLK is input to the gate terminal of the transistor M5.
  • the latch circuit L1 includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, a transistor M13, and a transistor M14.
  • the transistor M11, the transistor M12, the transistor M13, and the transistor M14 are N-channel field effect transistors.
  • the transistor M7, the transistor M8, the transistor M9, and the transistor M10 are P-channel field effect transistors. Under the condition that the latch function of the latch circuit L1 can be obtained, the type of each transistor constituting the latch circuit L1 can be arbitrarily selected.
  • the gate terminal of the transistor M7 is connected to the drain terminal of the transistor M2.
  • the signal AP output from the differential amplifier circuit A1 is input to the gate terminal of the transistor M7.
  • the gate terminal of the transistor M8 is connected to the drain terminal of the transistor M1.
  • the signal AN output from the differential amplifier circuit A1 is input to the gate terminal of the transistor M8.
  • the source terminal of the transistor M9 is connected to the power supply that outputs the power supply voltage VDD.
  • the drain terminal of the transistor M9 is connected to the source terminal of the transistor M7.
  • the source terminal of the transistor M10 is connected to the power supply that outputs the power supply voltage VDD.
  • the drain terminal of the transistor M10 is connected to the source terminal of the transistor M8.
  • the source terminal of the transistor M11 is connected to the ground GND.
  • the drain terminal of the transistor M11 is connected to the drain terminal of the transistor M7, the gate terminal of the transistor M10, the gate terminal of the transistor M12, and the drain terminal of the transistor M13.
  • the gate terminal of the transistor M11 is connected to the gate terminal of the transistor M9, the drain terminal of the transistor M8, the drain terminal of the transistor M12, and the drain terminal of the transistor M14.
  • the source terminal of the transistor M12 is connected to the ground GND.
  • the drain terminal of the transistor M12 is connected to the drain terminal of the transistor M8, the gate terminal of the transistor M9, the gate terminal of the transistor M11, and the drain terminal of the transistor M14.
  • the gate terminal of the transistor M12 is connected to the gate terminal of the transistor M10, the drain terminal of the transistor M7, the drain terminal of the transistor M11, and the drain terminal of the transistor M13.
  • the source terminal of the transistor M13 is connected to the ground GND.
  • the drain terminal of the transistor M13 is connected to the drain terminal of the transistor M11, the drain terminal of the transistor M7, the gate terminal of the transistor M10, and the gate terminal of the transistor M12.
  • the inverted internal clock signal BIT_CLKb is input to the gate terminal of the transistor M13.
  • the source terminal of the transistor M14 is connected to the ground GND.
  • the drain terminal of the transistor M14 is connected to the drain terminal of the transistor M8, the drain terminal of the transistor M12, the gate terminal of the transistor M9, and the gate terminal of the transistor M11.
  • the inverted internal clock signal BIT_CLKb is input to the gate terminal of the transistor M14.
  • the drain terminal of the transistor M14 is connected to the first output terminal.
  • the drain terminal of the transistor M13 is connected to the second output terminal.
  • the signal VOPO is output from the first output terminal and the signal VONO is output from the second output terminal.
  • Internal clock signal BIT_CLK and inverted internal clock signal BIT_CLKb are supplied from a control circuit (not shown) to comparator CMPO.
  • internal clock signal BIT_CLK goes high.
  • the operation when the internal clock signal BIT_CLK is at low level will be described.
  • the internal clock signal BIT_CLK is at a low level
  • the inverted internal clock signal BIT_CLKb is at a high level. Therefore, the transistor M5 of the differential amplifier circuit A1 is turned off, and the transistors M3 and M4 are turned on. The transistor M13 and the transistor M14 of the latch circuit L1 are turned on.
  • the potentials of the signal AN and the signal AP are raised to the power supply voltage VDD. Since the signals AN and AP are input to the gate terminals of the transistors M7 and M8, the transistors M7 and M8 are turned off. On the other hand, the transistor M13 and the transistor M14 are turned on. The potentials of the signals VOPO and VONO are pulled down to the ground GND via the transistors M13 and M14.
  • the transistor M5 is turned on by switching the internal clock signal BIT_CLK from the low level to the high level. Therefore, a drain current flows to the transistor M5.
  • the transistor M3 and the transistor M4 are turned off.
  • Transistor M1 draws charge from the parasitic capacitance coupled to node NAN at the drain terminal of transistor M1.
  • Transistor M2 draws charge from the parasitic capacitance coupled to node NAP at the drain terminal of transistor M2.
  • the difference in potential between the signal VIO and the signal VIC causes a difference in the speed at which charge is drawn from the parasitic capacitance.
  • the signal VIO is larger than the signal VIC (VIO> VIC)
  • the current flowing through the transistor M1 is larger than the current flowing through the transistor M2.
  • the potential of the signal AN falls faster than the potential of the signal AP.
  • Internal clock signal BIT_CLK changes from low level to high level
  • inverted internal clock signal BIT_CLKb changes from high level to low level.
  • the potentials of the signal VOPO and the signal VONO rise toward the power supply voltage VDD. Since the potential of the signal AN drops faster than the potential of the signal AP, the transistor M8 turns on earlier than the transistor M7. Therefore, the rising speed of the potential of the signal VOPO is higher than the rising speed of the potential of the signal VONO. As a result, the potential of the signal VOPO is pulled up toward the power supply voltage VDD.
  • the inverter formed by the transistors M7, M9, and M11 is cross-coupled to the inverter formed by the transistors M8, M10, and M12.
  • the transistor M9 in which the signal VOPO is applied to the gate terminal is turned off.
  • the signal VONO is pulled down to the ground GND. Therefore, signal VOPO and signal VONO having logic levels according to the magnitude relationship between signal VIO and signal VIC are output from comparator CMPO.
  • the potential of signal VOPO is the potential of power supply voltage VDD
  • the potential of signal VONO is the potential of ground GND.
  • the comparator CMPO outputs a binary signal VOPO and a signal VONO indicating the magnitude relationship between the signal VIO and the signal VIC.
  • the comparator CMPO is a dynamic comparator. In the comparator CMPO, only a through current due to a state change flows as an operating current, as in the CMOS logic. That is, in comparator CMPO, current flows transiently only when the signal levels of internal clock signal BIT_CLK and inverted internal clock signal BIT_CLKb transition from high level to low level or low level to high level, and steady current (idle Current does not occur. Therefore, the comparator CMPO is suitable for reducing power consumption.
  • FIG. 3 shows signals relating to the operation of the AD converter ADC.
  • the state of the DAC circuit CDACO is shown.
  • the control signal SMPLO and the control signal SMPLC are shown.
  • the digital signal DO [6: 1] is shown in hexadecimal.
  • voltages of each of node VIO and node VIC are shown.
  • the horizontal axis indicates time, and the vertical axis indicates signal level.
  • the AD converter ADC performs sampling operation SAMP to sample the signal input to the DAC circuit CDACO.
  • the video signal VSIG1 is input from the signal source SIG_ODD to the node VIO.
  • the reference signal VCM is input from the reference signal source VCM_G to the node VIC.
  • the bits DO1 to DO6 which are "H" are input to the switches SW1O to SW6O.
  • the first terminal S1 and the third terminal D of each of the switches SW1O to SW6O are connected.
  • the voltage of the node VIO is maintained at the voltage of the video signal VSIG1
  • the voltage of the node VIC is maintained at the voltage of the reference signal VCM.
  • the charges based on the video signal VSIG1 are held in the capacitors C1O to C6O
  • the charges based on the reference signal VCM are held in the capacitors C1C to C6C.
  • the AD converter ADC performs AD conversion operation CONV to perform AD conversion of the signal sampled in the DAC circuit CDACO.
  • the switch SWSMPLO since the switch SWSMPLO is off, the input of the video signal VSIG1 from the signal source SIG_ODD to the node VIO is stopped. Further, in the period T1 'to the period T7', the switch SWSMPLC is off, so the input of the reference signal VCM from the reference signal source VCM_G to the node VIC is stopped.
  • the period T2 'to the period T7' correspond to a period for the AD converter ADC (comparator CMPO) to compare MSB to LSB based on the charge held in the DAC circuit CDACO.
  • comparator CMPO compares the voltages of node VIO and node VIC. By this comparison, the logic of the most significant bit DO6 of the AD conversion result is determined.
  • the comparator CMPO outputs the comparison result to the control circuit SARLOGICO.
  • control circuit SARLOGICO outputs bit DO6 according to the comparison result in period T2'.
  • the voltage of the node VIO is represented as VIO
  • the voltage of the node VIC is represented as VIC.
  • the logic level of bit DO6 is "H”.
  • the logic level of bit DOi is set to “L”. If the determination result in bit DOi is VIC> VIO, the logic level of bit DOi is set to “L”, and the logic level of the immediately preceding bit DO (i + 1) is set to “H”.
  • i is an integer of 1 to 5;
  • control circuit SARLOGICO sets the logic of bit DO6 to “L”.
  • the digital signal DO [6: 1] expressed in hexadecimal changes from 3F (111111) to 1F (0111111).
  • the logic level of bit DO6 is output to switch SWO6.
  • the switch SWO6 is switched to the state in which the second terminal S2 and the third terminal D are connected.
  • the ground level is input to the second electrode of the capacitor C6O.
  • the comparator CMPO compares the voltages of the node VIO and the node VIC to determine the logic level of the bit DO5 in a period T3 '.
  • control circuit SARLOGICO sets the logic of bit DO5 to "L” and sets the logic of bit DO6 to "H”.
  • the digital signal DO [6: 1] expressed in hexadecimal changes from 1F (011111) to 2F (101111).
  • the logic level of bit DO6 is output to switch SW6O
  • the logic level of bit DO5 is output to switch SW5O.
  • the switch SW6O is switched to the state in which the first terminal S1 and the third terminal D are connected.
  • the reference voltage VREF is input to the second electrode of the capacitor C6O.
  • the switch SW5O switches to a state in which the second terminal S2 and the third terminal D are connected.
  • the ground level is input to the second electrode of the capacitor C50.
  • the comparator CMPO compares the voltages of the node VIO and the node VIC to determine the logic level of the bit DO4.
  • control circuit SARLOGICO sets the logic of bit DO4 to "L".
  • the digital signal DO [6: 1] expressed in hexadecimal changes from 2F (101111) to 27 (100111).
  • the logic level of bit DO4 is output to switch SW4O. Therefore, the switch SW4O switches to a state in which the second terminal S2 and the third terminal D are connected.
  • comparator CMPO compares voltages of node VIO and node VIC to determine the logic level of bit DO3 in period T5 '.
  • control circuit SARLOGICO sets the logic of bit DO3 to "L".
  • the digital signal DO [6: 1] expressed in hexadecimal changes from 27 (100111) to 23 (100011).
  • the logic level of bit DO3 is output to switch SWO3. Therefore, the switch SW3O is switched to the state in which the second terminal S2 and the third terminal D are connected.
  • the ground level is input to the second electrode of the capacitor C3O.
  • the state of the switch SW3O changes, whereby the potential of the node VIO drops by (1/2 4 ) VREF.
  • the comparator CMPO compares the voltages of the nodes VIO and VIC to determine the logic level of the bit DO2.
  • control circuit SARLOGICO sets the logic of bit DO2 to "L” and sets the logic of bit DO3 to "H”.
  • the digital signal DO [6: 1] expressed in hexadecimal changes from 23 (100011) to 25 (100101).
  • the logic level of bit DO3 is output to switch SW3O, and the logic level of bit DO2 is output to switch SW2O.
  • the switch SW3O is switched to the state in which the first terminal S1 and the third terminal D are connected.
  • the reference voltage VREF is input to the second electrode of the capacitor C3O.
  • the switch SW2O is switched to a state in which the second terminal S2 and the third terminal D are connected.
  • the ground level is input to the second electrode of the capacitor C2O.
  • the comparator CMPO compares the voltages of the node VIO and the node VIC to determine the logic level of the bit DO1.
  • control circuit SARLOGICO sets the logic of bit DO1 to "L” and sets the logic of bit DO2 to "H”.
  • the digital signal DO [6: 1] expressed in hexadecimal changes from 25 (100101) to 26 (100110).
  • the digital signal DO [6: 1] obtained in this manner is used in an external signal processing system.
  • the determination result in the period T7 ' is not used to control the switch SW2O and the switch SW1O.
  • a control signal that is always “H” may be input to the switch SW1O.
  • the DAC circuit in the AD converter according to each aspect of the present invention may not have a configuration other than the capacitance.
  • the signal input to the AD converter according to each aspect of the present invention and to be subjected to AD conversion may be a signal other than the video signal.
  • the sample switch SWSMPLO and the sample switch SWSMPLC are turned off during the AD conversion period.
  • the impedance to the ground estimated from the node VIO of the capacitors C1O to C6O and the impedance to the ground estimated from the node VIC of the capacitors C1C to C6C are kept the same.
  • the effects of kickback noise generated each time the comparator CMPO, which is a dynamic comparator, performs a reset operation are balanced.
  • highly accurate AD conversion results can be obtained.
  • power consumption can be suppressed by using a dynamic comparator as the comparator CMPO.
  • FIGS. 4 to 6 show a simulation example that can be confirmed to suppress an AD conversion error by the function of the balance capacitance.
  • FIG. 4 shows an analog signal restored from the result of AD conversion of a sinusoidal analog signal.
  • the horizontal axis indicates time, and the vertical axis indicates voltage.
  • the voltage AV1 indicates an example of an analog signal input to an AD converter having a balance capacitance (capacitance array CDACC).
  • the voltage AV2 indicates an example of an analog signal input to the AD converter having no balance capacitance.
  • FIG. 5 shows voltages of the node VIO and the node VIC in each of the AD converter with the balancing capacitance (capacitance array CDACC) and the AD converter without the balancing capacitance.
  • the horizontal axis shows time
  • the vertical axis shows voltage.
  • the voltage at node VIO is higher than the voltage at node VIC.
  • the voltage of the node VIO is lower than the voltage of the node VIC.
  • the relationship between the voltage magnitudes of the node VIO and the node VIC is different between the AD converter having the balanced capacitance and the AD converter having no balanced capacitance at and after the time ty. It is obvious that the above-mentioned cause is that the voltage of the node VIC is not affected by the kickback noise by keeping the node VIC at low impedance in the absence of the balancing capacitance.
  • FIG. 6 shows the difference (VIC ⁇ VIO) between the voltage of the node VIC and the voltage of the node VIO.
  • the AD converter operates such that the difference between the voltage of the node VIC and the voltage of the node VIO approaches the target voltage, that is, 0, by performing AD conversion.
  • the differential voltage (VIC-VIO) is substantially the same regardless of the presence or absence of the balance capacitance.
  • the difference voltage (VIC ⁇ VIO) approaches the target voltage as soon as it is away from the target voltage.
  • the differential voltage (VIC ⁇ VIO) always approaches the target voltage.
  • the error of the differential voltage (VIC-VIO) with respect to the target voltage when a determination error occurs at any time is equal to or greater than the error of the differential voltage (VIC-VIO) with respect to the target voltage when no determination error occurs.
  • FIG. 7 shows the entire configuration of the image sensor IMG.
  • the image sensor IMG includes an imaging unit PIX, a timing generator TG, a column processing unit COLS, and an AD conversion circuit ADCa.
  • the imaging unit PIX has a plurality of pixels P arranged in a matrix. In FIG. 7, some of the plurality of pixels P are omitted. When each pixel P is distinguished, the pixel P is described together with the row number m and the column number n. m is an integer of 1 or more and n is an integer of 2 or more. n may be any even number.
  • the pixel P arranged in the i-th row and j-th column is a pixel P [i, j]. i is an integer of 1 or more and m or less. j is an integer of 1 or more and n or less.
  • the imaging unit PIX has m ⁇ n pixels P [1, 1] to P [m, n].
  • N vertical signal lines VL ⁇ 1> to VL ⁇ n> are arranged in the column direction.
  • the pixels P [1, 1] to P [m, n] are connected to the vertical signal lines VL ⁇ 1> to VL ⁇ n> in units of columns. That is, the pixels P [1, j] to P [m, j] in the j-th column are connected to the vertical signal line VL ⁇ j>.
  • the pixel P outputs, to the column processing unit COLS, a reset signal when each pixel P is reset, and a video signal corresponding to light incident on each pixel P.
  • the pixel P has a photodiode, and accumulates a signal according to the light incident on the pixel P in the photodiode.
  • the pixel P outputs a video signal based on the signal accumulated in the photodiode to the column processing unit COLS.
  • the column processing unit COLS has a plurality of column circuits COL arranged for each column of the plurality of pixels P. In FIG. 7, some of the plurality of column circuits COL are omitted. When each column circuit COL is distinguished, the column circuit COL is described together with the column number n.
  • the column circuit COL disposed in the j-th column is a column circuit COL ⁇ j>.
  • the column processing unit COLS has n column circuits COL ⁇ 1> to COL ⁇ n>. Column circuits COL ⁇ 1> to COL ⁇ n> are arranged for each of vertical signal lines VL ⁇ 1> to VL ⁇ n>.
  • the column circuit COL ⁇ j> in the j-th column is connected to the vertical signal line VL ⁇ j>.
  • the reset signal and the video signal output from the pixels P [1, j] to P [m, j] in the j-th column are input to the column circuit COL ⁇ j> in the j-th column.
  • the column circuits COL ⁇ 1> to COL ⁇ n> are connected to the AD conversion circuit ADCa via the horizontal signal line HL.
  • the column circuits COL ⁇ 1> to COL ⁇ n> cancel reset noise and the like included in the video signal output from the pixels P [1, 1] to P [m, n].
  • the column circuits COL ⁇ 1> to COL ⁇ n> generate the video signal VSIG and output the video signal VSIG to the AD conversion circuit ADCa.
  • the AD conversion circuit ADCa is connected to the horizontal signal line HL.
  • the AD conversion circuit ADCa converts the video signal VSIG (analog voltage signal) output from the column circuits COL ⁇ 1> to COL ⁇ n> into a digital signal.
  • the AD conversion circuit ADCa includes an odd AD converter ADCO and an even AD converter ADCE.
  • the timing generator TG is connected to the imaging unit PIX, the column processing unit COLS, and the AD conversion circuit ADCa via a signal line (not shown).
  • the timing generator TG supplies signals necessary for controlling the image sensor IMG to each part.
  • the timing generator TG supplies the row selection signal RSEL ⁇ 1> to the pixel P [1,1] to the pixel P [1, n] in the first row, and the row selection signal RSEL ⁇ m> in the mth row The signal is supplied to P [m, 1] to pixel P [m, n].
  • the timing generator TG supplies similar signals to the pixels P for the other rows.
  • the row selection signal RSEL ⁇ i> is “L (Low)”
  • the pixel P [i, 1] to the pixel P [i, n] to which the row selection signal RSEL ⁇ i> is supplied are the vertical signal lines VL. It is not connected to ⁇ 1> to VL ⁇ n>.
  • the pixel P [i, 1] to the pixel P [i, n] to which the row selection signal RSEL ⁇ i> is supplied are the vertical signal lines VL. It is connected to ⁇ 1> to VL ⁇ n>.
  • the timing generator TG supplies a control signal CLP_R and a control signal CLP_S to the column circuits COL ⁇ 1> to COL ⁇ n>.
  • the control signal CLP_R is a control signal for sampling the reset signal output from the pixel P by the column circuits COL ⁇ 1> to COL ⁇ n>.
  • the control signal CLP_R changes to “H”.
  • the column circuits COL ⁇ 1> to COL ⁇ n> sample reset signals.
  • this sampling operation ends.
  • the control signal CLP_S is a control signal for sampling the video signal output from the pixel P by the column circuits COL ⁇ 1> to COL ⁇ n>.
  • the control signal CLP_S changes to “H”.
  • the column circuits COL ⁇ 1> to COL ⁇ n> sample the video signal.
  • this sampling operation ends.
  • the timing generator TG supplies column selection signals CSEL ⁇ 1> to CSEL ⁇ n> to column circuits COL ⁇ 1> to COL ⁇ n>.
  • column select signals CSEL ⁇ 1> to CSEL ⁇ n> change to “H”
  • column circuits COL ⁇ 1> to COL ⁇ n> are connected to horizontal signal line HL.
  • the column circuits COL ⁇ 1> to COL ⁇ n> output the video signal VSIG ⁇ x> based on the difference VPIX ⁇ x> between the reset signal and the video signal to the AD conversion circuit ADCa.
  • x is an integer of 1 or more and n or less.
  • the video signal VSIG ⁇ x> is a signal based on the reference voltage VREF.
  • the video signal VSIG is expressed by equation (3).
  • the video signal VSIG has a negative polarity.
  • VSIG VREF-VPIX ⁇ x> (3)
  • VPIX_SAT is the saturated (maximum) voltage of VPIX.
  • VSIG VREF-0 (4)
  • VSIG VREF-VPIX_SAT (5)
  • the video signal VSIG has a negative polarity.
  • the video signal VSIG may have positive polarity.
  • FIGS. 8 and 9 show signals related to the operation of the image sensor IMG.
  • Row selection signals RSEL ⁇ 1> to RSEL ⁇ m> are shown in FIG.
  • the voltage of the vertical signal line VL ⁇ 1>, the video signal VSIG, the control signal CLP_R, the control signal CLP_S, and the column selection signals CSEL ⁇ 1> to CSEL ⁇ n> are shown.
  • the state of the odd AD converter ADCO, the state of the even AD converter ADCE, and bit strings D ⁇ 1> to D ⁇ n> of the AD conversion result (AD_RESULT) are shown.
  • the horizontal axis represents time
  • the vertical axis represents signal level.
  • the resolution in the time direction is different between FIG. 8 and FIG.
  • the period from time t100 to time t101 in FIG. 8 corresponds to the period from time t1 to time t10 in FIG.
  • row selection signal RSEL ⁇ 1> changes to "H”.
  • Row select signals RSEL ⁇ 2> to RSEL ⁇ m> are maintained at “L”.
  • row selection signal RSEL ⁇ 1> changes to "L”
  • row selection signal RSEL ⁇ 2> changes to "H”.
  • row selection signals RSEL ⁇ 3> to RSEL ⁇ m> in each row sequentially change to “H”.
  • row selection signal RSEL ⁇ m-1> changes to "L”
  • row selection signal RSEL ⁇ m> changes to "H”.
  • the row selection signal RSEL ⁇ m> changes to "L”. Changes in row selection signals RSEL ⁇ 1> to RSEL ⁇ m> from time t200 to time t300 are similar to changes in row selection signals RSEL ⁇ 1> to RSEL ⁇ m> from time t100 to time t110.
  • the pixels P [1, 1] to P [1, n] in the first row are read out at time t1 in FIG. 9, the pixels P [1, 1] to P [1, n] The photodiode is reset to a predetermined voltage and exposed for a predetermined time.
  • the following description will focus on the readout of signals from the pixels P [1,1] to P [1, n] in the first row.
  • the readout of the signals from the pixels P in the other rows is similar to the readout of the signals from the pixels P in the first row.
  • the odd AD converter ADCO and the even AD converter ADCE are in the inactive state STAB.
  • the row selection signal RSEL ⁇ 1> changes to “H”, whereby the pixels P [1,1] to P [1, n] in the first row are each connected to the vertical signal lines VL ⁇ 1> to VL. Connected to ⁇ n>.
  • the pixels P [1,1] to P [1, n] start outputting the reset signals VRST ⁇ 1> to VRST ⁇ n>.
  • the reset signals VRST ⁇ 1> to VRST ⁇ n> of each column only the reset signal VRST ⁇ 1> of the first column is shown in FIG. 9 as a representative.
  • the control signal CLP_R becomes "H".
  • column circuits COL ⁇ 1> to COL ⁇ n> start sampling operations of reset signals VRST ⁇ 1> to VRST ⁇ n>.
  • the control signal CLP_R becomes “L” at time t2.
  • the level of the reset signal held in column circuits COL ⁇ 1> to COL ⁇ n> is determined.
  • the pixels P [1,1] to P [1, n] start outputting the video signals PIXOUT ⁇ 1> to PIXOUT ⁇ n>.
  • the control signal CLP_S goes high.
  • the column circuits COL ⁇ 1> to COL ⁇ n> start sampling operations of the video signals PIXOUT ⁇ 1> to PIXOUT ⁇ n>.
  • the column circuits COL ⁇ 1> to COL ⁇ n> complete the sampling operation of the video signals PIXOUT ⁇ 1> to PIXOUT ⁇ n>.
  • column circuits COL ⁇ 1> to COL ⁇ n> reset of pixels included in video signals PIXOUT ⁇ 1> to PIXOUT ⁇ n> input from pixels P [1, 1] to P [1, n]. Noise is canceled.
  • Column circuits COL ⁇ 1> to COL ⁇ n> hold video signal VSIG whose amplitude is VPIX ⁇ 1> to VPIX ⁇ n> with reference to reference voltage VREF.
  • the video signal VSIG whose amplitude is VPIX ⁇ 1> is output from the column circuit COL ⁇ 1> in the first column.
  • This signal is sampled by the odd AD converter ADCO of the AD conversion circuit ADCa. After the short-time reset operation RESET is performed, the odd AD converter ADCO starts the sampling operation SAMP.
  • the column selection signal CSEL ⁇ 1> becomes "L"
  • the column selection signal CSEL ⁇ 2> becomes "H”.
  • a video signal VSIG whose amplitude is VPIX ⁇ 2> is output from the column circuit COL ⁇ 2> in the second column.
  • This signal is sampled by the even AD converter ADCE of the AD conversion circuit ADCa.
  • the even AD converter ADCE starts the sampling operation SAMP.
  • the odd AD converter ADCO ends the sampling operation SAMP.
  • the odd AD converter ADCO starts an AD conversion operation CONV.
  • the AD conversion circuit ADCa updates the AD conversion result AD_RESULT, and outputs a bit string D ⁇ 1> as the conversion result.
  • the bit string D ⁇ 1> is a signal configured by the digital signal DO [6: 1] or the digital signal DE [6: 1].
  • the sampling operation SAMP of the video signal VSIG output from the column circuit COL ⁇ n> starts at time t7 and ends at time t8.
  • the AD conversion operation CONV of the video signal VSIG output from the column circuit COL ⁇ n> starts at time t8 and ends at time t9.
  • the video signal VSIG output from the column circuits COL ⁇ 1> to COL ⁇ n-1> of the odd columns is sampled by the odd AD converter ADCO of the AD conversion circuit ADCa.
  • the video signals VSIG output from the column circuits COL ⁇ 2> to COL ⁇ n> of the even columns are sampled by the even AD converters ADCE of the AD conversion circuit ADCa. While one AD converter performs the sampling operation SAMP, the other AD converter performs the AD conversion operation CONV. In addition, there is always a short reset operation RESET between the sampling operation SAMP and the AD conversion operation CONV.
  • the sampling operation SAMP by one AD converter and the AD conversion operation CONV by the other AD converter are performed in parallel. In a period in which no column circuit is selected, the odd AD converter ADCO and the even AD converter ADCE of the AD conversion circuit ADCa are in the inactive state STAB.
  • AD conversion circuit ADCa generates column circuit COL ⁇ i> of the column corresponding to column selection signal CSEL ⁇ i> at the moment when column selection signals CSEL ⁇ 1> to CSEL ⁇ n> change from “H” to “L”. End the sampling of the video signal VSIG output from and start the AD conversion. Every time AD conversion is completed, the AD conversion circuit ADCa updates the bit strings D ⁇ 1> to D ⁇ n> and sequentially outputs (updates) the AD conversion result AD_RESULT.
  • the row selection signal RSEL ⁇ 1> switches from “H” to “L” at time t101 (corresponding to time t10) after the readout from the pixel P [1, n] in the first row and the nth column is completed.
  • the row selection signal RSEL ⁇ 2> switches from “L” to “H”.
  • signals from the pixels P from the pixel P [2, 1] in the second row and the first column to the pixel P [2, n] in the second row and the nth column pass through the column circuits COL ⁇ 1> to COL ⁇ n>. It is read out.
  • the signals from the pixels P in the third to m-th rows are read out, and the reading is completed at time t300.
  • the image sensor IMG at least includes the AD conversion circuit ADCa, the plurality of pixels P, and the plurality of column circuits COL.
  • the plurality of pixels P are arranged in a matrix.
  • the plurality of column circuits COL are arranged for each column of the plurality of pixels P.
  • the video signal VSIG output from the column circuits COL ⁇ 1> to COL ⁇ n-1> arranged in the odd columns of the plurality of pixels P is either one of the odd AD converter ADCO and the even AD converter ADCE. Or the odd AD converter ADCO.
  • the signals output from the column circuits COL ⁇ 2> to COL ⁇ n> arranged in the even columns of the plurality of pixels P are the column circuits arranged in the even columns among the odd AD converter ADCO and the even AD converter ADCE.
  • the signals output from COL ⁇ 2> to COL ⁇ n>, that is, the video signal VSIG are input to an even AD converter ADCE different from the odd AD converter ADCO.
  • FIG. 10 shows the configuration of the AD conversion circuit ADCa.
  • the AD conversion circuit ADCa includes an odd AD converter ADCO, an even AD converter ADCE, and a capacitance array CDACC.
  • the odd AD converter ADCO has a DAC circuit CDACO, a comparator CMPO, and a control circuit SARLOGICO.
  • the even AD converter ADCE has a DAC circuit CDACE, a comparator CMPE, and a control circuit SARLOGICE.
  • the odd AD converter ADCO and the capacitance array CDACC constitute a first AD converter.
  • the even AD converter ADCE and the capacitance array CDACC constitute a second AD converter. That is, the AD conversion circuit ADCa includes two single-ended AD converters.
  • the first AD converter and the second AD converter share a fixed capacity capacitance array CDACC.
  • the first AD converter performs a sampling operation (first operation) in parallel with the AD conversion operation (second operation) by the second AD converter, and the second AD converter performs the first operation.
  • the AD conversion operation is performed.
  • the video signal VSIG1 is sampled by the DAC circuit CDACO, and the reference signal VCM is sampled by the capacitors C1C to C6C.
  • the video signal VSIG2 is sampled by the DAC circuit CDACE, and the reference signal VCM is sampled by the capacitors C1C to C6C.
  • AD conversion AD conversion is sequentially performed based on the voltages of the video signal VSIG1 sampled by the sampling operation and the reference signal VCM.
  • the first AD converter and the second AD converter alternately perform the sampling operation and the AD conversion operation.
  • the first AD converter and the second AD converter While switching between the sampling operation and the AD conversion operation, the first AD converter and the second AD converter have capacitances C1C to C6C in a period shorter than the period for performing the sampling operation and the period for performing the AD conversion operation.
  • a reset operation (third operation) for resetting the voltage of the sampled reference signal VCM is performed.
  • the detailed configuration of the AD conversion circuit ADCa will be described.
  • the configurations of the odd AD converter ADCO and the capacitance array CDACC are the same as the respective configurations in the first embodiment.
  • the even AD converter ADCE is configured in the same manner as the odd AD converter ADCO.
  • the DAC circuit CDACE is configured similarly to the DAC circuit CDACO.
  • the DAC circuit CDACE has capacitors C1E to C6E, switches SW1E to SW6E, and a sample switch SWSMPLE.
  • the sample switch SWSMPLE is configured in the same manner as the sample switch SWSMPLO.
  • the state of the sample switch SWSMPLE is controlled by the control signal SMPLE.
  • the sample switch SWSMPLE samples the video signal VSIG2 from the signal source SIG_EVEN.
  • the capacitors C1E to C6E are configured in the same manner as the capacitors C1O to C6O.
  • the sum of capacitance values of the plurality of capacitances C1E to C6E and the sum of capacitance values of the plurality of capacitances C1C to C6C are substantially the same.
  • the capacitors C1E to C6E hold the video signal VSIG2 sampled by the sample switch SWSMPLE.
  • the switches SW1E to SW6E are configured in the same manner as the switches SW1O to SW6O.
  • the states of the switches SW1E to SW6E are controlled by bits DE1 to DE6 of the AD conversion result.
  • the DAC circuit CDACE is connected to the signal source SIG_EVEN.
  • the video signal VSIG2 generated by the signal source SIG_EVEN is supplied to the node VIE.
  • the signal source SIG_EVEN corresponds to the imaging unit PIX shown in FIG. 7 and the column circuits COL ⁇ 2> to COL ⁇ n> of the even columns. Further, the signal source SIG_ODD corresponds to the imaging unit PIX and the column circuits COL ⁇ 1> to COL ⁇ n ⁇ 1> in odd columns shown in FIG.
  • the node VIE which is a charge summing node, is connected to the second terminal of the sample switch SWSMPLE, the first electrodes of the capacitors C1E to C6E, and the first input terminal of the comparator CMPE.
  • the node VIE is an arbitrary position on the signal line electrically connected to them.
  • the comparator CMPE is configured in the same manner as the comparator CMPO.
  • the comparator CMPE compares the voltage of the node VIE with the voltage of the node VIC.
  • the comparator CMPE outputs a signal VONE based on the comparison result from the first output terminal, and outputs a signal VOPE based on the comparison result from the second output terminal.
  • Control circuit SARLOGICE is configured in the same manner as the control circuit SARLOGICO.
  • Control circuit SARLOGICE generates digital signal DE [6: 1] of the AD conversion result based on signal VOPE and signal VONE from comparator CMPE, and outputs digital signal DE [6: 1] from the output terminal.
  • the bits DE1 to DE6 constituting the digital signal DE [6: 1] are output to the switches SW1E to SW6E of the DAC circuit CDACE.
  • the control circuit SARLOGICE controls the DAC circuit CDACE by outputting the bits DE1 to DE6 to the switches SW1E to SW6E.
  • FIG. 11 shows signals related to the operation of the AD conversion circuit ADCa.
  • the state of the DAC circuit CDACO and the state of the DAC circuit CDACE are shown.
  • a control signal SMPLO, a control signal SMPLE, and a control signal SMPLC are shown.
  • the digital signal DO [6: 1] and the digital signal DE [6: 1] are shown in hexadecimal.
  • the respective potentials of node VIO, node VIE and node VIC are shown.
  • the horizontal axis indicates time, and the vertical axis indicates signal level.
  • the AD conversion circuit ADCa performs a reset operation.
  • the video signal VSIG1 is input from the signal source SIG_ODD to the node VIO.
  • the video signal VSIG2 is input from the signal source SIG_EVEN to the node VIE.
  • the switch SWSMPLC since the switch SWSMPLC is on, the reference signal VCM is input from the reference signal source VCM_G to the node VIC.
  • period T1 the voltage of node VIO is kept at the voltage of video signal VSIG1, the voltage of node VIE is kept at the voltage of video signal VSIG2, and the voltage of node VIC is kept at the voltage of reference signal VCM.
  • charges based on video signal VSIG1 are held in capacitors C1O to C6O
  • charges based on video signal VSIG2 are held in capacitors C1E to C6E
  • charges based on reference signal VCM are held in capacitors C1C to C6C .
  • the odd number AD converter ADCO performs sampling operation SAMP to sample the signal input to the DAC circuit CDACO.
  • the video signal VSIG1 is input from the signal source SIG_ODD to the node VIO.
  • the bits DO1 to DO6 which are "H" are input to the switches SW1O to SW6O.
  • the first terminal S1 and the third terminal D of each of the switches SW1O to SW6O are connected.
  • the voltage of the node VIO is maintained at the voltage of the video signal VSIG1.
  • the even AD converter ADCE performs AD conversion operation CONV to perform AD conversion of the signal sampled in the DAC circuit CDACE.
  • the switch SWSMPLE since the switch SWSMPLE is off, the input of the video signal VSIG2 from the signal source SIG_EVEN to the node VIE is stopped.
  • the switch SWSMPLC since the switch SWSMPLC is off, the input of the reference signal VCM from the reference signal source VCM_G to the node VIC is stopped.
  • the period T2 to the period T7 correspond to a period for the even AD converter ADCE (comparator CMPE) to compare MSB to LSB based on the charge held in the DAC circuit CDACE.
  • comparator CMPE compares the voltages of node VIE and node VIC. This comparison determines the logic of the most significant bit DE6 of the AD conversion result.
  • the comparator CMPE outputs the comparison result to the control circuit SARLOGICE.
  • control circuit SARLOGICE outputs bit DE6 according to the comparison result in period T2.
  • the voltage of the node VIE is denoted as VIE and the voltage of the node VIC is denoted as VIC.
  • the logic level of bit DE6 is "H”.
  • the logic level of the bit DEi is set to “L”.
  • the logic level of bit DEi is set to “L”, and the logic level of the immediately preceding bit DE (i + 1) is set to “H”.
  • i is an integer of 1 to 5;
  • control circuit SARLOGICE sets the logic of bit DE6 to "L".
  • the digital signal DE [6: 1] expressed in hexadecimal changes from 3F (111111) to 1F (0111111).
  • the logic level of bit DE6 is output to switch SWE6. Therefore, the switch SWE6 is switched to the state in which the second terminal S2 and the third terminal D are connected. Thereby, the ground level is input to the second electrode of the capacitor C6E.
  • the comparator CMPE compares the voltages of the node VIE and the node VIC to determine the logic level of the bit DE5.
  • control circuit SARLOGICE sets the logic of bit DE5 to "L” and the logic of bit DE6 to "H”.
  • the digital signal DE [6: 1] expressed in hexadecimal changes from 1F (011111) to 2F (101111).
  • the logic level of bit DE6 is output to switch SW6E, and the logic level of bit DE5 is output to switch SW5E.
  • the switch SW6E is switched to the state in which the first terminal S1 and the third terminal D are connected.
  • the reference voltage VREF is input to the second electrode of the capacitor C6E.
  • the switch SW5E switches to a state in which the second terminal S2 and the third terminal D are connected.
  • the ground level is input to the second electrode of the capacitor C5E.
  • the comparator CMPE compares the voltages of the node VIE and the node VIC to determine the logic level of the bit DE4.
  • control circuit SARLOGICE sets the logic of bit DE4 to "L".
  • the digital signal DE [6: 1] expressed in hexadecimal changes from 2F (101111) to 27 (100111).
  • the logic level of the bit DE4 is output to the switch SW4E. Therefore, the switch SW4E is switched to the state in which the second terminal S2 and the third terminal D are connected.
  • the ground level is input to the second electrode of the capacitor C4E.
  • the state of the switch SW4E changes, whereby the potential of the node VIE decreases by (1/2 3 ) VREF.
  • the comparator CMPE compares the voltages of the node VIE and the node VIC to determine the logic level of the bit DE3.
  • control circuit SARLOGICE sets the logic of bit DE3 to "L” and sets the logic of bit DE4 to "H”.
  • the digital signal DE [6: 1] expressed in hexadecimal changes from 27 (100111) to 2B (101011).
  • the logic level of bit DE4 is output to switch SW4E, and the logic level of bit DE3 is output to switch SW3E.
  • the switch SW4E is switched to the state in which the first terminal S1 and the third terminal D are connected.
  • the reference voltage VREF is input to the second electrode of the capacitor C4E.
  • the switch SW3E switches to a state in which the second terminal S2 and the third terminal D are connected.
  • the ground level is input to the second electrode of the capacitor C3E.
  • the comparator CMPE compares the voltages of the node VIE and the node VIC to determine the logic level of the bit DE2.
  • control circuit SARLOGICE sets the logic of bit DE2 to "L".
  • the digital signal DE [6: 1] expressed in hexadecimal changes from 2B (101011) to 29 (101001).
  • the logic level of the bit DE2 is output to the switch SW2E.
  • the switch SW2E switches to a state in which the second terminal S2 and the third terminal D are connected.
  • the ground level is input to the second electrode of the capacitor C2E.
  • the state of the switch SW2E changes, whereby the potential of the node VIE decreases by (1/2 5 ) VREF.
  • the comparator CMPE compares the voltages of the node VIE and the node VIC to determine the logic level of the bit DE1.
  • control circuit SARLOGICE sets the logic of bit DE1 to "L".
  • the digital signal DE [6: 1] expressed in hexadecimal changes from 29 (101001) to 28 (101000).
  • the digital signal DE [6: 1] obtained in this manner is used in an external signal processing system.
  • the determination result in the period T7 is not used to control the switch SW1E.
  • a control signal that is always “H” may be input to the switch SW1E.
  • the operation in the period T1 ' is similar to the operation in the period T1.
  • the AD conversion circuit ADCa performs a reset operation.
  • the odd AD converter ADCO performs AD conversion operation CONV to perform AD conversion of the signal sampled in the DAC circuit CDACO.
  • the even AD converter ADCE performs sampling operation SAMP to sample the signal input to the DAC circuit CDACE.
  • the digital signal DO [6: 1] is used in an external signal processing system.
  • operations other than the above-described operation are similar to the operations in the period T2 to the period T7.
  • the image sensor according to each aspect of the present invention may not have a configuration other than the plurality of pixels, the plurality of column circuits, and the AD converter.
  • the other AD converter performs a sampling operation while any one of two AD converters performs an AD conversion operation.
  • the two AD converters of the AD conversion circuit ADCa can perform the sampling operation and the AD conversion operation simultaneously. Therefore, the speed of AD conversion is approximately doubled. That is, the AD conversion circuit ADCa can perform AD conversion at high speed.
  • the capacitance array CDACC which is a fixed capacitance for alleviating kickback noise, is shared by two AD converters, it is possible to reduce the chip area required for mounting the fixed capacitance. Therefore, it is possible to realize a high speed, high accuracy, and further compact AD conversion circuit.
  • the AD conversion circuit ADCa included in the image sensor IMG of the second embodiment can perform AD conversion at high speed and with high accuracy. Also, the AD conversion circuit ADCa is compact and consumes less power. Thereby, the image sensor IMG can perform imaging at high speed, and can acquire a high quality image. Further, the image sensor IMG is compact and consumes less power.
  • the voltages of the node VIO and the node VIE to which the video signal is input are not constant. Therefore, a certain amount of time is required to stabilize the voltage at each node.
  • the AD conversion circuit ADCa can perform the reset operation in a short time.
  • FIG. 12 shows the entire configuration of the image sensor IMGa.
  • points different from the configuration shown in FIG. 7 will be described.
  • the odd AD converters ADCO are connected to the column circuits COL ⁇ 1> to COL ⁇ n-1> in odd columns
  • the even AD converters ADCE are column circuits COL ⁇ 2> to COL ⁇ even in even columns. Connected to n>.
  • the image sensor IMGa has two different horizontal signal lines HLO and horizontal signal lines HLE.
  • the horizontal signal line HLO is connected to the column circuits COL ⁇ 1> to COL ⁇ n-1> of the odd columns and the odd AD converter ADCO.
  • the horizontal signal line HLE is connected to the column circuits COL ⁇ 2> to COL ⁇ n> and the even AD converter ADCE in the even columns.
  • the number of column circuits COL connected to each of the horizontal signal lines HLO and the horizontal signal lines HLE is half of the number of column circuits COL connected to the horizontal signal lines HL of the image sensor IMG shown in FIG.
  • the configuration shown in FIG. 12 is the same as the configuration shown in FIG.
  • the column circuit COL Since an analog switch (not shown) is present inside the column circuit COL, a parasitic capacitance is generated at the output terminal of the column circuit COL.
  • the column circuit COL has to drive this parasitic capacitance in addition to the DAC circuit.
  • parasitic capacitances connected to the horizontal signal line HLO and the horizontal signal line HLE are reduced compared to parasitic capacitances connected to the horizontal signal line HL of the image sensor IMG.
  • the image sensor IMGa can operate at higher speed and lower power consumption.
  • FIG. 13 shows the entire configuration of the image sensor IMGb.
  • points different from the configuration shown in FIG. 12 will be described.
  • the image sensor IMGb has a selection switch SEL3 in addition to the configuration of the image sensor IMGa.
  • the selection switch SEL3 has a first input terminal S1, a second input terminal S2, a first output terminal D1, and a second output terminal D2.
  • the first input terminal S1 of the selection switch SEL3 is connected to the horizontal signal line HLO.
  • the video signals VSIG from the column circuits COL ⁇ 1> to COL ⁇ n-1> of the odd-numbered columns are input to the first input terminal S1 of the selection switch SEL3.
  • the second input terminal S2 of the selection switch SEL3 is connected to the horizontal signal line HLE.
  • Video signals VSIG from the column circuits COL ⁇ 2> to COL ⁇ n> of even columns are input to the second input terminal S2 of the selection switch SEL3.
  • the first output terminal D1 of the selection switch SEL3 is connected to the odd AD converter ADCO of the AD conversion circuit ADCa.
  • the second output terminal D2 of the selection switch SEL3 is connected to the even AD converter ADCE of the AD conversion circuit ADCa.
  • the imaging unit PIX in the image sensor IMGa is changed to an imaging unit PIXa.
  • Each of the plurality of pixels P arranged in the imaging unit PIXa has a color filter.
  • the plurality of pixels P includes a pixel P (G) including a green color filter, a pixel P (B) including a blue color filter, and a pixel P (R) including a red color filter.
  • the green color filter transmits only green light of visible light.
  • the blue color filter transmits only blue light of visible light.
  • the red color filter transmits only red light of visible light.
  • the pixel P (G) is described as "G”
  • the pixel P (B) is described as "B”
  • the pixel P (R) is described as "R”.
  • the number of pixels P including color filters of each color is four or more.
  • the number of rows and the number of columns of the pixel P are integers of 2 or more.
  • the pixels P including the color filters of each color are periodically arranged.
  • the plurality of pixels P constitute a Bayer array.
  • Two pixels P (G), one pixel P (B), and one pixel P (R) constitute a unit array of Bayer arrangement.
  • the unit arrays are periodically arranged in two dimensions.
  • the pixels P in the odd rows and odd columns are the pixels P (G).
  • the pixels P in the odd rows and even columns are pixels P (R).
  • the pixels P in the even rows and odd columns are the pixels P (B).
  • the pixels P in the even rows and even columns are pixels P (G).
  • the configuration shown in FIG. 13 is the same as the configuration shown in FIG.
  • the first input terminal S1 of the selection switch SEL3 and the first output terminal D1 of the selection switch SEL3 are connected, and the second input of the selection switch SEL3
  • the terminal S2 is connected to the second output terminal D2 of the selection switch SEL3.
  • the first input terminal S1 of the selection switch SEL3 and the second output terminal D2 of the selection switch SEL3 are connected, and the second input of the selection switch SEL3
  • the terminal S2 is connected to the first output terminal D1 of the selection switch SEL3.
  • the other operations are the same as the operation of the image sensor IMG of the second embodiment.
  • the image sensor IMGb has pixels P of three colors.
  • the image sensor IMGb may have pixels P of two or more colors.
  • the color filter that each pixel P has may be a complementary color filter. That is, the pixel P (G) may be replaced by a magenta pixel P, the pixel P (B) may be replaced by a yellow pixel P, and the pixel P (R) may be replaced by a cyan pixel P .
  • the combination of color filters may be other than this. The arrangement of the color filters can be freely modified within the scope of the claims.
  • the image sensor IMGb includes the AD conversion circuit ADCa and the plurality of pixels P arranged in a matrix.
  • the plurality of pixels P includes a plurality of first pixels P and a plurality of second pixels P.
  • the first pixel P has a color filter of the first color.
  • the second pixel P has a color filter of a second color different from the first color.
  • the first color and the second color are any two of green, blue and red.
  • the plurality of first pixels P and the plurality of second pixels P are periodically arranged.
  • the signal output from the first pixel P is input to any one of the first AD converter and the second AD converter.
  • the signal output from the second pixel P is input to an AD converter different from the AD converter to which the signal output from the first pixel P of the first AD converter and the second AD converter is input. It is input.
  • the video signal VSIG output from the pixel P (G) is sampled by the odd AD converter ADCO, and the video signal VSIG output from the pixel P (B) or the pixel P (R) is even AD converted Sampled by the ADCE.
  • the video signal VSIG output from the pixel P including the color filter of the same color is always processed by the same analog signal processing system. Therefore, the influence of the individual variation of the odd AD converter ADCO and the even AD converter ADCE on the imaging result of the image sensor IMGb can be minimized. In particular, color noise due to individual variation of the odd AD converter ADCO and the even AD converter ADCE is reduced. Therefore, the image sensor IMGb can acquire a high quality image.
  • FIG. 14 shows the entire configuration of the image sensor IMGc.
  • the configuration shown in FIG. 14 will be described about differences from the configuration shown in FIG.
  • the imaging unit PIX in the image sensor IMG is changed to an imaging unit PIXa.
  • the imaging unit PIXa is the same as the imaging unit PIXa included in the image sensor IMGb illustrated in FIG.
  • the configuration shown in FIG. 13 is the same as the configuration shown in FIG.
  • the image sensor IMGc does not have the selection switch SEL3.
  • the image sensor IMGc appropriately controls the switch SWSMPLO of the odd AD converter ADCO and the switch SWSMPLE of the even AD converter ADCE, a function equivalent to the function of the image sensor IMGb shown in FIG. 13 is realized.
  • the switch SWSMPLO of the odd AD converter ADCO is turned on, and the switches of the even AD converter ADCE SWSMPLE is turned off.
  • the video signal VSIG output from the pixels P (G) in the odd rows and the pixels P (G) in the even rows is input to the odd AD converter ADCO.
  • the switch SWSMPLO of the odd AD converter ADCO When reading out the signals from the pixels P in the odd rows and even columns and the pixels P in the even rows and odd columns, the switch SWSMPLO of the odd AD converter ADCO is turned off, and the switch SWSMPLE of the even AD converter ADCE is It turns on.
  • the video signal VSIG output from the pixels P (R) in the odd rows and the pixels P (B) in the even rows is input to the even AD converter ADCE.
  • the video signal VSIG output from the pixel P (G) is sampled by the odd AD converter ADCO, and the video signal VSIG output from the pixel P (B) or the pixel P (R) is even AD converted Sampled by the ADCE. For this reason, the image sensor IMGc can acquire a high-quality image as in the case of the image sensor IMGb.
  • the single-ended AD converter, the AD conversion circuit, and the image sensor can obtain highly accurate AD conversion results.
  • ADC AD converter ADCa AD converter circuit ADCO Odd AD converter ADCE Even AD converter CDACO, CDACE DAC circuit CDACC Capacitive array CMPO, CMPE comparator SARLOGICO, SARLOGICE Control circuit A1 Differential amplifier circuit L1 Latch circuit IMG, IMGa, IMGb, IMGc Image sensor PIX, PIXa Imaging unit P pixel TG timing generator COLS Column processing unit COL Column circuit SEL3 selection switch

Abstract

This single-ended AD converter comprises a DAC circuit, a fixed capacitor, a dynamic comparator, and a control circuit. The DAC circuit has a plurality of capacitors with weighted capacitance values. The plurality of capacitors hold an analog voltage signal. The fixed capacitor holds a reference voltage signal. The dynamic comparator compares the voltage of the analog voltage signal and the voltage of the reference voltage signal. The control circuit controls the DAC circuit in accordance with the result of the comparison by the dynamic comparator. The total of the capacitance values of the plurality of capacitors of the DAC circuit and the capacitance value of the fixed capacitor are approximately the same.

Description

シングルエンド型ＡＤ変換器、ＡＤ変換回路、およびイメージセンサSingle-ended AD converter, AD converter, and image sensor
　本発明は、シングルエンド型ＡＤ変換器、ＡＤ変換回路、およびイメージセンサに関する。 The present invention relates to a single-ended AD converter, an AD converter circuit, and an image sensor.
　図１５は、特許文献１に開示された従来のシングルエンド型ＳＡＲＡＤＣ（Ｓｕｃｃｅｓｓｉｖｅ　Ａｐｐｒｏｘｉｍａｔｉｏｎ　Ｒｅｇｉｓｔｅｒ　Ａｎａｌｏｇ　ｔｏ　Ｄｉｇｉｔａｌ　Ｃｏｎｖｅｒｔｅｒ）の構成を示す。図１５に示すように、シングルエンド型ＳＡＲＡＤＣは、ＤＡＣ（Ｄｉｇｉｔａｌ　ｔｏ　Ａｎａｌｏｇ　Ｃｏｎｖｅｒｔｅｒ）１２と、コンパレータ１３と、逐次比較論理回路１４と、容量Ｃ１～Ｃｎとを有する。コンパレータ１３の第１の入力端子はグランドレベルに接続され、かつコンパレータ１３の第２の入力端子は容量Ｃ１～Ｃｎのトッププレート側に接続されている。容量Ｃ１～Ｃｎのボトムプレート側は、グランドレベルおよび基準電圧Ｖｒｅｆのいずれか１つに接続される。容量Ｃ１～Ｃｎのボトムプレート側の接続ノードは、コンパレータ１３による判定の結果と、逐次比較論理回路１４が実行する処理のアルゴリズムとにより決定される。 FIG. 15 shows the configuration of a conventional single-ended SAR ADC (Successive Approximation Register Analog to Digital Converter) disclosed in Patent Document 1. As shown in FIG. As shown in FIG. 15, the single-ended SAR ADC has a DAC (Digital to Analog Converter) 12, a comparator 13, a successive approximation logic circuit 14, and capacitors C1 to Cn. The first input terminal of the comparator 13 is connected to the ground level, and the second input terminal of the comparator 13 is connected to the top plate side of the capacitors C1 to Cn. The bottom plate sides of the capacitors C1 to Cn are connected to any one of the ground level and the reference voltage Vref. The connection node on the bottom plate side of the capacitors C1 to Cn is determined by the result of the determination by the comparator 13 and the algorithm of the process executed by the successive approximation logic circuit 14.
　近年、ダイナミックコンパレータを比較器として用いたＳＡＲＡＤＣが学会等で報告されている。例えば、特許文献２に開示されたダイナミックコンパレータにおいて、比較動作を行わない期間には消費電流が発生しないという利点がある。 In recent years, a SAR ADC using a dynamic comparator as a comparator has been reported at academic conferences and the like. For example, in the dynamic comparator disclosed in Patent Document 2, there is an advantage that no current consumption occurs during a period in which the comparison operation is not performed.
米国特許出願公開第２０１１／２４１９１２号明細書U.S. Patent Application Publication No. 2011/241912 米国特許第８８９６４７６号明細書U.S. Pat. No. 8,896,476
　しかしながら、ダイナミックコンパレータを従来のシングルエンド型ＳＡＲＡＤＣに適用した場合には、ダイナミックコンパレータが比較動作毎に行うリセット動作に起因するキックバックノイズにより、ＡＤ変換結果に誤差が生じる。コンパレータ１３の第１の入力端子はグランドレベル、すなわち低インピーダンスノードに接続されている。このため、コンパレータ１３の第１の入力端子はキックバックノイズの影響を受けない。一方、ハイインピーダンスノードに接続されているコンパレータ１３の第２の入力端子は、少なからずキックバックノイズの影響を受ける。これが、ＡＤ変換結果に誤差が生じる理由である。 However, when the dynamic comparator is applied to the conventional single-ended SAR ADC, an error occurs in the AD conversion result due to kickback noise caused by the reset operation performed by the dynamic comparator for each comparison operation. The first input terminal of the comparator 13 is connected to the ground level, ie to the low impedance node. Therefore, the first input terminal of the comparator 13 is not affected by the kickback noise. On the other hand, the second input terminal of the comparator 13 connected to the high impedance node is affected to some extent by kickback noise. This is the reason why an error occurs in the AD conversion result.
　特許文献２に記載された全差動型ＡＤ変換器では、キックバックノイズの影響がダイナミックコンパレータの２つの入力端子でバランスされる。このため、キックバックノイズはＡＤ変換結果に悪影響を与えない。しかしながら、全差動型ＳＡＲＡＤＣの入力ドライバには全差動アンプが必要であるため、シングルエンド型ＡＤＣを採用したシステムに比べて入力ドライバのアンプ構成が複雑になる。 In the fully differential AD converter described in Patent Document 2, the effects of kickback noise are balanced at the two input terminals of the dynamic comparator. Therefore, kickback noise does not adversely affect the AD conversion result. However, since a fully differential amplifier is required for the input driver of the fully differential SAR ADC, the amplifier configuration of the input driver becomes complicated as compared with a system employing a single-ended ADC.
　本発明は、高精度なＡＤ変換結果を得ることができるシングルエンド型ＡＤ変換器、ＡＤ変換回路、およびイメージセンサを提供することを目的とする。 An object of the present invention is to provide a single-ended AD converter, an AD converter circuit, and an image sensor capable of obtaining highly accurate AD conversion results.
　本発明の第１の態様によれば、シングルエンド型ＡＤ変換器は、ＤＡＣ回路と、固定容量と、ダイナミックコンパレータと、制御回路とを有する。前記ＤＡＣ回路は、容量値が重み付けされた複数の容量を有する。前記複数の容量は、前記シングルエンド型ＡＤ変換器の外部から入力されるアナログ電圧信号を保持する。前記固定容量は、前記シングルエンド型ＡＤ変換器の外部から入力される基準電圧信号を保持する。前記ダイナミックコンパレータは、前記ＤＡＣ回路に保持された前記アナログ電圧信号の電圧と、前記固定容量に保持された前記基準電圧信号の電圧とを比較する。前記制御回路は、前記ダイナミックコンパレータの比較結果に応じて、前記ＤＡＣ回路を制御する。前記ＤＡＣ回路が有する前記複数の前記容量の容量値の合計と、前記固定容量の容量値とは、略同一である。 According to a first aspect of the present invention, a single-ended AD converter includes a DAC circuit, a fixed capacitance, a dynamic comparator, and a control circuit. The DAC circuit has a plurality of capacitances whose capacitance values are weighted. The plurality of capacitors hold analog voltage signals input from the outside of the single-ended AD converter. The fixed capacitance holds a reference voltage signal input from the outside of the single-ended AD converter. The dynamic comparator compares the voltage of the analog voltage signal held by the DAC circuit with the voltage of the reference voltage signal held by the fixed capacitor. The control circuit controls the DAC circuit in accordance with the comparison result of the dynamic comparator. The sum of the capacitance values of the plurality of capacitors included in the DAC circuit is substantially equal to the capacitance value of the fixed capacitor.
　本発明の第２の態様によれば、第１の態様において、前記ＡＤ変換器は、前記アナログ電圧信号が入力される第１の入力ノードと、前記基準電圧信号が入力される第２の入力ノードとを有してもよい。前記複数の前記容量および前記固定容量の各々は、互いに対向する第１の電極および第２の電極を有してもよい。前記ダイナミックコンパレータは第１の入力端子および第２の入力端子を有してもよい。前記複数の前記容量の前記第１の電極は、前記第１の入力ノードおよび前記第１の入力端子に接続されてもよい。前記複数の前記容量の前記第２の電極は、グランドまたは所定の基準電圧に接続されてもよい。前記固定容量の前記第１の電極は、前記第２の入力ノードおよび前記第２の入力端子に接続されてもよい。前記固定容量の前記第２の電極は、グランドに接続されてもよい。 According to a second aspect of the present invention, in the first aspect, the AD converter includes: a first input node to which the analog voltage signal is input; and a second input to which the reference voltage signal is input. It may have a node. Each of the plurality of capacitors and the fixed capacitor may have a first electrode and a second electrode facing each other. The dynamic comparator may have a first input terminal and a second input terminal. The first electrodes of the plurality of capacitors may be connected to the first input node and the first input terminal. The second electrodes of the plurality of capacitors may be connected to ground or a predetermined reference voltage. The first electrode of the fixed capacitance may be connected to the second input node and the second input terminal. The second electrode of the fixed capacitance may be connected to ground.
　本発明の第３の態様によれば、ＡＤ変換回路は、前記シングルエンド型ＡＤ変換器である第１のＡＤ変換器および第２のＡＤ変換器を有する。前記第１のＡＤ変換器および前記第２のＡＤ変換器は、前記固定容量を共有する。前記第１のＡＤ変換器は、前記第２のＡＤ変換器による第２の動作と並行して第１の動作を行い、かつ前記第２のＡＤ変換器は、前記第１のＡＤ変換器による第２の動作と並行して第１の動作を行う。前記第１の動作において、前記アナログ電圧信号が前記ＤＡＣ回路にサンプリングされる。前記第２の動作において、前記第１の動作によりサンプリングされた前記アナログ電圧信号および前記基準電圧信号の各々に基づいて順次ＡＤ変換が行われる。前記第１のＡＤ変換器および前記第２のＡＤ変換器は、前記第１の動作および前記第２の動作を交互に行う。前記第１のＡＤ変換器および前記第２のＡＤ変換器が、前記第１の動作と前記第２の動作とを切り替える間に、前記第１の動作を行う期間および前記第２の動作を行う期間よりも短い期間で、前記固定容量にサンプリングされた前記基準電圧信号をリセットする第３の動作を行う。 According to a third aspect of the present invention, an AD conversion circuit includes a first AD converter and a second AD converter which are the single-ended AD converter. The first AD converter and the second AD converter share the fixed capacity. The first AD converter performs a first operation in parallel with a second operation by the second AD converter, and the second AD converter performs the first operation by the first AD converter. The first operation is performed in parallel with the second operation. In the first operation, the analog voltage signal is sampled into the DAC circuit. In the second operation, AD conversion is sequentially performed based on each of the analog voltage signal and the reference voltage signal sampled by the first operation. The first AD converter and the second AD converter alternately perform the first operation and the second operation. The first AD converter and the second AD converter perform the first operation and the second operation while switching the first operation and the second operation. A third operation of resetting the reference voltage signal sampled to the fixed capacitance is performed in a period shorter than the period.
　本発明の第４の態様によれば、イメージセンサは、前記ＡＤ変換回路を有する。 According to a fourth aspect of the present invention, an image sensor includes the AD conversion circuit.
　本発明の第５の態様によれば、第４の態様において、前記イメージセンサは、複数の画素と、複数の列回路とを有してもよい。前記複数の画素は、行列状に配置されている。前記複数の列回路は、前記複数の画素の列毎に配置されている。前記複数の画素の奇数列に配置された前記列回路から出力された信号は、前記第１のＡＤ変換器および前記第２のＡＤ変換器のいずれか１つに入力されてもよい。前記複数の画素の偶数列に配置された前記列回路から出力された信号は、前記第１のＡＤ変換器および前記第２のＡＤ変換器のうち前記偶数列に配置された前記列回路から出力された前記信号が入力されるＡＤ変換器と異なるＡＤ変換器に入力されてもよい。 According to a fifth aspect of the present invention, in the fourth aspect, the image sensor may have a plurality of pixels and a plurality of column circuits. The plurality of pixels are arranged in a matrix. The plurality of column circuits are arranged for each column of the plurality of pixels. The signal output from the column circuit arranged in the odd-numbered column of the plurality of pixels may be input to any one of the first AD converter and the second AD converter. The signal output from the column circuit arranged in the even column of the plurality of pixels is output from the column circuit arranged in the even column of the first AD converter and the second AD converter. The input signal may be input to an AD converter different from the input AD converter.
　本発明の第６の態様によれば、第４の態様において、前記イメージセンサは、行列状に配置された複数の画素を有してもよい。前記複数の画素は、複数の第１の画素と複数の第２の画素とを含んでもよい。前記第１の画素は、第１の色のカラーフィルタを有してもよい。前記第２の画素は、前記第１の色と異なる第２の色のカラーフィルタを有してもよい。前記複数の第１の画素および前記複数の第２の画素は周期的に配置されてもよい。前記第１の画素から出力された信号は、前記第１のＡＤ変換器および前記第２のＡＤ変換器のいずれか１つに入力されてもよい。前記第２の画素から出力された信号は、前記第１のＡＤ変換器および前記第２のＡＤ変換器のうち前記第１の画素から出力された前記信号が入力されるＡＤ変換器と異なるＡＤ変換器に入力されてもよい。 According to a sixth aspect of the present invention, in the fourth aspect, the image sensor may have a plurality of pixels arranged in a matrix. The plurality of pixels may include a plurality of first pixels and a plurality of second pixels. The first pixel may have a color filter of a first color. The second pixel may have a color filter of a second color different from the first color. The plurality of first pixels and the plurality of second pixels may be periodically arranged. The signal output from the first pixel may be input to any one of the first AD converter and the second AD converter. The signal output from the second pixel is an AD different from the AD converter to which the signal output from the first pixel of the first AD converter and the second AD converter is input. It may be input to the converter.
　上記の各態様によれば、シングルエンド型ＡＤ変換器、ＡＤ変換回路、およびイメージセンサは、高精度なＡＤ変換結果を得ることができる。 According to each of the above aspects, the single-ended AD converter, the AD conversion circuit, and the image sensor can obtain highly accurate AD conversion results.
本発明の第１の実施形態のＡＤ変換器の構成を示す回路図である。It is a circuit diagram showing composition of an AD converter of a 1st embodiment of the present invention. 本発明の第１の実施形態の比較器の構成を示す回路図である。It is a circuit diagram showing composition of a comparator of a 1st embodiment of the present invention. 本発明の第１の実施形態のＡＤ変換器の動作を示すタイミングチャートである。It is a timing chart which shows operation of AD converter of a 1st embodiment of the present invention. 本発明の第１の実施形態のＡＤ変換器の効果に関するシミュレーション結果を示すグラフである。It is a graph which shows the simulation result regarding the effect of the AD converter of the 1st Embodiment of this invention. 本発明の第１の実施形態のＡＤ変換器のチャージサミングノードの電圧を示すグラフである。It is a graph which shows the voltage of the charge summing node of AD converter of the 1st Embodiment of this invention. 本発明の第１の実施形態のＡＤ変換器のチャージサミングノードの電圧の関係を示すグラフである。It is a graph which shows the relationship of the voltage of the charge summing node of AD converter of the 1st Embodiment of this invention. 本発明の第２の実施形態のイメージセンサの全体構成を示すブロック図である。It is a block diagram which shows the whole structure of the image sensor of the 2nd Embodiment of this invention. 本発明の第２の実施形態のイメージセンサの動作を示すタイミングチャートである。It is a timing chart which shows operation of an image sensor of a 2nd embodiment of the present invention. 本発明の第２の実施形態のイメージセンサの動作を示すタイミングチャートである。It is a timing chart which shows operation of an image sensor of a 2nd embodiment of the present invention. 本発明の第２の実施形態のＡＤ変換回路の構成を示す回路図である。It is a circuit diagram showing the composition of the AD conversion circuit of a 2nd embodiment of the present invention. 本発明の第２の実施形態のＡＤ変換回路の動作を示すタイミングチャートである。It is a timing chart which shows operation of the AD conversion circuit of a 2nd embodiment of the present invention. 本発明の第２の実施形態の変形例のイメージセンサの全体構成を示すブロック図である。It is a block diagram which shows the whole structure of the image sensor of the modification of the 2nd Embodiment of this invention. 本発明の第３の実施形態のイメージセンサの全体構成を示すブロック図である。It is a block diagram which shows the whole structure of the image sensor of the 3rd Embodiment of this invention. 本発明の第３の実施形態の変形例のイメージセンサの全体構成を示すブロック図である。It is a block diagram which shows the whole structure of the image sensor of the modification of the 3rd Embodiment of this invention. 従来技術のシングルエンド型ＳＡＲＡＤＣの構成を示す回路図である。It is a circuit diagram showing the composition of single end type SAR ADC of prior art.
　図面を参照し、本発明の実施形態を説明する。 Embodiments of the present invention will be described with reference to the drawings.
　（第１の実施形態）
　図１は、本発明の第１の実施形態のＡＤ変換器ＡＤＣの構成を示す。ＡＤ変換器ＡＤＣの概略構成について説明する。ＡＤ変換器ＡＤＣは、シングルエンド型ＡＤ変換器である。ＡＤ変換器ＡＤＣは、少なくとも、ＤＡＣ回路ＣＤＡＣＯと、容量Ｃ１Ｃ～Ｃ６Ｃと、比較器ＣＭＰＯと、制御回路ＳＡＲＬＯＧＩＣＯとを有する。 First Embodiment
FIG. 1 shows the configuration of an AD converter ADC according to a first embodiment of the present invention. The schematic configuration of the AD converter ADC will be described. The AD converter ADC is a single-ended AD converter. The AD converter ADC at least includes a DAC circuit CDACO, capacitors C1C to C6C, a comparator CMPO, and a control circuit SARLOGICO.
　ＤＡＣ回路ＣＤＡＣＯは、容量値が重み付けされた複数の容量Ｃ１Ｏ～Ｃ６Ｏを有する。複数の容量Ｃ１Ｏ～Ｃ６Ｏは、ＡＤ変換器ＡＤＣの外部から入力されるアナログ電圧信号すなわち映像信号ＶＳＩＧ１を保持する。複数の容量Ｃ１Ｃ～Ｃ６Ｃは、固定容量である。複数の容量Ｃ１Ｃ～Ｃ６Ｃは、ＡＤ変換器ＡＤＣの外部から入力される基準電圧信号すなわち基準信号ＶＣＭを保持する。比較器ＣＭＰＯは、ダイナミックコンパレータである。比較器ＣＭＰＯは、ＤＡＣ回路ＣＤＡＣＯに保持された映像信号ＶＳＩＧ１の電圧と、複数の容量Ｃ１Ｃ～Ｃ６Ｃに保持された基準信号ＶＣＭの電圧とを比較する。制御回路ＳＡＲＬＯＧＩＣＯは、逐次比較回路である。制御回路ＳＡＲＬＯＧＩＣＯは、比較器ＣＭＰＯの比較結果に応じて、ＤＡＣ回路ＣＤＡＣＯを制御する。ＤＡＣ回路ＣＤＡＣＯが有する複数の容量Ｃ１Ｏ～Ｃ６Ｏの容量値の合計と、複数の容量Ｃ１Ｃ～Ｃ６Ｃの容量値の合計とは、略同一である。 The DAC circuit CDACO has a plurality of capacitances C1O to C6O whose capacitance values are weighted. The plurality of capacitors C1O to C6O hold an analog voltage signal input from the outside of the AD converter ADC, that is, a video signal VSIG1. The plurality of capacitances C1C to C6C are fixed capacitances. The plurality of capacitors C1C to C6C hold a reference voltage signal input from the outside of the AD converter ADC, that is, a reference signal VCM. The comparator CMPO is a dynamic comparator. The comparator CMPO compares the voltage of the video signal VSIG1 held in the DAC circuit CDACO with the voltage of the reference signal VCM held in the plurality of capacitors C1C to C6C. The control circuit SARLOGICO is a successive approximation circuit. The control circuit SARLOGICO controls the DAC circuit CDACO according to the comparison result of the comparator CMPO. The sum of the capacitance values of the plurality of capacitors C1O to C6O of the DAC circuit CDACO and the sum of the capacitance values of the plurality of capacitors C1C to C6C are substantially the same.
　また、ＡＤ変換器ＡＤＣは、アナログ電圧信号すなわち映像信号ＶＳＩＧ１が入力されるノードＶＩＯ（第１の入力ノード）と、基準電圧信号すなわち基準信号ＶＣＭが入力されるノードＶＩＣ（第２の入力ノード）とを有する。複数の容量Ｃ１Ｏ～Ｃ６Ｏおよび複数の容量Ｃ１Ｃ～Ｃ６Ｃの各々は、互いに対向する第１の電極および第２の電極を有する。比較器ＣＭＰＯは、第１の入力端子および第２の入力端子を有する。複数の容量Ｃ１Ｏ～Ｃ６Ｏの第１の電極は、ノードＶＩＯおよび比較器ＣＭＰＯの第１の入力端子に接続されている。複数の容量Ｃ１Ｏ～Ｃ６Ｏの第２の電極は、グランドＧＮＤまたは所定の基準電圧（基準電圧ＶＲＥＦ）に接続されている。複数の容量Ｃ１Ｃ～Ｃ６Ｃの第１の電極は、ノードＶＩＣおよび比較器ＣＭＰＯの第２の入力端子に接続されている。比較器ＣＭＰＯの第２の電極は、グランドＧＮＤに接続されている。 The AD converter ADC also includes a node VIO (first input node) to which an analog voltage signal, that is, the video signal VSIG1 is input, and a node VIC (second input node) to which a reference voltage signal, that is, a reference signal VCM is input. And. Each of the plurality of capacitors C1O to C6O and the plurality of capacitors C1C to C6C has a first electrode and a second electrode facing each other. The comparator CMPO has a first input terminal and a second input terminal. The first electrodes of the plurality of capacitors C1O to C6O are connected to the node VIO and a first input terminal of the comparator CMPO. The second electrodes of the plurality of capacitors C1O to C6O are connected to the ground GND or a predetermined reference voltage (reference voltage VREF). The first electrodes of the plurality of capacitors C1C to C6C are connected to the node VIC and the second input terminal of the comparator CMPO. The second electrode of the comparator CMPO is connected to the ground GND.
　ＡＤ変換器ＡＤＣの詳細な構成について説明する。図１に示すように、ＡＤ変換器ＡＤＣは、奇数ＡＤ変換器ＡＤＣＯおよび容量アレーＣＤＡＣＣを有する。奇数ＡＤ変換器ＡＤＣＯは、ＤＡＣ回路ＣＤＡＣＯと、比較器ＣＭＰＯと、制御回路ＳＡＲＬＯＧＩＣＯとを有する。ＤＡＣ回路ＣＤＡＣＯは、容量Ｃ１Ｏ～Ｃ６Ｏと、スイッチＳＷ１Ｏ～ＳＷ６Ｏと、サンプルスイッチＳＷＳＭＰＬＯとを有する。容量アレーＣＤＡＣＣは、容量Ｃ１Ｃ～Ｃ６ＣおよびサンプルスイッチＳＷＳＭＰＬＣを有する。 The detailed configuration of the AD converter ADC will be described. As shown in FIG. 1, the AD converter ADC has an odd AD converter ADCO and a capacitance array CDACC. The odd AD converter ADCO has a DAC circuit CDACO, a comparator CMPO, and a control circuit SARLOGICO. The DAC circuit CDACO has capacitors C1O to C6O, switches SW1O to SW6O, and a sample switch SWSMPLO. The capacitance array CDACC has capacitances C1C to C6C and a sample switch SWSMPLC.
　サンプルスイッチＳＷＳＭＰＬＯは、第１の端子および第２の端子を有する。サンプルスイッチＳＷＳＭＰＬＯの第１の端子は、信号源ＳＩＧ＿ＯＤＤに接続されている。サンプルスイッチＳＷＳＭＰＬＯの第２の端子は、ノードＶＩＯに接続されている。サンプルスイッチＳＷＳＭＰＬＯの状態は、オンとオフとの間で切り替わる。サンプルスイッチＳＷＳＭＰＬＯがオンであるとき、サンプルスイッチＳＷＳＭＰＬＯの第１の端子と第２の端子とが電気的に接続される。このとき、信号源ＳＩＧ＿ＯＤＤからの映像信号ＶＳＩＧ１がノードＶＩＯに入力される。サンプルスイッチＳＷＳＭＰＬＯがオフであるとき、サンプルスイッチＳＷＳＭＰＬＯの第１の端子と第２の端子とが高インピーダンス状態になる。サンプルスイッチＳＷＳＭＰＬＯの状態は、制御信号ＳＭＰＬＯによって制御される。制御信号ＳＭＰＬＯが“Ｈ（Ｈｉｇｈ）”である場合、サンプルスイッチＳＷＳＭＰＬＯはオンである。制御信号ＳＭＰＬＯが“Ｌ（Ｌｏｗ）”である場合、サンプルスイッチＳＷＳＭＰＬＯはオフである。サンプルスイッチＳＷＳＭＰＬＯは、信号源ＳＩＧ＿ＯＤＤからの映像信号ＶＳＩＧ１をサンプリングする。 The sample switch SWSMPLO has a first terminal and a second terminal. The first terminal of the sample switch SWSMPLO is connected to the signal source SIG_ODD. The second terminal of the sample switch SWSMPLO is connected to the node VIO. The state of the sample switch SWSMPLO switches between on and off. When the sample switch SWSMPLO is on, the first terminal and the second terminal of the sample switch SWSMPLO are electrically connected. At this time, the video signal VSIG1 from the signal source SIG_ODD is input to the node VIO. When the sample switch SWSMPLO is off, the first and second terminals of the sample switch SWSMPLO are in a high impedance state. The state of the sample switch SWSMPLO is controlled by the control signal SMPLO. When the control signal SMPLO is “H (High)”, the sample switch SWSMPLO is on. When the control signal SMPLO is “L (Low)”, the sample switch SWSMPLO is off. The sample switch SWSMPLO samples the video signal VSIG1 from the signal source SIG_ODD.
　スイッチＳＷ１Ｏ～ＳＷ６Ｏは、第１の端子Ｓ１と、第２の端子Ｓ２と、第３の端子Ｄとを有する。スイッチＳＷ１Ｏ～ＳＷ６Ｏの第１の端子Ｓ１は、基準電圧ＶＲＥＦに接続されている。スイッチＳＷ１Ｏ～ＳＷ６Ｏの第２の端子Ｓ２は、グランドＧＮＤに接続されている。スイッチＳＷ１Ｏ～ＳＷ６Ｏの第３の端子Ｄは、容量Ｃ１Ｏ～Ｃ６Ｏの第２の電極に接続されている。スイッチＳＷ１Ｏ～ＳＷ６Ｏの状態は、第１の状態と第２の状態との間で切り替わる。スイッチＳＷ１Ｏ～ＳＷ６Ｏが第１の状態であるとき、スイッチＳＷ１Ｏ～ＳＷ６Ｏの第１の端子Ｓ１とスイッチＳＷ１Ｏ～ＳＷ６Ｏの第３の端子Ｄとが電気的に接続される。このとき、容量Ｃ１Ｏ～Ｃ６Ｏは基準電圧ＶＲＥＦに接続される。スイッチＳＷ１Ｏ～ＳＷ６Ｏが第２の状態であるとき、スイッチＳＷ１Ｏ～ＳＷ６Ｏの第２の端子Ｓ２とスイッチＳＷ１Ｏ～ＳＷ６Ｏの第３の端子Ｄとが電気的に接続される。このとき、容量Ｃ１Ｏ～Ｃ６ＯはグランドＧＮＤに接続される。スイッチＳＷ１Ｏ～ＳＷ６Ｏの状態は、ＡＤ変換結果のビットＤＯ１～ＤＯ６によって制御される。ビットＤＯ１～ＤＯ６が“Ｈ”である場合、スイッチＳＷ１Ｏ～ＳＷ６Ｏは第１の状態である。ビットＤＯ１～ＤＯ６が“Ｌ”である場合、スイッチＳＷ１Ｏ～ＳＷ６Ｏは第２の状態である。容量Ｃ１Ｏ～Ｃ６Ｏにおいて電荷が保存された状態でスイッチＳＷ１Ｏ～ＳＷ６Ｏの接続状態が変化することにより、ノードＶＩＯの電圧が変化する。 The switches SW1O to SW6O have a first terminal S1, a second terminal S2, and a third terminal D. The first terminals S1 of the switches SW1O to SW6O are connected to the reference voltage VREF. The second terminals S2 of the switches SW1O to SW6O are connected to the ground GND. The third terminals D of the switches SW1O to SW6O are connected to the second electrodes of the capacitors C1O to C6O. The states of the switches SW1O to SW6O switch between the first state and the second state. When the switches SW1O to SW6O are in the first state, the first terminals S1 of the switches SW1O to SW6O are electrically connected to the third terminals D of the switches SW1O to SW6O. At this time, the capacitors C1O to C6O are connected to the reference voltage VREF. When the switches SW1O to SW6O are in the second state, the second terminals S2 of the switches SW1O to SW6O and the third terminals D of the switches SW1O to SW6O are electrically connected. At this time, the capacitors C1O to C6O are connected to the ground GND. The states of the switches SW1O to SW6O are controlled by bits DO1 to DO6 of the AD conversion result. When the bits DO1 to DO6 are "H", the switches SW1O to SW6O are in the first state. When the bits DO1 to DO6 are "L", the switches SW1O to SW6O are in the second state. By changing the connection state of the switches SW1O to SW6O in a state where charges are stored in the capacitors C1O to C6O, the voltage of the node VIO changes.
　容量Ｃ１Ｏ～Ｃ６Ｏは、第１の電極および第２の電極を有する。容量Ｃ１Ｏ～Ｃ６Ｏの第１の電極は、ノードＶＩＯに接続されている。容量Ｃ１Ｏ～Ｃ６Ｏの第２の電極は、スイッチＳＷ１Ｐ～ＳＷ６Ｐの第３の端子Ｄに接続されている。容量Ｃ１Ｏ～Ｃ６Ｏは、サンプルスイッチＳＷＳＭＰＬＯによってサンプリングされた映像信号ＶＳＩＧ１を保持する。 The capacitors C1O to C6O have a first electrode and a second electrode. The first electrodes of the capacitors C1O to C6O are connected to the node VIO. The second electrodes of the capacitors C1O to C6O are connected to the third terminal D of the switches SW1P to SW6P. The capacitors C1O to C6O hold the video signal VSIG1 sampled by the sample switch SWSMPLO.
　サンプルスイッチＳＷＳＭＰＬＣは、第１の端子および第２の端子を有する。サンプルスイッチＳＷＳＭＰＬＣの第１の端子は、基準信号源ＶＣＭ＿Ｇに接続されている。サンプルスイッチＳＷＳＭＰＬＣの第２の端子は、ノードＶＩＣに接続されている。サンプルスイッチＳＷＳＭＰＬＣの状態は、オンとオフとの間で切り替わる。サンプルスイッチＳＷＳＭＰＬＣがオンであるとき、サンプルスイッチＳＷＳＭＰＬＣの第１の端子と第２の端子とが電気的に接続される。このとき、基準信号源ＶＣＭ＿Ｇからの基準信号ＶＣＭがノードＶＩＣに入力される。サンプルスイッチＳＷＳＭＰＬＣがオフであるとき、サンプルスイッチＳＷＳＭＰＬＣの第１の端子と第２の端子とが高インピーダンス状態になる。サンプルスイッチＳＷＳＭＰＬＣの状態は、制御信号ＳＭＰＬＣによって制御される。制御信号ＳＭＰＬＣが“Ｈ”である場合、サンプルスイッチＳＷＳＭＰＬＣはオンである。制御信号ＳＭＰＬＣが“Ｌ”である場合、サンプルスイッチＳＷＳＭＰＬＣはオフである。 The sample switch SWSMPLC has a first terminal and a second terminal. The first terminal of the sample switch SWSMPLC is connected to the reference signal source VCM_G. The second terminal of the sample switch SWSMPLC is connected to the node VIC. The state of the sample switch SWSMPLC switches between on and off. When the sample switch SWSMPLC is on, the first terminal and the second terminal of the sample switch SWSMPLC are electrically connected. At this time, the reference signal VCM from the reference signal source VCM_G is input to the node VIC. When the sample switch SWSMPLC is off, the first and second terminals of the sample switch SWSMPLC are in a high impedance state. The state of the sample switch SWSMPLC is controlled by the control signal SMPLC. When the control signal SMPLC is “H”, the sample switch SWSMPLC is on. When the control signal SMPLC is “L”, the sample switch SWSMPLC is off.
　容量Ｃ１Ｃ～Ｃ６Ｃは、第１の電極および第２の電極を有する。容量Ｃ１Ｃ～Ｃ６Ｃの第１の電極は、ノードＶＩＣに接続されている。容量Ｃ１Ｃ～Ｃ６Ｃの第２の電極は、グランドＧＮＤに接続されている。容量Ｃ１Ｃ～Ｃ６Ｃは、サンプルスイッチＳＷＳＭＰＬＣによってサンプリングされた基準信号ＶＣＭを保持する。 The capacitors C1C to C6C have a first electrode and a second electrode. The first electrodes of the capacitors C1C to C6C are connected to the node VIC. The second electrodes of the capacitors C1C to C6C are connected to the ground GND. The capacitors C1C to C6C hold the reference signal VCM sampled by the sample switch SWSMPLC.
　容量Ｃ１Ｏ～Ｃ６Ｏおよび容量Ｃ１Ｃ～Ｃ６Ｃの容量値は重み付けされている。説明の便宜のため、各容量の容量値は各容量の符号で表される。各容量の容量値は、式（１）により示される。
　Ｃ１Ｏ＝Ｃ１Ｃ＝Ｃｕ、Ｃ２Ｏ＝Ｃ２Ｃ＝Ｃｕ、Ｃ３Ｏ＝Ｃ３Ｃ＝２Ｃｕ（２（２－１）Ｃｕ）、・・・、Ｃ６Ｏ＝Ｃ６Ｃ＝１６Ｃｕ（２（５－１）Ｃｕ）　　・・・（１） The capacitance values of the capacitors C1O to C6O and the capacitors C1C to C6C are weighted. For convenience of description, the capacitance value of each capacitance is represented by the sign of each capacitance. The capacitance value of each capacitance is shown by equation (1).
C1O = C1C = Cu, C2O = C2C = Cu, C3O = C3C = 2Cu (2 (2-1) Cu), ..., C6O = C6 C = 16 Cu (2 (5-1) Cu) (1 )
　容量Ｃ１Ｏおよび容量Ｃ１Ｃは、ダミー容量としての性質を有する容量である。容量Ｃ１Ｏおよび容量Ｃ１Ｃは、ＤＡＣ回路ＣＤＡＣＯおよび容量アレーＣＤＡＣＣの各々における容量の合計値Ｃを式（２）のように２５Ｃｕにするために必要である。
　Ｃ＝Ｃｕ＋２０Ｃｕ＋２１Ｃｕ＋２２Ｃｕ＋・・＋２４Ｃｕ　　・・・（２） The capacitance C1O and the capacitance C1C are capacitances having properties as dummy capacitances. The capacitance C1O and the capacitance C1C are necessary to make the total value C of capacitances in each of the DAC circuit CDACO and the capacitance array CDACC into 25 Cu as in equation (2).
C = Cu + 2 0 Cu + 2 1 Cu + 2 2 Cu + · · · 2 4 Cu (2)
　ダミー容量としての性質を有する容量Ｃ１Ｏおよび容量Ｃ１ＣはＡＤ変換器ＡＤＣの構成に必須の要件ではない。しかし、容量Ｃ１Ｏおよび容量Ｃ１Ｃは、後述する説明を簡潔にするため、および実際の設計において高精度なＡＤ変換器を実現するためには必要な要素である。このため、本発明の各実施形態において、容量Ｃ１Ｏおよび容量Ｃ１Ｃを敢えて記載している。 The capacitance C1O and the capacitance C1C having a nature as a dummy capacitance are not essential requirements for the configuration of the AD converter ADC. However, the capacitances C1O and C1C are necessary elements to simplify the description to be described later and to realize a high accuracy AD converter in an actual design. Therefore, in each embodiment of the present invention, the capacitance C1O and the capacitance C1C are described purposefully.
　ＤＡＣ回路ＣＤＡＣＯは、信号源ＳＩＧ＿ＯＤＤに接続されている。容量アレーＣＤＡＣＣは、基準信号源ＶＣＭ＿Ｇに接続されている。信号源ＳＩＧ＿ＯＤＤによって生成された映像信号ＶＳＩＧ１は、ノードＶＩＯに供給される。基準信号源ＶＣＭ＿Ｇによって生成された基準信号ＶＣＭは、ノードＶＩＣに供給される。 The DAC circuit CDACO is connected to the signal source SIG_ODD. The capacitance array CDACC is connected to the reference signal source VCM_G. The video signal VSIG1 generated by the signal source SIG_ODD is supplied to the node VIO. The reference signal VCM generated by the reference signal source VCM_G is supplied to the node VIC.
　チャージサミングノードであるノードＶＩＯは、サンプルスイッチＳＷＳＭＰＬＯの第２の端子と、容量Ｃ１Ｏ～Ｃ６Ｏの第１の電極と、比較器ＣＭＰＯの第１の入力端子とに接続されている。ノードＶＩＯは、これらに電気的に接続された信号線上の任意の位置である。チャージサミングノードであるノードＶＩＣは、サンプルスイッチＳＷＳＭＰＬＣの第２の端子と、容量Ｃ１Ｃ～Ｃ６Ｃの第１の電極と、比較器ＣＭＰＯの第２の入力端子とに接続されている。ノードＶＩＣは、これらに電気的に接続された信号線上の任意の位置である。 The node VIO which is a charge summing node is connected to the second terminal of the sample switch SWSMPLO, the first electrodes of the capacitors C1O to C6O, and the first input terminal of the comparator CMPO. The node VIO is an arbitrary position on the signal line electrically connected to them. The node VIC, which is a charge summing node, is connected to the second terminal of the sample switch SWSMPLC, the first electrodes of the capacitors C1C to C6C, and the second input terminal of the comparator CMPO. The node VIC is an arbitrary position on a signal line electrically connected to them.
　比較器ＣＭＰＯは、第１の入力端子（非反転入力端子）と、第２の入力端子（反転入力端子）と、第１の出力端子（反転出力端子）と、第２の出力端子（非反転出力端子）とを有する。比較器ＣＭＰＯの第１の入力端子は、ノードＶＩＯに接続されている。映像信号ＶＳＩＧ１に基づく電圧が比較器ＣＭＰＯの第１の入力端子に入力される。比較器ＣＭＰＯの第２の入力端子は、ノードＶＩＣに接続されている。基準信号ＶＣＭに基づく電圧が比較器ＣＭＰＯの第２の入力端子に入力される。比較器ＣＭＰＯの第１の出力端子および第２の出力端子は、制御回路ＳＡＲＬＯＧＩＣＯに接続されている。比較器ＣＭＰＯは、ノードＶＩＯの電圧とノードＶＩＣの電圧とを比較する。比較器ＣＭＰＯは、比較結果に基づく信号ＶＯＮＯを第１の出力端子から出力し、かつ比較結果に基づく信号ＶＯＰＯを第２の出力端子から出力する。 The comparator CMPO has a first input terminal (non-inverted input terminal), a second input terminal (inverted input terminal), a first output terminal (inverted output terminal), and a second output terminal (non-inverted And an output terminal). The first input terminal of the comparator CMPO is connected to the node VIO. A voltage based on the video signal VSIG1 is input to a first input terminal of the comparator CMPO. The second input terminal of the comparator CMPO is connected to the node VIC. A voltage based on the reference signal VCM is input to a second input terminal of the comparator CMPO. The first output terminal and the second output terminal of the comparator CMPO are connected to the control circuit SARLOGICO. The comparator CMPO compares the voltage of the node VIO with the voltage of the node VIC. The comparator CMPO outputs a signal VONO based on the comparison result from the first output terminal, and outputs a signal VOPO based on the comparison result from the second output terminal.
　制御回路ＳＡＲＬＯＧＩＣＯは、第１の入力端子と、第２の入力端子と、出力端子とを有する。制御回路ＳＡＲＬＯＧＩＣＯの第１の入力端子は比較器ＣＭＰＯの第１の出力端子に接続されている。制御回路ＳＡＲＬＯＧＩＣＯの第２の入力端子は比較器ＣＭＰＯの第２の出力端子に接続されている。信号ＶＯＮＯが制御回路ＳＡＲＬＯＧＩＣＯの第１の入力端子に入力され、かつ信号ＶＯＰＯが制御回路ＳＡＲＬＯＧＩＣＯの第２の入力端子に入力される。制御回路ＳＡＲＬＯＧＩＣＯは、比較器ＣＭＰＯからの信号ＶＯＰＯおよび信号ＶＯＮＯに基づいてＡＤ変換結果のデジタル信号ＤＯ［６：１］を生成し、かつデジタル信号ＤＯ［６：１］を出力端子から出力する。ＡＤ変換器ＡＤＣは、６ビット出力のＡＤ変換器であるが、この例に限らない。ＡＤ変換器ＡＤＣの出力ビット数は、任意に設定され得る。 The control circuit SARLOGICO has a first input terminal, a second input terminal, and an output terminal. A first input of the control circuit SARLOGICO is connected to a first output of the comparator CMPO. The second input terminal of the control circuit SARLOGICO is connected to the second output terminal of the comparator CMPO. The signal VONO is input to a first input terminal of the control circuit SARLOGICO, and the signal VOPO is input to a second input terminal of the control circuit SARLOGICO. The control circuit SARLOGICO generates the digital signal DO [6: 1] of the AD conversion result based on the signal VOPO and the signal VONO from the comparator CMPO, and outputs the digital signal DO [6: 1] from the output terminal. The AD converter ADC is a 6-bit output AD converter, but is not limited to this example. The number of output bits of the AD converter ADC can be set arbitrarily.
　デジタル信号ＤＯ［６：１］を構成するビットＤＯ１～ＤＯ６は、ＤＡＣ回路ＣＤＡＣＯのスイッチＳＷ１Ｏ～ＳＷ６Ｏに出力される。制御回路ＳＡＲＬＯＧＩＣＯは、ビットＤＯ１～ＤＯ６をスイッチＳＷ１Ｏ～ＳＷ６Ｏに出力することにより、ＤＡＣ回路ＣＤＡＣＯを制御する。 The bits DO1 to DO6 constituting the digital signal DO [6: 1] are output to the switches SW1O to SW6O of the DAC circuit CDACO. The control circuit SARLOGICO controls the DAC circuit CDACO by outputting the bits DO1 to DO6 to the switches SW1O to SW6O.
　ＤＡＣ回路ＣＤＡＣＯが有する複数の容量Ｃ１Ｏ～Ｃ６Ｏの容量値の合計と、複数の容量Ｃ１Ｃ～Ｃ６Ｃの容量値の合計とは、同一であることが望ましい。しかし、通常、容量値にはばらつきが生じる。一般的に、容量値の絶対値のばらつきは、公称値の１０％から３０％である。例えば、容量値の絶対値のばらつきが公称値の１０％である場合、容量Ｃ１Ｏ～Ｃ６Ｏの容量値の合計および容量Ｃ１Ｃ～Ｃ６Ｃの容量値の合計は、０．９Ｃｏから１．１Ｃｏの範囲内である。Ｃｏは、容量Ｃ１Ｏ～Ｃ６Ｏの容量値の公称値の合計かつ容量Ｃ１Ｃ～Ｃ６Ｃの容量値の公称値の合計である。このため、容量Ｃ１Ｏ～Ｃ６Ｏの容量値の合計と容量Ｃ１Ｃ～Ｃ６Ｃの容量値の合計との比は、０．８（＝０．９Ｃｏ／１．１Ｃｏ）から１．２（＝１．１Ｃｏ／０．９Ｃｏ）の範囲内である。したがって、その比がこの範囲内である場合、容量Ｃ１Ｏ～Ｃ６Ｏの容量値の合計および容量Ｃ１Ｃ～Ｃ６Ｃの容量値の合計は略同一であるとみなせる。 It is desirable that the sum of the capacitance values of the plurality of capacitors C1O to C6O of the DAC circuit CDACO be equal to the sum of the capacitance values of the plurality of capacitors C1C to C6C. However, usually, the capacitance value varies. Generally, the variation of the absolute value of the capacitance value is 10% to 30% of the nominal value. For example, if the variation of the absolute value of the capacitance value is 10% of the nominal value, the sum of the capacitance values of the capacitances C1O to C6O and the sum of the capacitance values of the capacitances C1C to C6C are within the range of 0.9 Co to 1.1 Co It is. Co is the sum of the nominal values of the capacitance values of the capacitances C1O to C6O and the sum of the nominal values of the capacitance values of the capacitances C1C to C6C. Therefore, the ratio of the sum of capacitance values of capacitances C1O to C6O to the sum of capacitance values of capacitances C1C to C6C is 0.8 (= 0.9Co / 1.1Co) to 1.2 (= 1.1Co / Within the range of 0.9 Co). Therefore, when the ratio is within this range, the sum of capacitance values of capacitances C1O to C6O and the sum of capacitance values of capacitances C1C to C6C can be regarded as substantially the same.
　図２は、比較器ＣＭＰＯの構成を示す。図２に示すように、比較器ＣＭＰＯは、差動増幅回路Ａ１およびラッチ回路Ｌ１を有する。 FIG. 2 shows the configuration of the comparator CMPO. As shown in FIG. 2, the comparator CMPO has a differential amplifier circuit A1 and a latch circuit L1.
　差動増幅回路Ａ１は、トランジスタＭ１と、トランジスタＭ２と、トランジスタＭ３と、トランジスタＭ４と、トランジスタＭ５とを有する。トランジスタＭ１と、トランジスタＭ２と、トランジスタＭ５とは、Ｎチャネル型の電界効果トランジスタである。トランジスタＭ３と、トランジスタＭ４とは、Ｐチャネル型の電界効果トランジスタである。差動増幅回路Ａ１の増幅機能を得ることができるという条件で、差動増幅回路Ａ１を構成する各トランジスタの種類は任意に選択され得る。 The differential amplifier circuit A1 includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, and a transistor M5. The transistor M1, the transistor M2, and the transistor M5 are N-channel field effect transistors. The transistor M3 and the transistor M4 are P-channel field effect transistors. Under the condition that the amplification function of the differential amplifier circuit A1 can be obtained, the types of the transistors constituting the differential amplifier circuit A1 can be arbitrarily selected.
　トランジスタＭ１のゲート端子は、第１の入力端子に接続されている。トランジスタＭ２のゲート端子は、第２の入力端子に接続されている。信号ＶＩＯがＤＡＣ回路ＣＤＡＣＯから第１の入力端子を介してトランジスタＭ１のゲート端子に入力される。信号ＶＩＯは、ノードＶＩＯの電圧に応じた信号である。信号ＶＩＣが容量アレーＣＤＡＣＣから第２の入力端子を介してトランジスタＭ２のゲート端子に入力される。信号ＶＩＣは、ノードＶＩＣの電圧に応じた信号である。 The gate terminal of the transistor M1 is connected to the first input terminal. The gate terminal of the transistor M2 is connected to the second input terminal. The signal VIO is input from the DAC circuit CDACO to the gate terminal of the transistor M1 via the first input terminal. Signal VIO is a signal corresponding to the voltage of node VIO. The signal VIC is input from the capacitance array CDACC to the gate terminal of the transistor M2 via the second input terminal. Signal VIC is a signal according to the voltage of node VIC.
　トランジスタＭ３のソース端子は、電源電圧ＶＤＤを出力する電源に接続されている。トランジスタＭ３のドレイン端子は、トランジスタＭ１のドレイン端子に接続されている。トランジスタＭ４のソース端子は、電源電圧ＶＤＤを出力する電源に接続されている。トランジスタＭ４のドレイン端子は、トランジスタＭ２のドレイン端子に接続されている。トランジスタＭ４のゲート端子は、トランジスタＭ３のゲート端子に接続されている。内部クロック信号ＢＩＴ＿ＣＬＫがトランジスタＭ３のゲート端子およびトランジスタＭ４のゲート端子に入力される。 The source terminal of the transistor M3 is connected to the power supply that outputs the power supply voltage VDD. The drain terminal of the transistor M3 is connected to the drain terminal of the transistor M1. The source terminal of the transistor M4 is connected to the power supply that outputs the power supply voltage VDD. The drain terminal of the transistor M4 is connected to the drain terminal of the transistor M2. The gate terminal of the transistor M4 is connected to the gate terminal of the transistor M3. The internal clock signal BIT_CLK is input to the gate terminal of the transistor M3 and the gate terminal of the transistor M4.
　トランジスタＭ５のソース端子は、グランドＧＮＤに接続されている。グランドＧＮＤは、最低電圧を与える。トランジスタＭ５のドレイン端子は、トランジスタＭ１のソース端子およびトランジスタＭ２のソース端子に接続されている。内部クロック信号ＢＩＴ＿ＣＬＫがトランジスタＭ５のゲート端子に入力される。 The source terminal of the transistor M5 is connected to the ground GND. The ground GND provides the lowest voltage. The drain terminal of the transistor M5 is connected to the source terminal of the transistor M1 and the source terminal of the transistor M2. The internal clock signal BIT_CLK is input to the gate terminal of the transistor M5.
　ラッチ回路Ｌ１は、トランジスタＭ７と、トランジスタＭ８と、トランジスタＭ９と、トランジスタＭ１０と、トランジスタＭ１１と、トランジスタＭ１２と、トランジスタＭ１３と、トランジスタＭ１４とを有する。トランジスタＭ１１と、トランジスタＭ１２と、トランジスタＭ１３と、トランジスタＭ１４とは、Ｎチャネル型の電界効果トランジスタである。トランジスタＭ７と、トランジスタＭ８と、トランジスタＭ９と、トランジスタＭ１０とは、Ｐチャネル型の電界効果トランジスタである。ラッチ回路Ｌ１のラッチ機能を得ることができるという条件で、ラッチ回路Ｌ１を構成する各トランジスタの種類は任意に選択され得る。 The latch circuit L1 includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, a transistor M13, and a transistor M14. The transistor M11, the transistor M12, the transistor M13, and the transistor M14 are N-channel field effect transistors. The transistor M7, the transistor M8, the transistor M9, and the transistor M10 are P-channel field effect transistors. Under the condition that the latch function of the latch circuit L1 can be obtained, the type of each transistor constituting the latch circuit L1 can be arbitrarily selected.
　トランジスタＭ７のゲート端子は、トランジスタＭ２のドレイン端子に接続されている。差動増幅回路Ａ１から出力された信号ＡＰがトランジスタＭ７のゲート端子に入力される。トランジスタＭ８のゲート端子は、トランジスタＭ１のドレイン端子に接続されている。差動増幅回路Ａ１から出力された信号ＡＮがトランジスタＭ８のゲート端子に入力される。 The gate terminal of the transistor M7 is connected to the drain terminal of the transistor M2. The signal AP output from the differential amplifier circuit A1 is input to the gate terminal of the transistor M7. The gate terminal of the transistor M8 is connected to the drain terminal of the transistor M1. The signal AN output from the differential amplifier circuit A1 is input to the gate terminal of the transistor M8.
　トランジスタＭ９のソース端子は、電源電圧ＶＤＤを出力する電源に接続されている。トランジスタＭ９のドレイン端子は、トランジスタＭ７のソース端子に接続されている。トランジスタＭ１０のソース端子は、電源電圧ＶＤＤを出力する電源に接続されている。トランジスタＭ１０のドレイン端子は、トランジスタＭ８のソース端子に接続されている。 The source terminal of the transistor M9 is connected to the power supply that outputs the power supply voltage VDD. The drain terminal of the transistor M9 is connected to the source terminal of the transistor M7. The source terminal of the transistor M10 is connected to the power supply that outputs the power supply voltage VDD. The drain terminal of the transistor M10 is connected to the source terminal of the transistor M8.
　トランジスタＭ１１のソース端子は、グランドＧＮＤに接続されている。トランジスタＭ１１のドレイン端子は、トランジスタＭ７のドレイン端子と、トランジスタＭ１０のゲート端子と、トランジスタＭ１２のゲート端子と、トランジスタＭ１３のドレイン端子とに接続されている。トランジスタＭ１１のゲート端子は、トランジスタＭ９のゲート端子と、トランジスタＭ８のドレイン端子と、トランジスタＭ１２のドレイン端子と、トランジスタＭ１４のドレイン端子とに接続されている。トランジスタＭ１２のソース端子は、グランドＧＮＤに接続されている。トランジスタＭ１２のドレイン端子は、トランジスタＭ８のドレイン端子と、トランジスタＭ９のゲート端子と、トランジスタＭ１１のゲート端子と、トランジスタＭ１４のドレイン端子とに接続されている。トランジスタＭ１２のゲート端子は、トランジスタＭ１０のゲート端子と、トランジスタＭ７のドレイン端子と、トランジスタＭ１１のドレイン端子と、トランジスタＭ１３のドレイン端子とに接続されている。 The source terminal of the transistor M11 is connected to the ground GND. The drain terminal of the transistor M11 is connected to the drain terminal of the transistor M7, the gate terminal of the transistor M10, the gate terminal of the transistor M12, and the drain terminal of the transistor M13. The gate terminal of the transistor M11 is connected to the gate terminal of the transistor M9, the drain terminal of the transistor M8, the drain terminal of the transistor M12, and the drain terminal of the transistor M14. The source terminal of the transistor M12 is connected to the ground GND. The drain terminal of the transistor M12 is connected to the drain terminal of the transistor M8, the gate terminal of the transistor M9, the gate terminal of the transistor M11, and the drain terminal of the transistor M14. The gate terminal of the transistor M12 is connected to the gate terminal of the transistor M10, the drain terminal of the transistor M7, the drain terminal of the transistor M11, and the drain terminal of the transistor M13.
　トランジスタＭ１３のソース端子は、グランドＧＮＤに接続されている。トランジスタＭ１３のドレイン端子は、トランジスタＭ１１のドレイン端子と、トランジスタＭ７のドレイン端子と、トランジスタＭ１０のゲート端子と、トランジスタＭ１２のゲート端子とに接続されている。反転内部クロック信号ＢＩＴ＿ＣＬＫｂがトランジスタＭ１３のゲート端子に入力される。トランジスタＭ１４のソース端子は、グランドＧＮＤに接続されている。トランジスタＭ１４のドレイン端子は、トランジスタＭ８のドレイン端子と、トランジスタＭ１２のドレイン端子と、トランジスタＭ９のゲート端子と、トランジスタＭ１１のゲート端子とに接続されている。反転内部クロック信号ＢＩＴ＿ＣＬＫｂがトランジスタＭ１４のゲート端子に入力される。 The source terminal of the transistor M13 is connected to the ground GND. The drain terminal of the transistor M13 is connected to the drain terminal of the transistor M11, the drain terminal of the transistor M7, the gate terminal of the transistor M10, and the gate terminal of the transistor M12. The inverted internal clock signal BIT_CLKb is input to the gate terminal of the transistor M13. The source terminal of the transistor M14 is connected to the ground GND. The drain terminal of the transistor M14 is connected to the drain terminal of the transistor M8, the drain terminal of the transistor M12, the gate terminal of the transistor M9, and the gate terminal of the transistor M11. The inverted internal clock signal BIT_CLKb is input to the gate terminal of the transistor M14.
　トランジスタＭ１４のドレイン端子は、第１の出力端子に接続されている。トランジスタＭ１３のドレイン端子は、第２の出力端子に接続されている。信号ＶＯＰＯが第１の出力端子から出力され、かつ信号ＶＯＮＯが第２の出力端子から出力される。 The drain terminal of the transistor M14 is connected to the first output terminal. The drain terminal of the transistor M13 is connected to the second output terminal. The signal VOPO is output from the first output terminal and the signal VONO is output from the second output terminal.
　比較器ＣＭＰＯの基本動作について説明する。内部クロック信号ＢＩＴ＿ＣＬＫおよび反転内部クロック信号ＢＩＴ＿ＣＬＫｂは、図示していない制御回路から比較器ＣＭＰＯに供給される。比較器ＣＭＰＯがノードＶＩＯおよびノードＶＩＣの電圧を比較する期間において、内部クロック信号ＢＩＴ＿ＣＬＫはハイレベルになる。 The basic operation of the comparator CMPO will be described. Internal clock signal BIT_CLK and inverted internal clock signal BIT_CLKb are supplied from a control circuit (not shown) to comparator CMPO. In a period in which comparator CMPO compares the voltages of node VIO and node VIC, internal clock signal BIT_CLK goes high.
　先ず、内部クロック信号ＢＩＴ＿ＣＬＫがローレベルである場合の動作について説明する。内部クロック信号ＢＩＴ＿ＣＬＫがローレベルであるとき、反転内部クロック信号ＢＩＴ＿ＣＬＫｂはハイレベルである。このため、差動増幅回路Ａ１のトランジスタＭ５はオフになり、かつトランジスタＭ３およびトランジスタＭ４はオンになる。ラッチ回路Ｌ１のトランジスタＭ１３およびトランジスタＭ１４はオンになる。 First, the operation when the internal clock signal BIT_CLK is at low level will be described. When the internal clock signal BIT_CLK is at a low level, the inverted internal clock signal BIT_CLKb is at a high level. Therefore, the transistor M5 of the differential amplifier circuit A1 is turned off, and the transistors M3 and M4 are turned on. The transistor M13 and the transistor M14 of the latch circuit L1 are turned on.
　この場合、信号ＡＮおよび信号ＡＰの電位は、電源電圧ＶＤＤに引き上げられる。信号ＡＮおよび信号ＡＰはトランジスタＭ７およびトランジスタＭ８のゲート端子に入力されるため、トランジスタＭ７およびトランジスタＭ８はオフになる。一方、トランジスタＭ１３およびトランジスタＭ１４はオンになる。信号ＶＯＰＯおよび信号ＶＯＮＯの電位は、トランジスタＭ１３およびトランジスタＭ１４を介してグランドＧＮＤに引き下げられる。 In this case, the potentials of the signal AN and the signal AP are raised to the power supply voltage VDD. Since the signals AN and AP are input to the gate terminals of the transistors M7 and M8, the transistors M7 and M8 are turned off. On the other hand, the transistor M13 and the transistor M14 are turned on. The potentials of the signals VOPO and VONO are pulled down to the ground GND via the transistors M13 and M14.
　信号ＶＩＯが信号ＶＩＣよりも大きい状態（ＶＩＯ＞ＶＩＣ）で、内部クロック信号ＢＩＴ＿ＣＬＫがローレベルからハイレベルに切り替わった場合の動作について説明する。 The operation when the internal clock signal BIT_CLK is switched from the low level to the high level in a state where the signal VIO is larger than the signal VIC (VIO> VIC) will be described.
　内部クロック信号ＢＩＴ＿ＣＬＫがローレベルからハイレベルに切り替わることにより、差動増幅回路Ａ１において、トランジスタＭ５はオンになる。このため、トランジスタＭ５にドレイン電流が流れる。トランジスタＭ３およびトランジスタＭ４はオフになる。トランジスタＭ１は、トランジスタＭ１のドレイン端子のノードＮＡＮに結合されている寄生容量から電荷を引き抜く。トランジスタＭ２は、トランジスタＭ２のドレイン端子のノードＮＡＰに結合されている寄生容量から電荷を引き抜く。 In the differential amplifier circuit A1, the transistor M5 is turned on by switching the internal clock signal BIT_CLK from the low level to the high level. Therefore, a drain current flows to the transistor M5. The transistor M3 and the transistor M4 are turned off. Transistor M1 draws charge from the parasitic capacitance coupled to node NAN at the drain terminal of transistor M1. Transistor M2 draws charge from the parasitic capacitance coupled to node NAP at the drain terminal of transistor M2.
　トランジスタＭ１およびトランジスタＭ２が上記の寄生容量から電荷を引き抜く過程で、信号ＶＩＯと信号ＶＩＣとの電位の違いにより、寄生容量から電荷が引き抜かれる速度に違いが生じる。信号ＶＩＯが信号ＶＩＣよりも大きい場合、（ＶＩＯ＞ＶＩＣ）、トランジスタＭ１に流れる電流は、トランジスタＭ２に流れる電流よりも大きい。その結果、信号ＡＮの電位は、信号ＡＰの電位よりも高速に低下する。 In the process in which the transistor M1 and the transistor M2 draw charge from the parasitic capacitance, the difference in potential between the signal VIO and the signal VIC causes a difference in the speed at which charge is drawn from the parasitic capacitance. When the signal VIO is larger than the signal VIC (VIO> VIC), the current flowing through the transistor M1 is larger than the current flowing through the transistor M2. As a result, the potential of the signal AN falls faster than the potential of the signal AP.
　内部クロック信号ＢＩＴ＿ＣＬＫがローレベルからハイレベルに変化し、かつ反転内部クロック信号ＢＩＴ＿ＣＬＫｂがハイレベルからローレベルに変化する。これにより、ラッチ回路Ｌ１において、信号ＶＯＰＯおよび信号ＶＯＮＯの電位は、電源電圧ＶＤＤに向かって上昇する。信号ＡＰの電位よりも信号ＡＮの電位の方が高速に低下するため、トランジスタＭ７よりもトランジスタＭ８の方が早くオンになる。このため、信号ＶＯＰＯの電位の上昇速度は、信号ＶＯＮＯの電位の上昇速度よりも大きくなる。その結果、信号ＶＯＰＯの電位は、電源電圧ＶＤＤに向かって引き上げられる。 Internal clock signal BIT_CLK changes from low level to high level, and inverted internal clock signal BIT_CLKb changes from high level to low level. Thus, in the latch circuit L1, the potentials of the signal VOPO and the signal VONO rise toward the power supply voltage VDD. Since the potential of the signal AN drops faster than the potential of the signal AP, the transistor M8 turns on earlier than the transistor M7. Therefore, the rising speed of the potential of the signal VOPO is higher than the rising speed of the potential of the signal VONO. As a result, the potential of the signal VOPO is pulled up toward the power supply voltage VDD.
　トランジスタＭ７，Ｍ９，Ｍ１１によって形成されるインバータと、トランジスタＭ８，Ｍ１０，Ｍ１２によって形成されるインバータとがクロスカップル接続されている。この場合、信号ＶＯＰＯがゲート端子に印加されるトランジスタＭ９はオフになる。このため、信号ＶＯＮＯは、グランドＧＮＤに向かって引き下げられる。したがって、信号ＶＩＯと信号ＶＩＣとの間の大きさの関係に応じた論理レベルを有する信号ＶＯＰＯおよび信号ＶＯＮＯが比較器ＣＭＰＯから出力される。 The inverter formed by the transistors M7, M9, and M11 is cross-coupled to the inverter formed by the transistors M8, M10, and M12. In this case, the transistor M9 in which the signal VOPO is applied to the gate terminal is turned off. Thus, the signal VONO is pulled down to the ground GND. Therefore, signal VOPO and signal VONO having logic levels according to the magnitude relationship between signal VIO and signal VIC are output from comparator CMPO.
　具体的には、信号ＶＩＯが信号ＶＩＣよりも大きい場合（ＶＩＯ＞ＶＩＣ）、信号ＶＯＰＯの電位は、電源電圧ＶＤＤの電位になり、かつ信号ＶＯＮＯの電位は、グランドＧＮＤの電位になる。信号ＶＩＣが信号ＶＩＯよりも大きい場合（ＶＩＣ＞ＶＩＯ）、信号ＶＯＮＯの電位は、電源電圧ＶＤＤの電位になり、かつ信号ＶＯＰＯの電位は、グランドＧＮＤの電位になる。このように、比較器ＣＭＰＯは、信号ＶＩＯと信号ＶＩＣとの間の大きさの関係を示す２値の信号ＶＯＰＯおよび信号ＶＯＮＯを出力する。 Specifically, when signal VIO is larger than signal VIC (VIO> VIC), the potential of signal VOPO is the potential of power supply voltage VDD, and the potential of signal VONO is the potential of ground GND. When the signal VIC is larger than the signal VIO (VIC> VIO), the potential of the signal VONO becomes the potential of the power supply voltage VDD, and the potential of the signal VOPO becomes the potential of the ground GND. Thus, the comparator CMPO outputs a binary signal VOPO and a signal VONO indicating the magnitude relationship between the signal VIO and the signal VIC.
　比較器ＣＭＰＯはダイナミックコンパレータである。比較器ＣＭＰＯにおいて、動作電流として、ＣＭＯＳロジックと同様に、状態変化による貫通電流のみが流れる。つまり、比較器ＣＭＰＯにおいて、内部クロック信号ＢＩＴ＿ＣＬＫおよび反転内部クロック信号ＢＩＴ＿ＣＬＫｂの信号レベルがハイレベルからローレベルまたはローレベルからハイレベルに遷移するときのみに過渡的に電流が流れ、かつ定常電流（アイドリング電流）が発生しない。このため、比較器ＣＭＰＯは、低消費電力化に適している。 The comparator CMPO is a dynamic comparator. In the comparator CMPO, only a through current due to a state change flows as an operating current, as in the CMOS logic. That is, in comparator CMPO, current flows transiently only when the signal levels of internal clock signal BIT_CLK and inverted internal clock signal BIT_CLKb transition from high level to low level or low level to high level, and steady current (idle Current does not occur. Therefore, the comparator CMPO is suitable for reducing power consumption.
　図３を用いてＡＤ変換器ＡＤＣの動作について説明する。図３は、ＡＤ変換器ＡＤＣの動作に関する信号を示す。図３において、ＤＡＣ回路ＣＤＡＣＯの状態が示されている。図３において、制御信号ＳＭＰＬＯおよび制御信号ＳＭＰＬＣが示されている。図３において、デジタル信号ＤＯ［６：１］が１６進数で示されている。図３において、ノードＶＩＯおよびノードＶＩＣの各々の電圧が示されている。図３において、横軸は時間を示し、かつ縦軸は信号レベルを示す。 The operation of the AD converter ADC will be described with reference to FIG. FIG. 3 shows signals relating to the operation of the AD converter ADC. In FIG. 3, the state of the DAC circuit CDACO is shown. In FIG. 3, the control signal SMPLO and the control signal SMPLC are shown. In FIG. 3, the digital signal DO [6: 1] is shown in hexadecimal. In FIG. 3, voltages of each of node VIO and node VIC are shown. In FIG. 3, the horizontal axis indicates time, and the vertical axis indicates signal level.
　期間Ｔ１から期間Ｔ７において、ＡＤ変換器ＡＤＣは、サンプリング動作ＳＡＭＰを行うことにより、ＤＡＣ回路ＣＤＡＣＯに入力される信号のサンプリングを行う。期間Ｔ１から期間Ｔ７において、スイッチＳＷＳＭＰＬＯがオンであるため、映像信号ＶＳＩＧ１が信号源ＳＩＧ＿ＯＤＤからノードＶＩＯに入力される。また、期間Ｔ１から期間Ｔ７において、スイッチＳＷＳＭＰＬＣがオンであるため、基準信号ＶＣＭが基準信号源ＶＣＭ＿ＧからノードＶＩＣに入力される。 In the period T1 to the period T7, the AD converter ADC performs sampling operation SAMP to sample the signal input to the DAC circuit CDACO. In the period T1 to the period T7, since the switch SWSMPLO is on, the video signal VSIG1 is input from the signal source SIG_ODD to the node VIO. Further, in the period T1 to the period T7, since the switch SWSMPLC is on, the reference signal VCM is input from the reference signal source VCM_G to the node VIC.
　期間Ｔ２から期間Ｔ７において、“Ｈ”であるビットＤＯ１～ＤＯ６がスイッチＳＷ１Ｏ～ＳＷ６Ｏに入力される。期間Ｔ２から期間Ｔ７において、スイッチＳＷ１Ｏ～ＳＷ６Ｏの各々の第１の端子Ｓ１と第３の端子Ｄとが接続される。期間Ｔ１から期間Ｔ７において、ノードＶＩＯの電圧は映像信号ＶＳＩＧ１の電圧に保たれ、かつノードＶＩＣの電圧は基準信号ＶＣＭの電圧に保たれる。期間Ｔ２から期間Ｔ７において、映像信号ＶＳＩＧ１に基づく電荷が容量Ｃ１Ｏ～Ｃ６Ｏに保持され、かつ基準信号ＶＣＭに基づく電荷が容量Ｃ１Ｃ～Ｃ６Ｃに保持される。 In the period T2 to the period T7, the bits DO1 to DO6 which are "H" are input to the switches SW1O to SW6O. In the period T2 to the period T7, the first terminal S1 and the third terminal D of each of the switches SW1O to SW6O are connected. In the period T1 to the period T7, the voltage of the node VIO is maintained at the voltage of the video signal VSIG1, and the voltage of the node VIC is maintained at the voltage of the reference signal VCM. In the periods T2 to T7, the charges based on the video signal VSIG1 are held in the capacitors C1O to C6O, and the charges based on the reference signal VCM are held in the capacitors C1C to C6C.
　期間Ｔ１’から期間Ｔ７’において、ＡＤ変換器ＡＤＣは、ＡＤ変換動作ＣＯＮＶを行うことにより、ＤＡＣ回路ＣＤＡＣＯにサンプリングされた信号のＡＤ変換を行う。期間Ｔ１’から期間Ｔ７’において、スイッチＳＷＳＭＰＬＯがオフであるため、ノードＶＩＯに対する、信号源ＳＩＧ＿ＯＤＤからの映像信号ＶＳＩＧ１の入力は停止される。また、期間Ｔ１’から期間Ｔ７’において、スイッチＳＷＳＭＰＬＣがオフであるため、ノードＶＩＣに対する、基準信号源ＶＣＭ＿Ｇからの基準信号ＶＣＭの入力は停止される。 In the period T1 'to the period T7', the AD converter ADC performs AD conversion operation CONV to perform AD conversion of the signal sampled in the DAC circuit CDACO. In the period T1 'to the period T7', since the switch SWSMPLO is off, the input of the video signal VSIG1 from the signal source SIG_ODD to the node VIO is stopped. Further, in the period T1 'to the period T7', the switch SWSMPLC is off, so the input of the reference signal VCM from the reference signal source VCM_G to the node VIC is stopped.
　期間Ｔ２’から期間Ｔ７’は、ＤＡＣ回路ＣＤＡＣＯに保持された電荷に基づいてＡＤ変換器ＡＤＣ（比較器ＣＭＰＯ）がＭＳＢからＬＳＢの比較を行うための期間に対応する。期間Ｔ２’において、比較器ＣＭＰＯはノードＶＩＯおよびノードＶＩＣの電圧を比較する。この比較により、ＡＤ変換結果の最上位ビットＤＯ６の論理が確定する。比較器ＣＭＰＯは、比較結果を制御回路ＳＡＲＬＯＧＩＣＯに出力する。期間Ｔ３’において、制御回路ＳＡＲＬＯＧＩＣＯは、期間Ｔ２’における比較結果に応じたビットＤＯ６を出力する。ビットＤＯ６に対する判定結果がＶＩＣ＜ＶＩＯである場合、ビットＤＯ６の論理レベルは“Ｌ”である。説明の便宜のため、ノードＶＩＯの電圧はＶＩＯと表され、かつノードＶＩＣの電圧はＶＩＣと表される。ビットＤＯ６に対する判定結果がＶＩＣ＞ＶＩＯである場合、ビットＤＯ６の論理レベルは“Ｈ”である。２番目以降のビットＤＯｉにおける判定結果がＶＩＣ＜ＶＩＯである場合、ビットＤＯｉの論理レベルは“Ｌ”に設定される。ビットＤＯｉにおける判定結果がＶＩＣ＞ＶＩＯである場合、ビットＤＯｉの論理レベルは“Ｌ”に設定され、かつ１つ前のビットＤＯ（ｉ＋１）の論理レベルが“Ｈ”に設定される。ｉは、１から５のいずれかの整数である。 The period T2 'to the period T7' correspond to a period for the AD converter ADC (comparator CMPO) to compare MSB to LSB based on the charge held in the DAC circuit CDACO. In period T2 ', comparator CMPO compares the voltages of node VIO and node VIC. By this comparison, the logic of the most significant bit DO6 of the AD conversion result is determined. The comparator CMPO outputs the comparison result to the control circuit SARLOGICO. In period T3 ', control circuit SARLOGICO outputs bit DO6 according to the comparison result in period T2'. When the determination result for bit DO6 is VIC <VIO, the logic level of bit DO6 is "L". For convenience of description, the voltage of the node VIO is represented as VIO, and the voltage of the node VIC is represented as VIC. When the determination result for bit DO6 is VIC> VIO, the logic level of bit DO6 is "H". When the determination result in the second and subsequent bits DOi is VIC <VIO, the logic level of bit DOi is set to “L”. If the determination result in bit DOi is VIC> VIO, the logic level of bit DOi is set to “L”, and the logic level of the immediately preceding bit DO (i + 1) is set to “H”. i is an integer of 1 to 5;
　図３に示す例の期間Ｔ２’において、ノードＶＩＯの電圧がノードＶＩＣの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＯは、ビットＤＯ６の論理を“Ｌ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＯ［６：１］は３Ｆ（１１１１１１）から１Ｆ（０１１１１１１）に変化する。期間Ｔ３’において、ビットＤＯ６の論理レベルは、スイッチＳＷＯ６に出力される。このため、スイッチＳＷＯ６は、第２の端子Ｓ２と第３の端子Ｄとが接続された状態に切り替わる。これにより、グランドレベルが容量Ｃ６Ｏの第２の電極に入力される。容量Ｃ１Ｏ～Ｃ６Ｏに蓄積されている電荷の総量が保存された状態でスイッチＳＷＯ６の状態が変化することにより、ノードＶＩＯの電位は（１／２１）ＶＲＥＦだけ低下する。 In period T2 ′ of the example shown in FIG. 3, since the voltage of node VIO is higher than the voltage of node VIC, control circuit SARLOGICO sets the logic of bit DO6 to “L”. As a result, the digital signal DO [6: 1] expressed in hexadecimal changes from 3F (111111) to 1F (0111111). In period T3 ', the logic level of bit DO6 is output to switch SWO6. Thus, the switch SWO6 is switched to the state in which the second terminal S2 and the third terminal D are connected. Thus, the ground level is input to the second electrode of the capacitor C6O. By changing the state of the switch SWO6 in a state where the total amount of charges accumulated in the capacitors C1O to C6O is stored, the potential of the node VIO is lowered by (1/2 1 ) VREF.
　ノードＶＩＯの電位の変動が安定した後、期間Ｔ３’において、比較器ＣＭＰＯは、ビットＤＯ５の論理レベルを判定するためにノードＶＩＯおよびノードＶＩＣの電圧を比較する。期間Ｔ３’において、ノードＶＩＣの電圧がノードＶＩＯの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＯは、ビットＤＯ５の論理を“Ｌ”に設定し、かつビットＤＯ６の論理を“Ｈ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＯ［６：１］は１Ｆ（０１１１１１）から２Ｆ（１０１１１１）に変化する。期間Ｔ４’において、ビットＤＯ６の論理レベルはスイッチＳＷ６Ｏに出力され、かつビットＤＯ５の論理レベルは、スイッチＳＷ５Ｏに出力される。このため、スイッチＳＷ６Ｏは、第１の端子Ｓ１と第３の端子Ｄとが接続された状態に切り替わる。これにより、基準電圧ＶＲＥＦが容量Ｃ６Ｏの第２の電極に入力される。スイッチＳＷ５Ｏは、第２の端子Ｓ２と第３の端子Ｄとが接続された状態に切り替わる。これにより、グランドレベルが容量Ｃ５Ｏの第２の電極に入力される。容量Ｃ１Ｏ～Ｃ６Ｏに蓄積されている電荷の総量が保存された状態で、スイッチＳＷ６ＯおよびスイッチＳＷ５Ｏの状態が変化することにより、ノードＶＩＯの電位は（１／２２）ＶＲＥＦだけ増加する。 After the fluctuation of the potential of the node VIO is stabilized, the comparator CMPO compares the voltages of the node VIO and the node VIC to determine the logic level of the bit DO5 in a period T3 '. In period T3 ', since the voltage of node VIC is higher than the voltage of node VIO, control circuit SARLOGICO sets the logic of bit DO5 to "L" and sets the logic of bit DO6 to "H". As a result, the digital signal DO [6: 1] expressed in hexadecimal changes from 1F (011111) to 2F (101111). In period T4 ', the logic level of bit DO6 is output to switch SW6O, and the logic level of bit DO5 is output to switch SW5O. Therefore, the switch SW6O is switched to the state in which the first terminal S1 and the third terminal D are connected. Thus, the reference voltage VREF is input to the second electrode of the capacitor C6O. The switch SW5O switches to a state in which the second terminal S2 and the third terminal D are connected. Thereby, the ground level is input to the second electrode of the capacitor C50. With the total amount of charges accumulated in the capacitors C1O to C6O being stored, the state of the switches SW6O and SW5O changes, whereby the potential of the node VIO is increased by (1/2 2 ) VREF.
　ノードＶＩＯの電位の変動が安定した後、期間Ｔ４’において、比較器ＣＭＰＯは、ビットＤＯ４の論理レベルを判定するためにノードＶＩＯおよびノードＶＩＣの電圧を比較する。期間Ｔ４’において、ノードＶＩＯの電圧がノードＶＩＣの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＯは、ビットＤＯ４の論理を“Ｌ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＯ［６：１］は２Ｆ（１０１１１１）から２７（１００１１１）に変化する。期間Ｔ５’において、ビットＤＯ４の論理レベルは、スイッチＳＷ４Ｏに出力される。このため、スイッチＳＷ４Ｏは、第２の端子Ｓ２と第３の端子Ｄとが接続された状態に切り替わる。これにより、グランドレベルが容量Ｃ４Ｏの第２の電極に入力される。容量Ｃ１Ｏ～Ｃ６Ｏに蓄積されている電荷の総量が保存された状態で、スイッチＳＷ４Ｏの状態が変化することにより、ノードＶＩＯの電位は（１／２３）ＶＲＥＦだけ低下する。 After the fluctuation of the potential of the node VIO is stabilized, in period T4 ′, the comparator CMPO compares the voltages of the node VIO and the node VIC to determine the logic level of the bit DO4. In period T4 ', since the voltage of node VIO is higher than the voltage of node VIC, control circuit SARLOGICO sets the logic of bit DO4 to "L". As a result, the digital signal DO [6: 1] expressed in hexadecimal changes from 2F (101111) to 27 (100111). In period T5 ', the logic level of bit DO4 is output to switch SW4O. Therefore, the switch SW4O switches to a state in which the second terminal S2 and the third terminal D are connected. Thereby, the ground level is input to the second electrode of the capacitor C4O. With the total amount of charges accumulated in the capacitors C1O to C6O being stored, the state of the switch SW4O changes, whereby the potential of the node VIO decreases by (1/2 3 ) VREF.
　ノードＶＩＯの電位の変動が安定した後、期間Ｔ５’において、比較器ＣＭＰＯは、ビットＤＯ３の論理レベルを判定するためにノードＶＩＯおよびノードＶＩＣの電圧を比較する。期間Ｔ５’において、ノードＶＩＯの電圧がノードＶＩＣの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＯは、ビットＤＯ３の論理を“Ｌ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＯ［６：１］は２７（１００１１１）から２３（１０００１１）に変化する。期間Ｔ６’において、ビットＤＯ３の論理レベルは、スイッチＳＷＯ３に出力される。このため、スイッチＳＷ３Ｏは、第２の端子Ｓ２と第３の端子Ｄとが接続された状態に切り替わる。これにより、グランドレベルが容量Ｃ３Ｏの第２の電極に入力される。容量Ｃ１Ｏ～Ｃ６Ｏに蓄積されている電荷の総量が保存された状態で、スイッチＳＷ３Ｏの状態が変化することにより、ノードＶＩＯの電位は（１／２４）ＶＲＥＦだけ低下する。 After the fluctuation of the potential of node VIO is stabilized, comparator CMPO compares voltages of node VIO and node VIC to determine the logic level of bit DO3 in period T5 '. In period T5 ', since the voltage of node VIO is higher than the voltage of node VIC, control circuit SARLOGICO sets the logic of bit DO3 to "L". As a result, the digital signal DO [6: 1] expressed in hexadecimal changes from 27 (100111) to 23 (100011). In period T6 ', the logic level of bit DO3 is output to switch SWO3. Therefore, the switch SW3O is switched to the state in which the second terminal S2 and the third terminal D are connected. Thus, the ground level is input to the second electrode of the capacitor C3O. With the total amount of charges accumulated in the capacitors C1O to C6O being stored, the state of the switch SW3O changes, whereby the potential of the node VIO drops by (1/2 4 ) VREF.
　ノードＶＩＯの電位の変動が安定した後、期間Ｔ６’において、比較器ＣＭＰＯは、ビットＤＯ２の論理レベルを判定するためにノードＶＩＯおよびノードＶＩＣの電圧を比較する。期間Ｔ６’において、ノードＶＩＣの電圧がノードＶＩＯの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＯは、ビットＤＯ２の論理を“Ｌ”に設定し、かつビットＤＯ３の論理を“Ｈ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＯ［６：１］は２３（１０００１１）から２５（１００１０１）に変化する。期間Ｔ７’において、ビットＤＯ３の論理レベルはスイッチＳＷ３Ｏに出力され、かつビットＤＯ２の論理レベルは、スイッチＳＷ２Ｏに出力される。このため、スイッチＳＷ３Ｏは、第１の端子Ｓ１と第３の端子Ｄとが接続された状態に切り替わる。これにより、基準電圧ＶＲＥＦが容量Ｃ３Ｏの第２の電極に入力される。スイッチＳＷ２Ｏは、第２の端子Ｓ２と第３の端子Ｄとが接続された状態に切り替わる。これにより、グランドレベルが容量Ｃ２Ｏの第２の電極に入力される。容量Ｃ１Ｏ～Ｃ６Ｏに蓄積されている電荷の総量が保存された状態で、スイッチＳＷ３ＯおよびスイッチＳＷ２Ｏの状態が変化することにより、ノードＶＩＯの電位は（１／２５）ＶＲＥＦだけ増加する。 After the fluctuation of the potential of the node VIO is stabilized, in period T6 ′, the comparator CMPO compares the voltages of the nodes VIO and VIC to determine the logic level of the bit DO2. In period T6 ', since the voltage of node VIC is higher than the voltage of node VIO, control circuit SARLOGICO sets the logic of bit DO2 to "L" and sets the logic of bit DO3 to "H". As a result, the digital signal DO [6: 1] expressed in hexadecimal changes from 23 (100011) to 25 (100101). In period T7 ', the logic level of bit DO3 is output to switch SW3O, and the logic level of bit DO2 is output to switch SW2O. Therefore, the switch SW3O is switched to the state in which the first terminal S1 and the third terminal D are connected. Thus, the reference voltage VREF is input to the second electrode of the capacitor C3O. The switch SW2O is switched to a state in which the second terminal S2 and the third terminal D are connected. Thus, the ground level is input to the second electrode of the capacitor C2O. With the total amount of charges accumulated in the capacitors C1O to C6O being stored, the state of the switches SW3O and SW2O changes, whereby the potential of the node VIO increases by (1/2 5 ) VREF.
　ノードＶＩＯの電位の変動が安定した後、期間Ｔ７’において、比較器ＣＭＰＯは、ビットＤＯ１の論理レベルを判定するためにノードＶＩＯおよびノードＶＩＣの電圧を比較する。期間Ｔ７’において、ノードＶＩＣの電圧がノードＶＩＯの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＯは、ビットＤＯ１の論理を“Ｌ”に設定し、かつビットＤＯ２の論理を“Ｈ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＯ［６：１］は２５（１００１０１）から２６（１００１１０）に変化する。このようにして得られたデジタル信号ＤＯ［６：１］は、外部の信号処理システムで利用される。 After the fluctuation of the potential of the node VIO is stabilized, in period T7 ', the comparator CMPO compares the voltages of the node VIO and the node VIC to determine the logic level of the bit DO1. In period T7 ', since the voltage of node VIC is higher than the voltage of node VIO, control circuit SARLOGICO sets the logic of bit DO1 to "L" and sets the logic of bit DO2 to "H". As a result, the digital signal DO [6: 1] expressed in hexadecimal changes from 25 (100101) to 26 (100110). The digital signal DO [6: 1] obtained in this manner is used in an external signal processing system.
　期間Ｔ７’における判定結果は、スイッチＳＷ２ＯおよびスイッチＳＷ１Ｏの制御に使用されない。スイッチＳＷ１Ｏには、常に“Ｈ”である制御信号が入力されてもよい。 The determination result in the period T7 'is not used to control the switch SW2O and the switch SW1O. A control signal that is always “H” may be input to the switch SW1O.
　本発明の各態様のＡＤ変換器におけるＤＡＣ回路は、容量以外の構成を有していなくてもよい。本発明の各態様のＡＤ変換器に入力され、かつＡＤ変換対象である信号は、映像信号以外の信号であってもよい。 The DAC circuit in the AD converter according to each aspect of the present invention may not have a configuration other than the capacitance. The signal input to the AD converter according to each aspect of the present invention and to be subjected to AD conversion may be a signal other than the video signal.
　第１の実施形態のＡＤ変換器ＡＤＣにおいて、ＡＤ変換期間中、サンプルスイッチＳＷＳＭＰＬＯおよびサンプルスイッチＳＷＳＭＰＬＣはオフになる。これにより、容量Ｃ１Ｏ～Ｃ６ＯのノードＶＩＯから見込んだ、グランドに対するインピーダンスと、容量Ｃ１Ｃ～Ｃ６ＣのノードＶＩＣから見込んだ、グランドに対するインピーダンスとが同じに保たれる。このため、ダイナミックコンパレータである比較器ＣＭＰＯがリセット動作をする度に生じるキックバックノイズの影響がバランスされる。この結果、高精度なＡＤ変換結果が得られる。また、比較器ＣＭＰＯとしてダイナミックコンパレータを使用することにより、消費電力を抑えることができる。 In the AD converter ADC of the first embodiment, the sample switch SWSMPLO and the sample switch SWSMPLC are turned off during the AD conversion period. Thereby, the impedance to the ground estimated from the node VIO of the capacitors C1O to C6O and the impedance to the ground estimated from the node VIC of the capacitors C1C to C6C are kept the same. For this reason, the effects of kickback noise generated each time the comparator CMPO, which is a dynamic comparator, performs a reset operation are balanced. As a result, highly accurate AD conversion results can be obtained. Further, power consumption can be suppressed by using a dynamic comparator as the comparator CMPO.
　図４から図６は、バランス容量の働きによりＡＤ変換エラーを抑えることが確認できるシミュレーション例を示す。図４は、正弦波状のアナログ信号のＡＤ変換結果から復元されたアナログ信号を示す。図４において、横軸は時間を示し、かつ縦軸は電圧を示す。電圧ＡＶ１は、バランス容量（容量アレーＣＤＡＣＣ）があるＡＤ変換器に入力されるアナログ信号の例を示す。電圧ＡＶ２は、バランス容量が無いＡＤ変換器に入力されるアナログ信号の例を示す。 FIGS. 4 to 6 show a simulation example that can be confirmed to suppress an AD conversion error by the function of the balance capacitance. FIG. 4 shows an analog signal restored from the result of AD conversion of a sinusoidal analog signal. In FIG. 4, the horizontal axis indicates time, and the vertical axis indicates voltage. The voltage AV1 indicates an example of an analog signal input to an AD converter having a balance capacitance (capacitance array CDACC). The voltage AV2 indicates an example of an analog signal input to the AD converter having no balance capacitance.
　図５は、バランス容量（容量アレーＣＤＡＣＣ）があるＡＤ変換器と、バランス容量が無いＡＤ変換器との各々におけるノードＶＩＯおよびノードＶＩＣの電圧を示す。図５において、横軸は時間を示し、かつ縦軸は電圧を示す。 FIG. 5 shows voltages of the node VIO and the node VIC in each of the AD converter with the balancing capacitance (capacitance array CDACC) and the AD converter without the balancing capacitance. In FIG. 5, the horizontal axis shows time, and the vertical axis shows voltage.
　図４の時刻ｔｙにおいて、バランス容量が無いＡＤ変換器に変換エラーが生じた結果、時刻ｔｘで最終的に確定するＡＤ変換結果の値に誤差が生じる。図５における時刻ｔｙは、図４における時刻ｔｙに対応する。時刻ｔｙ以前の時間におけるノードＶＩＯおよびノードＶＩＣの電圧の大きさの関係は、バランス容量の有無にかかわらず、同じである。 As a result of the conversion error occurring in the AD converter having no balanced capacity at time ty in FIG. 4, an error occurs in the value of the AD conversion result finally determined at time tx. The time ty in FIG. 5 corresponds to the time ty in FIG. The relationship between the voltage magnitudes of node VIO and node VIC before time ty is the same regardless of the presence or absence of the balance capacitance.
　バランス容量があるＡＤ変換器では、時刻ｔｙにおいて、ノードＶＩＯの電圧はノードＶＩＣの電圧よりも高い。一方、バランス容量が無いＡＤ変換器では、時刻ｔｙにおいて、ノードＶＩＯの電圧は、ノードＶＩＣの電圧よりも低い。時刻ｔｙ以降の時間において、バランス容量があるＡＤ変換器と、バランス容量が無いＡＤ変換器とでは、ノードＶＩＯおよびノードＶＩＣの電圧の大きさの関係が異なる。バランス容量が無い場合、ノードＶＩＣが低インピーダンスに保たれることにより、ノードＶＩＣの電圧がキックバックノイズの影響を受けないことが上記の原因であることは明白である。 In an AD converter having a balancing capacitance, at time ty, the voltage at node VIO is higher than the voltage at node VIC. On the other hand, in the AD converter without the balance capacitance, at time ty, the voltage of the node VIO is lower than the voltage of the node VIC. The relationship between the voltage magnitudes of the node VIO and the node VIC is different between the AD converter having the balanced capacitance and the AD converter having no balanced capacitance at and after the time ty. It is obvious that the above-mentioned cause is that the voltage of the node VIC is not affected by the kickback noise by keeping the node VIC at low impedance in the absence of the balancing capacitance.
　図５における電圧の状態をより明確に説明するため、図６を用いて補足説明を行う。図６は、ノードＶＩＣの電圧とノードＶＩＯの電圧との差（ＶＩＣ－ＶＩＯ）を示す。ＡＤ変換器は、ＡＤ変換の実施によりノードＶＩＣの電圧とノードＶＩＯの電圧との差が目標電圧すなわち０に近づくように動作する。 In order to explain the state of the voltage in FIG. 5 more clearly, a supplementary explanation is given using FIG. FIG. 6 shows the difference (VIC−VIO) between the voltage of the node VIC and the voltage of the node VIO. The AD converter operates such that the difference between the voltage of the node VIC and the voltage of the node VIO approaches the target voltage, that is, 0, by performing AD conversion.
　時刻ｔｙ以前の時間において、差電圧（ＶＩＣ－ＶＩＯ）は、バランス容量の有無に関わらず、ほぼ同じである。しかしながら、時刻ｔｙにおいて判定エラーが生じることにより、バランス容量が無いＡＤ変換器では、差電圧（ＶＩＣ－ＶＩＯ）は、一旦目標電圧から遠ざかった後に目標電圧に漸近する。一方、バランス容量があるＡＤ変換器では、差電圧（ＶＩＣ－ＶＩＯ）は、常に目標電圧に漸近する。任意の時刻において、判定エラーが生じた場合における目標電圧に対する差電圧（ＶＩＣ－ＶＩＯ）の誤差は、判定エラーが生じない場合における目標電圧に対する差電圧（ＶＩＣ－ＶＩＯ）の誤差以上である。したがって、バランス容量があるＡＤ変換器では、バランス容量が無いＡＤ変換器に比べて、目標電圧の収束が速やかに行われることが確認できる。つまり、バランス容量があるＡＤ変換器では、バランス容量が無いＡＤ変換器に比べて、高精度なＡＤ変換結果が得られる。 At time before time ty, the differential voltage (VIC-VIO) is substantially the same regardless of the presence or absence of the balance capacitance. However, due to the occurrence of the determination error at time ty, in the AD converter without the balance capacitance, the difference voltage (VIC−VIO) approaches the target voltage as soon as it is away from the target voltage. On the other hand, in an AD converter having a balanced capacitance, the differential voltage (VIC−VIO) always approaches the target voltage. The error of the differential voltage (VIC-VIO) with respect to the target voltage when a determination error occurs at any time is equal to or greater than the error of the differential voltage (VIC-VIO) with respect to the target voltage when no determination error occurs. Therefore, it can be confirmed that the convergence of the target voltage is performed more quickly in the AD converter having the balance capacitance than in the AD converter having no balance capacitance. That is, in an AD converter having a balanced capacity, highly accurate AD conversion results can be obtained as compared with an AD converter having no balanced capacity.
　（第２の実施形態）
　図７を用いて、本発明の第２の実施形態のイメージセンサＩＭＧの全体構成について説明する。図７は、イメージセンサＩＭＧの全体構成を示している。図７に示すように、イメージセンサＩＭＧは、撮像部ＰＩＸと、タイミングジェネレータＴＧと、列処理部ＣＯＬＳと、ＡＤ変換回路ＡＤＣａとを有する。 Second Embodiment
The entire configuration of the image sensor IMG according to the second embodiment of the present invention will be described with reference to FIG. FIG. 7 shows the entire configuration of the image sensor IMG. As shown in FIG. 7, the image sensor IMG includes an imaging unit PIX, a timing generator TG, a column processing unit COLS, and an AD conversion circuit ADCa.
　撮像部ＰＩＸは、行列状に配置された複数の画素Ｐを有する。図７において、複数の画素Ｐの一部は省略されている。各画素Ｐが区別される場合、画素Ｐは行番号ｍおよび列番号ｎと一緒に記載される。ｍは１以上、ｎは２以上の任意の整数である。ｎは任意の偶数であってもよい。ｉ行ｊ列に配置された画素Ｐは、画素Ｐ［ｉ，ｊ］である。ｉは１以上かつｍ以下の整数である。ｊは１以上かつｎ以下の整数である。撮像部ＰＩＸは、ｍ×ｎ個の画素Ｐ［１，１］～Ｐ［ｍ，ｎ］を有する。ｎ本の垂直信号線ＶＬ＜１＞～ＶＬ＜ｎ＞が列方向に配置されている。画素Ｐ［１，１］～Ｐ［ｍ，ｎ］は、列単位で垂直信号線ＶＬ＜１＞～ＶＬ＜ｎ＞に接続されている。つまり、ｊ列目の画素Ｐ［１，ｊ］～Ｐ［ｍ，ｊ］は、垂直信号線ＶＬ＜ｊ＞に接続されている。画素Ｐは、各画素Ｐがリセットされたときのリセット信号と、各画素Ｐに入射した光に応じた映像信号とを列処理部ＣＯＬＳに出力する。画素Ｐは、フォトダイオードを有し、かつ画素Ｐに入射した光に応じた信号をフォトダイオードに蓄積する。画素Ｐは、フォトダイオードに蓄積された信号に基づく映像信号を列処理部ＣＯＬＳに出力する。 The imaging unit PIX has a plurality of pixels P arranged in a matrix. In FIG. 7, some of the plurality of pixels P are omitted. When each pixel P is distinguished, the pixel P is described together with the row number m and the column number n. m is an integer of 1 or more and n is an integer of 2 or more. n may be any even number. The pixel P arranged in the i-th row and j-th column is a pixel P [i, j]. i is an integer of 1 or more and m or less. j is an integer of 1 or more and n or less. The imaging unit PIX has m × n pixels P [1, 1] to P [m, n]. N vertical signal lines VL <1> to VL <n> are arranged in the column direction. The pixels P [1, 1] to P [m, n] are connected to the vertical signal lines VL <1> to VL <n> in units of columns. That is, the pixels P [1, j] to P [m, j] in the j-th column are connected to the vertical signal line VL <j>. The pixel P outputs, to the column processing unit COLS, a reset signal when each pixel P is reset, and a video signal corresponding to light incident on each pixel P. The pixel P has a photodiode, and accumulates a signal according to the light incident on the pixel P in the photodiode. The pixel P outputs a video signal based on the signal accumulated in the photodiode to the column processing unit COLS.
　列処理部ＣＯＬＳは、複数の画素Ｐの列毎に配置された複数の列回路ＣＯＬを有する。図７において、複数の列回路ＣＯＬの一部は省略されている。各列回路ＣＯＬが区別される場合、列回路ＣＯＬは列番号ｎと一緒に記載される。ｊ列に配置された列回路ＣＯＬは、列回路ＣＯＬ＜ｊ＞である。列処理部ＣＯＬＳは、ｎ個の列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞を有する。列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞は、垂直信号線ＶＬ＜１＞～ＶＬ＜ｎ＞毎に配置されている。ｊ列目の列回路ＣＯＬ＜ｊ＞は、垂直信号線ＶＬ＜ｊ＞に接続されている。ｊ列目の画素Ｐ［１，ｊ］～Ｐ［ｍ，ｊ］から出力されたリセット信号と映像信号とがｊ列目の列回路ＣＯＬ＜ｊ＞に入力される。列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞は、水平信号線ＨＬを介してＡＤ変換回路ＡＤＣａに接続されている。列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞は、画素Ｐ［１，１］～Ｐ［ｍ，ｎ］から出力された映像信号に含まれるリセットノイズ等をキャンセルする。これによって、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞は、映像信号ＶＳＩＧを生成し、かつ映像信号ＶＳＩＧをＡＤ変換回路ＡＤＣａに出力する。 The column processing unit COLS has a plurality of column circuits COL arranged for each column of the plurality of pixels P. In FIG. 7, some of the plurality of column circuits COL are omitted. When each column circuit COL is distinguished, the column circuit COL is described together with the column number n. The column circuit COL disposed in the j-th column is a column circuit COL <j>. The column processing unit COLS has n column circuits COL <1> to COL <n>. Column circuits COL <1> to COL <n> are arranged for each of vertical signal lines VL <1> to VL <n>. The column circuit COL <j> in the j-th column is connected to the vertical signal line VL <j>. The reset signal and the video signal output from the pixels P [1, j] to P [m, j] in the j-th column are input to the column circuit COL <j> in the j-th column. The column circuits COL <1> to COL <n> are connected to the AD conversion circuit ADCa via the horizontal signal line HL. The column circuits COL <1> to COL <n> cancel reset noise and the like included in the video signal output from the pixels P [1, 1] to P [m, n]. Thus, the column circuits COL <1> to COL <n> generate the video signal VSIG and output the video signal VSIG to the AD conversion circuit ADCa.
　ＡＤ変換回路ＡＤＣａは、水平信号線ＨＬに接続されている。ＡＤ変換回路ＡＤＣａは、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞から出力された映像信号ＶＳＩＧ（アナログ電圧信号）をデジタル信号に変換する。ＡＤ変換回路ＡＤＣａは、奇数ＡＤ変換器ＡＤＣＯと偶数ＡＤ変換器ＡＤＣＥとを有する。 The AD conversion circuit ADCa is connected to the horizontal signal line HL. The AD conversion circuit ADCa converts the video signal VSIG (analog voltage signal) output from the column circuits COL <1> to COL <n> into a digital signal. The AD conversion circuit ADCa includes an odd AD converter ADCO and an even AD converter ADCE.
　タイミングジェネレータＴＧは、図示しない信号線により、撮像部ＰＩＸと、列処理部ＣＯＬＳと、ＡＤ変換回路ＡＤＣａとに接続されている。タイミングジェネレータＴＧは、イメージセンサＩＭＧの制御に必要な信号を各部に供給する。 The timing generator TG is connected to the imaging unit PIX, the column processing unit COLS, and the AD conversion circuit ADCa via a signal line (not shown). The timing generator TG supplies signals necessary for controlling the image sensor IMG to each part.
　タイミングジェネレータＴＧは、行選択信号ＲＳＥＬ＜１＞を１行目の画素Ｐ［１，１］～画素Ｐ［１，ｎ］に供給し、かつ行選択信号ＲＳＥＬ＜ｍ＞をｍ行目の画素Ｐ［ｍ，１］～画素Ｐ［ｍ，ｎ］に供給する。タイミングジェネレータＴＧは、他の行に関しても、同様の信号を画素Ｐに供給する。行選択信号ＲＳＥＬ＜ｉ＞が“Ｌ（Ｌｏｗ）”である場合、行選択信号ＲＳＥＬ＜ｉ＞が供給される画素Ｐ［ｉ，１］～画素Ｐ［ｉ，ｎ］は、垂直信号線ＶＬ＜１＞～ＶＬ＜ｎ＞に接続されない。行選択信号ＲＳＥＬ＜ｉ＞が“Ｈ（Ｈｉｇｈ）”である場合、行選択信号ＲＳＥＬ＜ｉ＞が供給される画素Ｐ［ｉ，１］～画素Ｐ［ｉ，ｎ］は、垂直信号線ＶＬ＜１＞～ＶＬ＜ｎ＞に接続される。 The timing generator TG supplies the row selection signal RSEL <1> to the pixel P [1,1] to the pixel P [1, n] in the first row, and the row selection signal RSEL <m> in the mth row The signal is supplied to P [m, 1] to pixel P [m, n]. The timing generator TG supplies similar signals to the pixels P for the other rows. When the row selection signal RSEL <i> is “L (Low)”, the pixel P [i, 1] to the pixel P [i, n] to which the row selection signal RSEL <i> is supplied are the vertical signal lines VL. It is not connected to <1> to VL <n>. When the row selection signal RSEL <i> is “H (High)”, the pixel P [i, 1] to the pixel P [i, n] to which the row selection signal RSEL <i> is supplied are the vertical signal lines VL. It is connected to <1> to VL <n>.
　タイミングジェネレータＴＧは、制御信号ＣＬＰ＿Ｒおよび制御信号ＣＬＰ＿Ｓを列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞に供給する。制御信号ＣＬＰ＿Ｒは、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞が画素Ｐから出力されたリセット信号をサンプリングするための制御信号である。画素Ｐからリセット信号が出力されるタイミングで、制御信号ＣＬＰ＿Ｒは“Ｈ”に変化する。このとき、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞は、リセット信号のサンプリングを行う。制御信号ＣＬＰ＿Ｒが“Ｌ”に変化したとき、このサンプリング動作は終了する。 The timing generator TG supplies a control signal CLP_R and a control signal CLP_S to the column circuits COL <1> to COL <n>. The control signal CLP_R is a control signal for sampling the reset signal output from the pixel P by the column circuits COL <1> to COL <n>. At the timing when the reset signal is output from the pixel P, the control signal CLP_R changes to “H”. At this time, the column circuits COL <1> to COL <n> sample reset signals. When the control signal CLP_R changes to "L", this sampling operation ends.
　制御信号ＣＬＰ＿Ｓは、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞が画素Ｐから出力された映像信号をサンプリングするための制御信号である。画素Ｐから映像信号が出力されるタイミングで、制御信号ＣＬＰ＿Ｓは“Ｈ”に変化する。このとき、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞は、映像信号のサンプリングを行う。制御信号ＣＬＰ＿Ｓが“Ｌ”に変化したとき、このサンプリング動作は終了する。 The control signal CLP_S is a control signal for sampling the video signal output from the pixel P by the column circuits COL <1> to COL <n>. At the timing when the video signal is output from the pixel P, the control signal CLP_S changes to “H”. At this time, the column circuits COL <1> to COL <n> sample the video signal. When the control signal CLP_S changes to "L", this sampling operation ends.
　タイミングジェネレータＴＧは、列選択信号ＣＳＥＬ＜１＞～ＣＳＥＬ＜ｎ＞を列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞に供給する。列選択信号ＣＳＥＬ＜１＞～ＣＳＥＬ＜ｎ＞が“Ｈ”に変化したとき、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞は水平信号線ＨＬに接続される。このとき、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞は、リセット信号と映像信号との差分ＶＰＩＸ＜ｘ＞に基づく映像信号ＶＳＩＧ＜ｘ＞をＡＤ変換回路ＡＤＣａに出力する。ｘは、１以上かつｎ以下の整数である。映像信号ＶＳＩＧ＜ｘ＞は、基準電圧ＶＲＥＦを基準とする信号である。 The timing generator TG supplies column selection signals CSEL <1> to CSEL <n> to column circuits COL <1> to COL <n>. When column select signals CSEL <1> to CSEL <n> change to “H”, column circuits COL <1> to COL <n> are connected to horizontal signal line HL. At this time, the column circuits COL <1> to COL <n> output the video signal VSIG <x> based on the difference VPIX <x> between the reset signal and the video signal to the AD conversion circuit ADCa. x is an integer of 1 or more and n or less. The video signal VSIG <x> is a signal based on the reference voltage VREF.
　映像信号ＶＳＩＧは、式（３）により示される。映像信号ＶＳＩＧは、負の極性を有する。
　ＶＳＩＧ＝ＶＲＥＦ－ＶＰＩＸ＜ｘ＞　　・・・（３） The video signal VSIG is expressed by equation (3). The video signal VSIG has a negative polarity.
VSIG = VREF-VPIX <x> (3)
　例えば、画素Ｐからの信号が最小レベル（黒レベル）である場合、映像信号ＶＳＩＧは、式（４）により示される。一方、画素Ｐからの信号が最大レベル（飽和レベル）である場合、映像信号ＶＳＩＧは、式（５）により示される。式（５）において、ＶＰＩＸ＿ＳＡＴは、ＶＰＩＸの飽和（最大）電圧である。
　ＶＳＩＧ＝ＶＲＥＦ－０　　・・・（４）
　ＶＳＩＧ＝ＶＲＥＦ－ＶＰＩＸ＿ＳＡＴ　　・・・（５） For example, when the signal from the pixel P is at the minimum level (black level), the video signal VSIG is represented by Expression (4). On the other hand, when the signal from the pixel P is at the maximum level (saturation level), the video signal VSIG is represented by Expression (5). In equation (5), VPIX_SAT is the saturated (maximum) voltage of VPIX.
VSIG = VREF-0 (4)
VSIG = VREF-VPIX_SAT (5)
　上記の例において、映像信号ＶＳＩＧは負の極性を有する。しかし、映像信号ＶＳＩＧは正の極性を有してもよい。 In the above example, the video signal VSIG has a negative polarity. However, the video signal VSIG may have positive polarity.
　図８および図９を用いて、イメージセンサＩＭＧによる信号の読み出し動作について、より詳細に説明する。図８および図９は、イメージセンサＩＭＧの動作に関する信号を示す。図８において、行選択信号ＲＳＥＬ＜１＞～ＲＳＥＬ＜ｍ＞が示されている。図９において、垂直信号線ＶＬ＜１＞の電圧と、映像信号ＶＳＩＧと、制御信号ＣＬＰ＿Ｒと、制御信号ＣＬＰ＿Ｓと、列選択信号ＣＳＥＬ＜１＞～ＣＳＥＬ＜ｎ＞とが示されている。図９において、奇数ＡＤ変換器ＡＤＣＯの状態と、偶数ＡＤ変換器ＡＤＣＥの状態と、ＡＤ変換結果（ＡＤ＿ＲＥＳＵＬＴ）のビット列Ｄ＜１＞～Ｄ＜ｎ＞とが示されている。図８および図９において、横軸は時間を示し、かつ縦軸は信号レベルを示す。図８と図９とでは、時間方向の分解能が異なる。図８における時刻ｔ１００から時刻ｔ１０１の期間は、図９における時刻ｔ１から時刻ｔ１０の期間に対応する。 The signal readout operation by the image sensor IMG will be described in more detail with reference to FIGS. 8 and 9. 8 and 9 show signals related to the operation of the image sensor IMG. Row selection signals RSEL <1> to RSEL <m> are shown in FIG. In FIG. 9, the voltage of the vertical signal line VL <1>, the video signal VSIG, the control signal CLP_R, the control signal CLP_S, and the column selection signals CSEL <1> to CSEL <n> are shown. In FIG. 9, the state of the odd AD converter ADCO, the state of the even AD converter ADCE, and bit strings D <1> to D <n> of the AD conversion result (AD_RESULT) are shown. In FIGS. 8 and 9, the horizontal axis represents time, and the vertical axis represents signal level. The resolution in the time direction is different between FIG. 8 and FIG. The period from time t100 to time t101 in FIG. 8 corresponds to the period from time t1 to time t10 in FIG.
　時刻ｔ１００において、行選択信号ＲＳＥＬ＜１＞が“Ｈ”に変化する。行選択信号ＲＳＥＬ＜２＞～ＲＳＥＬ＜ｍ＞は“Ｌ”に保たれる。時刻ｔ１０１において、行選択信号ＲＳＥＬ＜１＞が“Ｌ”に変化し、かつ行選択信号ＲＳＥＬ＜２＞が“Ｈ”に変化する。その後、各行の行選択信号ＲＳＥＬ＜３＞～ＲＳＥＬ＜ｍ＞は順番に“Ｈ”に変化する。時刻ｔ１０９において、行選択信号ＲＳＥＬ＜ｍ－１＞が“Ｌ”に変化し、かつ行選択信号ＲＳＥＬ＜ｍ＞が“Ｈ”に変化する。時刻ｔ１１０において、行選択信号ＲＳＥＬ＜ｍ＞が“Ｌ”に変化する。時刻ｔ２００から時刻ｔ３００における行選択信号ＲＳＥＬ＜１＞～ＲＳＥＬ＜ｍ＞の変化は、時刻ｔ１００から時刻ｔ１１０における行選択信号ＲＳＥＬ＜１＞～ＲＳＥＬ＜ｍ＞の変化と同様である。 At time t100, row selection signal RSEL <1> changes to "H". Row select signals RSEL <2> to RSEL <m> are maintained at “L”. At time t101, row selection signal RSEL <1> changes to "L", and row selection signal RSEL <2> changes to "H". Thereafter, row selection signals RSEL <3> to RSEL <m> in each row sequentially change to “H”. At time t109, row selection signal RSEL <m-1> changes to "L", and row selection signal RSEL <m> changes to "H". At time t110, the row selection signal RSEL <m> changes to "L". Changes in row selection signals RSEL <1> to RSEL <m> from time t200 to time t300 are similar to changes in row selection signals RSEL <1> to RSEL <m> from time t100 to time t110.
　図９の時刻ｔ１において１行目の画素Ｐ［１，１］～Ｐ［１，ｎ］からの信号の読み出しが行われる前に、画素Ｐ［１，１］～Ｐ［１，ｎ］のフォトダイオードは所定の電圧にリセットされ、かつ所定の時間露光される。以下では、１行目の画素Ｐ［１，１］～画素Ｐ［１，ｎ］からの信号の読み出しを中心に説明する。他の行の画素Ｐからの信号の読み出しも１行目の画素Ｐからの信号の読み出しと同様である。時刻ｔ１において、奇数ＡＤ変換器ＡＤＣＯおよび偶数ＡＤ変換器ＡＤＣＥは、休止状態ＳＴＡＢである。 Before the signals from the pixels P [1, 1] to P [1, n] in the first row are read out at time t1 in FIG. 9, the pixels P [1, 1] to P [1, n] The photodiode is reset to a predetermined voltage and exposed for a predetermined time. The following description will focus on the readout of signals from the pixels P [1,1] to P [1, n] in the first row. The readout of the signals from the pixels P in the other rows is similar to the readout of the signals from the pixels P in the first row. At time t1, the odd AD converter ADCO and the even AD converter ADCE are in the inactive state STAB.
　時刻ｔ１において、行選択信号ＲＳＥＬ＜１＞が“Ｈ”になることにより、１行目の画素Ｐ［１，１］～Ｐ［１，ｎ］は夫々、垂直信号線ＶＬ＜１＞～ＶＬ＜ｎ＞に接続される。このタイミングで、画素Ｐ［１，１］～Ｐ［１，ｎ］はリセット信号ＶＲＳＴ＜１＞～ＶＲＳＴ＜ｎ＞の出力を開始する。各列のリセット信号ＶＲＳＴ＜１＞～ＶＲＳＴ＜ｎ＞のうち１列目のリセット信号ＶＲＳＴ＜１＞のみが代表として図９に示されている。このタイミングで、制御信号ＣＬＰ＿Ｒは“Ｈ”になる。これによって、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞はリセット信号ＶＲＳＴ＜１＞～ＶＲＳＴ＜ｎ＞のサンプリング動作を開始する。 At time t1, the row selection signal RSEL <1> changes to “H”, whereby the pixels P [1,1] to P [1, n] in the first row are each connected to the vertical signal lines VL <1> to VL. Connected to <n>. At this timing, the pixels P [1,1] to P [1, n] start outputting the reset signals VRST <1> to VRST <n>. Of the reset signals VRST <1> to VRST <n> of each column, only the reset signal VRST <1> of the first column is shown in FIG. 9 as a representative. At this timing, the control signal CLP_R becomes "H". Thus, column circuits COL <1> to COL <n> start sampling operations of reset signals VRST <1> to VRST <n>.
　時刻ｔ１から所定の時間が経過し、かつリセット信号ＶＲＳＴ＜１＞～ＶＲＳＴ＜ｎ＞が安定した後、時刻ｔ２において、制御信号ＣＬＰ＿Ｒは“Ｌ”になる。これによって、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞に保持されたリセット信号のレベルが決定される。このタイミングで、画素Ｐ［１，１］～Ｐ［１，ｎ］は映像信号ＰＩＸＯＵＴ＜１＞～ＰＩＸＯＵＴ＜ｎ＞の出力を開始する。同時に制御信号ＣＬＰ＿Ｓは“Ｈ”になる。これによって、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞は映像信号ＰＩＸＯＵＴ＜１＞～ＰＩＸＯＵＴ＜ｎ＞のサンプリング動作を開始する。 After a predetermined time has elapsed from time t1 and the reset signals VRST <1> to VRST <n> become stable, the control signal CLP_R becomes “L” at time t2. Thus, the level of the reset signal held in column circuits COL <1> to COL <n> is determined. At this timing, the pixels P [1,1] to P [1, n] start outputting the video signals PIXOUT <1> to PIXOUT <n>. At the same time, the control signal CLP_S goes high. Thus, the column circuits COL <1> to COL <n> start sampling operations of the video signals PIXOUT <1> to PIXOUT <n>.
　時刻ｔ３において、制御信号ＣＬＰ＿Ｓが“Ｌ”になることにより、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞は映像信号ＰＩＸＯＵＴ＜１＞～ＰＩＸＯＵＴ＜ｎ＞のサンプリング動作を終了する。列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞の内部では、画素Ｐ［１，１］～Ｐ［１，ｎ］から入力された映像信号ＰＩＸＯＵＴ＜１＞～ＰＩＸＯＵＴ＜ｎ＞に含まれる画素のリセットノイズ等がキャンセルされる。列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞は、基準電圧ＶＲＥＦを基準とし、振幅がＶＰＩＸ＜１＞～ＶＰＩＸ＜ｎ＞である映像信号ＶＳＩＧを保持する。 At time t3, as the control signal CLP_S becomes “L”, the column circuits COL <1> to COL <n> complete the sampling operation of the video signals PIXOUT <1> to PIXOUT <n>. In column circuits COL <1> to COL <n>, reset of pixels included in video signals PIXOUT <1> to PIXOUT <n> input from pixels P [1, 1] to P [1, n]. Noise is canceled. Column circuits COL <1> to COL <n> hold video signal VSIG whose amplitude is VPIX <1> to VPIX <n> with reference to reference voltage VREF.
　時刻ｔ３において、列選択信号ＣＳＥＬ＜１＞が“Ｈ”になることにより、１列目の列回路ＣＯＬ＜１＞から、振幅がＶＰＩＸ＜１＞である映像信号ＶＳＩＧが出力される。この信号は、ＡＤ変換回路ＡＤＣａの奇数ＡＤ変換器ＡＤＣＯによってサンプリングされる。短時間のリセット動作ＲＥＳＥＴが行われた後、奇数ＡＤ変換器ＡＤＣＯは、サンプリング動作ＳＡＭＰを開始する。 At time t3, when the column selection signal CSEL <1> changes to “H”, the video signal VSIG whose amplitude is VPIX <1> is output from the column circuit COL <1> in the first column. This signal is sampled by the odd AD converter ADCO of the AD conversion circuit ADCa. After the short-time reset operation RESET is performed, the odd AD converter ADCO starts the sampling operation SAMP.
　時刻ｔ４において、列選択信号ＣＳＥＬ＜１＞が“Ｌ”になり、かつ同時に列選択信号ＣＳＥＬ＜２＞が“Ｈ”になる。これによって、２列目の列回路ＣＯＬ＜２＞から、振幅がＶＰＩＸ＜２＞である映像信号ＶＳＩＧが出力される。この信号は、ＡＤ変換回路ＡＤＣａの偶数ＡＤ変換器ＡＤＣＥによってサンプリングされる。短時間のリセット動作ＲＥＳＥＴが行われた後、偶数ＡＤ変換器ＡＤＣＥは、サンプリング動作ＳＡＭＰを開始する。時刻ｔ４において、奇数ＡＤ変換器ＡＤＣＯはサンプリング動作ＳＡＭＰを終了する。短時間のリセット動作ＲＥＳＥＴが行われた後、奇数ＡＤ変換器ＡＤＣＯは、ＡＤ変換動作ＣＯＮＶを開始する。時刻ｔ４から変換時間ｔｄが経過した後の時刻ｔ５において、ＡＤ変換回路ＡＤＣａはＡＤ変換結果ＡＤ＿ＲＥＳＵＬＴを更新し、かつ変換結果としてビット列Ｄ＜１＞を出力する。本発明の実施形態において、ビット列Ｄ＜１＞は、デジタル信号ＤＯ［６：１］またはデジタル信号ＤＥ［６：１］により構成される信号である。 At time t4, the column selection signal CSEL <1> becomes "L", and at the same time, the column selection signal CSEL <2> becomes "H". As a result, a video signal VSIG whose amplitude is VPIX <2> is output from the column circuit COL <2> in the second column. This signal is sampled by the even AD converter ADCE of the AD conversion circuit ADCa. After the short-time reset operation RESET is performed, the even AD converter ADCE starts the sampling operation SAMP. At time t4, the odd AD converter ADCO ends the sampling operation SAMP. After the short-time reset operation RESET is performed, the odd AD converter ADCO starts an AD conversion operation CONV. At time t5 after the conversion time td has elapsed from time t4, the AD conversion circuit ADCa updates the AD conversion result AD_RESULT, and outputs a bit string D <1> as the conversion result. In the embodiment of the present invention, the bit string D <1> is a signal configured by the digital signal DO [6: 1] or the digital signal DE [6: 1].
　時刻ｔ５の後も同様に、列選択信号ＣＳＥＬ＜３＞～ＣＳＥＬ＜ｎ＞が順次“Ｈ”になることにより、列回路ＣＯＬ＜３＞～ＣＯＬ＜ｎ＞から映像信号ＶＳＩＧが順次出力され、かつＡＤ変換回路ＡＤＣａに入力される。 Similarly, after time t5, column selection signals CSEL <3> to CSEL <n> sequentially become “H”, whereby video signal VSIG is sequentially output from column circuits COL <3> to COL <n>. And, it is input to the AD conversion circuit ADCa.
　列回路ＣＯＬ＜ｎ＞から出力された映像信号ＶＳＩＧのサンプリング動作ＳＡＭＰは時刻ｔ７に開始し、かつ時刻ｔ８に終了する。列回路ＣＯＬ＜ｎ＞から出力された映像信号ＶＳＩＧのＡＤ変換動作ＣＯＮＶは時刻ｔ８に開始し、かつ時刻ｔ９に終了する。 The sampling operation SAMP of the video signal VSIG output from the column circuit COL <n> starts at time t7 and ends at time t8. The AD conversion operation CONV of the video signal VSIG output from the column circuit COL <n> starts at time t8 and ends at time t9.
　上記の動作において、奇数列の列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ－１＞から出力された映像信号ＶＳＩＧはＡＤ変換回路ＡＤＣａの奇数ＡＤ変換器ＡＤＣＯによってサンプリングされる。偶数列の列回路ＣＯＬ＜２＞～ＣＯＬ＜ｎ＞から出力された映像信号ＶＳＩＧはＡＤ変換回路ＡＤＣａの偶数ＡＤ変換器ＡＤＣＥによってサンプリングされる。一方のＡＤ変換器がサンプリング動作ＳＡＭＰを行う期間において、他方のＡＤ変換器はＡＤ変換動作ＣＯＮＶを行う。また、サンプリング動作ＳＡＭＰとＡＤ変換動作ＣＯＮＶとの間には必ず短時間のリセット動作ＲＥＳＥＴが存在する。一方のＡＤ変換器によるサンプリング動作ＳＡＭＰと他方のＡＤ変換器によるＡＤ変換動作ＣＯＮＶとは、並行的に行われる。いずれの列回路も選択されない期間において、ＡＤ変換回路ＡＤＣａの奇数ＡＤ変換器ＡＤＣＯおよび偶数ＡＤ変換器ＡＤＣＥは休止状態ＳＴＡＢになる。 In the above operation, the video signal VSIG output from the column circuits COL <1> to COL <n-1> of the odd columns is sampled by the odd AD converter ADCO of the AD conversion circuit ADCa. The video signals VSIG output from the column circuits COL <2> to COL <n> of the even columns are sampled by the even AD converters ADCE of the AD conversion circuit ADCa. While one AD converter performs the sampling operation SAMP, the other AD converter performs the AD conversion operation CONV. In addition, there is always a short reset operation RESET between the sampling operation SAMP and the AD conversion operation CONV. The sampling operation SAMP by one AD converter and the AD conversion operation CONV by the other AD converter are performed in parallel. In a period in which no column circuit is selected, the odd AD converter ADCO and the even AD converter ADCE of the AD conversion circuit ADCa are in the inactive state STAB.
　ＡＤ変換回路ＡＤＣａは、列選択信号ＣＳＥＬ＜１＞～ＣＳＥＬ＜ｎ＞が“Ｈ”から“Ｌ”に切り替わる瞬間に、その列選択信号ＣＳＥＬ＜ｉ＞に対応する列の列回路ＣＯＬ＜ｉ＞から出力された映像信号ＶＳＩＧのサンプリングを終了し、かつＡＤ変換を開始する。ＡＤ変換が終了する度に、ＡＤ変換回路ＡＤＣａは、ビット列Ｄ＜１＞～Ｄ＜ｎ＞を更新し、かつＡＤ変換結果ＡＤ＿ＲＥＳＵＬＴを順次出力（更新）する。 AD conversion circuit ADCa generates column circuit COL <i> of the column corresponding to column selection signal CSEL <i> at the moment when column selection signals CSEL <1> to CSEL <n> change from “H” to “L”. End the sampling of the video signal VSIG output from and start the AD conversion. Every time AD conversion is completed, the AD conversion circuit ADCa updates the bit strings D <1> to D <n> and sequentially outputs (updates) the AD conversion result AD_RESULT.
　１行ｎ列目の画素Ｐ［１，ｎ］からの読み出しが終了した後の時刻ｔ１０１（時刻ｔ１０に相当）において、行選択信号ＲＳＥＬ＜１＞は“Ｈ”から“Ｌ”に切り替わる。同時に行選択信号ＲＳＥＬ＜２＞は“Ｌ”から“Ｈ”に切り替わる。その後、２行１列目の画素Ｐ［２，１］から２行ｎ列目の画素Ｐ［２，ｎ］までの各画素Ｐから信号が、列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ＞を通して読み出される。その後、同様に３行目からｍ行目の各画素Ｐからの信号が読み出され、かつ時刻ｔ３００に読み出しは完了する。この読み出しが終了した後、再び各画素Ｐの露光が行われる。この露光が終了した後、時刻ｔ４００において行選択信号ＲＳＥＬ＜１＞が“Ｌ”から“Ｈ”に切り替わることにより、１行目の画素Ｐ［１，１］～Ｐ［１，ｎ］からの読み出しが再び開始される。 The row selection signal RSEL <1> switches from “H” to “L” at time t101 (corresponding to time t10) after the readout from the pixel P [1, n] in the first row and the nth column is completed. At the same time, the row selection signal RSEL <2> switches from “L” to “H”. Thereafter, signals from the pixels P from the pixel P [2, 1] in the second row and the first column to the pixel P [2, n] in the second row and the nth column pass through the column circuits COL <1> to COL <n>. It is read out. Thereafter, similarly, the signals from the pixels P in the third to m-th rows are read out, and the reading is completed at time t300. After this readout is completed, exposure of each pixel P is performed again. After this exposure is completed, the row selection signal RSEL <1> changes from “L” to “H” at time t400, whereby the pixels P [1,1] to P [1, n] The reading is started again.
　上記のように、イメージセンサＩＭＧは、ＡＤ変換回路ＡＤＣａと、複数の画素Ｐと、複数の列回路ＣＯＬとを少なくとも有する。複数の画素Ｐは、行列状に配置されている。複数の列回路ＣＯＬは、複数の画素Ｐの列毎に配置されている。複数の画素Ｐの奇数列に配置された列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ－１＞から出力された信号すなわち映像信号ＶＳＩＧは、奇数ＡＤ変換器ＡＤＣＯおよび偶数ＡＤ変換器ＡＤＣＥのいずれか１つすなわち奇数ＡＤ変換器ＡＤＣＯに入力される。複数の画素Ｐの偶数列に配置された列回路ＣＯＬ＜２＞～ＣＯＬ＜ｎ＞から出力された信号は、奇数ＡＤ変換器ＡＤＣＯおよび偶数ＡＤ変換器ＡＤＣＥのうち偶数列に配置された列回路ＣＯＬ＜２＞～ＣＯＬ＜ｎ＞から出力された信号すなわち映像信号ＶＳＩＧが入力される奇数ＡＤ変換器ＡＤＣＯと異なる偶数ＡＤ変換器ＡＤＣＥに入力される。 As described above, the image sensor IMG at least includes the AD conversion circuit ADCa, the plurality of pixels P, and the plurality of column circuits COL. The plurality of pixels P are arranged in a matrix. The plurality of column circuits COL are arranged for each column of the plurality of pixels P. The video signal VSIG output from the column circuits COL <1> to COL <n-1> arranged in the odd columns of the plurality of pixels P is either one of the odd AD converter ADCO and the even AD converter ADCE. Or the odd AD converter ADCO. The signals output from the column circuits COL <2> to COL <n> arranged in the even columns of the plurality of pixels P are the column circuits arranged in the even columns among the odd AD converter ADCO and the even AD converter ADCE. The signals output from COL <2> to COL <n>, that is, the video signal VSIG are input to an even AD converter ADCE different from the odd AD converter ADCO.
　図１０を用いて、ＡＤ変換回路ＡＤＣａの構成について説明する。図１０は、ＡＤ変換回路ＡＤＣａの構成を示す。 The configuration of the AD conversion circuit ADCa will be described with reference to FIG. FIG. 10 shows the configuration of the AD conversion circuit ADCa.
　ＡＤ変換回路ＡＤＣａの概略構成について説明する。ＡＤ変換回路ＡＤＣａは、奇数ＡＤ変換器ＡＤＣＯと、偶数ＡＤ変換器ＡＤＣＥと、容量アレーＣＤＡＣＣとを有する。奇数ＡＤ変換器ＡＤＣＯは、ＤＡＣ回路ＣＤＡＣＯと、比較器ＣＭＰＯと、制御回路ＳＡＲＬＯＧＩＣＯとを有する。偶数ＡＤ変換器ＡＤＣＥは、ＤＡＣ回路ＣＤＡＣＥと、比較器ＣＭＰＥと、制御回路ＳＡＲＬＯＧＩＣＥとを有する。奇数ＡＤ変換器ＡＤＣＯおよび容量アレーＣＤＡＣＣは、第１のＡＤ変換器を構成する。偶数ＡＤ変換器ＡＤＣＥおよび容量アレーＣＤＡＣＣは、第２のＡＤ変換器を構成する。つまり、ＡＤ変換回路ＡＤＣａは、２つのシングルエンド型ＡＤ変換器を有する。第１のＡＤ変換器および第２のＡＤ変換器は、固定容量である容量アレーＣＤＡＣＣを共有する。 The schematic configuration of the AD conversion circuit ADCa will be described. The AD conversion circuit ADCa includes an odd AD converter ADCO, an even AD converter ADCE, and a capacitance array CDACC. The odd AD converter ADCO has a DAC circuit CDACO, a comparator CMPO, and a control circuit SARLOGICO. The even AD converter ADCE has a DAC circuit CDACE, a comparator CMPE, and a control circuit SARLOGICE. The odd AD converter ADCO and the capacitance array CDACC constitute a first AD converter. The even AD converter ADCE and the capacitance array CDACC constitute a second AD converter. That is, the AD conversion circuit ADCa includes two single-ended AD converters. The first AD converter and the second AD converter share a fixed capacity capacitance array CDACC.
　第１のＡＤ変換器は、第２のＡＤ変換器によるＡＤ変換動作（第２の動作）と並行してサンプリング動作（第１の動作）を行い、かつ第２のＡＤ変換器は、第１のＡＤ変換器によるサンプリング動作と並行してＡＤ変換動作を行う。サンプリング動作において、映像信号ＶＳＩＧ１がＤＡＣ回路ＣＤＡＣＯにサンプリングされ、かつ基準信号ＶＣＭが容量Ｃ１Ｃ～Ｃ６Ｃにサンプリングされる。あるいは、サンプリング動作において、映像信号ＶＳＩＧ２がＤＡＣ回路ＣＤＡＣＥにサンプリングされ、かつ基準信号ＶＣＭが容量Ｃ１Ｃ～Ｃ６Ｃにサンプリングされる。ＡＤ変換動作において、サンプリング動作によりサンプリングされた映像信号ＶＳＩＧ１および基準信号ＶＣＭのそれぞれの電圧に基づいて順次ＡＤ変換が行われる。第１のＡＤ変換器および第２のＡＤ変換器は、サンプリング動作およびＡＤ変換動作を交互に行う。 The first AD converter performs a sampling operation (first operation) in parallel with the AD conversion operation (second operation) by the second AD converter, and the second AD converter performs the first operation. In parallel with the sampling operation by the AD converter, the AD conversion operation is performed. In the sampling operation, the video signal VSIG1 is sampled by the DAC circuit CDACO, and the reference signal VCM is sampled by the capacitors C1C to C6C. Alternatively, in the sampling operation, the video signal VSIG2 is sampled by the DAC circuit CDACE, and the reference signal VCM is sampled by the capacitors C1C to C6C. In the AD conversion operation, AD conversion is sequentially performed based on the voltages of the video signal VSIG1 sampled by the sampling operation and the reference signal VCM. The first AD converter and the second AD converter alternately perform the sampling operation and the AD conversion operation.
　第１のＡＤ変換器および第２のＡＤ変換器は、サンプリング動作とＡＤ変換動作とを切り替える間に、サンプリング動作を行う期間およびＡＤ変換動作を行う期間よりも短い期間で、容量Ｃ１Ｃ～Ｃ６Ｃにサンプリングされた基準信号ＶＣＭの電圧をリセットするリセット動作（第３の動作）を行う。 While switching between the sampling operation and the AD conversion operation, the first AD converter and the second AD converter have capacitances C1C to C6C in a period shorter than the period for performing the sampling operation and the period for performing the AD conversion operation. A reset operation (third operation) for resetting the voltage of the sampled reference signal VCM is performed.
　ＡＤ変換回路ＡＤＣａの詳細な構成について説明する。奇数ＡＤ変換器ＡＤＣＯおよび容量アレーＣＤＡＣＣの構成は、第１の実施形態におけるそれぞれの構成と同一である。 The detailed configuration of the AD conversion circuit ADCa will be described. The configurations of the odd AD converter ADCO and the capacitance array CDACC are the same as the respective configurations in the first embodiment.
　偶数ＡＤ変換器ＡＤＣＥは、奇数ＡＤ変換器ＡＤＣＯと同様に構成されている。ＤＡＣ回路ＣＤＡＣＥは、ＤＡＣ回路ＣＤＡＣＯと同様に構成されている。ＤＡＣ回路ＣＤＡＣＥは、容量Ｃ１Ｅ～Ｃ６Ｅと、スイッチＳＷ１Ｅ～ＳＷ６Ｅと、サンプルスイッチＳＷＳＭＰＬＥとを有する。 The even AD converter ADCE is configured in the same manner as the odd AD converter ADCO. The DAC circuit CDACE is configured similarly to the DAC circuit CDACO. The DAC circuit CDACE has capacitors C1E to C6E, switches SW1E to SW6E, and a sample switch SWSMPLE.
　サンプルスイッチＳＷＳＭＰＬＥは、サンプルスイッチＳＷＳＭＰＬＯと同様に構成されている。サンプルスイッチＳＷＳＭＰＬＥの状態は、制御信号ＳＭＰＬＥによって制御される。サンプルスイッチＳＷＳＭＰＬＥは、信号源ＳＩＧ＿ＥＶＥＮからの映像信号ＶＳＩＧ２をサンプリングする。 The sample switch SWSMPLE is configured in the same manner as the sample switch SWSMPLO. The state of the sample switch SWSMPLE is controlled by the control signal SMPLE. The sample switch SWSMPLE samples the video signal VSIG2 from the signal source SIG_EVEN.
　容量Ｃ１Ｅ～Ｃ６Ｅは、容量Ｃ１Ｏ～Ｃ６Ｏと同様に構成されている。複数の容量Ｃ１Ｅ～Ｃ６Ｅの容量値の合計と、複数の容量Ｃ１Ｃ～Ｃ６Ｃの容量値の合計とは、略同一である。容量Ｃ１Ｅ～Ｃ６Ｅは、サンプルスイッチＳＷＳＭＰＬＥによってサンプリングされた映像信号ＶＳＩＧ２を保持する。 The capacitors C1E to C6E are configured in the same manner as the capacitors C1O to C6O. The sum of capacitance values of the plurality of capacitances C1E to C6E and the sum of capacitance values of the plurality of capacitances C1C to C6C are substantially the same. The capacitors C1E to C6E hold the video signal VSIG2 sampled by the sample switch SWSMPLE.
　スイッチＳＷ１Ｅ～ＳＷ６Ｅは、スイッチＳＷ１Ｏ～ＳＷ６Ｏと同様に構成されている。スイッチＳＷ１Ｅ～ＳＷ６Ｅの状態は、ＡＤ変換結果のビットＤＥ１～ＤＥ６によって制御される。 The switches SW1E to SW6E are configured in the same manner as the switches SW1O to SW6O. The states of the switches SW1E to SW6E are controlled by bits DE1 to DE6 of the AD conversion result.
　ＤＡＣ回路ＣＤＡＣＥは、信号源ＳＩＧ＿ＥＶＥＮに接続されている。信号源ＳＩＧ＿ＥＶＥＮによって生成された映像信号ＶＳＩＧ２は、ノードＶＩＥに供給される。信号源ＳＩＧ＿ＥＶＥＮは、図７に示す撮像部ＰＩＸと偶数列の列回路ＣＯＬ＜２＞～ＣＯＬ＜ｎ＞とに対応する。また、信号源ＳＩＧ＿ＯＤＤは、図７に示す撮像部ＰＩＸと奇数列の列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ－１＞とに対応する。 The DAC circuit CDACE is connected to the signal source SIG_EVEN. The video signal VSIG2 generated by the signal source SIG_EVEN is supplied to the node VIE. The signal source SIG_EVEN corresponds to the imaging unit PIX shown in FIG. 7 and the column circuits COL <2> to COL <n> of the even columns. Further, the signal source SIG_ODD corresponds to the imaging unit PIX and the column circuits COL <1> to COL <n−1> in odd columns shown in FIG.
　チャージサミングノードであるノードＶＩＥは、サンプルスイッチＳＷＳＭＰＬＥの第２の端子と、容量Ｃ１Ｅ～Ｃ６Ｅの第１の電極と、比較器ＣＭＰＥの第１の入力端子とに接続されている。ノードＶＩＥは、これらに電気的に接続された信号線上の任意の位置である。 The node VIE, which is a charge summing node, is connected to the second terminal of the sample switch SWSMPLE, the first electrodes of the capacitors C1E to C6E, and the first input terminal of the comparator CMPE. The node VIE is an arbitrary position on the signal line electrically connected to them.
　比較器ＣＭＰＥは、比較器ＣＭＰＯと同様に構成されている。比較器ＣＭＰＥは、ノードＶＩＥの電圧とノードＶＩＣの電圧とを比較する。比較器ＣＭＰＥは、比較結果に基づく信号ＶＯＮＥを第１の出力端子から出力し、かつ比較結果に基づく信号ＶＯＰＥを第２の出力端子から出力する。 The comparator CMPE is configured in the same manner as the comparator CMPO. The comparator CMPE compares the voltage of the node VIE with the voltage of the node VIC. The comparator CMPE outputs a signal VONE based on the comparison result from the first output terminal, and outputs a signal VOPE based on the comparison result from the second output terminal.
　制御回路ＳＡＲＬＯＧＩＣＥは、制御回路ＳＡＲＬＯＧＩＣＯと同様に構成されている。制御回路ＳＡＲＬＯＧＩＣＥは、比較器ＣＭＰＥからの信号ＶＯＰＥおよび信号ＶＯＮＥに基づいてＡＤ変換結果のデジタル信号ＤＥ［６：１］を生成し、かつデジタル信号ＤＥ［６：１］を出力端子から出力する。 The control circuit SARLOGICE is configured in the same manner as the control circuit SARLOGICO. Control circuit SARLOGICE generates digital signal DE [6: 1] of the AD conversion result based on signal VOPE and signal VONE from comparator CMPE, and outputs digital signal DE [6: 1] from the output terminal.
　デジタル信号ＤＥ［６：１］を構成するビットＤＥ１～ＤＥ６は、ＤＡＣ回路ＣＤＡＣＥのスイッチＳＷ１Ｅ～ＳＷ６Ｅに出力される。制御回路ＳＡＲＬＯＧＩＣＥは、ビットＤＥ１～ＤＥ６をスイッチＳＷ１Ｅ～ＳＷ６Ｅに出力することにより、ＤＡＣ回路ＣＤＡＣＥを制御する。 The bits DE1 to DE6 constituting the digital signal DE [6: 1] are output to the switches SW1E to SW6E of the DAC circuit CDACE. The control circuit SARLOGICE controls the DAC circuit CDACE by outputting the bits DE1 to DE6 to the switches SW1E to SW6E.
　図１１を用いてＡＤ変換回路ＡＤＣａの動作について説明する。図１１は、ＡＤ変換回路ＡＤＣａの動作に関する信号を示す。図１１において、ＤＡＣ回路ＣＤＡＣＯの状態と、ＤＡＣ回路ＣＤＡＣＥの状態とが示されている。図１１において、制御信号ＳＭＰＬＯと、制御信号ＳＭＰＬＥと、制御信号ＳＭＰＬＣとが示されている。図１１において、デジタル信号ＤＯ［６：１］およびデジタル信号ＤＥ［６：１］が１６進数で示されている。図１１において、ノードＶＩＯと、ノードＶＩＥと、ノードＶＩＣとの各々の電位が示されている。図１１において、横軸は時間を示し、かつ縦軸は信号レベルを示す。 The operation of the AD conversion circuit ADCa will be described with reference to FIG. FIG. 11 shows signals related to the operation of the AD conversion circuit ADCa. In FIG. 11, the state of the DAC circuit CDACO and the state of the DAC circuit CDACE are shown. In FIG. 11, a control signal SMPLO, a control signal SMPLE, and a control signal SMPLC are shown. In FIG. 11, the digital signal DO [6: 1] and the digital signal DE [6: 1] are shown in hexadecimal. In FIG. 11, the respective potentials of node VIO, node VIE and node VIC are shown. In FIG. 11, the horizontal axis indicates time, and the vertical axis indicates signal level.
　期間Ｔ１において、ＡＤ変換回路ＡＤＣａはリセット動作を行う。期間Ｔ１において、スイッチＳＷＳＭＰＬＯがオンであるため、映像信号ＶＳＩＧ１が信号源ＳＩＧ＿ＯＤＤからノードＶＩＯに入力される。また、期間Ｔ１において、スイッチＳＷＳＭＰＬＥがオンであるため、映像信号ＶＳＩＧ２が信号源ＳＩＧ＿ＥＶＥＮからノードＶＩＥに入力される。また、期間Ｔ１において、スイッチＳＷＳＭＰＬＣがオンであるため、基準信号ＶＣＭが基準信号源ＶＣＭ＿ＧからノードＶＩＣに入力される。期間Ｔ１において、ノードＶＩＯの電圧は映像信号ＶＳＩＧ１の電圧に保たれ、ノードＶＩＥの電圧は映像信号ＶＳＩＧ２の電圧に保たれ、かつノードＶＩＣの電圧は基準信号ＶＣＭの電圧に保たれる。期間Ｔ１において、映像信号ＶＳＩＧ１に基づく電荷が容量Ｃ１Ｏ～Ｃ６Ｏに保持され、映像信号ＶＳＩＧ２に基づく電荷が容量Ｃ１Ｅ～Ｃ６Ｅに保持され、かつ基準信号ＶＣＭに基づく電荷が容量Ｃ１Ｃ～Ｃ６Ｃに保持される。基準信号ＶＣＭが容量Ｃ１Ｃ～Ｃ６Ｃにサンプリングされることにより、容量Ｃ１Ｃ～Ｃ６Ｃにおける基準信号ＶＣＭの電圧はリセットされる。 In the period T1, the AD conversion circuit ADCa performs a reset operation. In the period T1, since the switch SWSMPLO is on, the video signal VSIG1 is input from the signal source SIG_ODD to the node VIO. Further, in the period T1, since the switch SWSMPLE is on, the video signal VSIG2 is input from the signal source SIG_EVEN to the node VIE. Further, in the period T1, since the switch SWSMPLC is on, the reference signal VCM is input from the reference signal source VCM_G to the node VIC. In period T1, the voltage of node VIO is kept at the voltage of video signal VSIG1, the voltage of node VIE is kept at the voltage of video signal VSIG2, and the voltage of node VIC is kept at the voltage of reference signal VCM. In period T1, charges based on video signal VSIG1 are held in capacitors C1O to C6O, charges based on video signal VSIG2 are held in capacitors C1E to C6E, and charges based on reference signal VCM are held in capacitors C1C to C6C . By sampling the reference signal VCM into the capacitors C1C to C6C, the voltage of the reference signal VCM in the capacitors C1C to C6C is reset.
　期間Ｔ２から期間Ｔ７において、奇数ＡＤ変換器ＡＤＣＯは、サンプリング動作ＳＡＭＰを行うことにより、ＤＡＣ回路ＣＤＡＣＯに入力される信号のサンプリングを行う。期間Ｔ２から期間Ｔ７において、スイッチＳＷＳＭＰＬＯがオンであるため、映像信号ＶＳＩＧ１が信号源ＳＩＧ＿ＯＤＤからノードＶＩＯに入力される。 In the period T2 to the period T7, the odd number AD converter ADCO performs sampling operation SAMP to sample the signal input to the DAC circuit CDACO. In the period T2 to the period T7, since the switch SWSMPLO is on, the video signal VSIG1 is input from the signal source SIG_ODD to the node VIO.
　期間Ｔ２から期間Ｔ７において、“Ｈ”であるビットＤＯ１～ＤＯ６がスイッチＳＷ１Ｏ～ＳＷ６Ｏに入力される。期間Ｔ２から期間Ｔ７において、スイッチＳＷ１Ｏ～ＳＷ６Ｏの各々の第１の端子Ｓ１と第３の端子Ｄとが接続される。期間Ｔ２から期間Ｔ７において、ノードＶＩＯの電圧は映像信号ＶＳＩＧ１の電圧に保たれる。 In the period T2 to the period T7, the bits DO1 to DO6 which are "H" are input to the switches SW1O to SW6O. In the period T2 to the period T7, the first terminal S1 and the third terminal D of each of the switches SW1O to SW6O are connected. In the period T2 to the period T7, the voltage of the node VIO is maintained at the voltage of the video signal VSIG1.
　期間Ｔ２から期間Ｔ７において、偶数ＡＤ変換器ＡＤＣＥは、ＡＤ変換動作ＣＯＮＶを行うことにより、ＤＡＣ回路ＣＤＡＣＥにサンプリングされた信号のＡＤ変換を行う。期間Ｔ２から期間Ｔ７において、スイッチＳＷＳＭＰＬＥがオフであるため、ノードＶＩＥに対する、信号源ＳＩＧ＿ＥＶＥＮからの映像信号ＶＳＩＧ２の入力は停止される。また、期間Ｔ２から期間Ｔ７において、スイッチＳＷＳＭＰＬＣがオフであるため、ノードＶＩＣに対する、基準信号源ＶＣＭ＿Ｇからの基準信号ＶＣＭの入力は停止される。 In the period T2 to the period T7, the even AD converter ADCE performs AD conversion operation CONV to perform AD conversion of the signal sampled in the DAC circuit CDACE. In the period T2 to the period T7, since the switch SWSMPLE is off, the input of the video signal VSIG2 from the signal source SIG_EVEN to the node VIE is stopped. Further, in the period T2 to the period T7, since the switch SWSMPLC is off, the input of the reference signal VCM from the reference signal source VCM_G to the node VIC is stopped.
　期間Ｔ２から期間Ｔ７は、ＤＡＣ回路ＣＤＡＣＥに保持された電荷に基づいて偶数ＡＤ変換器ＡＤＣＥ（比較器ＣＭＰＥ）がＭＳＢからＬＳＢの比較を行うための期間に対応する。期間Ｔ２において、比較器ＣＭＰＥはノードＶＩＥおよびノードＶＩＣの電圧を比較する。この比較により、ＡＤ変換結果の最上位ビットＤＥ６の論理が確定する。比較器ＣＭＰＥは、比較結果を制御回路ＳＡＲＬＯＧＩＣＥに出力する。期間Ｔ３において、制御回路ＳＡＲＬＯＧＩＣＥは、期間Ｔ２における比較結果に応じたビットＤＥ６を出力する。ビットＤＥ６に対する判定結果がＶＩＣ＜ＶＩＥである場合、ビットＤＥ６の論理レベルは“Ｌ”である。説明の便宜のため、ノードＶＩＥの電圧はＶＩＥと表され、かつノードＶＩＣの電圧はＶＩＣと表される。ビットＤＥ６に対する判定結果がＶＩＣ＞ＶＩＥである場合、ビットＤＥ６の論理レベルは“Ｈ”である。２番目以降のビットＤＥｉにおける判定結果がＶＩＣ＜ＶＩＥである場合、ビットＤＥｉの論理レベルは“Ｌ”に設定される。ビットＤＥｉにおける判定結果がＶＩＣ＞ＶＩＥである場合、ビットＤＥｉの論理レベルは“Ｌ”に設定され、かつ１つ前のビットＤＥ（ｉ＋１）の論理レベルが“Ｈ”に設定される。ｉは、１から５のいずれかの整数である。 The period T2 to the period T7 correspond to a period for the even AD converter ADCE (comparator CMPE) to compare MSB to LSB based on the charge held in the DAC circuit CDACE. In period T2, comparator CMPE compares the voltages of node VIE and node VIC. This comparison determines the logic of the most significant bit DE6 of the AD conversion result. The comparator CMPE outputs the comparison result to the control circuit SARLOGICE. In period T3, control circuit SARLOGICE outputs bit DE6 according to the comparison result in period T2. When the determination result for bit DE6 is VIC <VIE, the logic level of bit DE6 is "L". For convenience of explanation, the voltage of the node VIE is denoted as VIE and the voltage of the node VIC is denoted as VIC. If the determination result for bit DE6 is VIC> VIE, the logic level of bit DE6 is "H". When the determination result in the second and subsequent bits DEi is VIC <VIE, the logic level of the bit DEi is set to “L”. If the determination result in bit DEi is VIC> VIE, the logic level of bit DEi is set to “L”, and the logic level of the immediately preceding bit DE (i + 1) is set to “H”. i is an integer of 1 to 5;
　図１１に示す例の期間Ｔ２において、ノードＶＩＥの電圧がノードＶＩＣの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＥは、ビットＤＥ６の論理を“Ｌ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＥ［６：１］は３Ｆ（１１１１１１）から１Ｆ（０１１１１１１）に変化する。期間Ｔ３において、ビットＤＥ６の論理レベルは、スイッチＳＷＥ６に出力される。このため、スイッチＳＷＥ６は、第２の端子Ｓ２と第３の端子Ｄとが接続された状態に切り替わる。これにより、グランドレベルが容量Ｃ６Ｅの第２の電極に入力される。容量Ｃ１Ｅ～Ｃ６Ｅに蓄積されている電荷の総量が保存された状態でスイッチＳＷＥ６の状態が変化することにより、ノードＶＩＥの電位は（１／２１）ＶＲＥＦだけ低下する。 In period T2 of the example shown in FIG. 11, since the voltage of node VIE is higher than the voltage of node VIC, control circuit SARLOGICE sets the logic of bit DE6 to "L". As a result, the digital signal DE [6: 1] expressed in hexadecimal changes from 3F (111111) to 1F (0111111). In period T3, the logic level of bit DE6 is output to switch SWE6. Therefore, the switch SWE6 is switched to the state in which the second terminal S2 and the third terminal D are connected. Thereby, the ground level is input to the second electrode of the capacitor C6E. By changing the state of the switch SWE6 in a state where the total amount of charges accumulated in the capacitors C1E to C6E is stored, the potential of the node VIE decreases by (1/2 1 ) VREF.
　ノードＶＩＥの電位の変動が安定した後、期間Ｔ３において、比較器ＣＭＰＥは、ビットＤＥ５の論理レベルを判定するためにノードＶＩＥおよびノードＶＩＣの電圧を比較する。期間Ｔ３において、ノードＶＩＣの電圧がノードＶＩＥの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＥは、ビットＤＥ５の論理を“Ｌ”に設定し、かつビットＤＥ６の論理を“Ｈ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＥ［６：１］は１Ｆ（０１１１１１）から２Ｆ（１０１１１１）に変化する。期間Ｔ４において、ビットＤＥ６の論理レベルはスイッチＳＷ６Ｅに出力され、かつビットＤＥ５の論理レベルは、スイッチＳＷ５Ｅに出力される。このため、スイッチＳＷ６Ｅは、第１の端子Ｓ１と第３の端子Ｄとが接続された状態に切り替わる。これにより、基準電圧ＶＲＥＦが容量Ｃ６Ｅの第２の電極に入力される。スイッチＳＷ５Ｅは、第２の端子Ｓ２と第３の端子Ｄとが接続された状態に切り替わる。これにより、グランドレベルが容量Ｃ５Ｅの第２の電極に入力される。容量Ｃ１Ｅ～Ｃ６Ｅに蓄積されている電荷の総量が保存された状態で、スイッチＳＷ６ＥおよびスイッチＳＷ５Ｅの状態が変化することにより、ノードＶＩＥの電位は（１／２２）ＶＲＥＦだけ増加する。 After the fluctuation of the potential of the node VIE is stabilized, in period T3, the comparator CMPE compares the voltages of the node VIE and the node VIC to determine the logic level of the bit DE5. In period T3, since the voltage of node VIC is higher than the voltage of node VIE, control circuit SARLOGICE sets the logic of bit DE5 to "L" and the logic of bit DE6 to "H". As a result, the digital signal DE [6: 1] expressed in hexadecimal changes from 1F (011111) to 2F (101111). In period T4, the logic level of bit DE6 is output to switch SW6E, and the logic level of bit DE5 is output to switch SW5E. Therefore, the switch SW6E is switched to the state in which the first terminal S1 and the third terminal D are connected. Thus, the reference voltage VREF is input to the second electrode of the capacitor C6E. The switch SW5E switches to a state in which the second terminal S2 and the third terminal D are connected. Thus, the ground level is input to the second electrode of the capacitor C5E. With the total amount of charges accumulated in the capacitors C1E to C6E being stored, the state of the switches SW6E and SW5E changes, whereby the potential of the node VIE increases by (1/2 2 ) VREF.
　ノードＶＩＥの電位の変動が安定した後、期間Ｔ４において、比較器ＣＭＰＥは、ビットＤＥ４の論理レベルを判定するためにノードＶＩＥおよびノードＶＩＣの電圧を比較する。期間Ｔ４において、ノードＶＩＥの電圧がノードＶＩＣの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＥは、ビットＤＥ４の論理を“Ｌ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＥ［６：１］は２Ｆ（１０１１１１）から２７（１００１１１）に変化する。期間Ｔ５において、ビットＤＥ４の論理レベルは、スイッチＳＷ４Ｅに出力される。このため、スイッチＳＷ４Ｅは、第２の端子Ｓ２と第３の端子Ｄとが接続された状態に切り替わる。これにより、グランドレベルが容量Ｃ４Ｅの第２の電極に入力される。容量Ｃ１Ｅ～Ｃ６Ｅに蓄積されている電荷の総量が保存された状態で、スイッチＳＷ４Ｅの状態が変化することにより、ノードＶＩＥの電位は（１／２３）ＶＲＥＦだけ低下する。 After the fluctuation of the potential of the node VIE is stabilized, in period T4, the comparator CMPE compares the voltages of the node VIE and the node VIC to determine the logic level of the bit DE4. In period T4, since the voltage of node VIE is higher than the voltage of node VIC, control circuit SARLOGICE sets the logic of bit DE4 to "L". As a result, the digital signal DE [6: 1] expressed in hexadecimal changes from 2F (101111) to 27 (100111). In the period T5, the logic level of the bit DE4 is output to the switch SW4E. Therefore, the switch SW4E is switched to the state in which the second terminal S2 and the third terminal D are connected. Thus, the ground level is input to the second electrode of the capacitor C4E. With the total amount of charges accumulated in the capacitors C1E to C6E being stored, the state of the switch SW4E changes, whereby the potential of the node VIE decreases by (1/2 3 ) VREF.
　ノードＶＩＥの電位の変動が安定した後、期間Ｔ５において、比較器ＣＭＰＥは、ビットＤＥ３の論理レベルを判定するためにノードＶＩＥおよびノードＶＩＣの電圧を比較する。期間Ｔ５において、ノードＶＩＣの電圧がノードＶＩＥの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＥは、ビットＤＥ３の論理を“Ｌ”に設定し、かつビットＤＥ４の論理を“Ｈ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＥ［６：１］は２７（１００１１１）から２Ｂ（１０１０１１）に変化する。期間Ｔ６において、ビットＤＥ４の論理レベルはスイッチＳＷ４Ｅに出力され、かつビットＤＥ３の論理レベルは、スイッチＳＷ３Ｅに出力される。このため、スイッチＳＷ４Ｅは、第１の端子Ｓ１と第３の端子Ｄとが接続された状態に切り替わる。これにより、基準電圧ＶＲＥＦが容量Ｃ４Ｅの第２の電極に入力される。スイッチＳＷ３Ｅは、第２の端子Ｓ２と第３の端子Ｄとが接続された状態に切り替わる。これにより、グランドレベルが容量Ｃ３Ｅの第２の電極に入力される。容量Ｃ１Ｅ～Ｃ６Ｅに蓄積されている電荷の総量が保存された状態で、スイッチＳＷ４ＥおよびスイッチＳＷ３Ｅの状態が変化することにより、ノードＶＩＥの電位は（１／２４）ＶＲＥＦだけ増加する。 After the fluctuation of the potential of the node VIE is stabilized, in period T5, the comparator CMPE compares the voltages of the node VIE and the node VIC to determine the logic level of the bit DE3. In period T5, since the voltage of node VIC is higher than the voltage of node VIE, control circuit SARLOGICE sets the logic of bit DE3 to "L" and sets the logic of bit DE4 to "H". As a result, the digital signal DE [6: 1] expressed in hexadecimal changes from 27 (100111) to 2B (101011). In period T6, the logic level of bit DE4 is output to switch SW4E, and the logic level of bit DE3 is output to switch SW3E. Therefore, the switch SW4E is switched to the state in which the first terminal S1 and the third terminal D are connected. Thereby, the reference voltage VREF is input to the second electrode of the capacitor C4E. The switch SW3E switches to a state in which the second terminal S2 and the third terminal D are connected. As a result, the ground level is input to the second electrode of the capacitor C3E. With the total amount of charges accumulated in the capacitors C1E to C6E being stored, the state of the switches SW4E and SW3E changes, whereby the potential of the node VIE increases by (1/2 4 ) VREF.
　ノードＶＩＥの電位の変動が安定した後、期間Ｔ６において、比較器ＣＭＰＥは、ビットＤＥ２の論理レベルを判定するためにノードＶＩＥおよびノードＶＩＣの電圧を比較する。期間Ｔ６において、ノードＶＩＥの電圧がノードＶＩＣの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＥは、ビットＤＥ２の論理を“Ｌ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＥ［６：１］は２Ｂ（１０１０１１）から２９（１０１００１）に変化する。期間Ｔ７において、ビットＤＥ２の論理レベルは、スイッチＳＷ２Ｅに出力される。このため、スイッチＳＷ２Ｅは、第２の端子Ｓ２と第３の端子Ｄとが接続された状態に切り替わる。これにより、グランドレベルが容量Ｃ２Ｅの第２の電極に入力される。容量Ｃ１Ｅ～Ｃ６Ｅに蓄積されている電荷の総量が保存された状態で、スイッチＳＷ２Ｅの状態が変化することにより、ノードＶＩＥの電位は（１／２５）ＶＲＥＦだけ低下する。 After the fluctuation of the potential of the node VIE is stabilized, in period T6, the comparator CMPE compares the voltages of the node VIE and the node VIC to determine the logic level of the bit DE2. In period T6, since the voltage of node VIE is higher than the voltage of node VIC, control circuit SARLOGICE sets the logic of bit DE2 to "L". As a result, the digital signal DE [6: 1] expressed in hexadecimal changes from 2B (101011) to 29 (101001). In the period T7, the logic level of the bit DE2 is output to the switch SW2E. Thus, the switch SW2E switches to a state in which the second terminal S2 and the third terminal D are connected. As a result, the ground level is input to the second electrode of the capacitor C2E. With the total amount of charges stored in the capacitors C1E to C6E being stored, the state of the switch SW2E changes, whereby the potential of the node VIE decreases by (1/2 5 ) VREF.
　ノードＶＩＥの電位の変動が安定した後、期間Ｔ７において、比較器ＣＭＰＥは、ビットＤＥ１の論理レベルを判定するためにノードＶＩＥおよびノードＶＩＣの電圧を比較する。期間Ｔ７において、ノードＶＩＥの電圧がノードＶＩＣの電圧よりも高いため、制御回路ＳＡＲＬＯＧＩＣＥは、ビットＤＥ１の論理を“Ｌ”に設定する。この結果、１６進数で表記されたデジタル信号ＤＥ［６：１］は２９（１０１００１）から２８（１０１０００）に変化する。このようにして得られたデジタル信号ＤＥ［６：１］は、外部の信号処理システムで利用される。 After the fluctuation of the potential of the node VIE is stabilized, in period T7, the comparator CMPE compares the voltages of the node VIE and the node VIC to determine the logic level of the bit DE1. In period T7, since the voltage of node VIE is higher than the voltage of node VIC, control circuit SARLOGICE sets the logic of bit DE1 to "L". As a result, the digital signal DE [6: 1] expressed in hexadecimal changes from 29 (101001) to 28 (101000). The digital signal DE [6: 1] obtained in this manner is used in an external signal processing system.
　期間Ｔ７における判定結果は、スイッチＳＷ１Ｅの制御に使用されない。スイッチＳＷ１Ｅには、常に“Ｈ”である制御信号が入力されてもよい。 The determination result in the period T7 is not used to control the switch SW1E. A control signal that is always “H” may be input to the switch SW1E.
　期間Ｔ１’における動作は、期間Ｔ１における動作と同様である。期間Ｔ１’において、ＡＤ変換回路ＡＤＣａはリセット動作を行う。 The operation in the period T1 'is similar to the operation in the period T1. In the period T1 ', the AD conversion circuit ADCa performs a reset operation.
　期間Ｔ２’から期間Ｔ７’において、奇数ＡＤ変換器ＡＤＣＯは、ＡＤ変換動作ＣＯＮＶを行うことにより、ＤＡＣ回路ＣＤＡＣＯにサンプリングされた信号のＡＤ変換を行う。期間Ｔ２’から期間Ｔ７’において、偶数ＡＤ変換器ＡＤＣＥは、サンプリング動作ＳＡＭＰを行うことにより、ＤＡＣ回路ＣＤＡＣＥに入力される信号のサンプリングを行う。デジタル信号ＤＯ［６：１］は、外部の信号処理システムで利用される。期間Ｔ２’から期間Ｔ７’において、上記の動作以外の動作は、期間Ｔ２から期間Ｔ７における動作と同様である。 In the period T2 'to the period T7', the odd AD converter ADCO performs AD conversion operation CONV to perform AD conversion of the signal sampled in the DAC circuit CDACO. In the period T2 'to the period T7', the even AD converter ADCE performs sampling operation SAMP to sample the signal input to the DAC circuit CDACE. The digital signal DO [6: 1] is used in an external signal processing system. In the period T2 'to the period T7', operations other than the above-described operation are similar to the operations in the period T2 to the period T7.
　本発明の各態様のイメージセンサは、複数の画素、複数の列回路、およびＡＤ変換器以外の構成を有していなくてもよい。 The image sensor according to each aspect of the present invention may not have a configuration other than the plurality of pixels, the plurality of column circuits, and the AD converter.
　第２の実施形態のＡＤ変換回路ＡＤＣａにおいて、２つのＡＤ変換器のいずれか１つがＡＤ変換動作を行う期間に、他方のＡＤ変換器はサンプリング動作を行う。このように、ＡＤ変換回路ＡＤＣａの２つのＡＤ変換器がサンプリング動作とＡＤ変換動作とを同時に行うことができる。このため、ＡＤ変換の速度は約２倍になる。つまり、ＡＤ変換回路ＡＤＣａは、ＡＤ変換を高速に行うことができる。キックバックノイズを緩和するための固定容量である容量アレーＣＤＡＣＣが２つのＡＤ変換器で共有されるため、固定容量を実装するために必要なチップ面積を抑えることができる。したがって、高速かつ高精度であり、さらに小型なＡＤ変換回路を実現することができる。 In the AD converter circuit ADCa of the second embodiment, the other AD converter performs a sampling operation while any one of two AD converters performs an AD conversion operation. Thus, the two AD converters of the AD conversion circuit ADCa can perform the sampling operation and the AD conversion operation simultaneously. Therefore, the speed of AD conversion is approximately doubled. That is, the AD conversion circuit ADCa can perform AD conversion at high speed. Since the capacitance array CDACC, which is a fixed capacitance for alleviating kickback noise, is shared by two AD converters, it is possible to reduce the chip area required for mounting the fixed capacitance. Therefore, it is possible to realize a high speed, high accuracy, and further compact AD conversion circuit.
　第２の実施形態のイメージセンサＩＭＧが有するＡＤ変換回路ＡＤＣａは、高速および高精度にＡＤ変換を行うことができる。また、ＡＤ変換回路ＡＤＣａは小型であり、かつ消費電力が小さい。これにより、イメージセンサＩＭＧは、高速に撮像を行うことができ、かつ高画質な画像を取得することができる。また、イメージセンサＩＭＧは小型であり、かつ消費電力が小さい。 The AD conversion circuit ADCa included in the image sensor IMG of the second embodiment can perform AD conversion at high speed and with high accuracy. Also, the AD conversion circuit ADCa is compact and consumes less power. Thereby, the image sensor IMG can perform imaging at high speed, and can acquire a high quality image. Further, the image sensor IMG is compact and consumes less power.
　映像信号が入力されるノードＶＩＯおよびノードＶＩＥの電圧は一定ではない。このため、各ノードの電圧が安定するために、ある程度の時間が必要である。一方、基準信号ＶＣＭ＿Ｇが入力されるノードＶＩＣの電圧は略一定であるため、ＡＤ変換回路ＡＤＣａは、短時間にリセット動作を行うことができる。 The voltages of the node VIO and the node VIE to which the video signal is input are not constant. Therefore, a certain amount of time is required to stabilize the voltage at each node. On the other hand, since the voltage of the node VIC to which the reference signal VCM_G is input is substantially constant, the AD conversion circuit ADCa can perform the reset operation in a short time.
　（第２の実施形態の変形例）
　図１２を用いて、第２の実施形態の変形例のイメージセンサＩＭＧａの全体構成について説明する。図１２は、イメージセンサＩＭＧａの全体構成を示している。図１２に示す構成について、図７に示す構成と異なる点を説明する。 (Modification of the second embodiment)
The entire configuration of an image sensor IMGa according to a modification of the second embodiment will be described with reference to FIG. FIG. 12 shows the entire configuration of the image sensor IMGa. Regarding the configuration shown in FIG. 12, points different from the configuration shown in FIG. 7 will be described.
　イメージセンサＩＭＧａにおいて、奇数ＡＤ変換器ＡＤＣＯは奇数列の列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ－１＞に接続され、かつ偶数ＡＤ変換器ＡＤＣＥは偶数列の列回路ＣＯＬ＜２＞～ＣＯＬ＜ｎ＞に接続されている。イメージセンサＩＭＧａは、２つの異なる水平信号線ＨＬＯおよび水平信号線ＨＬＥを有する。水平信号線ＨＬＯは、奇数列の列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ－１＞および奇数ＡＤ変換器ＡＤＣＯに接続されている。水平信号線ＨＬＥは、偶数列の列回路ＣＯＬ＜２＞～ＣＯＬ＜ｎ＞および偶数ＡＤ変換器ＡＤＣＥに接続されている。水平信号線ＨＬＯおよび水平信号線ＨＬＥの各々に接続される列回路ＣＯＬの数は、図７に示すイメージセンサＩＭＧの水平信号線ＨＬに接続される列回路ＣＯＬの数の半分である。上記以外の点については、図１２に示す構成は、図７に示す構成と同様である。 In the image sensor IMGa, the odd AD converters ADCO are connected to the column circuits COL <1> to COL <n-1> in odd columns, and the even AD converters ADCE are column circuits COL <2> to COL <even in even columns. Connected to n>. The image sensor IMGa has two different horizontal signal lines HLO and horizontal signal lines HLE. The horizontal signal line HLO is connected to the column circuits COL <1> to COL <n-1> of the odd columns and the odd AD converter ADCO. The horizontal signal line HLE is connected to the column circuits COL <2> to COL <n> and the even AD converter ADCE in the even columns. The number of column circuits COL connected to each of the horizontal signal lines HLO and the horizontal signal lines HLE is half of the number of column circuits COL connected to the horizontal signal lines HL of the image sensor IMG shown in FIG. Regarding the points other than the above, the configuration shown in FIG. 12 is the same as the configuration shown in FIG.
　列回路ＣＯＬの内部には図示しないアナログスイッチが存在するため、列回路ＣＯＬの出力端子に寄生容量が発生する。列回路ＣＯＬは、ＤＡＣ回路に加えてこの寄生容量を駆動する必要がある。イメージセンサＩＭＧａにおいて、水平信号線ＨＬＯおよび水平信号線ＨＬＥに接続される寄生容量は、イメージセンサＩＭＧの水平信号線ＨＬに接続される寄生容量よりも低減される。このため、イメージセンサＩＭＧａは、より高速かつ低消費電力で動作することができる。 Since an analog switch (not shown) is present inside the column circuit COL, a parasitic capacitance is generated at the output terminal of the column circuit COL. The column circuit COL has to drive this parasitic capacitance in addition to the DAC circuit. In the image sensor IMGa, parasitic capacitances connected to the horizontal signal line HLO and the horizontal signal line HLE are reduced compared to parasitic capacitances connected to the horizontal signal line HL of the image sensor IMG. Thus, the image sensor IMGa can operate at higher speed and lower power consumption.
　（第３の実施形態）
　図１３を用いて、本発明の第３の実施形態のイメージセンサＩＭＧｂの全体構成について説明する。図１３は、イメージセンサＩＭＧｂの全体構成を示している。図１３に示す構成について、図１２に示す構成と異なる点を説明する。 Third Embodiment
The entire configuration of the image sensor IMGb according to the third embodiment of the present invention will be described with reference to FIG. FIG. 13 shows the entire configuration of the image sensor IMGb. Regarding the configuration shown in FIG. 13, points different from the configuration shown in FIG. 12 will be described.
　イメージセンサＩＭＧｂは、イメージセンサＩＭＧａが有する構成に加えて選択スイッチＳＥＬ３を有する。選択スイッチＳＥＬ３は、第１の入力端子Ｓ１と、第２の入力端子Ｓ２と、第１の出力端子Ｄ１と、第２の出力端子Ｄ２とを有する。選択スイッチＳＥＬ３の第１の入力端子Ｓ１は、水平信号線ＨＬＯに接続されている。奇数列の列回路ＣＯＬ＜１＞～ＣＯＬ＜ｎ－１＞からの映像信号ＶＳＩＧが選択スイッチＳＥＬ３の第１の入力端子Ｓ１に入力される。選択スイッチＳＥＬ３の第２の入力端子Ｓ２は、水平信号線ＨＬＥに接続されている。偶数列の列回路ＣＯＬ＜２＞～ＣＯＬ＜ｎ＞からの映像信号ＶＳＩＧが選択スイッチＳＥＬ３の第２の入力端子Ｓ２に入力される。選択スイッチＳＥＬ３の第１の出力端子Ｄ１は、ＡＤ変換回路ＡＤＣａの奇数ＡＤ変換器ＡＤＣＯに接続されている。選択スイッチＳＥＬ３の第２の出力端子Ｄ２は、ＡＤ変換回路ＡＤＣａの偶数ＡＤ変換器ＡＤＣＥに接続されている。 The image sensor IMGb has a selection switch SEL3 in addition to the configuration of the image sensor IMGa. The selection switch SEL3 has a first input terminal S1, a second input terminal S2, a first output terminal D1, and a second output terminal D2. The first input terminal S1 of the selection switch SEL3 is connected to the horizontal signal line HLO. The video signals VSIG from the column circuits COL <1> to COL <n-1> of the odd-numbered columns are input to the first input terminal S1 of the selection switch SEL3. The second input terminal S2 of the selection switch SEL3 is connected to the horizontal signal line HLE. Video signals VSIG from the column circuits COL <2> to COL <n> of even columns are input to the second input terminal S2 of the selection switch SEL3. The first output terminal D1 of the selection switch SEL3 is connected to the odd AD converter ADCO of the AD conversion circuit ADCa. The second output terminal D2 of the selection switch SEL3 is connected to the even AD converter ADCE of the AD conversion circuit ADCa.
　イメージセンサＩＭＧａにおける撮像部ＰＩＸは、撮像部ＰＩＸａに変更される。撮像部ＰＩＸａに配置された複数の画素Ｐの各々は、カラーフィルタを有する。複数の画素Ｐは、緑カラーフィルタを含む画素Ｐ（Ｇ）と、青カラーフィルタを含む画素Ｐ（Ｂ）と、赤カラーフィルタを含む画素Ｐ（Ｒ）とを含む。緑カラーフィルタは、可視光のうち緑色光のみを透過する。青カラーフィルタは、可視光のうち青色光のみを透過する。赤カラーフィルタは、可視光のうち赤色光のみを透過する。図１３において、画素Ｐ（Ｇ）は“Ｇ”と記載され、かつ画素Ｐ（Ｂ）は“Ｂ”と記載され、かつ画素Ｐ（Ｒ）は“Ｒ”と記載されている。各色のカラーフィルタを含む画素Ｐの数は４以上である。画素Ｐの行数および列数は２以上の整数である。 The imaging unit PIX in the image sensor IMGa is changed to an imaging unit PIXa. Each of the plurality of pixels P arranged in the imaging unit PIXa has a color filter. The plurality of pixels P includes a pixel P (G) including a green color filter, a pixel P (B) including a blue color filter, and a pixel P (R) including a red color filter. The green color filter transmits only green light of visible light. The blue color filter transmits only blue light of visible light. The red color filter transmits only red light of visible light. In FIG. 13, the pixel P (G) is described as "G", the pixel P (B) is described as "B", and the pixel P (R) is described as "R". The number of pixels P including color filters of each color is four or more. The number of rows and the number of columns of the pixel P are integers of 2 or more.
　各色のカラーフィルタを含む画素Ｐは、周期的に配置されている。複数の画素Ｐは、ベイヤー配列を構成する。２個の画素Ｐ（Ｇ）と、１個の画素Ｐ（Ｂ）と、１個の画素Ｐ（Ｒ）とは、ベイヤー配列の単位配列を構成する。この単位配列が２次元に周期的に配置されている。奇数行かつ奇数列の画素Ｐは、画素Ｐ（Ｇ）である。奇数行かつ偶数列の画素Ｐは、画素Ｐ（Ｒ）である。偶数行かつ奇数列の画素Ｐは、画素Ｐ（Ｂ）である。偶数行かつ偶数列の画素Ｐは、画素Ｐ（Ｇ）である。上記以外の点については、図１３に示す構成は、図１２に示す構成と同様である。 The pixels P including the color filters of each color are periodically arranged. The plurality of pixels P constitute a Bayer array. Two pixels P (G), one pixel P (B), and one pixel P (R) constitute a unit array of Bayer arrangement. The unit arrays are periodically arranged in two dimensions. The pixels P in the odd rows and odd columns are the pixels P (G). The pixels P in the odd rows and even columns are pixels P (R). The pixels P in the even rows and odd columns are the pixels P (B). The pixels P in the even rows and even columns are pixels P (G). Regarding the points other than the above, the configuration shown in FIG. 13 is the same as the configuration shown in FIG.
　奇数行の画素Ｐからの信号の読み出しが行われるとき、選択スイッチＳＥＬ３の第１の入力端子Ｓ１と選択スイッチＳＥＬ３の第１の出力端子Ｄ１とが接続され、かつ選択スイッチＳＥＬ３の第２の入力端子Ｓ２と選択スイッチＳＥＬ３の第２の出力端子Ｄ２とが接続される。これによって、奇数列の画素Ｐ（Ｇ）から出力された映像信号ＶＳＩＧは奇数ＡＤ変換器ＡＤＣＯに入力され、かつ偶数列の画素Ｐ（Ｒ）から出力された映像信号ＶＳＩＧは偶数ＡＤ変換器ＡＤＣＥに入力される。 When reading out the signal from the pixel P in the odd-numbered row, the first input terminal S1 of the selection switch SEL3 and the first output terminal D1 of the selection switch SEL3 are connected, and the second input of the selection switch SEL3 The terminal S2 is connected to the second output terminal D2 of the selection switch SEL3. Thus, the video signal VSIG output from the pixel P (G) in the odd column is input to the odd AD converter ADCO, and the video signal VSIG output from the pixel P (R) in the even column is the even AD converter ADCE. Is input to
　偶数行の画素Ｐからの信号の読み出しが行われるとき、選択スイッチＳＥＬ３の第１の入力端子Ｓ１と選択スイッチＳＥＬ３の第２の出力端子Ｄ２とが接続され、かつ選択スイッチＳＥＬ３の第２の入力端子Ｓ２と選択スイッチＳＥＬ３の第１の出力端子Ｄ１とが接続される。これによって、偶数列の画素Ｐ（Ｇ）から出力された映像信号ＶＳＩＧは奇数ＡＤ変換器ＡＤＣＯに入力され、かつ奇数列の画素Ｐ（Ｂ）から出力された映像信号ＶＳＩＧは偶数ＡＤ変換器ＡＤＣＥに入力される。 When reading out the signals from the pixels P in the even-numbered rows, the first input terminal S1 of the selection switch SEL3 and the second output terminal D2 of the selection switch SEL3 are connected, and the second input of the selection switch SEL3 The terminal S2 is connected to the first output terminal D1 of the selection switch SEL3. Thus, the video signal VSIG output from the pixels P (G) in the even columns is input to the odd AD converter ADCO, and the video signal VSIG output from the pixels P (B) in the odd columns is the even AD converter ADCE. Is input to
　イメージセンサＩＭＧｂの動作に関して、上記以外の動作は、第２の実施形態のイメージセンサＩＭＧの動作と同一である。 Regarding the operation of the image sensor IMGb, the other operations are the same as the operation of the image sensor IMG of the second embodiment.
　イメージセンサＩＭＧｂは、３色の画素Ｐを有する。イメージセンサＩＭＧｂは、２色以上の画素Ｐを有していればよい。各画素Ｐが有するカラーフィルタは、補色系フィルタであってもよい。つまり、画素Ｐ（Ｇ）はマゼンダ色の画素Ｐによって置き換えられ、かつ画素Ｐ（Ｂ）は黄色の画素Ｐで置き換えられ、かつ画素Ｐ（Ｒ）はシアン色の画素Ｐで置き換えられてもよい。カラーフィルタの組み合わせは、これ以外であってもよい。特許請求の範囲に記載された事項の範囲内でカラーフィルタの配列は自由に変形できる。 The image sensor IMGb has pixels P of three colors. The image sensor IMGb may have pixels P of two or more colors. The color filter that each pixel P has may be a complementary color filter. That is, the pixel P (G) may be replaced by a magenta pixel P, the pixel P (B) may be replaced by a yellow pixel P, and the pixel P (R) may be replaced by a cyan pixel P . The combination of color filters may be other than this. The arrangement of the color filters can be freely modified within the scope of the claims.
　上記のように、イメージセンサＩＭＧｂは、ＡＤ変換回路ＡＤＣａと、行列状に配置された複数の画素Ｐとを有する。複数の画素Ｐは、複数の第１の画素Ｐと複数の第２の画素Ｐとを含む。第１の画素Ｐは、第１の色のカラーフィルタを有する。第２の画素Ｐは、第１の色と異なる第２の色のカラーフィルタを有する。例えば、第１の色および第２の色は、緑、青、および赤のいずれか２つである。複数の第１の画素Ｐおよび複数の第２の画素Ｐは周期的に配置されている。第１の画素Ｐから出力された信号は、第１のＡＤ変換器および第２のＡＤ変換器のいずれか１つに入力される。第２の画素Ｐから出力された信号は、第１のＡＤ変換器および第２のＡＤ変換器のうち第１の画素Ｐから出力された信号が入力されるＡＤ変換器と異なるＡＤ変換器に入力される。 As described above, the image sensor IMGb includes the AD conversion circuit ADCa and the plurality of pixels P arranged in a matrix. The plurality of pixels P includes a plurality of first pixels P and a plurality of second pixels P. The first pixel P has a color filter of the first color. The second pixel P has a color filter of a second color different from the first color. For example, the first color and the second color are any two of green, blue and red. The plurality of first pixels P and the plurality of second pixels P are periodically arranged. The signal output from the first pixel P is input to any one of the first AD converter and the second AD converter. The signal output from the second pixel P is input to an AD converter different from the AD converter to which the signal output from the first pixel P of the first AD converter and the second AD converter is input. It is input.
　上記の制御により、画素Ｐ（Ｇ）から出力された映像信号ＶＳＩＧは奇数ＡＤ変換器ＡＤＣＯによってサンプリングされ、かつ画素Ｐ（Ｂ）または画素Ｐ（Ｒ）から出力された映像信号ＶＳＩＧは偶数ＡＤ変換器ＡＤＣＥによってサンプリングされる。この結果、同一の色のカラーフィルタを含む画素Ｐから出力された映像信号ＶＳＩＧが、常に同一のアナログ信号処理系で処理される。したがって、奇数ＡＤ変換器ＡＤＣＯおよび偶数ＡＤ変換器ＡＤＣＥの個体バラツキがイメージセンサＩＭＧｂの撮像結果に与える影響が最小限に抑えられる。特に、奇数ＡＤ変換器ＡＤＣＯおよび偶数ＡＤ変換器ＡＤＣＥの個体バラツキによる色雑音が低減される。このため、イメージセンサＩＭＧｂは、高画質な画像を取得することができる。 With the above control, the video signal VSIG output from the pixel P (G) is sampled by the odd AD converter ADCO, and the video signal VSIG output from the pixel P (B) or the pixel P (R) is even AD converted Sampled by the ADCE. As a result, the video signal VSIG output from the pixel P including the color filter of the same color is always processed by the same analog signal processing system. Therefore, the influence of the individual variation of the odd AD converter ADCO and the even AD converter ADCE on the imaging result of the image sensor IMGb can be minimized. In particular, color noise due to individual variation of the odd AD converter ADCO and the even AD converter ADCE is reduced. Therefore, the image sensor IMGb can acquire a high quality image.
　（第３の実施形態の変形例）
　図１４を用いて、第３の実施形態の変形例のイメージセンサＩＭＧｃの全体構成について説明する。図１４は、イメージセンサＩＭＧｃの全体構成を示している。図１４に示す構成について、図７に示す構成と異なる点を説明する。 (Modification of the third embodiment)
The entire configuration of an image sensor IMGc of a modification of the third embodiment will be described using FIG. FIG. 14 shows the entire configuration of the image sensor IMGc. The configuration shown in FIG. 14 will be described about differences from the configuration shown in FIG.
　イメージセンサＩＭＧにおける撮像部ＰＩＸは、撮像部ＰＩＸａに変更される。撮像部ＰＩＸａは、図１３に示すイメージセンサＩＭＧｂが有する撮像部ＰＩＸａと同一である。上記以外の点については、図１３に示す構成は、図７に示す構成と同様である。 The imaging unit PIX in the image sensor IMG is changed to an imaging unit PIXa. The imaging unit PIXa is the same as the imaging unit PIXa included in the image sensor IMGb illustrated in FIG. Regarding the points other than the above, the configuration shown in FIG. 13 is the same as the configuration shown in FIG.
　イメージセンサＩＭＧｃは、選択スイッチＳＥＬ３を有していない。しかし、イメージセンサＩＭＧｃが奇数ＡＤ変換器ＡＤＣＯのスイッチＳＷＳＭＰＬＯおよび偶数ＡＤ変換器ＡＤＣＥのスイッチＳＷＳＭＰＬＥを適切に制御することにより、図１３に示すイメージセンサＩＭＧｂの機能と同等の機能が実現される。例えば、奇数行かつ奇数列の画素Ｐおよび偶数行かつ偶数列の画素Ｐからの信号の読み出しが行われるとき、奇数ＡＤ変換器ＡＤＣＯのスイッチＳＷＳＭＰＬＯがオンになり、かつ偶数ＡＤ変換器ＡＤＣＥのスイッチＳＷＳＭＰＬＥがオフになる。これにより、奇数行の画素Ｐ（Ｇ）および偶数行の画素Ｐ（Ｇ）から出力された映像信号ＶＳＩＧは奇数ＡＤ変換器ＡＤＣＯに入力される。奇数行かつ偶数列の画素Ｐおよび偶数行かつ奇数列の画素Ｐからの信号の読み出しが行われるとき、奇数ＡＤ変換器ＡＤＣＯのスイッチＳＷＳＭＰＬＯがオフになり、かつ偶数ＡＤ変換器ＡＤＣＥのスイッチＳＷＳＭＰＬＥがオンになる。これにより、奇数行の画素Ｐ（Ｒ）および偶数行の画素Ｐ（Ｂ）から出力された映像信号ＶＳＩＧは偶数ＡＤ変換器ＡＤＣＥに入力される。 The image sensor IMGc does not have the selection switch SEL3. However, when the image sensor IMGc appropriately controls the switch SWSMPLO of the odd AD converter ADCO and the switch SWSMPLE of the even AD converter ADCE, a function equivalent to the function of the image sensor IMGb shown in FIG. 13 is realized. For example, when reading out signals from pixels P in odd rows and odd columns and pixels P in even rows and even columns, the switch SWSMPLO of the odd AD converter ADCO is turned on, and the switches of the even AD converter ADCE SWSMPLE is turned off. As a result, the video signal VSIG output from the pixels P (G) in the odd rows and the pixels P (G) in the even rows is input to the odd AD converter ADCO. When reading out the signals from the pixels P in the odd rows and even columns and the pixels P in the even rows and odd columns, the switch SWSMPLO of the odd AD converter ADCO is turned off, and the switch SWSMPLE of the even AD converter ADCE is It turns on. Thus, the video signal VSIG output from the pixels P (R) in the odd rows and the pixels P (B) in the even rows is input to the even AD converter ADCE.
　イメージセンサＩＭＧｃにおいて、画素Ｐ（Ｇ）から出力された映像信号ＶＳＩＧは奇数ＡＤ変換器ＡＤＣＯによってサンプリングされ、かつ画素Ｐ（Ｂ）または画素Ｐ（Ｒ）から出力された映像信号ＶＳＩＧは偶数ＡＤ変換器ＡＤＣＥによってサンプリングされる。このため、イメージセンサＩＭＧｂと同様にイメージセンサＩＭＧｃは、高画質な画像を取得することができる。 In the image sensor IMGc, the video signal VSIG output from the pixel P (G) is sampled by the odd AD converter ADCO, and the video signal VSIG output from the pixel P (B) or the pixel P (R) is even AD converted Sampled by the ADCE. For this reason, the image sensor IMGc can acquire a high-quality image as in the case of the image sensor IMGb.
　以上、本発明の好ましい実施形態を説明したが、本発明はこれら実施形態およびその変形例に限定されることはない。本発明の趣旨を逸脱しない範囲で、構成の付加、省略、置換、およびその他の変更が可能である。また、本発明は前述した説明によって限定されることはなく、添付のクレームの範囲によってのみ限定される。 Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments and their modifications. Additions, omissions, substitutions, and other modifications of the configuration are possible without departing from the spirit of the present invention. Also, the present invention is not limited by the above description, and is limited only by the scope of the attached claims.
　本発明の各実施形態によれば、シングルエンド型ＡＤ変換器、ＡＤ変換回路、およびイメージセンサは、高精度なＡＤ変換結果を得ることができる。 According to each embodiment of the present invention, the single-ended AD converter, the AD conversion circuit, and the image sensor can obtain highly accurate AD conversion results.
　ＡＤＣ　ＡＤ変換器
　ＡＤＣａ　ＡＤ変換回路
　ＡＤＣＯ　奇数ＡＤ変換器
　ＡＤＣＥ　偶数ＡＤ変換器
　ＣＤＡＣＯ，ＣＤＡＣＥ　ＤＡＣ回路
　ＣＤＡＣＣ　容量アレー
　ＣＭＰＯ，ＣＭＰＥ　比較器
　ＳＡＲＬＯＧＩＣＯ，ＳＡＲＬＯＧＩＣＥ　制御回路
　Ａ１　差動増幅回路
　Ｌ１　ラッチ回路
　ＩＭＧ，ＩＭＧａ，ＩＭＧｂ，ＩＭＧｃ　イメージセンサ
　ＰＩＸ，ＰＩＸａ　撮像部
　Ｐ　画素
　ＴＧ　タイミングジェネレータ
　ＣＯＬＳ　列処理部
　ＣＯＬ　列回路
　ＳＥＬ３　選択スイッチ ADC AD converter ADCa AD converter circuit ADCO Odd AD converter ADCE Even AD converter CDACO, CDACE DAC circuit CDACC Capacitive array CMPO, CMPE comparator SARLOGICO, SARLOGICE Control circuit A1 Differential amplifier circuit L1 Latch circuit IMG, IMGa, IMGb, IMGc Image sensor PIX, PIXa Imaging unit P pixel TG timing generator COLS Column processing unit COL Column circuit SEL3 selection switch

Claims (6)

  1. 　シングルエンド型ＡＤ変換器であって、
    　容量値が重み付けされた複数の容量を有し、前記複数の容量は、前記シングルエンド型ＡＤ変換器の外部から入力されるアナログ電圧信号を保持するＤＡＣ回路と、
    　前記シングルエンド型ＡＤ変換器の外部から入力される基準電圧信号を保持する固定容量と、
    　前記ＤＡＣ回路に保持された前記アナログ電圧信号の電圧と、前記固定容量に保持された前記基準電圧信号の電圧とを比較するダイナミックコンパレータと、
    　前記ダイナミックコンパレータの比較結果に応じて、前記ＤＡＣ回路を制御する制御回路と、
    　を有し、
    　前記ＤＡＣ回路が有する前記複数の前記容量の容量値の合計と、前記固定容量の容量値とは、略同一である、
    　シングルエンド型ＡＤ変換器。     A single-ended AD converter,
    A DAC circuit having a plurality of capacitances whose capacitance values are weighted, wherein the plurality of capacitances hold analog voltage signals input from the outside of the single-ended AD converter;
    A fixed capacitance for holding a reference voltage signal input from the outside of the single-ended AD converter;
    A dynamic comparator that compares the voltage of the analog voltage signal held by the DAC circuit with the voltage of the reference voltage signal held by the fixed capacitor;
    A control circuit that controls the DAC circuit according to the comparison result of the dynamic comparator;
    Have
    A sum of capacitance values of the plurality of capacitors included in the DAC circuit is substantially equal to a capacitance value of the fixed capacitor.
    Single-ended AD converter.
  2. 　前記アナログ電圧信号が入力される第１の入力ノードと、
    　前記基準電圧信号が入力される第２の入力ノードと、
    　を有し、
    　前記複数の前記容量および前記固定容量の各々は、互いに対向する第１の電極および第２の電極を有し、
    　前記ダイナミックコンパレータは第１の入力端子および第２の入力端子を有し、
    　前記複数の前記容量の前記第１の電極は、前記第１の入力ノードおよび前記第１の入力端子に接続され、
    　前記複数の前記容量の前記第２の電極は、グランドまたは所定の基準電圧に接続され、
    　前記固定容量の前記第１の電極は、前記第２の入力ノードおよび前記第２の入力端子に接続され、
    　前記固定容量の前記第２の電極は、グランドに接続されている
    　請求項１に記載のシングルエンド型ＡＤ変換器。     A first input node to which the analog voltage signal is input;
    A second input node to which the reference voltage signal is input;
    Have
    Each of the plurality of capacitances and the fixed capacitance has a first electrode and a second electrode facing each other,
    The dynamic comparator has a first input terminal and a second input terminal,
    The first electrodes of the plurality of capacitors are connected to the first input node and the first input terminal,
    The second electrodes of the plurality of capacitors are connected to ground or a predetermined reference voltage,
    The first electrode of the fixed capacitance is connected to the second input node and the second input terminal,
    The single-ended AD converter according to claim 1, wherein the second electrode of the fixed capacitance is connected to a ground.
  3. 　請求項１または請求項２に記載のシングルエンド型ＡＤ変換器である第１のＡＤ変換器および第２のＡＤ変換器を有するＡＤ変換回路であって、
    　前記第１のＡＤ変換器および前記第２のＡＤ変換器は、前記固定容量を共有し、
    　前記第１のＡＤ変換器は、前記第２のＡＤ変換器による第２の動作と並行して第１の動作を行い、かつ前記第２のＡＤ変換器は、前記第１のＡＤ変換器による第２の動作と並行して第１の動作を行い、
    　前記第１の動作において、前記アナログ電圧信号が前記ＤＡＣ回路にサンプリングされ、　前記第２の動作において、前記第１の動作によりサンプリングされた前記アナログ電圧信号および基準電圧信号の各々に基づいて順次ＡＤ変換が行われ、
    　前記第１のＡＤ変換器および前記第２のＡＤ変換器は、前記第１の動作および前記第２の動作を交互に行い、
    前記第１のＡＤ変換器および前記第２のＡＤ変換器が、前記第１の動作と前記第２の動作とを切り替える間に、前記第１の動作を行う期間および前記第２の動作を行う期間よりも短い期間で、前記固定容量にサンプリングされた前記基準電圧信号の電圧をリセットする第３の動作を行う
    　ＡＤ変換回路。     An AD conversion circuit comprising a first AD converter and a second AD converter as the single-ended AD converter according to claim 1 or 2,
    The first AD converter and the second AD converter share the fixed capacity,
    The first AD converter performs a first operation in parallel with a second operation by the second AD converter, and the second AD converter performs the first operation by the first AD converter. Perform the first operation in parallel with the second operation,
    In the first operation, the analog voltage signal is sampled by the DAC circuit, and in the second operation, AD is sequentially generated based on each of the analog voltage signal and the reference voltage signal sampled by the first operation. Conversion takes place,
    The first AD converter and the second AD converter alternately perform the first operation and the second operation,
    The first AD converter and the second AD converter perform the first operation and the second operation while switching the first operation and the second operation. An AD conversion circuit performing a third operation of resetting the voltage of the reference voltage signal sampled to the fixed capacitance in a period shorter than the period.
  4. 　請求項３に記載のＡＤ変換回路を有するイメージセンサ。 An image sensor comprising the AD conversion circuit according to claim 3.
  5. 　行列状に配置された複数の画素と、
    　前記複数の画素の列毎に配置された複数の列回路と、
    　を有し、
    　前記複数の画素の奇数列に配置された前記列回路から出力された信号は、前記第１のＡＤ変換器および前記第２のＡＤ変換器のいずれか１つに入力され、
    　前記複数の画素の偶数列に配置された前記列回路から出力された信号は、前記第１のＡＤ変換器および前記第２のＡＤ変換器のうち前記偶数列に配置された前記列回路から出力された前記信号が入力されるＡＤ変換器と異なるＡＤ変換器に入力される
    　請求項４に記載のイメージセンサ。     A plurality of pixels arranged in a matrix form,
    A plurality of column circuits arranged for each column of the plurality of pixels;
    Have
    A signal output from the column circuit arranged in an odd column of the plurality of pixels is input to any one of the first AD converter and the second AD converter,
    The signal output from the column circuit arranged in the even column of the plurality of pixels is output from the column circuit arranged in the even column of the first AD converter and the second AD converter. The image sensor according to claim 4, wherein the signal that has been input is input to an AD converter different from the input AD converter.
  6. 　行列状に配置された複数の画素を有し、
    　前記複数の画素は、複数の第１の画素と複数の第２の画素とを含み、前記第１の画素は、第１の色のカラーフィルタを有し、前記第２の画素は、前記第１の色と異なる第２の色のカラーフィルタを有し、
    　前記複数の第１の画素および前記複数の第２の画素は周期的に配置され、
    　前記第１の画素から出力された信号は、前記第１のＡＤ変換器および前記第２のＡＤ変換器のいずれか１つに入力され、
    　前記第２の画素から出力された信号は、前記第１のＡＤ変換器および前記第２のＡＤ変換器のうち前記第１の画素から出力された前記信号が入力されるＡＤ変換器と異なるＡＤ変換器に入力される
    　請求項４に記載のイメージセンサ。     Having a plurality of pixels arranged in a matrix,
    The plurality of pixels includes a plurality of first pixels and a plurality of second pixels, the first pixel includes a color filter of a first color, and the second pixel includes the first pixel and the second pixel. Have a color filter of a second color different from one color,
    The plurality of first pixels and the plurality of second pixels are periodically arranged;
    The signal output from the first pixel is input to any one of the first AD converter and the second AD converter,
    The signal output from the second pixel is an AD different from the AD converter to which the signal output from the first pixel of the first AD converter and the second AD converter is input. The image sensor according to claim 4, which is input to a converter.
PCT/JP2017/011727 2017-03-23 2017-03-23 Single-ended ad converter, ad conversion circuit, and image sensor WO2018173196A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05196417A (en) * 1991-12-20 1993-08-06 Ando Electric Co Ltd Optical position detection circuit reducing detection time to half
JP2011082879A (en) * 2009-10-09 2011-04-21 Renesas Electronics Corp Semiconductor integrated circuit device
JP2011120092A (en) * 2009-12-04 2011-06-16 Yamaha Corp Successive approximation a/d converter
US20110241912A1 (en) * 2008-10-13 2011-10-06 Nxp B.V. adc

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05196417A (en) * 1991-12-20 1993-08-06 Ando Electric Co Ltd Optical position detection circuit reducing detection time to half
US20110241912A1 (en) * 2008-10-13 2011-10-06 Nxp B.V. adc
JP2011082879A (en) * 2009-10-09 2011-04-21 Renesas Electronics Corp Semiconductor integrated circuit device
JP2011120092A (en) * 2009-12-04 2011-06-16 Yamaha Corp Successive approximation a/d converter

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