WO2018171390A1 - High speed dac test system and method - Google Patents

Abstract

A high speed digital-to-analog converter (DAC) test system and method, comprising: a simulation module, which is used for generating a Dual Polarization Quadrature Phase Shift Keying (DP-QPSK) data stream, achieving DP-QPSK coding modulation, decoding and recovery, and carrying out a comparison implementation test; an arbitrary waveform generator, which is used for receiving the DP-QPSK data stream and outputting a clock signal; a code generator, which is used for receiving the DP-QPSK data stream and outputting a low speed digital signal and a control signal; a high speed cache circuit, which is used for converting the low speed digital signal to a high speed digital signal; a high speed DAC, which is used for converting the high speed digital signal to a high speed analog signal according to the clock signal; a high speed oscilloscope, which is used for sending the high speed analog signal to the simulation module. The system and method of the present invention independently test the high speed DAC, having simple modes and methods of implementation and being low cost.

Description

High-speed DAC test system and method Technical field

 The invention relates to the technical field of optical communication optical fiber transmission systems, in particular to a high speed DAC testing system and method.

Background technique

When 100G enters people's field of vision, how to achieve a smooth upgrade of the existing 10G system has become the key to discussion, and dual-polarization coherent four-phase phase shift keying (DP-QPSK) technology not only improves the spectrum utilization, but also reduces the Dependence on the signal link.

The principle of code-modulation of DP-QPSK is that the light wave emitted by the CW laser is split into two mutually orthogonal optical waves by a polarization splitter for respectively modulating two QPSK modulators, and the QPSK modulator is modulated by two Mach-Zehnder The device (MZM) is composed of 4 MZMs. Each MZM is driven by an electrical signal that does not return to zero at a baseband rate of 25 Gbps. The two orthogonal modulation signals (I and Q channels) of the QPSK modulator are respectively obtained by one MZM output signal and another MZM through the output signal of the 90° phase retarder, and then the I and Q signals are coupled. Together, a bunch of QPSK modulated optical signals are obtained. Two QPSK modulators respectively modulate two optical signals with orthogonal polarization states, and then couple them together through a combiner to form a DP-QPSK signal, which is finally sent into the fiber link for transmission. The electric drive signals of the four MZMs are generated by a high speed digital to analog conversion chip. It provides the function of converting the digital signal into an analog signal that has been modulated in the next step.

The current method of testing high-speed DACs in DP-QPSK systems has inherent drawbacks: it is very expensive to build a complete high-speed DP-QPSK system with hardware, and the DACs are generally integrated in commercial DSPs, cannot be evaluated separately, and require complex development. FPGA algorithm.

Summary of the invention

The main object of the present invention is to overcome the shortcomings of the prior art test high-speed DAC which is too costly and cannot be separately evaluated, and propose a high-speed DAC test system and method, which has simple test methods and steps and low cost.

The invention adopts the following technical solutions:

A high speed DAC test system, including

The simulation module comprises a DP-QPSK signal source unit, a DP-QPSK unit and an optical receiver, wherein the DP-QPSK signal source unit is configured to generate a DP-QPSK data stream, and the DP-QPSK unit is used to implement DP-QPSK code modulation to obtain DP - QPSK modulating the optical signal; the optical receiver is coupled to the DP-QPSK unit to decode and recover the DP-QPSK modulated optical signal;

An arbitrary waveform generator connected to the simulation module to receive the DP-QPSK data stream and output a clock signal;

a code generator connected to the simulation module to receive the DP-QPSK data stream, and output a low-speed digital signal and a control signal;

a cache circuit coupled to the pattern generator for converting the low speed digital signal to a high speed digital signal;

a high speed DAC coupled to an arbitrary waveform generator and a cache circuit for converting a high speed digital signal to a high speed analog signal based on a clock signal;

A high speed oscilloscope connected to a high speed DAC for transmitting high speed analog signals to the simulation module;

The simulation module receives the high-speed analog signal, implements the DP-QPSK code modulation in combination with the DP-QPSK unit, performs signal decoding and recovery through the optical receiver, and compares the recovered signal with the DP-QPSK data stream for testing.

Preferably, the DP-QPSK unit comprises a laser, a polarization splitter, four linear amplifiers, a combiner and two QPSK modulators; the laser continuously emits laser light; the splitter receives the light wave emitted by the laser, and outputs two Orthogonal optical waves to corresponding QPSK modulators; each linear amplifier receives a high-speed analog signal and amplifies it and sends it to a QPSK modulator; the two QPSK modulators perform QPSK modulation of the optical wave and high-speed analog signal and output two orthogonal The QPSK modulates the optical signal; the multiplexer is coupled to the two QPSK modulators to couple the two orthogonal QPSK modulated optical signals to obtain a DP-QPSK modulated optical signal.

Preferably, the QPSK modulator comprises a beam splitter, two light combiners, and two MZM modulators; the splitter is connected to the polarization splitter to split the light wave into two paths; the two MZM modulators respectively correspond to The optical splitter and the linear amplifier are connected to modulate the optical wave according to the change of the high-speed analog signal to obtain two orthogonal modulated signals; the combiner is connected to the two MZM modulators to couple the two orthogonal modulated signals to obtain QPSK. Modulate the optical signal.

Preferably, the simulation module further includes a comparison unit, the comparison unit is connected to the optical receiver and the DP-QPSK signal source unit to compare the recovered signal with the DP-QPSK data stream to calculate a bit error rate of the signal. And error vector magnitude EVM.

Preferably, the simulation module further includes a Labview control unit, the DP-QPSK signal source unit, the pattern generator, the arbitrary waveform generator, the high speed oscilloscope, and the DP-QPSK unit. Connected for implementing data interaction between the DP-QPSK signal source unit and the pattern generator and the arbitrary waveform generator, the high speed oscilloscope and the DP-QPSK unit.

Preferably, the pattern generator, the arbitrary waveform generator, the high speed oscilloscope, and the simulation module are all provided with a data communication interface supporting a GPIB or USB or TCP/IP communication protocol.

Preferably, the pattern generator is provided with at least six digital signal outputs and three control signal outputs.

Preferably, the arbitrary waveform generator is provided with at least two clock signal outputs, and the sampling rate is greater than twice the clock signal rate.

Preferably, the sampling rate and bandwidth of the high speed oscilloscope are greater than the rate and bandwidth of the high speed DAC.

A high speed DAC test method, comprising the steps of:

1) generating a DP-QPSK data stream through the simulation module;

2) inputting the DP-QPSK data stream into the pattern generator to output the low speed digital signal and the control signal, and inputting the DP-QPSK data stream into the arbitrary waveform generator to output the clock signal;

3) converting the low-speed digital signal into a high-speed digital signal, and converting the high-speed digital signal into a high-speed analog signal according to the clock signal;

4) transmitting a high-speed analog signal to the simulation module, and the simulation module performs DP-QPSK code modulation to obtain a DP-QPSK modulated optical signal;

5) The optical receiver decodes and recovers the DP-QPSK modulated optical signal, and then compares the recovered signal with the DP-QPSK data stream. As can be seen from the above description of the present invention, the present invention has the following advantageous effects as compared with the prior art:

The system and method of the present invention generates a DP-QPSK data stream through a simulation module, inputs it into a pattern generator and an arbitrary waveform generator to output a low-speed digital signal and a clock signal, converts the low-speed digital signal into a high-speed digital signal, and The clock signal converts the high-speed digital signal into a high-speed analog signal; then sends the high-speed analog signal to the simulation module, performs DP-QPSK code modulation to obtain the DP-QPSK modulated optical signal, and performs signal decoding and recovery through the optical receiver, and the recovered signal is recovered. Compare with the DP-QPSK data stream to calculate the bit error rate and error vector magnitude EVM of the signal to test and evaluate the performance of the high speed DAC. The system and method of the present invention test the high speed DAC separately, and the implementation method and method are simple and low in cost.

DRAWINGS

Figure 1 is a block diagram of the components of the system of the present invention;

2 is a composition diagram of a DP-QPSK unit of the present invention;

Among them: 10, simulation module, 11, DP-QPSK signal source unit, 12, Labview control unit, 13, DP-QPSK unit, 14, optical receiver, 15, comparison unit, 16, laser, 17, splitter, 18, linear amplifier, 19, combiner, 20, QPSK modulator, 21, splitter, 22, light combiner, 23, MZM modulator, 30, arbitrary waveform generator, 40, pattern generator, 50, Cache circuit, 60, high speed DAC, 70, high speed oscilloscope.

detailed description

The invention is further described below by way of specific embodiments.

Referring to FIG. 1, a high speed DAC test system includes: a simulation module 10, an arbitrary waveform generator 30, a pattern generator 40, a cache circuit 50, a high speed DAC 60, and a high speed oscilloscope 70.

The simulation module 10 includes a DP-QPSK signal source unit 11, a Labview control unit 12, a DP-QPSK unit 13, an optical receiver 14, and a comparison unit 15. The DP-QPSK signal source unit 11 is for generating a DP-QPSK data stream and inputting it to the arbitrary waveform generator 30 and the pattern generator 40. The DP-QPSK unit 13 is used to implement DP-QPSK coded modulation to obtain a DP-QPSK modulated optical signal. The optical receiver 14 is coupled to the DP-QPSK unit 13 to decode and recover the DP-QPSK modulated optical signal. The comparing unit 15 is connected to the optical receiver 14 and the DP-QPSK signal source unit 11 to compare the recovered signal with the DP-QPSK data stream to calculate the bit error rate and the error vector magnitude EVM of the signal, thereby realizing the evaluation of the high speed DAC 60. The Labview control unit 12 is connected to the DP-QPSK signal source unit 11, the pattern generator 40, the arbitrary waveform generator 30, the high speed oscilloscope 70, and the DP-QPSK unit 13 for implementing the DP-QPSK signal source unit 11 and pattern generation. Between the device 40 and the arbitrary waveform generator 30, the data exchange between the high speed oscilloscope 70 and the DP-QPSK unit 13 uses data files such as txt or csv files to exchange data. The Labview control unit 12 is provided with a data communication interface that supports GPIB, USB or TCP/IP communication protocols.

Arbitrary waveform generator 30 is coupled to emulation module 10 to receive the DP-QPSK data stream and output a clock signal having a data communication interface that supports GPIB, USB or TCP/IP communication protocols. The arbitrary waveform generator 30 is also provided with at least two clock signal outputs, and its sampling rate is greater than twice the clock signal rate.

The pattern generator 40 is connected to the simulation module 10 to receive the DP-QPSK data stream, output low-speed digital signals and control signals, and has a data communication interface supporting GPIB, USB or TCP/IP communication protocols, and at least six digital signal outputs. End and three control signal outputs.

A cache circuit 50 for converting a low speed digital signal into a high speed digital signal having a low speed digital signal and control signal input coupled to the pattern generator 40 and a high speed digital signal output coupled to the high speed DAC 60.

The high speed DAC 60 is coupled to the arbitrary waveform generator 30 and the cache circuit 50 for converting the high speed digital signal to a high speed analog signal in accordance with the clock signal. It has a high speed digital signal input, a high speed clock signal input and a high speed analog signal output.

A high speed oscilloscope 70, coupled to the high speed DAC 60, is used to transmit high speed analog signals to the simulation module 10. It has a data communication interface that supports GPIB, USB or TCP/IP communication protocols, and a high-speed analog signal input terminal. The sampling rate and bandwidth of the high speed oscilloscope 70 is greater than the speed and bandwidth of the high speed DAC 60.

Referring to FIG. 2, the DP-QPSK unit 13 includes a laser 16, a polarization splitter 17, four linear amplifiers 18, a splitter 19, and two QPSK modulators 20. The laser 16 is a CW laser that simulates continuous laser emission in a continuous manner over a longer period of time. The polarization splitter 17 receives the light waves emitted by the laser 16 and outputs two orthogonal optical waves, the two outputs of which are connected in one-to-one correspondence with the two QPSK modulators 20. Each linear amplifier 18 receives a high speed analog signal through the Labview control unit 12, and amplifies the amplitude of the signal and sends it to the QPSK modulator 20 to satisfy the modulation amplitude of the back end MZM modulator 23 (Mach Zehnder Modulator). It is required that two of the linear amplifiers 18 correspond to one QPSK modulator 20. The QPSK modulator 20 performs QPSK modulation on the optical wave and the high speed analog signal and outputs a QPSK modulated optical signal, and the two QPSK modulators 20 output two orthogonal QPSK modulated optical signals. The combiner 19 is coupled to the output of the two QPSK modulators 20 to couple the two orthogonal QPSK modulated optical signals to obtain a DP-QPSK modulated optical signal.

Among them, the QPSK modulator 20 includes a beam splitter 21, two light combiners 22, and two MZM modulators 23. The beam splitter 21 is connected to an output of the polarization splitter 17 to split the light wave into two paths. The two MZM modulators 23 are respectively connected to the beam splitter 21 and the corresponding two linear amplifiers 18. Since the MZM modulator 23 controls the bias voltage thereof, modulation of different sidebands can be realized. Each MZM modulator 23 modulates the light wave according to a change of the high speed analog signal to obtain a modulated signal, and the phases of the two MZM modulators 23 are different by 90° to obtain two orthogonal modulated signals. The combiner 22 is coupled to the outputs of the two MZM modulators 23 to couple the two orthogonal modulated signals to obtain a QPSK modulated optical signal.

The optical receiver 14 receives the DP-QPSK modulated optical signal for signal decoding and recovery, and sends it to the comparing unit 15. The comparing unit 15 compares the recovered signal with the DP-QPSK data stream, and calculates the bit error rate and the error vector magnitude EVM of the signal. Different performance high-speed DAC60 can result in a difference in final bit error rate and EVM, which can test and evaluate the performance of high-speed DAC60.

The invention also proposes a high speed DAC test method, comprising the following steps:

1) generating a DP-QPSK data stream through the DP-QPSK signal source unit 11 of the simulation module 10;

2) The DP-QPSK data stream is transmitted to the pattern generator 40 and the arbitrary waveform generator 30 through the TCP/IP protocol in the form of a data file via the Labview control unit 12, and the sampling rate of the pattern generator 40 is 1 GHz, and is stored. The depth is 128M, which outputs low-speed digital signals and control signals. The arbitrary waveform generator 30 has a sampling rate of 100 GHz, an output clock of 50 GHz, and outputs two phase signals that are 180[deg.] out of phase with each other.

3) Write the data to the Flash of the cache circuit 50 at a rate of 100 Mbps. The Flash buffer can store 1 M of data, and the Flash has 60 data output channels, each of which can be read at a rate of 5 Gb/s or less. The sixty-six data output channels of Flash convert sixty-five 5Gb/s data into six 50Gb/s data through a parallel-to-serial circuit, and the high-speed DAC60 to be tested outputs the six-way 50Gb of the cache circuit 50 at a high-speed working clock of 50 GHz. The /s data is converted to a high speed analog signal.

4) High-speed oscilloscope 70 captures the analog signal output from the high-speed DAC60, high-speed oscilloscope 70 sampling rate 160GHz, bandwidth 50GHz, two analog input channels, high-speed oscilloscope 70 acquisition of analog waveforms, data acquisition to Labview through TCP/IP protocol The control unit 12 enters the simulation module 10 for processing and saves it as a data file. The Labview control unit 12 restores the high speed analog signal to an electrical signal and sends it to the linear amplifier 18, and performs DP-QPSK coded modulation in conjunction with the DP-QPSK unit 13 to obtain a DP-QPSK modulated optical signal.

5) The optical receiver 14 can recover and decode the received signal, and then compare with the signal of the DP-QPSK signal source unit 11, and calculate the bit error rate and the error vector magnitude EVM of the signal. High-speed DAC60 with different performance can result in a difference in final bit error rate and EVM, so that the performance of high-speed DACs can be tested and evaluated.

The above is only a specific embodiment of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modification of the present invention by this concept should be an infringement of the scope of protection of the present invention.

Claims (10)

1. A high speed DAC test system, including

The simulation module comprises a DP-QPSK signal source unit, a DP-QPSK unit and an optical receiver, wherein the DP-QPSK signal source unit is configured to generate a DP-QPSK data stream, and the DP-QPSK unit is used to implement DP-QPSK code modulation to obtain DP - QPSK modulating the optical signal; the optical receiver is coupled to the DP-QPSK unit to decode and recover the DP-QPSK modulated optical signal;

An arbitrary waveform generator connected to the simulation module to receive the DP-QPSK data stream and output a clock signal;

a code generator connected to the simulation module to receive the DP-QPSK data stream, and output a low-speed digital signal and a control signal;

a cache circuit coupled to the pattern generator for converting the low speed digital signal to a high speed digital signal;

a high speed DAC coupled to an arbitrary waveform generator and a cache circuit for converting a high speed digital signal to a high speed analog signal based on a clock signal;

A high speed oscilloscope connected to a high speed DAC for transmitting high speed analog signals to the simulation module;

The simulation module receives the high-speed analog signal, implements the DP-QPSK code modulation in combination with the DP-QPSK unit, performs signal decoding and recovery through the optical receiver, and compares the recovered signal with the DP-QPSK data stream for testing.

A high speed DAC test system according to claim 1 wherein said DP-QPSK unit comprises a laser, a splitter, four linear amplifiers, a combiner and two QPSK modulators; the laser continues to emit a laser; the depolarizer receives the light wave emitted by the laser and outputs two orthogonal optical waves to the corresponding QPSK modulator; each linear amplifier receives the high speed analog signal and amplifies it and sends it to the QPSK modulator; the two QPSK modulators The light wave and the high-speed analog signal are QPSK modulated and output two orthogonal QPSK modulated optical signals; the combiner is coupled with two QPSK modulators to couple two orthogonal QPSK modulated optical signals to obtain DP-QPSK modulated light. signal.

A high speed DAC test system according to claim 2, wherein said QPSK modulator comprises a beam splitter, two light combiners, and two MZM modulators; said splitter being coupled to said splitter Dividing the light wave into two paths; the two MZM modulators are respectively connected with the corresponding beam splitter and the linear amplifier to modulate the light wave according to the change of the high speed analog signal to obtain two orthogonal modulated signals; the combiner and the two MZM modulations The devices are connected to couple the two orthogonal modulated signals to obtain a QPSK modulated optical signal.

A high speed DAC test system according to claim 1 wherein said simulation module further comprises a comparison unit coupled to said optical receiver and said DP-QPSK signal source unit for restoration The signal is compared to the DP-QPSK data stream to calculate the bit error rate and error vector magnitude EVM of the signal.

A high-speed DAC test system according to claim 1, wherein said simulation module further comprises a Labview control unit, said Labview control unit and DP-QPSK signal source unit, said pattern generator, said arbitrary a waveform generator, the high speed oscilloscope, and the DP-QPSK unit are connected to implement between a DP-QPSK signal source unit and the pattern generator and the arbitrary waveform generator, the high speed oscilloscope and the DP - Data interaction between QPSK units.

A high speed DAC test system according to claim 1, wherein said pattern generator, said arbitrary waveform generator, said high speed oscilloscope, said simulation module are each provided with support for GPIB or USB or TCP. Data communication interface of the /IP communication protocol.

A high speed DAC test system according to claim 1, wherein said pattern generator is provided with at least six digital signal outputs and three control signal outputs.

A high speed DAC test system according to claim 1 wherein said arbitrary waveform generator is provided with at least two clock signal outputs and having a sampling rate greater than twice the clock signal rate.

A high speed DAC test system according to claim 1 wherein said high speed oscilloscope has a sampling rate and bandwidth greater than the rate and bandwidth of said high speed DAC.

A high speed DAC test method, comprising the steps of:

1) generating a DP-QPSK data stream through the simulation module;

2) inputting the DP-QPSK data stream into the pattern generator to output the low speed digital signal and the control signal, and inputting the DP-QPSK data stream into the arbitrary waveform generator to output the clock signal;

3) converting the low-speed digital signal into a high-speed digital signal, and converting the high-speed digital signal into a high-speed analog signal according to the clock signal;

4) transmitting a high-speed analog signal to the simulation module, and the simulation module performs DP-QPSK code modulation to obtain a DP-QPSK modulated optical signal;

5) The optical receiver decodes and recovers the DP-QPSK modulated optical signal, and then compares the recovered signal with the DP-QPSK data stream.