WO2018157795A1 - Data processing method and apparatus - Google Patents

Abstract

Provided in one embodiment of the present application is a data processing method. The method comprises: a communication apparatus divides a bit sequence to acquire a plurality of first sub-bit sequences; the length of some or all of the first sub-bit sequences in the plurality of first sub-bit sequences is not a standard length; when the length of a first sub-bit sequence is not a standard length, the communication apparatus fills in the first sub-bit sequence to acquire a second sub-bit sequence; and the length of the second sub-bit sequence is a standard length. The present method enables the code rates of each code block to be close, improving decoding performance, and thereby improving the system performance.

Description

Data processing method and device

The present application claims the priority of the Chinese Patent Application, which is filed on March 3, 2017, the Chinese Patent Application No. PCT Application No. .

Technical field

The present application relates to communication technologies, and more particularly to a method and apparatus for data processing.

Background technique

In a long term evolution (LTE) system, information is encoded using a Trubo code. Since the maximum code block (CB) supported by the Trubo code encoder is limited, a code block segmentation technique is proposed. For example, the Trubo code encoder supports a maximum code block length of 6144. For a transport block (TB) with a length greater than 6144, it needs to be divided into multiple code blocks. That is, it can be understood that the bit sequence having a length greater than 6144 is divided into a plurality of sub-bit sequences so as to be able to satisfy the Trubo encoder's requirement for the code block length. For the specific segmentation method, refer to the related content of section 5.1.2 of the communication standard TS 36.212 v14.1.1 (2007-1) of the third generation partnership project (3GPP).

With the development of technology, a low density parity check code (LDPC) is introduced in the communication system to encode information. The existing code block segmentation technique is used in a communication system that uses LDPC for encoding, which may cause performance degradation.

Summary of the invention

The method and apparatus for data processing provided by the embodiments of the present application are for improving the performance of a communication system.

In a first aspect, an embodiment of the present application provides a data processing method, where the method includes:

Segmenting the bit sequence to obtain a plurality of first sub-bit sequences; wherein a length of part or all of the first sub-bit sequences of the plurality of first sub-bit sequences is not a standard length;

The first sub-bit sequence that is not the standard length is padded to obtain a second sub-bit sequence having a standard length.

Optionally, the length of the second sub-bit sequence is a minimum standard length greater than the length of the first sub-bit sequence.

Optionally, the length of the multiple first sub-bit sequences belongs to a length set, where the length set includes a standard length set and a non-standard length set.

Optionally, the length of the second sub-bit sequence belongs to the standard length set.

Optionally, the splitting the bit sequence comprises: dividing the bit sequence according to the length set.

Optionally, in the length set, a partial value in the standard length set is adjacent to a partial value in the non-standard length set.

Optionally, a part of the first sub-bit sequence of the plurality of first sub-bit sequences has a length of K ₊ , and another part of the first sub-bit sequence has a length of K ₋ , K ₊ ≠K ₋ .

Optionally, K _- is a maximum of less than K ₊ in the set of lengths.

Optionally, the value in the standard length set is associated with a matrix spread factor.

Optionally, the pair of bit sequences is a transport block, the first sub-bit sequence is a first code block, and the second sub-bit sequence is a second code block.

In a second aspect, the embodiment of the present application further provides a data processing method, including:

The communication device divides the bit sequence into a plurality of sub-bit sequences according to the set of lengths;

The length of the sub-bit sequence is a length that does not need to be filled in the sub-bit sequence, and the length set includes a first sub-length set that needs to be filled in the sub-bit sequence and a second sub-sub-port that does not need to be filled in the sub-bit sequence. Length collection.

Optionally, the partial values of the first sub-length set are distributed between partial values of the second sub-length set.

Optionally, the value in the set of lengths is associated with a low density parity check code LDPC.

Optionally, the method further includes: the communication device performing channel coding on the plurality of sub-bit sequences.

Optionally, the value of the second sub-length set is associated with a matrix spreading factor.

Optionally, a part of the plurality of sub-bit sequences includes padding bits.

In a third aspect, the embodiment of the present application further provides a data processing method, including:

The communication device performs a first process on the bit sequence to obtain one or more first sub-bit sequences and one or more second sub-bit sequences; the first process is a split and a first padding, or the first process is a segmentation;

When the length of the first sub-bit sequence belongs to a non-standard length set, the communication device performs a second padding on the first sub-bit sequence such that the length of the first sub-bit sequence is equal to the first of the standard length sets is greater than the first The minimum length of the sub-bit sequence; or,

When the length of the second sub-bit sequence belongs to a non-standard length set, the communication device performs a second padding on the second sub-bit sequence such that the length of the second sub-bit sequence is equal to the second of the standard length set is greater than the second The minimum length of the sub-bit sequence.

Optionally, the length of the first sub-bit sequence and the second sub-bit sequence belong to a length set, and the length set includes the non-standard length set and the standard length set.

Optionally, the value in the standard length set is associated with a matrix spread factor.

Optionally, the length of the second sub-bit sequence is a maximum value in the length set that is smaller than a length of the first sub-bit sequence.

Optionally, the second processing of the first sub-bit sequence by the communications device includes: the communications device filling N bits in the foremost or last part of the first sub-bit sequence; wherein N is equal to the standard length set The difference between the minimum value of the length of the first sub-bit sequence and the length of the first sub-bit sequence.

Optionally, the second processing performed by the communications apparatus on the second sub-bit sequence includes:

The communication device fills M bits in the foremost or last part of the second sub-bit sequence; wherein M is equal to a minimum value of the length of the standard length set greater than the second sub-bit sequence and the second sub-bit sequence The difference in length.

Optionally, the first processing by the communication device on the bit sequence includes: the communication device splits and fills the bit sequence; or the communication device divides the bit sequence.

In a fourth aspect, the embodiment of the present application further provides a data processing method, including:

The communication device divides the transport block into a plurality of code blocks according to the set of lengths.

The length set includes a first sub-length set and a second sub-length set, the elements in the first sub-length set are standard lengths, and the code blocks having the standard length need not be padded, and the elements in the second sub-length set For non-standard lengths, code blocks with non-standard lengths need to be filled;

The length of the plurality of divided code blocks belongs to the first sub-length set.

Optionally, the value of the part of the second length set is between the values of the at least one adjacent element in the first subset set.

Optionally, the method further includes: the communication device performing channel coding on the plurality of sub-bit sequences.

Optionally, the value of the length set that does not need to be filled is associated with a matrix expansion factor.

Optionally, a part of the plurality of sub-bit sequences includes padding bits.

Optionally, the method is for a communication system employing a low density base even code LDPC.

In a fifth aspect, an embodiment of the present application provides a communication apparatus. The communication device can be used to implement the method of any of the above first to fourth aspects. The communication device can be a terminal, a base station, or a baseband chip, or a data signal processing chip, or a general purpose chip.

As an alternative design, the communication device includes a processor. The processor is for performing the functions of the various parts of any of the first to fourth aspects.

As another alternative design, the transmitting device includes a processor and a memory. The memory is for storing a program implementing the method of any of the first to fourth aspects, the processor being operative to run the above program to implement the methods of the first to fourth aspects.

Optionally, the above communication device may include a transceiver.

In a sixth aspect, the embodiment of the present application further provides a computer program product, where the program product includes a program for implementing the methods of the first to fourth aspects.

In a seventh aspect, the embodiment of the present application further provides a computer readable storage medium, where the medium stores the program of the sixth aspect.

In the technical solution of the present application, by uniformly distributing the number of code blocks on adjacent standard lengths, the code rates of different code blocks can be approximated, and the number of padding bits is also reasonable, which is helpful for improving the decoding performance.

DRAWINGS

In order to more clearly illustrate the technical solution of the present application, a brief description will be made below of the drawings used in the description of the embodiments.

1 is a simplified schematic diagram of a wireless communication system;

2 is a schematic diagram showing a simplified structure of a terminal;

3 is a simplified schematic diagram of a structure of a base station;

4 is a schematic diagram of a transport block process;

5 is a schematic diagram of a code block partitioning and a code block cyclic redundancy check adding part;

6 is a schematic diagram of a method of data processing;

7 is a schematic diagram of another method of data processing;

Figure 8 is a schematic diagram of still another method of data processing;

9 is a schematic diagram of still another method of data processing;

Figure 10 is a schematic diagram of still another method of data processing.

detailed description

Embodiments of the present application will be described below in conjunction with the drawings in the present application.

Some terms and conventions in this application are described below.

In the present application, a bit sequence is a sequence consisting of bits "0" and/or "1". The length of the bit sequence refers to the number of bits included in the bit sequence. For example, the bit sequence "0100" includes 4 bits and has a length of 4.

In the present application, a transport block (TB) and a code block (CB) can be regarded as a bit sequence. The code block is obtained by dividing the transport block, so the bit sequence corresponding to the CB can be regarded as a sub-bit sequence of the bit sequence corresponding to the TB. It will be appreciated that as technology advances, transport blocks or code blocks may have different titles.

In the present application, the length can sometimes be understood as the number of bits, or the number of bits, and sometimes also referred to as size.

In the present application, the number of bits may sometimes be referred to as the number of bits, or the number of bits, or the length of the bit sequence, and the like.

In the present application, elements in a collection may sometimes be referred to as items in a collection or lengths in a collection, and the like. Different elements, items, or lengths have different values. The elements, terms, or lengths, etc., can also be represented by an index. In this application, tables may also be referred to as tables, collections, groups, and may be represented in a variety of forms identifiable by a communication device.

In the present application, the standard length refers to the length of the (code block) supported by the communication system, which may sometimes be referred to as the native (code block) length of the encoder, legal (code block) length, and does not require (second) padding. Length, etc.

In the present application, the non-standard block length is a length relative to the standard length, and generally refers to a (code block) length that the communication system does not support at the time of encoding. Sometimes it can also be called non-native (code block) length, illegal (code block) length, length of (second) padding, etc.

In the present application, the standard length set includes one or more standard lengths, and the non-standard length set includes one or more non-standard lengths.

In the present application, the difference in adjacent lengths may sometimes be referred to as the pitch. For example, taking a set of 3 elements as an example, it can be expressed as {length 1:10, length 2:15, length 3:25}, or Table A below or other forms.

index	Value
1	10
2	15
3	25
4	45

Table A

Wherein, the spacing between the length 1 and the length 2 is 5, the spacing between the long dimension 2 and the length 3 is 10, and the spacing between the lengths 2 and 4 is 30. Length 1 and length 2 are adjacent lengths (or adjacent elements, adjacent items), and length 2 and length 3 are adjacent lengths (or adjacent elements, adjacent items), ie, length 1 and length 2 are adjacent, length 2 is adjacent to length 3.

In the present application, channel coding may sometimes be referred to simply as coding.

In the present application, a communication device is a device having a communication function. For example, the communication device may be a base station, or a terminal, or a baseband chip, or a communication chip, or a sensor chip or the like.

In the present application, the length of a code block is sometimes also simply referred to as a code block length.

In the present application, the term "comprises" and variations thereof may mean non-limiting inclusion; the term "or" and its variants may mean "and/or"; the terms "associated", "associated", "corresponding" And their variants can refer to "bound", "bound to", "mapped", "configured", "allocated", "based on", or "according to... The term "pass" and its variants may mean "utilizing", "using", or "on", etc.; the terms "acquiring", "determining" and their variants may mean "selecting", "query" "," "calculation", etc.; the term "when" can mean "if", "under" conditions, and the like.

In the present application, for example, the content in parentheses "()" may be an example, or may be another expression, which may be a description that may be omitted, or may be further explained and explained.

The technical solution of the present application can be applied to different communication devices. The embodiments of the present application are mainly described by using a base station and a terminal as an example.

The technical solution of the present application can be used in a wireless communication system as shown in FIG. 1. As shown in FIG. 1, the wireless communication system includes a base station B200 and a terminal T100. The base station B200 can communicate with the terminal T100 using different communication resources. For example, the base station B200 can communicate with the terminal T100 using a wide beam and/or a narrow beam. The wireless communication system may be a 4G communication system, such as an LTE (long term evolution) system, a 5G communication system, such as an NR (new radio) system, and a communication system in which various communication technologies are integrated (for example, LTE technology). Communication system integrated with NR technology).

The terminal T100 is a device having a wireless communication function, and may be a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem. Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc.

A schematic diagram of the structure of the terminal T100 can be as shown in FIG. 2. For ease of illustration, Figure 2 shows only the main components of the terminal. As shown in FIG. 2, the terminal T100 includes a processor, a memory, a radio frequency circuit, an antenna, and an input and output device. The processor is mainly used for processing communication protocols and communication data, and controlling terminals, executing software programs, processing data of software programs, and the like. Memory is primarily used to store software programs and data. The RF circuit is mainly used for the conversion of the baseband signal and the RF signal and the processing of the RF signal. The antenna is mainly used to transmit and receive RF signals in the form of electromagnetic waves. Input and output devices, such as touch screens, display screens, keyboards, etc., are primarily used to receive user input data and output data to the user. Some types of terminals do not have input and output devices.

When the terminal is powered on, the processor can read the software program (instruction) in the storage unit, interpret and execute the instructions of the software program, and process the data of the software program. When the data needs to be sent, the processor performs baseband processing on the data to be sent, and outputs the baseband signal to the radio frequency circuit. The radio frequency circuit performs radio frequency processing on the baseband signal, and then sends the radio frequency signal to the outside through the antenna in the form of electromagnetic waves. When data is sent to the terminal, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor, which converts the baseband signal into data and processes the data.

For ease of illustration, Figure 2 shows only one memory and processor. In an actual user device, there may be multiple processors and memories. The memory may also be referred to as a storage medium or a storage device, and the like.

As an optional implementation manner, the processor may include a baseband processor and/or a central processing unit. The baseband processor is mainly used to process a communication protocol and communication data, and the central processing unit is mainly used to control the entire terminal. Execute a software program that processes the data of the software program. The processor in FIG. 2 integrates the functions of the baseband processor and the central processing unit. Those skilled in the art can understand that the baseband processor and the central processing unit can also be independent processors and interconnected by technologies such as a bus. Optionally, the terminal may include multiple baseband processors to adapt to different network standards. Alternatively, the terminal may include multiple central processors to enhance its processing capabilities. Optionally, the functions of the baseband processor and the central processing unit can be integrated on one processor. Alternatively, the various components of the terminal can be connected via various buses. The baseband processor can also be expressed as a baseband processing circuit or a baseband processing chip. The central processing unit can also be expressed as a central processing circuit or a central processing chip. Optionally, the function of processing the communication protocol and the communication data may be built in the processor, or may be stored in the storage unit in the form of a software program, and the processor executes the software program to implement the baseband processing function.

In the embodiment of the present application, the antenna and the radio frequency circuit having the transceiving function can be regarded as the transceiving unit of the terminal, and the processor having the processing function can be regarded as the processing unit of the terminal. As shown in FIG. 2, the terminal T100 includes a transceiver unit 101 and a processing unit 102. The transceiver unit can also be referred to as a transceiver, a transceiver, a transceiver, and the like. The processing unit may also be referred to as a processor, a processing board, a processing module, a processing device, and the like. Optionally, the device for implementing the receiving function in the transceiver unit 101 can be regarded as a receiving unit, and the device for implementing the sending function in the transceiver unit 101 is regarded as a sending unit, that is, the transceiver unit 101 includes a receiving unit and a sending unit. The receiving unit may also be referred to as a receiver, a receiver, a receiving circuit, etc., and the transmitting unit may be referred to as a transmitter, a transmitter, or a transmitting circuit or the like.

The base station B200, which may also be referred to as a base station device, is a device deployed in a wireless access network to provide wireless communication functions. For example, a base station in an LTE network is called an evolved Node B (eNB or eNodeB), and a base station in an NR network is called a TRP (transmission reception point) or a gNB (generation node B, next generation Node B). ). The structure of the base station B200 can be as shown in FIG. The base station B200 shown in FIG. 3 may be a split base station. For example, FIG. 3 shows, on the left, a distributed base station including antennas, a remote radio unit (RRU), and a baseband unit (BBU). The base station shown in FIG. 3 may also be an integrated base station, such as a small cell shown to the right in FIG. In general, a base station includes a 201 portion and a 202 portion. Part 201 is mainly used for the transmission and reception of radio frequency signals and the conversion of radio frequency signals and baseband signals; the 202 part is mainly used for baseband processing and base station control. Section 201 can be generally referred to as a transceiver unit, a transceiver, a transceiver circuit, a transceiver, and the like. Section 202 can generally be referred to as a processing unit. Usually part 202 is the control center of the base station.

As an optional implementation, part 201 may include an antenna and a radio frequency unit, wherein the radio frequency unit is mainly used for radio frequency processing. Optionally, the device for implementing the receiving function in part 201 may be regarded as a receiving unit, and the device for implementing the transmitting function may be regarded as a transmitting unit, that is, the part 201 includes a receiving unit and a transmitting unit. Illustratively, the receiving unit may also be referred to as a receiver, a receiver, a receiving circuit, etc., and the transmitting unit may be referred to as a transmitter, a transmitter, or a transmitting circuit or the like.

As an optional implementation, the 202 part may include one or more boards, each of the boards may include a processor and a memory, and the processor is configured to read and execute a program in the memory to implement a baseband processing function and a base station. control. If multiple boards exist, the boards can be interconnected to increase processing power.

As another optional implementation manner, with the development of the system-on-chip (SoC) technology, the functions of the 202 part and the 201 part can be implemented by the SoC technology, that is, by a base station function. The chip realizes that the base station function chip integrates a processor, a memory, an antenna interface and the like, and the program of the base station related function is stored in the memory, and the program is executed by the processor to implement the related functions of the base station.

In the present application, the communication device can be a terminal or a base station.

In the course of communication, the processing of the transport block is typically performed by the processing unit of the communication device. As an example, as shown in FIG. 4, the processing for the transport block may include the following parts: a TB cyclic redundancy check (CRC) attachment section, a code block partition, and a code block loop. A code block segmentation and code block CRC attachment portion, a channel coding portion, and a rate matching portion.

The transport block cyclic redundancy check adding part is mainly used for adding a CRC bit to the transport block, and outputting a transport block including a CRC bit; the code block partitioning and the code block cyclic redundancy check code adding part are mainly used for the transport block. The cyclic redundancy check adds a partial output transport block into a plurality of code blocks, adds a CRC bit for each code block, and outputs a code block to which a CRC bit is added; the channel coding portion is mainly used for code block partitioning and code block loop The redundancy check code adds a partial output code block to encode, and outputs a code block including redundant bits; the rate matching part is mainly used for repeating or puncture the code block outputted by the channel coding part to match The carrying capacity of the physical channel.

As an optional design, the processing of the code block partitioning and the code block cyclic redundancy check adding part may be implemented by a code block splitter, which may be simply referred to as a splitter.

As an optional design, code block partitioning can be implemented by a code block partitioner, and code block cyclic redundancy check addition can be implemented by a check code adder. Optionally, the transport block cyclic redundancy check addition part may also be implemented by a check code adder.

As an alternative design, the channel coding portion can be implemented by an encoder.

The code block divider, the check code adder, and the encoder may be circuits internal to the processing unit or may be logical components of the processing unit. An encoder using a turbo code may be referred to as a turbo code encoder, and an encoder employing an LDPC may be referred to as an LDPC encoder. The length of the code block for channel coding needs to meet certain conditions according to different coding characteristics. That is, the length of the code block subjected to channel coding is not an arbitrary length. The length of the code block that can be processed during channel coding may be referred to as the code block length supported by the communication system, and may also be referred to as a standard (code block) length, or a legal (code block) length, or a native (code block) length. In order to distinguish the code block lengths involved in different coding, the code block length supported by the LDPC communication system may be referred to as the code block length supported by the LDPC, the standard (code block) length of the LDPC, and the legal (code block) length of the LDPC. Similarly, the code block length supported by the communication system using the turbo code may be referred to as the code block length supported by the turbo code, the standard (code block) length of the turbo code, and the legal (code block) length of the turbo code. It should be noted that the same communication system can support multiple encodings. In such a system, when channel coding is performed using a turbo code, the code block length needs to satisfy the standard length of the turbo code. When channel coding is performed using LDPC, the code block length needs to satisfy the standard length of the LDPC.

Depending on the design of the different communication systems, the communication system can support multiple standard lengths for the same code. For example, for Turbo codes, the LTE system can support 188 code block lengths as shown in Table 1. The maximum code block length supported by the LTE system is 6144. As another example, for LDPC, the communication system can support code block lengths as shown in Table 2, Table 3, or Table 4. For LDPC, the maximum code block length supported by the communication system can be 8192 or according to system design settings. It should be noted that there may be multiple LDPC encoders in the communication system to cope with different scenarios, so the maximum code block length supported by the communication system for different scenarios may be different. In Tables 1 to 4, i denotes the sequence number of the code block length, and K denotes the code block length. The code block lengths listed in Table 2 - Table 4 can be considered as the standard length of the LDPC. It should be noted that the table in this application is merely an example and is not a limitation on the standard length. In a communication system, the actual set of standard lengths of Turbo codes or LDPCs may be the above table, or a subset of the tables, or include other values.

As an alternative design, the standard length of the LDPC is related to the matrix expansion factor Z. For example, the definition LDPC base matrix includes mb rows and nb columns, and the number of information bit columns kb=mb-nb is defined. The range of the extension factor Z supported by the LDPC matrix is

Then, the standard length of the LDPC code is expressed as K = kb × Z _i , 0 ≤ i < i _max . Optionally, the same LDPC encoder can support multiple LDPC base matrices and extension factor value ranges, and the length calculated by the LDPC base matrix and the extension factor value range can be regarded as the standard of the LDPC encoder. length.

i	K	i	K	i	K	i	K
1	40	48	416	95	1120	142	3200
2	48	49	424	96	1152	143	3264
3	56	50	432	97	1184	144	3328
4	64	51	440	98	1216	145	3392
5	72	52	448	99	1248	146	3456
6	80	53	456	100	1280	147	3520
7	88	54	464	101	1312	148	3584
8	96	55	472	102	1344	149	3648
9	104	56	480	103	1376	150	3712
10	112	57	488	104	1408	151	3776
11	120	58	496	105	1440	152	3840
12	128	59	504	106	1472	153	3904
13	136	60	512	107	1504	154	3968
14	144	61	528	108	1536	155	4032
15	152	62	544	109	1568	156	4096
16	160	63	560	110	1600	157	4160
17	168	64	576	111	1632	158	4224
18	176	65	592	112	1664	159	4288
19	184	66	608	113	1696	160	4352
20	192	67	624	114	1728	161	4416
twenty one	200	68	640	115	1760	162	4480
twenty two	208	69	656	116	1792	163	4544
twenty three	216	70	672	117	1824	164	4608
twenty four	224	71	688	118	1856	165	4672
25	232	72	704	119	1888	166	4736
26	240	73	720	120	1920	167	4800
27	248	74	736	121	1952	168	4864
28	256	75	752	122	1984	169	4928
29	264	76	768	123	2016	170	4992
30	272	77	784	124	2048	171	5056
31	280	78	800	125	2112	172	5120
32	288	79	816	126	2176	173	5184
33	296	80	832	127	2240	174	5248
34	304	81	848	128	2304	175	5312
35	312	82	864	129	2368	176	5376
36	320	83	880	130	2432	177	5440
37	328	84	896	131	2496	178	5504

38	336	85	912	132	2560	179	5568
39	344	86	928	133	2624	180	5632
40	352	87	944	134	2688	181	5696
41	360	88	960	135	2752	182	5760
42	368	89	976	136	2816	183	5824
43	376	90	992	137	2880	184	5888
44	384	91	1008	138	2944	185	5952
45	392	92	1024	139	3008	186	6016
46	400	93	1056	140	3072	187	6080
47	408	94	1088	141	3136	188	6144

Table 1

i	K	i	K
1	64	16	896
2	80	17	1024
3	96	18	1280
4	112	19	1536
5	128	20	1792
6	160	twenty one	2048
7	192	twenty two	2560
8	224	twenty three	3072
9	256	twenty four	3584
10	320	25	4096
11	384	26	5120
12	448	27	6144
13	512	28	7168
14	640	29	8192
15	768

Table 2

i	K	i	K
1	128	14	1280
2	160	15	1536
3	192	16	1792
4	224	17	2048
5	256	18	2560
6	320	19	3072
7	384	20	3584
8	448	twenty one	4096
9	512	twenty two	5120
10	640	twenty three	6144
11	768	16	7168
12	896	17	8192
13	1024

table 3

i	K	i	K	i	K	i	K
1	48	15	288	29	960	43	3328
2	64	16	320	30	1024	44	3584
3	80	17	352	31	1152	45	3840
4	96	18	384	32	1280	46	4096
5	112	19	416	33	1408	47	4608
6	128	20	448	34	1536	48	5120
7	144	twenty one	480	35	1664	49	5632
8	160	twenty two	512	36	1792	50	6144
9	176	twenty three	576	37	1920	51	6656
10	192	twenty four	640	38	2048	52	7168
11	208	25	704	39	2304	53	7680
12	224	26	768	40	2560	54	8192
13	240	27	832	41	2816	55
14	256	28	896	42	3072	56

Table 4

As an optional design, for the code block partitioning and the code block cyclic redundancy check adding part, the code length of the transport block when the input code block partitioning and the code block cyclic redundancy check is added is greater than the communication system support. When the maximum code block length is used, the transport block can be divided into code blocks of two code block lengths. For example, there are 4 code blocks after the division, wherein the length of 3 code blocks is 5504, and the length of the other code block is 5568. A code block having a longer code block length may be simply referred to as a longer code block, and a code block having a shorter code block length may be simply referred to as a shorter code block.

For convenience of explanation, the length of a longer code block can be expressed as K ₊ , and the length of a shorter code block can be expressed as K _- ; the number of longer code blocks can be expressed as C ₊ , and the number of shorter code blocks It can be expressed as C _- ; the total number of code blocks can be expressed as C, C = C ₊ + C _- ; B represents the length of the transport block of the input code block partition and the code block cyclic redundancy check added portion; Z represents the communication system support Maximum code block length; L represents the number of CRC bits added for each code block;

Indicates rounding up;

Indicates rounding down; B' indicates the sum of the lengths after adding CRC bits to each code block, B'=B+C·L.

As shown in FIG. 5, the processing of the code block division and the code block cyclic redundancy check addition portion mainly includes the following parts. For the scheme of code block segmentation, the embodiment of the present application provides three alternative designs. For ease of explanation, the above three alternative designs will be described in conjunction with the various portions shown in FIG. It should be noted that the various parts of the above three designs may also be combined or replaced according to system requirements. In addition, it should be noted that the numbering of the following parts does not mean the order of time, and can be adjusted according to the actual situation.

S101: Determine the number of code blocks after the transport block is divided.

For example: can be based on

To determine the number of code blocks. Optionally, the transport block is a transport block with a transport block CRC code added, for example, B=B _o +L _TB , where B _o represents the length of the transport block before the CRC addition, and L _TB represents the transport block CRC bit. quantity. Optionally, the transport block is a transport block with a transport block CRC code and a code block group CRC code added, for example, B=B _o +L _TB +N _CBG ·L _CB , where B _o indicates before the CRC is added. The length of the transport block, L _TB represents the number of transport block CRC bits, L _CB represents the number of code block CRC bits, and N _CBG represents the number of code block groups. A transport block can be divided into multiple code block groups and can be designed according to system needs.

Optionally, in the first to third alternative designs, the above may be employed

To determine the number of code blocks.

Optional, the first to third alternative designs can be

Deformation is performed to determine the number of code blocks. For example, the maximum code block size supported by the system is not used to determine the number of code blocks. Optionally, Z may be replaced by Z _v , and Z _v represents an equivalent code block length, and the equivalent code block length may be determined according to an equivalent code rate of the transport block, that is, the number of code blocks and the equivalent code of the transport block. Rate establishes associations.

S102: Determine the length of the longer code block.

In the first alternative design, the minimum code block length that satisfies C·K ≥ B' can be obtained as the length of the longer code block in the code block length supported by the communication system, that is, in the standard code block length. For example: For Turbo codes, the value of K may be selected to meet the above requirements as K ₊ in Table 1; for the LDPC, the value of K may be selected to meet the above requirements as K ₊ in Table 2-4.

In a second alternative design, obtaining K _1, K ₁ is equal to satisfy C · K ₁ ≥B 'smallest integer value, acquired in the standard code block size K satisfies the minimum value K≥K ₁ as K _+. For example, for LDPC, the K values in accordance with the above conditions are selected in Table 2-4. Alternatively, in the second alternative design, K ₁ can also be directly used as K ₊ . At this time, K ₊ may be a standard length or a non-standard block length (referred to as a non-standard length).

In a third alternative design, a non-standard length may be selected as the length of the longer code block, ie the length of the longer code block may be a standard length or may be a non-standard length. For example, for LDPC, the most K value satisfying C·K ≥ B' can be obtained as K ₊ in Table 5 below.

Incidentally, in the first and third alternative design, if C · K ₊ = B ', it indicates that the transport block may be segmented code block length, etc. In this case, C ₊ = C, each The length of the code block is K ₊ ; in the second alternative design, if C·K ₊ = B', it means that the transport block can be divided into code blocks of equal length, in this case, C ₊ = C, each The length of the code block is K ₊ .

S103: Determine the length of the shorter code block.

In the first alternative design, the maximum code block length that satisfies K < K ₊ can be obtained as the length of the shorter code block in the code block length supported by the communication system, that is, in the standard code block length. For example, for a Turbo code, a K value that satisfies the above conditions can be selected as K _- in Table 1, and for LDPC, a K value that satisfies the above conditions can be selected as K ₊ in Table 2-4.

In a second alternative design, K ₂ , K ₂ =K ₁ -1 is obtained, and a minimum K value satisfying K ≥ K ₂ is obtained as a K _- in the standard code block length. Alternatively, K ₂ can be taken as K _- , where K _- may be a standard length or a non-standard length.

In a third alternative design, the non-standard length may be selected as the length of the shorter code block, ie the length of the shorter code block may be a standard length or may be a non-standard length. For example, for LDPC, the maximum K value satisfying K<K ₊ can be obtained as K _- in Table 5 below.

In the following sections S102 and S103, the third alternative design selects a non-standard length or a standard length as a scheme for the length of a longer code block or the length of a shorter code block.

As shown in Table 5, the non-standard lengths are included in Table 5, as well as the standard lengths of Table 4. Multiple non-standard lengths may be referred to as non-standard length sets, and multiple standard lengths may be referred to as standard length sets. Table 5 may be referred to as a set of lengths, including a set of standard lengths and a set of non-standard lengths. The standard length set and the non-standard length set may also be referred to as a sub-length set of the length set. The length set is defined according to the system design, or is stipulated by the communication standard, that is, the length set is known in advance on the receiving side and the transmitting side, or the rule of the length set is generated. The length set can be one or more, and different length sets, standard length sets, or non-standard length sets can be used under different conditions.

Alternatively, values in a non-standard length set can be generated from values in a standard length set. For example, when the non-standard length is within a threshold range, the spacing between the plurality of non-standard lengths is small, and when the non-standard length is within another threshold range, the spacing between the plurality of non-standard lengths is larger. The above thresholds can be formulated based on the standard length.

It should be noted that Table 5 is only an example and is not a limitation on the standard length and non-standard length of the LDPC. In a communication system, the set of standard lengths and non-standard lengths of the LDPC may be Table 5, or a subset of Table 5, or include other values.

table 5

In a third alternative design, the minimum code block length that satisfies C·K ≥ B' can be obtained as the length of the longer code block in the non-standard length and the standard length. For example, for LDPC, the K value that satisfies the above conditions can be selected in Table 5 as K ₊ .

In an optional design of the third, the maximum code block length satisfying K < K ₊ can be obtained as the length of the shorter code block in the non-standard length and the standard length. For example, for LDPC, a K value that satisfies the above conditions can be selected in Table 5 as K _- .

Due to the large interval of the standard length of the LDPC, when the first alternative design is adopted, the difference between K ₊ and K _- is large, which may result in a large difference in the code rate of different code blocks. When using the second or third alternative design, the difference between K ₊ and K _- is more appropriate, and the code rate difference of different code blocks may be reduced compared with the code rate difference of the first alternative design. Small, you can get better system performance.

S104: Determine the number of shorter code blocks.

In the first and third alternative designs, the number of shorter code blocks C _- can pass

To obtain, where Δ _K =K ₊ -K _- .

In a second alternative design, the number of short code blocks C _- by _{C - = C · K 1 -B} ' is obtained.

S105: Determine the number of longer code blocks.

In the first, second and third alternative designs, the number C _{+ of} longer code blocks can be obtained by C ₊ =CC _- .

S106: Perform padding, adding a code block cyclic redundancy check, and dividing the bits of the transport block into each code block.

Each code block can be used

Here, r denotes a code block number, K _r -1 denotes a bit number in the code block, and K _r denotes a length of a code block whose code block number is r, that is, K _r =K ₊ or K _- .

In the first and third alternative designs, if C ₊ · K ₊ + C _- · K _- >B', padding is required, and the number of filled bits F is equal to C ₊ · K ₊ + C _- · K _- -B'. The padding here can be understood as the filling of the code block, and can also be understood as the filling of the transport block. The position of the padded bits in the transport block or code block can be designed as needed, which is not limited in this application. For example, padding may be performed at the foremost or last portion of the transport block, ie, the first code block and the last code block are padded, and may be padded at the foremost or last portion of the first code block. For example: c _0k =<NULL>, k=0...F-1, where c _0k represents the kth bit of the first code block, and <NULL> indicates padding. Alternatively, if C ₊ · K ₊ + C _- · K _- = B', there is no need to fill the corresponding code block.

In the second alternative design, if K _- > K ₁ , the shorter code block needs to be filled, the number of filled bits F ₁ is equal to K _{- -} K ₁ ; when K ₊ > K ₂ , it is necessary to compare The long code block is padded, and the number of filled bits F ₂ is equal to K ₊ -K ₂ . The position filled in the code block is not limited in this application. For example: padding can be done at the end of the code block, for shorter code blocks: c _rk =<NULL>, k=K ₂ ... K _- -1, r=0...C _- -1, and for Longer code blocks: c _rk = <NULL>, k = K ₁ ... K ₊ -1, r = C _- ... C ₊ -1. Alternatively, if K _- = K ₁ or K ₊ = K ₂ , there is no need to fill the corresponding code block.

In the present application, the padding in the S106 portion may be referred to as a first padding.

Optionally, in the foregoing first to third alternative designs, the bit represented as <NULL> may be regarded as a value 0 when encoding, or may be a bit in the matrix and represented as <NULL> when encoding. The corresponding column is deleted, and the input bit segment is encoded using the matrix after column deletion.

Optionally, in the foregoing first to third alternative designs, the bit represented as <NULL> may be skipped when the encoder generates the output bit segment, or may be skipped when the rate matching generates the output bit segment. .

Optionally, the operations filled in the above S106 may be implemented by a separate filler (as shown in FIG. 5). The filler can be a circuit inside the processing unit or can be a logical component of the processing unit.

In the first to third alternative designs described above, the bits of the transport block may be divided into individual code blocks according to different algorithms. For example, reference may be made to the relevant content of section 5.1.2 of the 3GPP standard 36.212 v14.1.1 (2017-1).

In the first to third alternative designs described above, an algorithm for adding CRC bits to a code block can be made as needed. For example, reference may be made to the relevant content of section 5.1.2 of the 3GPP standard 36.212 v14.1.1 (2017-1).

For the first alternative design, the length of the code block output in the S106 portion is a standard length, which can be directly encoded.

For the second optional design, when the code block length outputted by the S106 portion is the standard length, the encoding process is performed without further padding, and when the code block length outputted by the S106 portion is a non-standard length, it may be further filled so that The code block length is a standard length.

For the third alternative design, the code block length output in section S106 may be non-standard length and further padding is required to make the code block length standard length. For example, S201.

S201: Fill the code block whose code block length is non-standard length, so that the length of the code block is a standard length.

In the third alternative design, if K _r is a non-standard length, for example, the minimum K value of K>K _r can be obtained in the standard length set of Table 5 as the pad length after padding, using K _org,r Said. The number of filled bits F _r is equal to K _org,r -K _r . For example, when the length of a longer code block is not the standard length, the number of filled bits is K _{+org, r} -K ₊ ; when the length of the shorter code block is not the standard length, the number of filled bits is K _{-org , r} -K _- . _Wherein, K _{+ org, r} represents the length of a standard set of K> K ₊ minimum value _K; K _{-org, r} represents the length of a standard set of K> K _- K of the minimum value.

Optionally, the padding can be done at the forefront, or the last part of the code block, or at other locations. For example, padding is done at the end of the code block, c _rk = <NULL>, k = K _r ... K _{org, r} -1.

In the present application, the padding in S201 may be referred to as a second padding.

Alternatively, the second padding may be implemented in a code block splitter, or may be implemented in an encoder, or may be implemented by a separate filler (as shown in FIG. 4). The filler can be a circuit inside the processing unit or can be a logical component of the processing unit.

The number of bits filled in the third alternative design may be smaller than the number of bits filled in the second alternative design, which helps to improve decoding performance.

Alternatively, the bit indicated as <NULL> in the S201 portion may be regarded as a value of 0 when encoded. When the S201 portion is performed in the encoder, the encoder skips the bit indicated as <NULL> when outputting in the encoding result. For example: the coded block is

N _r represents the length of the coded block after the coded, and the code block of the output encoder is

In the output, the code block indicated as <NULL> in the S201 portion is skipped.

Alternatively, for the second alternative design, the filling of the S106 portion can also be performed by the encoder. At this time, the encoder skips the bit indicated as <NULL> when outputting in the encoding result.

Optionally, in the S201 part, for the second optional design, when K ₊ or K _- is a non-standard length, the third design may be referred to for the second filling.

Alternatively, the bits indicated as <NULL> in the S201 portion are skipped during rate matching or may be skipped when the encoder outputs.

The second optional design described above can improve the system performance by reducing the difference between different code block lengths, so that the code rates of different code blocks are close to or the same.

The third optional design described above can make the code rates of different code blocks close to each other by uniformly distributing the number of code blocks on adjacent standard lengths, and the number of padding bits is also reasonable, which is helpful for improving the decoding performance. .

It should be noted that the above check code takes CRC as an example. With the development of technology, the above CRC bits can be replaced by other check codes. It should be noted that as the technology develops, code blocks may be grouped, and a check code, that is, a code block group check code, is added to the code block group. It should be noted that, in the above technical solution, it is also possible to not add a check code.

It should be noted that the above process exemplarily illustrates the code block division and coding on the transmitting side. Correspondingly, the receiving side needs to perform decoding and code block cascading according to the above technical solution. In the first alternative design, when the rate is matched, the padded bits are backfilled to the corresponding locations for the CRC of the code block, and the padded bits are removed before the code block is cascaded. In the second alternative design, when the first padding is not performed in the encoder, when the rate is matched, the padded bits are backfilled to the corresponding position for the CRC of the block, and at the block level. The padded bits are removed before the joint; when the first padding is performed in the encoder, the decoder will backfill the padding bits to the corresponding position, and after the decoding is completed, the padding bits are removed before the decoding result is output. In a third alternative design, when the rate is matched, the first padded bit is backfilled to the corresponding position to perform the CRC of the code block, and the first padded bit is removed before the code block is concatenated, and decoded. The second padded bits are backfilled to the corresponding locations, and after the decoding is completed, the second padded bits are removed before the decoding result is output.

In order to more clearly illustrate the technical solution of the present application, the technical solution shown in FIG. 5 will be described below from different angles.

The embodiment of the present application provides a data processing method, as shown in FIG. 6. For the principle, effect and the like of the method shown in FIG. 6, reference may be made to the description of the third alternative design in the technical solution shown in FIG. 5.

The method includes:

S301: The communication device performs a first process on the bit sequence to obtain one or more first sub-bit sequences and one or more second sub-bit sequences.

For the S301, reference may be made to the description of the third optional design in the S106 part of the technical solution shown in FIG. 5.

S302: If the length of the first sub-bit sequence belongs to a non-standard length set, the communications device performs a second processing on the first sub-bit sequence, such that the length of the first sub-bit sequence is equal to the greater than the standard length set. The minimum length of a sub-bit sequence; or,

If the length of the second sub-bit sequence belongs to a non-standard length set, the communication device performs a second processing on the second sub-bit sequence such that the length of the second sub-bit sequence is equal to the second length of the standard length set. The minimum length of the bit sequence.

For the S301, refer to the description of part S201 in the technical solution shown in FIG. 5.

Optionally, the first sub-bit sequence may be a longer code block in the scheme shown in FIG. 5, and the second sub-bit sequence may be a shorter code block in the scheme shown in FIG. 5.

Optionally, the number of the one or more first sub-bit sequences may be C ₊ in the scheme shown in FIG. 5 , and the number of the one or more second sub-bit sequences may be C ₋ in the scheme shown in FIG. 5 . For example, the communication device may obtain the length of the first sub-bit sequence and the length of the second sub-bit sequence according to the length set including the standard length set and the non-standard length set, that is, the length of the first sub-bit sequence and the second sub-bit sequence. The length belongs to the length set.

Optionally, the length of the first sub-bit sequence may be K ₊ in the scheme shown in FIG. 5 , and the length of the second sub-bit sequence may be K ₋ in the scheme shown in FIG. 5 . For example, the length of the second sub-bit sequence is a maximum value smaller than the length of the first sub-bit sequence in the standard length set, that is, the length of the second sub-bit sequence is adjacent to the length of the first sub-bit sequence in the standard length set.

For the acquisition of C ₊ , C _- , K ₊ , K _- , reference may be made to the third alternative design in the technical solution shown in FIG.

Optionally, the first process may be S106 in the solution shown in FIG. 5, that is, the first process includes dividing the bit sequence, and the optional first process may further include the first padding. It should be understood by those skilled in the art that when the length of the bit sequence is exactly the sum of the lengths of the sub-bit sequences of the standard length, the first padding is not required.

Optionally, the standard length set may be a standard length set in Table 5, or a subset of the standard length set in Table 5, or a standard length set of LDPC specified by the 3GPP standard.

Optionally, the non-standard length set may be a non-standard length set in Table 5, or a subset of the non-standard length set in Table 5, or a non-standard length set of LDPC specified by the 3GPP standard.

Optionally, the range matrix expansion factor of the standard length set is associated.

Optionally, the length of the first sub-bit sequence belongs to the non-standard length set, and the length of the first sub-bit sequence may be expressed as a non-standard length, or may be expressed as the length of the first sub-bit sequence is not a standard length, or may be expressed as The length of the first sub-bit sequence does not belong to the standard length set.

Optionally, the length of the second sub-bit sequence belongs to a non-standard length set, and the length of the second sub-bit sequence may be expressed as a non-standard length, or may be expressed as the length of the second sub-bit sequence is not a standard length, or may be expressed as The length of the second sub-bit sequence does not belong to the standard length set.

Optionally, the second process is a second padding.

Optionally, the length of the second padded first sub-bit sequence may be K _+org,r in the scheme shown in FIG. 5 _, and the second padded bit number may be K _+org in the scheme shown in FIG. 5 _{, r} -K ₊ . That is, the number of bits of the second padding is a difference between the minimum value of the length of the standard length set greater than the length of the first sub bit sequence and the length of the first sub bit sequence.

Optionally, the length of the second sub-bit sequence after the second padding may be K- _org,r in the scheme shown in FIG. 5, and the number of bits in the second padding may be K- _org in the scheme shown in FIG _{. r} -K _- . That is, the number of bits of the second padding is the difference between the minimum value of the length of the standard length set greater than the length of the second sub bit sequence and the length of the second sub bit sequence.

Optionally, the communication device may be a base station, a terminal, or a chip.

The embodiment of the present application provides a data processing method, as shown in FIG. 7. For the principle, effect and the like of the method shown in FIG. 7, reference may be made to the description of the third alternative design in the technical solution shown in FIG. 5.

The method includes:

S401: Determine a length and a quantity of the first sub-bit sequence;

S402: Determine a length and a quantity of the second sub-bit sequence;

For the S401-S402, refer to the description of the third optional design in the part of S102-S105 in the technical solution shown in FIG. 5.

S403: Generate one or more of the first sub-bit sequence and one or more of the second sub-bit sequences.

For the S403, refer to the description of the third optional design in the S106 part of the technical solution shown in FIG. 5.

Optionally, the first sub-bit sequence may be a longer code block in the technical solution shown in FIG. 5, and the second sub-bit sequence may be a shorter code block in the technical solution shown in FIG. 5.

Optionally, the length of the first sub-bit sequence may be K ₊ in the technical solution shown in FIG. 5 , and the length of the second sub-bit sequence may be K ₋ in the technical solution shown in FIG. 5 .

Optionally, the number of the first sub-bit sequences may be C ₊ in the technical solution shown in FIG. 5 , and the number of the second sub-bit sequences may be C ₋ in the technical solution shown in FIG. 5 .

Optionally, the length of the first sub-bit sequence is a non-standard length or a standard length; and the length of the second sub-bit sequence is a non-standard length or a standard length. That is, the lengths of the sub-bit sequences of the S401 portion and the S402 portion may be determined based on a set of lengths including a standard length set and a non-standard length set. Optionally, S401 may be expressed as determining a length of the first sub-bit sequence in the length set, and S402 may be expressed as determining a length of the second sub-bit sequence in the length set; wherein the length set includes a standard length set and a non-standard length set.

Optionally, regarding the length set, the standard length set, and the non-standard length set, reference may be made to the description of the technical solution shown in FIG. 5 or FIG. 6.

Optionally, generating the first sub-bit sequence and the second sub-bit sequence may include:

1) dividing and first filling the bit sequence; or,

2) Divide the bit sequence.

For the content related to the partitioning and the first filling, reference may be made to the contents of the technical solutions shown in FIG. 5 and FIG. 6.

"Generating the first sub-bit sequence and the second sub-bit sequence" may also be expressed as dividing a bit sequence to obtain the first sub-bit sequence and the second sub-bit sequence

Optionally, the method may further include S404.

S404: If the length of the first sub-bit sequence belongs to a non-standard length set, the communications device performs a second processing on the first sub-bit sequence, such that the length of the first sub-bit sequence is equal to the greater than the standard length set. The minimum length of a sub-bit sequence; or,

If the length of the second sub-bit sequence belongs to a non-standard length set, the communication device performs a second processing on the second sub-bit sequence such that the length of the second sub-bit sequence is equal to the second length of the standard length set. The minimum length of the bit sequence.

The second process can be expressed as a second padding.

For a description of the relevant part of S404, reference may be made to the related content in S302 in FIG.

The embodiment of the present application further provides a data processing method, as shown in FIG. 8. For the principle, effect and the like of the method shown in FIG. 8, reference may be made to the description of the third alternative design in the technical solution shown in FIG. 5.

The method includes:

S501: The communication device divides the transport block into a plurality of code blocks according to the length set.

The length set includes a first sub-length set and a second sub-length set, the elements in the first sub-length set are standard lengths, and the code blocks having the standard length need not be padded, and the elements in the second sub-length set For non-standard lengths, code blocks with non-standard lengths need to be filled;

The length of the plurality of divided code blocks belongs to the first sub-length set.

The code block divided by S501 refers to the code block (sub-bit sequence) outputted in part S201 of FIG. 5. The segmentation of S501 can be understood to include the division of the bit sequence, and also includes a first padding or a second padding. The implementation of S501 can be found in sections S106 and S201. Optionally, the segmentation of S501 may further include part or all of S101 to S105. Regarding the code block length, the number, and the number of longer code blocks, the content of the number of shorter code blocks can be referred to the S101-S105 part.

Optionally, the value in the first set of sub-lengths is therefore associated with the matrix extension.

Optionally, part or all of the plurality of divided code blocks may include padding bits. For example, it may be a padding bit of the first padding, and/or a padding bit of the second padding.

Optionally, the value of the part of the second length set is between the values of the at least one adjacent two elements in the first subset set. For example, in Table 5, one or more non-standard lengths are distributed between standard lengths.

Optionally, the method further includes:

S502: The communication device performs channel coding on the multiple sub-bit sequences.

For a description of channel coding, reference may be made to the description of channel coding after section S201.

Alternatively, S501 may be implemented by a splitter or may be implemented by a splitter and an encoder.

Alternatively, S502 can be implemented by an encoder.

The embodiment of the present application further provides a data processing method, as shown in FIG. For the principle, effect and the like of the method shown in FIG. 9, reference may be made to the description of the third alternative design in the technical solution shown in FIG. 5.

S601: Segment the bit sequence to obtain a plurality of first sub-bit sequences; wherein, a length of part or all of the first sub-bit sequences of the plurality of first sub-bit sequences is not a standard length;

The plurality of first sub-bit sequences obtained in the S601 part may be the code blocks obtained after S106. For a description of S601, refer to section S106. Optionally, the S601 part may further include a part of S101-S105, that is, including determining the number of code blocks, determining the length of the code block, and the like.

S602: Filling the first sub-bit sequence that is not the standard length to obtain a second sub-bit sequence having a standard length.

Among them, the S602 part can refer to the content of the S201 part.

It should be noted that the second sub-bit sequence having a standard length may be expressed as: the length of the second sub-bit sequence is a standard length.

Optionally, the length of the second sub-bit sequence is a minimum standard length greater than the length of the first sub-bit sequence.

Optionally, the length of the multiple first sub-bit sequences belongs to a length set, where the length set includes a standard length set and a non-standard length set.

Optionally, the length of the second sub-bit sequence belongs to the standard length set.

Optionally, the splitting the bit sequence comprises: dividing the bit sequence according to the length set. That is, the length of the divided bit sequence belongs to the length set.

Optionally, in the length set, a partial value in the standard length set is adjacent to a partial value in the non-standard length set.

Optionally, a part of the first sub-bit sequence of the plurality of first sub-bit sequences has a length of K ₊ , and another part of the first sub-bit sequence has a length of K ₋ , K ₊ ≠K ₋ .

Optionally, K _- is a maximum of less than K ₊ in the set of lengths.

Optionally, the value in the standard length set is associated with a matrix spread factor.

Optionally, the pair of bit sequences is a transport block, the first sub-bit sequence is a first code block, and the second sub-bit sequence is a second code block.

Optionally, the foregoing length set may be, for example, a set of Table 5, the standard length set may be a set of each standard length in Table 5, and the non-standard length may be a set of each non-standard length in Table 5.

Optionally, the execution subject performing the method may be a communication device, and the communication device may be a base station or a terminal.

The embodiment of the present application further provides a data processing method, as shown in FIG. For the principle, effect and the like of the method shown in FIG. 10, reference may be made to the description of the second alternative design in the technical solution shown in FIG. 5.

The method includes:

S701: Determine the length and number of the first sub-bit sequence, and the length and number of the second sub-bit sequence.

S702: Segment the bit sequence.

S703: The communication device fills the first sub-bit sequence.

S704: The communication device fills the second sub-bit sequence.

Optionally, the first sub-bit sequence may be a longer code block, and the second sub-bit sequence may be a shorter code block.

Alternatively, the bit length of the first sub-sequence may be the solution shown in FIG. 5 K _+, the number of the first sub bit sequence may be the solution shown in FIG. 5 C _+, the second sub-bit sequence The length may be K _- in the technical solution shown in FIG. 5, and the number of the first sub-bit sequence may be C _- in the technical solution shown in FIG.

For the acquisition of C ₊ , C _- , K ₊ , K _- , reference may be made to the second alternative design in the technical solution shown in FIG. 5.

For the parts S702 to S704, reference may be made to the description of the second alternative design in the S106 part of the technical solution shown in FIG. 5.

The S703 and S704 portions may be implemented by a splitter or by an encoder.

The embodiment of the present application further provides a communication device, which can be used as the third optional design in FIG. 5, and the communication device in FIG. 6, FIG. 7, FIG. 8 and FIG. 9 is used to implement the data provided by the embodiment of the present application. The method of processing. The structure of the communication device can be as shown in FIG. 2 or FIG. 3. Optionally, the communication device may be a base station or a terminal.

As an alternative embodiment, the processing unit 102 can be used to implement the third alternative design of FIG. 5, the methods of FIG. 6, FIG. 7, FIG. 8 and FIG.

As another alternative embodiment, the memory of the communication device can be used to store programs that implement the third alternative design of Figure 5, the methods of the above described methods in Figures 6, 7, 8, and 9. Processing unit 102 is operative to execute programs in memory to implement related functions of data processing.

The embodiment of the present application further provides a chip, which can be used as the third optional design in FIG. 5, and the communication device in FIG. 6, FIG. 7, FIG. 8 and FIG. 9 is used to implement the data processing provided by the embodiment of the present application. Methods. The chip can include a divider and an encoder. The optional chip may also include a check code appender. For the method of how the splitter, the encoder, and the check code splitter implement the data processing provided by the embodiment of the present application, refer to the third alternative design in FIG. 5, and the technical solutions in FIG. 6, FIG. 7, FIG. 8 and FIG. instruction of.

The embodiment of the present application further provides a computer program product, the program product comprising the program for implementing the third alternative design of FIG. 5, the methods of FIG. 6, FIG. 7, FIG. 8 and FIG.

The embodiment of the present application further provides a computer readable storage medium storing a program for implementing the third alternative design of FIG. 5, the methods of FIG. 6, FIG. 7, FIG. 8 and FIG.

The embodiment of the present application further provides another communication device, which can be used as the second optional design in FIG. 5 and the communication device in FIG. 10 to implement the power control method provided by the embodiment of the present application. Optionally, the node may be a base station. The structure of the communication device can be as shown in FIG. 2 or FIG. 3. Optionally, the communication device may be a base station or a terminal.

As an alternative embodiment, the processing unit 102 can be used to implement the second alternative design of FIG. 5, and the above method of FIG.

As another alternative embodiment, the memory of the communication device can be used to store a program that implements the second alternative design of FIG. 5, and the above method of FIG. Processing unit 102 is operative to execute programs in memory to implement related functions of data processing.

The embodiment of the present application further provides a chip, which can be used as the second optional design in FIG. 5, and the communication device in FIG. 10, for implementing the data processing method provided by the embodiment of the present application. The chip can include a divider and an encoder. The optional chip may also include a check code appender. For the method of the data processing provided by the embodiment of the present application, the second optional design in FIG. 5 and the description of the technical solution in FIG. 10 can be referred to.

The embodiment of the present application further provides a computer program product, which comprises a program for implementing the second optional design in FIG. 5 or the method in FIG.

The embodiment of the present application further provides a computer readable storage medium storing a program for implementing the second optional design in FIG. 5 or the method in FIG.

Those skilled in the art should be aware that the above different optional parts/implementations and the like can be combined and replaced according to different network requirements.

The data processing method, the communication device, the computer program product, and the computer readable storage medium provided by the embodiments of the present application can make the length and the number of different code blocks closer to each other by introducing a non-standard length during the segmentation, and can maintain the code block. The sum of the code rates is stable and the code rates of different code blocks are close. In addition, by making the lengths of different code blocks as equal as possible at the time of division, the code rates of different code blocks can be made close to or the same.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

The above software function parts can be stored in the storage unit. The storage unit includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) or a processor to perform some of the steps of the methods described in various embodiments of the present application. The storage unit includes: one or more memories, such as a read-only memory (ROM), a random access memory (RAM), and an electrically erasable programmable read only memory (EEPROM). and many more. The storage unit may exist independently or may be integrated with the processor.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, only the division of each functional module described above is exemplified. In practical applications, the above function assignment can be completed by different functional modules as needed, that is, the device is installed. The internal structure is divided into different functional modules to perform all or part of the functions described above. For the specific working process of the device described above, refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

It will be understood by those skilled in the art that the various numbers of the first, second, etc., which are referred to herein, are merely for convenience of description and are not intended to limit the scope of the embodiments of the present application.

It will be understood by those skilled in the art that in various embodiments of the present application, the size of the sequence numbers of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, without The implementation process of the embodiments of the present application should be constituting any limitation.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transfer to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.). The computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media. The usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

Finally, it should be noted that the above embodiments are only for explaining the technical solutions of the present application, and are not limited thereto; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present application. range.

Claims (34)

1. A method of data processing, comprising:

   Segmenting the bit sequence to obtain a plurality of first sub-bit sequences; wherein, a length of part or all of the first sub-bit sequences of the plurality of first sub-bit sequences is not a standard length;

   The first sub-bit sequence that is not the standard length is padded to obtain a second sub-bit sequence having a standard length.
2. The method of claim 1 wherein the length of the second sub-bit sequence is a minimum standard length greater than the length of the first sub-bit sequence.
3. The method according to claim 1 or 2, wherein the length of the plurality of first sub-bit sequences belongs to a length set, and the length set comprises a standard length set and a non-standard length set.
4. The method of claim 3 wherein the length of the second sub-bit sequence belongs to the standard length set.
5. The method of claim 3 or 4, wherein the segmenting the bit sequence comprises:

   The bit sequence is segmented according to the set of lengths.
6. The method of any of claims 3-5, wherein in the set of lengths, a partial value in the set of standard lengths is adjacent to a partial value in the set of non-standard lengths.
7. The method according to any one of claims 3-6, wherein a part of the first sub-bit sequence of the plurality of first sub-bit sequences has a length of K ₊ , and another part of the first sub-bit sequence has a length of K _- , K ₊ ≠K _- .
8. The method of claim 7 wherein K _- is a maximum of less than K ₊ in said set of lengths.
9. A method according to any of claims 3-8, wherein the values in the set of standard lengths are associated with a matrix spreading factor.
10. The method according to any one of claims 1-9, wherein the pair of bit sequences is a transport block, the first sub-bit sequence is a first code block, and the second sub-bit sequence is a second code block.
11. A data processing method, comprising:

    Dividing the bit sequence into a plurality of sub-bit sequences according to the set of lengths;

    The length of the sub-bit sequence is a length that does not need to be filled in the sub-bit sequence, the length set includes a first sub-length set that needs to be filled in the sub-bit sequence, and the sub-bit sequence is not required to be The second subset of the length of the padding.
12. The method of claim 11 wherein:

    The partial values of the first set of sub-lengths are distributed between partial values of the second set of sub-lengths.
13. A method according to claim 11 or 12, wherein

    The values in the set of lengths are associated with a low density parity check code LDPC.
14. The method of any of claims 11-13, wherein the method further comprises:

    Channel coding the plurality of sub-bit sequences.
15. A method according to any of claims 11-14, wherein

    The value of the second set of sublengths is associated with a matrix spread factor.
16. A method according to any of claims 11-15, wherein

    A portion of the plurality of sub-bit sequences includes padding bits.
17. A data processing method comprising:

    Performing a first process on the bit sequence to obtain one or more first sub-bit sequences and one or more second sub-bit sequences; the first process is segmentation and first padding, or the first process is segmentation;

    When the length of the first sub-bit sequence belongs to a non-standard length set, the first sub-bit sequence is second-filled such that the length of the first sub-bit sequence is equal to the standard length set is greater than the first The minimum length of a sub-bit sequence; or,

    When the length of the second sub-bit sequence belongs to a non-standard length set, performing a second padding on the second sub-bit sequence such that the length of the second sub-bit sequence is equal to the standard length set is greater than the first The minimum value of the length of the two sub-bit sequences.
18. The method of claim 17, wherein

    The lengths of the first sub-bit sequence and the second sub-bit sequence belong to a length set, and the length set includes the non-standard length set and the standard length set.
19. The method of claim 17 or 18, characterized in that

    The values in the set of standard lengths are associated with a matrix spread factor.
20. The method of any of claims 17-19, characterized in that

    The length of the second sub-bit sequence is a maximum of the length set that is smaller than the length of the first sub-bit sequence.
21. A method according to any one of claims 17 to 20, characterized in that

    Performing the second processing on the first sub-bit sequence includes:

    Encapsulating N bits in a frontmost portion or a last portion of the first sub-bit sequence; wherein N is equal to a minimum value of the length of the standard length set that is greater than a length of the first sub-bit sequence and the first The difference in length of the sub-bit sequence.
22. A method according to any one of claims 17 to 20, characterized in that

    Performing the second processing on the second sub-bit sequence includes:

    Encapsulating M bits in a frontmost portion or a last portion of the second sub-bit sequence; wherein M is equal to a minimum value of the length of the standard length set that is greater than a length of the second sub-bit sequence and the second The difference in length of the sub-bit sequence.
23. The method of any of claims 17-22, characterized in that

    Performing the first processing on the bit sequence includes: dividing and filling the bit sequence; or dividing the bit sequence.
24. A data processing method, comprising:

    Dividing the transport block into multiple code blocks according to the length set,

    The length set includes a first sub-length set and a second sub-length set, the elements in the first sub-length set are a standard length, and the code block having a standard length does not need to be padded, and the second sub-length set The elements in the non-standard length need to be filled for code blocks with non-standard lengths;

    The length of the plurality of divided code blocks belongs to the first sub-length set.
25. The method of claim 24, wherein

    The value of the partial element in the second length set is between the values of at least one adjacent two elements in the first subset set.
26. The method of claim 24 or 25, wherein the method further comprises:

    Channel coding the plurality of sub-bit sequences.
27. The method of any of claims 24-26, characterized in that

    The value of the set of lengths that do not need to be filled is associated with a matrix expansion factor.
28. The method of any of claims 24-27, characterized in that

    A portion of the plurality of sub-bit sequences includes padding bits.
29. The method of any of claims 24-28, characterized in that

    The method is for a communication system employing a low density base even code LDPC.
30. A communication device, comprising:

    A processor for coupling with a memory, reading an instruction in the memory, executing the instruction to perform the method of any of claims 1-29.
31. The device of claim 30, further comprising:

    The memory.
32. A communication device characterized by comprising the communication device and the transceiver as described in claim 30 or 31.
33. A computer program product comprising instructions characterized by causing a communication device to perform the method of any of claims 1-29 when operating on a communication device.
34. A computer readable storage medium comprising instructions, wherein when the instructions are executed on a communication device, causing the communication device to perform the method of any of claims 1-29.

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