WO2018155297A1

WO2018155297A1 - Solid-state imaging device

Info

Publication number: WO2018155297A1
Application number: PCT/JP2018/005215
Authority: WO
Inventors: 裕之網川; 進一荻田; 生熊　誠; 勝野　元成; 憲一仲田; 中村　哲也; 良平宮川; 浩久大槻; 平田　達也
Original assignee: パナソニックＩｐマネジメント株式会社; パナソニック・タワージャズセミコンダクター株式会社
Priority date: 2017-02-27
Filing date: 2018-02-15
Publication date: 2018-08-30

Abstract

Provided is a solid-state imaging device (100) having a plurality of pixel cells (101), wherein each of the plurality of pixel cells (101) includes: a first photoelectric conversion portion (120); a first floating diffusion portion (128); a first transfer transistor (121); a second photoelectric conversion portion (122) having a light receiving area smaller than that of the first photoelectric conversion portion (120); a charge accumulation portion (124) for accumulating a signal charge photoelectrically converted by the second photoelectric conversion portion (122); a second floating diffusion portion (129); and a second transfer transistor (123) for transferring the signal charge accumulated in the charge accumulation portion (124) to the second floating diffusion portion (129). The charge accumulation portion (124) has an insulating film (141) on a semiconductor substrate (140), and an electrode portion (124a) formed on the insulating film (141).

Description

Solid-state imaging device

The present disclosure relates to a solid-state imaging device having a plurality of pixel cells arranged on a matrix.

In recent years, digital cameras with a built-in solid-state imaging device have become widespread.

FIG. 15 is a cross-sectional view illustrating a configuration of a unit pixel of the solid-state imaging device described in Patent Document 1. This solid-state imaging device has a plurality of unit pixels that are two-dimensionally arranged on the semiconductor substrate 30 at a constant pitch. As shown in FIG. 15, each unit pixel has a saturated charge more than the first photodiode 31a for photoelectrically converting and storing incident light and the first photodiode 31a for photoelectrically converting and storing incident light. A second photodiode 31b having a large amount, a first microlens 33a for condensing light on the first photodiode 31a, and a first for condensing light on the second photodiode 31b. And a second micro lens 33b having a smaller opening than the micro lens 33a. The first photodiode 31a corresponds to a high sensitivity pixel, and the second photodiode 31b corresponds to a low sensitivity pixel.

The solid-state imaging device configured in this manner reads both the signals of the first photodiode 31a and the second photodiode 31b when the signal charge is low and the illuminance is low, and outputs the second signal when the signal charge is high and the illuminance is high. Only the signal of the photodiode 31b is read out. As a result, the dynamic range is expanded.

JP 2011-188148 A

By the way, in recent years, LED light sources have become popular in the world due to technological progress of LED (Light Emitting Diode) light sources. As a method for adjusting the light amount of the LED light source, there is a method of periodically turning on and off the light source.

FIG. 14 is a time chart showing the blinking timing of the LED light source and the exposure timing at which the photodiode of the solid-state imaging device receives light. Here, (a) the LED light source is repeatedly turned on and off at a period of, for example, 1/100 s. Further, (b) the frame period of the solid-state imaging device is set to 1/30 s, for example. As operations of the solid-state imaging device, (c) imaging with electronic SHT (that is, electronic shutter) operation and (d) imaging without electronic SHT operation (always exposure operation) are shown. The electronic SHT operation refers to clearing the signal charge of the photodiode. In (c) and (d), the vertical axis indicates the scanning line from the first line to the last line. (C) In imaging with an electronic SHT (shutter) operation, a rolling shutter operation in which an electronic SHT operation (dashed timing) and a signal readout operation (thick solid line timing) are sequentially repeated for each row from the first row to the last row is shown. ing.

First, for (c) imaging with an electronic SHT operation, the width of the hatched portion, that is, the time from the electronic SHT operation (dashed line) to the signal readout operation (thick solid line) is the exposure period. When the LED light source is turned on during this period, the signal charge photoelectrically converted by the photodiode is accumulated. In the figure, in the second and fifth frames marked with a cross among the six frames, the LED light source is turned off during the exposure period, and the image is taken darkly or the LED light source is imaged without being illuminated. On the other hand, in the 1st, 3rd, 4th, and 6th frames marked with a circle, the LED light source is lit during the exposure period, and the bright image is taken, or the LED light source is illuminated and taken. As a result, when multiple frame imaging is repeated, the solid-state imaging device generates a dark frame and a bright frame. When the frames are continuously displayed, the flicker phenomenon (hereinafter referred to as the LED flicker phenomenon) is repeatedly turned on and off at the LED light source portion of the captured image. May occur).

As a general method for improving the LED flicker phenomenon, there is (d) imaging without electronic SHT operation (always exposure operation). In other words, by always exposing the solid-state imaging device, the photodiode receives light without missing the lighting timing of the LED light source, and in the first to sixth frames (all frames) marked with a circle, the LED light source is not exposed during the exposure period. Illuminated and brightly imaged, or LED light source is illuminated and imaged. Thus, (d) without the electronic SHT operation (always exposure operation), it is possible to suppress the occurrence of the flicker phenomenon in the LED light source of the captured image.

However, when this general method is performed with the low-sensitivity pixel of the conventional disclosed technique (Patent Document 1), the photodiode is easily saturated by the constant exposure operation, and there is a problem that a captured image cannot be obtained. To do. Furthermore, since it becomes impossible to set an optimal exposure period according to the shooting scene, an image is generated only with high-sensitivity pixels having photodiodes having a smaller area than low-sensitivity pixels, and only images with a narrow dynamic range are obtained. The problem that cannot be done occurs.

Therefore, an object of the present disclosure is to provide a solid-state imaging device that obtains an image in which a flicker phenomenon is suppressed in a configuration in which unit pixels are formed by two types of pixels, a high-sensitivity pixel and a low-sensitivity pixel.

In order to solve the above problem, a solid-state imaging device according to the present disclosure is a solid-state imaging device having a plurality of pixel cells arranged on a matrix, and each of the plurality of pixel cells is formed on a semiconductor substrate. One photoelectric conversion unit, a first floating diffusion unit, a first transfer transistor that transfers a signal charge photoelectrically converted by the first photoelectric conversion unit to the first floating diffusion unit, and the first A second photoelectric conversion unit having a light receiving area smaller than that of the photoelectric conversion unit, a charge storage unit that stores signal charges photoelectrically converted by the second photoelectric conversion unit, a second floating diffusion unit, and the charge A second transfer transistor for transferring the signal charge stored in the storage unit to the second floating diffusion unit, Load storage unit includes an insulating film on the semiconductor substrate, and an electrode portion formed on the insulating film.

According to the present disclosure, an image in which the flicker phenomenon is suppressed can be obtained in a configuration in which a unit pixel is formed by two types of pixels, a high sensitivity pixel and a low sensitivity pixel.

Since the second photoelectric conversion unit having a light receiving area smaller than that of the first photoelectric conversion unit has a charge storage unit, the saturation charge amount can be increased while the photoelectric conversion unit has a lower sensitivity. A low-sensitivity pixel that can realize a wide dynamic range can be obtained. Here, an image in which the flicker phenomenon of the LED light source is suppressed can be obtained by always exposing the low-sensitivity pixels. In addition, since the light receiving area of the first photoelectric conversion unit is larger than that of the second photoelectric conversion unit, a high-sensitivity pixel that secures a saturated charge amount can be configured. Obtainable. That is, by combining the image in which the flicker phenomenon of the LED light source is suppressed with the low sensitivity pixel including the second photoelectric conversion unit and the captured image of the high sensitivity pixel, an image having a dynamic range in which the flicker phenomenon is suppressed is obtained. be able to.

That is, it is possible to generate an image signal in which flicker generation by a pulse light source is suppressed with one solid-state imaging device.

FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device according to the embodiment. FIG. 2 is a diagram illustrating an example of a circuit configuration of a pixel cell in the solid-state imaging device according to the embodiment. FIG. 3 is a diagram illustrating a first example of a pixel layout configuration in the solid-state imaging device according to the embodiment. FIG. 4 is a schematic diagram illustrating a cross section of a low-sensitivity pixel, a cross section of a semiconductor substrate, and a potential (potential) after (a) a reset operation and (b) during charge transfer in the solid-state imaging device according to the embodiment. FIG. 5 is a diagram illustrating a relationship between subject illuminance and signal charge amount of high-sensitivity pixels and low-sensitivity pixels in the solid-state imaging device according to the embodiment. FIG. 6 is a diagram illustrating a second example of the pixel layout configuration in the solid-state imaging device according to the embodiment. FIG. 7 is a diagram illustrating a third example of the pixel layout configuration in the solid-state imaging device according to the embodiment. FIG. 8 is a diagram illustrating an example of a schematic cross section of the solid-state imaging device according to the embodiment. FIG. 9 is a diagram illustrating another example of the schematic cross section of the solid-state imaging device according to the embodiment. FIG. 10 is a diagram illustrating a first example of a schematic cross section of (a) a high-sensitivity pixel and (b) a low-sensitivity pixel in the solid-state imaging device according to the embodiment. FIG. 11 is a diagram illustrating a relationship between the optical waveguide width and the light collection efficiency in the solid-state imaging device according to the embodiment. FIG. 12 is a diagram illustrating a second example of a schematic cross section of (a) a high-sensitivity pixel and (b) a low-sensitivity pixel in the solid-state imaging device according to the embodiment. FIG. 13 is a diagram illustrating a third example of a schematic cross section of (a) a high-sensitivity pixel and (b) a low-sensitivity pixel in the solid-state imaging device according to the embodiment. FIG. 14 is a time chart showing the blinking timing of the LED light source and the exposure timing at which the photodiode of the solid-state imaging device receives light. FIG. 15 is a cross-sectional view showing a configuration of a conventional solid-state imaging device.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that each of the embodiments described below shows a specific example of the present disclosure. Numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of constituent elements, drive timings, and the like shown in the following embodiments are merely examples, and are not intended to limit the present disclosure. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present disclosure are described as arbitrary constituent elements. Also, the drawings are not necessarily shown strictly.

In the embodiment described below, a component corresponding to a high-sensitivity pixel may be given a first, and a component corresponding to a low-sensitivity pixel may be given a second.

Further, the solution (effect) of the LED flicker phenomenon according to the present disclosure is not limited to the LED (LED light source, light emitting diode, light emitting diode light source) that is a pulse light source, as shown in the embodiments described below. Other pulse light sources (for example, LD (LD light source, laser diode, laser diode light source), and as specific examples, traffic lights equipped with LED light sources, LD light sources, LED light sources, LD light sources, etc., head rides, The same effect can be obtained for transportation equipment (for example, an automobile) used for a stop lamp or the like. However, in order to facilitate understanding of the present disclosure, a flicker phenomenon caused by a pulse light source other than an LED is also referred to as an LED flicker phenomenon in the present embodiment.

Hereinafter, the solid-state imaging device according to each embodiment will be described using a MOS image sensor (CMOS image sensor) as an example with reference to the drawings.

FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device 100 according to the embodiment. As shown in FIG. 1, the solid-state imaging device 100 according to the present embodiment includes a pixel array unit 102, a driver circuit 103, a vertical scanning circuit 104, a vertical signal line VL, a constant current source circuit 105, a column readout circuit 106, a horizontal scanning. A circuit 107 is provided.

The pixel array unit 102 includes a large number of pixel cells (also referred to as unit cells or unit pixels) 101 that perform photoelectric conversion arranged in a matrix.

The driver circuit 103 outputs various control signals for driving the pixel array unit 102 for each row scanned by the vertical scanning circuit 104.

The vertical scanning circuit 104 scans the pixel array unit 102 in units of rows of the pixel cells 101.

The vertical signal line VL is provided for each column of the pixel cells 101 and transmits a signal of the pixel cell 101 to the column readout circuit 106. A constant current source circuit 105 and a column readout circuit 106 are connected to the vertical signal line VL.

The constant current source circuit 105 has a constant current source for each column connected to the vertical signal line VL for each column. The constant current source is paired with the amplification transistor in the pixel cell 101 to form a source follower circuit.

The column readout circuit 106 has a noise canceller (CDS: Correlated Double Sampling) circuit and an analog-to-digital conversion (ADC) circuit provided for each column. The noise canceller (CDS) circuit receives two pixel signals (reset level and signal level) from the corresponding column and takes the difference between the two pixel signals. The analog-digital conversion circuit receives the pixel signal (difference) from the CDS circuit and converts the analog data into digital data.

The horizontal scanning circuit 107 performs scanning that sequentially selects the columns of the pixel cells 101, and sequentially outputs the digital data of the selected columns to the outside of the solid-state imaging device 100.

The CDS circuit included in the column readout circuit 106 is connected for each column of the pixel cells 101 arranged in a matrix in the pixel array unit 102, for example. The CDS circuit is generated in the pixel cell 101 by CDS (correlated double sampling) processing on a signal output from the pixel cell 101 in the row selected by the vertical scanning circuit 104 through the vertical signal line VL. The signal processing for removing the reset noise and the fixed pattern noise specific to the pixel due to the threshold value variation of the transistor is performed, and the pixel signal after the signal processing is temporarily held.

The analog-digital conversion circuit (ADC) has an AGC (Auto-Gain-Control) function and an analog-digital conversion function, and the ADC converts a pixel signal that is an analog signal held in the CDS circuit into a digital signal. .

FIG. 2 is a diagram illustrating an example of a circuit configuration of the pixel cell 101 in the solid-state imaging device 100 according to the embodiment. The pixel cell 101 includes a first photoelectric conversion unit 120, a first transfer transistor 121, a second photoelectric conversion unit 122, a second transfer transistor 123, a charge storage unit 124, a switch transistor 125, a reset transistor 126, and an amplification transistor. 127, a first FD (Floating Diffusion) unit 128, and a second FD unit 129. A high-sensitivity pixel 110 surrounded by a broken line in FIG. 2 corresponds to the first photoelectric conversion unit 120, the first FD unit 128, and the first transfer transistor 121. The low sensitivity pixel 111 corresponds to the second photoelectric conversion unit 122, the second FD unit 129, the second transfer transistor 123, and the charge storage unit 124.

The first photoelectric conversion unit 120 (hereinafter also referred to as the first photodiode 120) is a photodiode formed on a semiconductor substrate, and electrically converts light into signal charges.

For example, the first transfer transistor 121 is turned on when the transfer control line TGL is at a high level. As a result, the first transfer transistor 121 transfers the signal charge photoelectrically converted by the first photoelectric conversion unit 120 to the first FD unit 128.

The second photoelectric conversion unit 122 (hereinafter also referred to as a second photodiode 122) is a photodiode formed on a semiconductor substrate, has a light receiving area smaller than that of the first photodiode 120, and transmits light as a signal. Converts to electric charge.

The second transfer transistor 123 is turned on when the transfer control line TGS is at a high level, for example. As a result, the second transfer transistor 123 transfers the signal charge photoelectrically converted by the second photoelectric conversion unit 122 and accumulated in the charge accumulation unit 124 to the second FD unit 129.

The charge storage unit 124 is a capacitive element that stores signal charges generated by photoelectric conversion in the second photoelectric conversion unit 122. The charge storage unit 124 is formed as a MOS capacitor, for example, and includes an insulating film on the semiconductor substrate and an electrode unit formed on the insulating film, and a signal is interposed between the semiconductor substrate and the electrode unit that sandwich the insulating film. Accumulate charge. When the charge storage unit 124 is a MOS capacitor, the electrode unit corresponds to a gate electrode. For example, when the control line CG connected to the electrode unit is at a high level, the charge storage unit 124 stores the signal charge photoelectrically converted by the second photoelectric conversion unit 122. The signal charge accumulated in the charge accumulation unit 124 is transferred to the second FD unit 129 by the second transfer transistor 123 when the control line CG is at low level and the transfer control line TGS is at high level. The charge storage unit 124 plays a role of greatly increasing the maximum storage capacity (that is, the saturation signal charge amount) of the signal charge generated by the photoelectric conversion of the second photodiode 122.

For example, when the switch control line SW is at a high level, the switch transistor 125 makes the first FD unit 128 and the second FD unit 129 conductive.

The reset transistor 126 resets the second FD unit 129 (to a high level), for example, when the reset control line RS is at a high level.

The amplification transistor 127 forms a source follower circuit paired with the constant current source in the constant current source circuit 105, converts the potential of the first FD unit 128 into a voltage, and outputs the voltage to the vertical signal line VL.

The first FD portion 128 is a floating diffusion layer formed on the semiconductor substrate, and holds the signal charge transferred by the first transfer transistor 121.

The second FD portion 129 is a floating diffusion layer formed on the semiconductor substrate, and holds the signal charge transferred by the second transfer transistor 123.

As described above, by adding the charge storage unit 124 to the second photoelectric conversion unit 122 having a light receiving area smaller than that of the first photoelectric conversion unit 120, the sensitivity is lower than that of the first photoelectric conversion unit 120, but saturation is achieved. The amount of charge can be increased. Therefore, the low sensitivity pixel 111 can realize a wide dynamic range. Thereby, the image which suppressed the flicker phenomenon of the LED light source can be obtained by always performing the exposure operation of the low sensitivity pixel 111. In addition, since the light receiving area of the first photoelectric conversion unit 120 is larger than that of the second photoelectric conversion unit 122, it is possible to obtain a high-sensitivity pixel that secures a saturated charge amount, and thus an image that secures a dynamic range is obtained. be able to. In other words, by synthesizing an image in which the LED photoelectric flicker phenomenon is suppressed with low-sensitivity pixels and a photographed image of the high-sensitivity pixels, an image having a dynamic range in which the flicker phenomenon is suppressed can be obtained.

Thereby, it is possible to generate an image signal in which flicker generation by a pulse light source is suppressed by one solid-state imaging device 100.

Next, the operation of the circuit example of the pixel cell 101 shown in FIG. 2 will be specifically described.

As shown in FIG. 2, in the pixel cell 101 according to this circuit example, the high sensitivity pixel 110 and the low sensitivity pixel 111 share the switch transistor 125, the reset transistor 126, and the amplification transistor 127. That is, the high-sensitivity pixel 110 includes an element that performs photoelectric conversion, for example, the first photodiode 120 and the first transfer transistor 121. The low sensitivity pixel 111 includes a second photodiode 122, a second transfer transistor 123, and a charge accumulation unit 124. Further, the pixel cell 101 includes a switch transistor 125, a reset transistor 126, and an amplification transistor 127 that are shared and used by the high sensitivity pixel 110 and the low sensitivity pixel 111. As each of the transistors 121 to 127, for example, an N-channel MOS transistor may be used. Note that the N-channel MOS transistor (Nch transistor) is turned on when the gate potential is “High” level, and is turned off when the gate voltage is “Low”. The P-channel MOS transistor (Pch transistor) is turned on when the gate potential is “Low” level, and is turned off when the gate voltage is “High”. In FIG. 2, it is assumed that the transistors 121 to 127 are N-channel MOS transistors.

The first transfer transistor 121 is connected between the cathode electrode of the first photodiode 120 and the first FD portion 128. A transfer control line TGL is connected to the gate electrode of the first transfer transistor 121. When the “High” level is applied to the gate electrode of the first transfer transistor 121 from the transfer control line TGL by the transfer pulse φTGL, the first transfer transistor 121 is turned on and photoelectrically converted by the first photodiode 120. The signal charges (specifically electrons) accumulated in the first photodiode 120 are transferred to the first FD unit 128.

The second transfer transistor 123 is connected between the cathode electrode of the second photodiode 122 and the semiconductor substrate of the charge storage unit 124 and the second FD unit 129. A transfer control line TGS is connected to the gate electrode of the second transfer transistor 123. When a “High” level is applied to the gate electrode of the second transfer transistor 123 from the transfer control line TGS by the transfer pulse φTGS, the second transfer transistor 123 is turned on and is photoelectrically converted by the second photodiode 122. Then, signal charges (specifically electrons) accumulated in the second photodiode 122 are transferred to the second FD portion 129.

Further, a control line CG is connected to the electrode part of the charge storage part 124. When the second transfer transistor 123 is turned on and a “Low” level is applied to the electrode portion of the charge storage portion 124 by the control pulse φCG from the control line CG, the charge storage portion 124 has a gap between the semiconductor substrate and the electrode portion. The accumulated signal charge (specifically, electrons) is transferred to the second FD portion 129 via the second transfer transistor 123. During the exposure period, the gate electrode of the charge storage unit 124 is given a “High” level by the control pulse φCG from the control line CG, and the charge storage unit 124 receives the signal charge generated by the second photodiode 122. accumulate.

As for the reset transistor 126, the reset control line RS is connected to the gate electrode, the pixel power supply wiring VDDC is connected to the drain electrode, and the second FD portion 129 is connected to the source electrode. In the switch transistor 125, the switch control line SW is connected to the gate electrode, the second FD portion 129 is connected to the drain electrode, and the first FD portion 128 is connected to the source electrode.

First, the readout control of the high sensitivity pixel 110 will be described.

Before transferring the signal charge from the first photodiode 120 to the first FD unit 128, the reset control line RS is transmitted to the gate electrode 126a of the reset transistor 126 to give a “High” level by the reset pulse φRS, Further, when the switch control line SW is transmitted to the gate electrode 125a of the switch transistor 125 and the “High” level is given by the switch pulse φSW, the reset transistor 126 and the switch transistor 125 are turned on. As a result, the potentials of the first FD unit 128 and the second FD unit 129 are reset to the power supply voltage AVDD. After the first FD portion 128 and the second FD portion 129 are reset to the power supply voltage AVDD, a “High” level is given to the gate electrode 126a of the reset transistor 126 by a reset pulse φRS, and the gate electrode 125a of the switch transistor 125 is given. Gives a “Low” level with the switch pulse φSW. As a result, the first FD unit 128 is in a state where the reset operation has been completed.

As for the amplification transistor 127, the gate electrode is connected to the first FD portion 128, the drain electrode is connected to the pixel power supply wiring VDDC, and the source electrode is connected to the vertical signal line VL. The amplification transistor 127 outputs the potential of the first FD portion 128 after being reset by the reset transistor 126 and the switch transistor 125 to the vertical signal line VL as a reset level, and further, the first transfer transistor 121 generates a signal charge. The potential of the first FD unit 128 after the transfer is output as a signal level to the vertical signal line VL.

Next, readout control of the low sensitivity pixel 111 will be described. Before the signal charge is transferred from the second photodiode 122 to the second FD portion 129, the reset transistor 126 and the switch transistor 125 are turned on, and the potentials of the first FD portion 128 and the second FD portion 129 are changed. Reset to power supply voltage AVDD. After the first FD portion 128 and the second FD portion 129 are reset to the power supply voltage AVDD, a “Low” level is given to the gate electrode 126a of the reset transistor by the reset pulse φRS, and the gate electrode 125a of the switch transistor is switched to the switch electrode A “High” level is given by the pulse φSW. Thereby, the reset operation is completed in a state where the first FD portion and the second FD portion are electrically connected.

The amplifying transistor 127 outputs the potentials of the first FD unit 128 and the second FD unit 129 after being reset by the reset transistor 126 and the switch transistor 125 to the vertical signal line VL as a reset level. The potentials of the first FD portion 128 and the second FD portion 129 after the signal charge is transferred by the transfer transistor 123 are output as signal levels to the vertical signal line VL. Here, in the first FD unit 128 and the second FD unit 129, a voltage corresponding to the signal charge amount is transmitted to the amplification transistor 127. The signal charge-to-voltage conversion formula is ΔV = Q / C, and the conversion efficiency η is expressed as η = 1 / C. The conversion efficiency η is determined by the capacitance value C of the first FD unit 128 and the second FD unit 129. In the case of the low-sensitivity pixel 111, the first FD portion 128 and the second FD portion 129 are connected to the gate electrode 127a of the amplification transistor, and therefore the gate electrode 127a of the amplification transistor in the case of the high-sensitivity pixel 110. Compared with the state where only the first FD unit 128 is connected to the converter, the conversion efficiency η is lowered.

Here, the higher the conversion efficiency η, the more efficiently the signal charge can be converted into voltage, and the voltage value of the signal amplitude can be increased. As a result, the ratio S / N of the pixel signal S to the noise component N generated in the constant current source circuit 105 and the column readout circuit 106 connected to the vertical signal line VL can be improved, and a high-quality image can be obtained. .

In the present disclosure, the high-sensitivity pixel 110 acquires image data of a subject under various environments from low illuminance to high illuminance, and the low-sensitivity pixel 111 captures an image in which the flicker phenomenon of the LED light source (pulse emission source) is suppressed. Acquired and combined to obtain image data in which the flicker phenomenon of the LED light source is suppressed.

At this time, the high-sensitivity pixel 110 is required to generate a high-quality image in order to acquire images under various environments. In particular, in order to obtain a high-quality image in a low illuminance environment of less than 1 lux, a higher conversion efficiency η is required. To realize this, the capacitance value C of the first FD unit 128 needs to be reduced.

On the other hand, the low-sensitivity pixel 111 always performs an exposure operation in order to obtain an image in which the flicker phenomenon of the LED light source is suppressed. In addition, a charge storage unit 124 is connected in order to ensure a dynamic range necessary for acquiring images of various LED light sources. Since the charge storage unit 124 stores a larger amount of signal charge, a small conversion efficiency η is required. For this purpose, it is necessary to increase the capacitance C connected to the second FD unit 129.

In the configuration of the present disclosure, the switch transistor 125 is provided between the first FD unit 128 and the second FD unit 129, and the amplification transistor 127 is connected to the first FD unit 128. As a result, when reading the signal charge of the high sensitivity pixel 110, the switch transistor 125 is read in the OFF state, so that only the first FD portion 128 is connected to the gate electrode 127a of the amplification transistor 127. Conversion efficiency η is obtained. Further, when the signal charge of the low-sensitivity pixel 111 is read out, the first FD portion 128 and the second FD portion 129 are connected to the gate electrode 127a of the amplification transistor by reading the switch transistor 125 in the ON state. Thus, a smaller conversion efficiency η is obtained.

Here, in order to obtain a desired conversion efficiency η for the low-sensitivity pixel 111, a capacity may be given to the second FD unit 129. At this time, since the high-sensitivity pixel 110 reads the signal charge with the switch transistor 125 turned off, the conversion efficiency η is not affected, and high image quality can be maintained.

In the reading operation of the high-sensitivity pixel 110, when the signal charge is read out similarly to the low-sensitivity pixel 111, the switch transistor 125 is turned on, the reset transistor 126 is turned off, and the first FD unit 128 and the second FD are turned on. The conversion may be performed by reducing the conversion efficiency η of the unit 129. This is because when a subject is imaged in a high-illuminance environment, the amount of signal charge accumulated in the first photodiode 120 of the high-sensitivity pixel 110 is larger than that in a low-illuminance environment. This is effective as a means for preventing the amount of voltage ΔV from exceeding the dynamic range of the vertical signal line VL.

The pixel cell 101 is configured such that one high-sensitivity pixel 110 and one low-sensitivity pixel 111 share the switch transistor 125, the reset transistor 126, and the amplification transistor 127. 110 and two low-sensitivity pixels 111 may share the switch transistor 125, the reset transistor 126, and the amplification transistor 127.

A selection transistor for selecting a row corresponding to the readout row of the pixel array portion 102 is connected between the source of the amplification transistor 127 and the vertical signal line VL between the amplification transistor 127 and the vertical signal line VL. It may be.

In FIG. 2, the gate electrode of the amplification transistor 127 may be connected to the second FD unit 129 instead of being connected to the first FD unit 128.

In FIG. 2, one FD may be provided instead of the first FD unit 128, the second FD unit 129, and the switch transistor 125. In other words, the switch transistor 125 may be omitted, and the first FD unit 128 and the second FD unit 129 may be integrated.

FIG. 3 is a diagram illustrating a first example of a pixel layout configuration in the solid-state imaging device 100 according to the embodiment. As shown in the figure, the pixel cell 101 includes a high sensitivity pixel 110 and a low sensitivity pixel 111.

The high-sensitivity pixel 110 includes a first photodiode 120 and a gate (first gate electrode) 121a of a first transfer transistor that transfers the signal charge photoelectrically converted by the first photodiode 120 to the first FD unit 128. Is provided.

The low-sensitivity pixel 111 includes a second photodiode 122 having an area smaller than that of the first photodiode 120, an electrode portion 124 a of the charge accumulation portion 124 that accumulates signal charges photoelectrically converted by the second photodiode 122, The gate electrode (second gate electrode) 123a of the second transfer transistor 123 that transfers the signal charge to the FD portion 129 is configured to sandwich the electrode portion 124a of the charge storage portion 124 and the second photodiode 122. The Here, an example of the gate material is Poly silicon. In addition, the elements such as the first photodiode 120 and the second photodiode 122 are electrically separated in the element isolation region 130. The gate electrode 125a of the switch transistor 125 is connected between the first FD portion 128 and the second FD portion 129, and the reset transistor 126 is connected between the pixel power supply line VDDC and the second FD portion 129. Gate electrode 126a is connected. In addition, the first FD portion 128 and the gate electrode 127a of the amplification transistor 127 are electrically connected. The pixel power supply line VDDC is connected to the drain of the amplification transistor 127 and the vertical signal line VL is connected to the source, and the pixel signal is amplified and transmitted to the vertical signal line VL.

Here, the high-sensitivity pixel 110 and the low-sensitivity pixel 111 are provided with filters of the same color, such as a green filter, and the LED light source that has been missed by the high-sensitivity pixel 110 is photoelectrically converted by the low-sensitivity pixel 111 that always performs an exposure operation. An image in which the LED flicker phenomenon is suppressed is generated by acquiring the pixel signal and combining the pixel signals of the high-sensitivity pixel 110 and the low-sensitivity pixel 111.

Further, in the low-sensitivity pixel 111, when the electrode portion 124a of the charge accumulation portion 124 is on the second photodiode 122, blue light having a short wavelength is absorbed by the gate electrode. The problem that blue light does not reach occurs. In FIG. 3, the electrode portion 124 a of the charge storage portion 124 is disposed in a region adjacent to the second photodiode 122. That is, the electrode portion 124a does not cover the second photodiode 122 in plan view. Thus, the layout avoids blue light attenuation.

In addition, the first photodiode 120 of the high-sensitivity pixel 110, the gate electrode 121a of the first transfer transistor, and the first FD portion 128 are arranged in the vertical direction, and signal charges are transferred upward in the drawing. On the other hand, also in the low-sensitivity pixel 111, the second photodiode 122, the gate electrode 123a of the second transfer transistor, and the second FD portion 129 are arranged in the vertical direction, and signal charges are transferred upward in the drawing. Thus, by matching the transfer direction between the high-sensitivity pixel 110 and the low-sensitivity pixel 111, a characteristic difference due to transfer variation between the first transfer transistor 121 and the second transfer transistor 123 (for example, the signal charge at the time of transfer Residual image characteristics remaining in the photodiode 120 and / or the second photodiode 122) can be suppressed.

In the low-sensitivity pixel 111, the electrode portion 124a of the charge storage portion 124 and the gate electrode 123a of the second transfer transistor are arranged so as to sandwich the second photodiode 122. Accordingly, the electrode portion 124a of the charge storage portion 124 extends the gate electrode in a direction opposite to the gate electrode 123a of the second transfer transistor, whereby the second photodiode 122 and the gate electrode 123a of the second transfer transistor. The charge accumulation amount of the charge accumulation unit 124 can be increased without affecting the efficiency (sensitivity) of photoelectric conversion and the transfer of signal charges (for example, afterimage characteristics).

FIG. 4 is a schematic diagram illustrating a cross section and a potential (potential) of the semiconductor substrate 140 of the low-sensitivity pixel 111 after the reset operation and (b) during charge transfer in the solid-state imaging device 100 according to the embodiment. is there. The upper stage in FIGS. 4A and 4B corresponds to the cross section taken along the dashed-dotted line IV-IV in FIGS. The lower part of FIGS. 4A and 4B shows the potential on the AA line of the upper part.

4A is after the reset operation, and in the low-sensitivity pixel 111, the second FD portion 129, the semiconductor substrate 140 under the gate electrode 123a of the second transfer transistor 123, and the second The potential on the AA line indicated by the broken line passing through the photodiode 122 (denoted as the second PD portion in the figure) and the semiconductor substrate 140 below the electrode portion 124a of the charge storage portion 124 is shown. As described above, after the reset operation, the second FD unit 129 is reset to the power supply voltage AVDD. At this time, the “Low” level is applied to the gate electrode 123a of the second transfer transistor 123 by the transfer pulse φTGS from the transfer control line TGS. Further, a “High” level is given to the electrode portion 124 a of the charge accumulation unit 124 by the control pulse φCG from the control line CG, and signal charges (that is, electrons) are accumulated in the charge accumulation unit 124. At this time, the potential of the semiconductor substrate 140 is the lowest at the lower part of the second transfer transistor 123, and the signal charge is stored in the lower part of the charge storage unit 124.

(B) of FIG. 4 shows the potential at the AA line indicated by a broken line during charge transfer. As described above, during charge transfer, the gate electrode 123a of the second transfer transistor 123 is given a “High” level from the transfer control line TGS by the transfer pulse φTGS. Further, the electrode portion 124 a of the charge storage unit 124 is given a “Low” level by the control pulse φCG from the control line CG, and the signal charge is transferred from the charge storage unit 124 to the second photoelectric conversion unit 122 via the second photoelectric conversion unit 122. It has been transferred to the FD unit 129. At this time, the potential of the semiconductor substrate 140 becomes, in descending order, the second FD portion 129, the lower portion of the gate electrode 123a of the second transfer transistor, the second photodiode 122, and the lower portion of the electrode portion 124a of the charge storage portion 124, It is possible to transfer the signal charges accumulated in the lower part of the photodiode 122 and the electrode portion 124 a of the charge accumulation portion 124 to the second FD portion 129. Here, assuming that the semiconductor substrate 140 is a P-type substrate having a hole charge concentration higher than the electron concentration, the potential of the semiconductor substrate 140 is GND, and the signal charge is composed of electrons, In order to move to the FD portion 129, it is necessary to control the potential potential of the semiconductor substrate 140 below the electrode portion 124a of the charge storage portion 124 between the potential potential of the second photodiode 122 and the GND potential. This is because the “Low” voltage of the control pulse φCG is controlled to GND or a negative voltage, whereby the semiconductor substrate 140 under the electrode portion 124a of the charge storage portion 124 enters a storage state in which hole charges are stored. As a result, the potential of the semiconductor substrate 140 that is electrically connected to the semiconductor substrate 140 and is lower than the electrode portion 124a of the charge storage portion 124 becomes GND, so that the desired potential can be made relatively easily.

On the other hand, if the electrode portion 124a of the charge storage portion 124 is disposed between the gate electrode 123a of the second transfer transistor 123 and the second photodiode 122, the potential of the semiconductor substrate 140 increases in the descending order of the second FD portion. 129, accumulated below the gate electrode 123a of the second transfer transistor, below the electrode portion 124a of the charge storage portion 124, and below the electrode portion 124a of the second photodiode 122 and the charge storage portion 124 as the second photodiode 122. The signal charge is transferred to the second FD unit 129. At this time, the potential of the semiconductor substrate 140 below the electrode portion 124a of the charge storage portion 124 needs to be controlled between the lower portion of the gate electrode 123a of the second transfer transistor 123 and the second photodiode 122. Control is difficult compared to setting the potential of the semiconductor substrate 140 below the electrode portion 124a of the charge storage portion 124 to GND. Therefore, in the low-sensitivity pixel 111, the gate electrode 123a of the second transfer transistor 123, the second photodiode 122, and the electrode portion 124a of the charge storage unit 124 are arranged in this order in order to control signal charge transfer. It is valid.

FIG. 5 is a diagram illustrating the relationship between the object illuminance and the signal charge amount of the high-sensitivity pixel 110 and the low-sensitivity pixel 111 in the solid-state imaging device 100 according to the embodiment. The horizontal axis represents subject illuminance, and the vertical axis represents signal charge amount. The diagram shows (A) a graph showing the signal charge amount of the high-sensitivity pixel 110 and (B) the signal charge amount of the low-sensitivity pixel 111 when there is no charge storage unit 124 or when the charge storage unit 124 is invalidated. And (C) a graph showing the signal charge amount of the low sensitivity pixel 111. The slope of the graph means sensitivity, and the sensitivity of the high-sensitivity pixel 110 having the first photodiode 120 having a larger light receiving area is higher, so the slope of the graph is steep.

When the subject illuminance L1 is reached, the saturation charge amount of the high-sensitivity pixel 110 is reached as shown in (A), and the signal charge amount Qs1 is constant regardless of the subject illuminance. However, since the high sensitivity pixel 110 performs the electronic SHT operation, the exposure time can be arbitrarily changed. Accordingly, it is possible to capture a higher subject illuminance by shortening the exposure time and making the inclination of the graph gentle (relatively lowering the sensitivity).

When the subject illuminance L2 is reached, the low-sensitivity pixel 111 reaches the saturation charge amount and becomes the signal charge amount Qs2 as indicated by the dotted line in FIG. The low-sensitivity pixel 111 needs to be constantly exposed in order to suppress the LED flicker phenomenon. Here, the low-sensitivity pixel 111 (without the charge storage unit 124) can obtain a signal charge corresponding to the subject illuminance only up to the subject illuminance L2.

When the object illuminance L3 is reached, the low-sensitivity pixel 111 reaches the saturation charge amount and becomes the signal charge amount Qs3 as shown in (C). Compared with (B), (C) has a wider range of subject illuminance that can be imaged, from 0 to L3, and a signal charge amount corresponding to the subject illuminance can be obtained even when the subject illuminance is relatively high.

In addition, the charge accumulation amount that can be accumulated in the charge accumulation unit 124 of the low-sensitivity pixel 111 can be increased by increasing the voltage applied to the electrode unit 124 a of the charge accumulation unit 124. This is because the charge storage amount Qsat, the MOS capacitance value is Cg, and the voltage Vg applied to the gate electrode can be expressed as Qsat = Cg × Vg. Usually, the photoelectrically converted signal charge is accumulated in the capacitor Cp of the second photodiode 122 itself. For this reason, since the area of the second photodiode 122 is smaller than that of the first photodiode 120, the charge accumulation amount of the second photoelectric conversion unit 122 itself is reduced. However, the low-sensitivity pixel 111 has a charge storage portion 124 in addition to the second photodiode 122. Typically, the charge storage unit 124 can be configured as a MOS capacitor by a gate electrode (that is, the electrode unit 124a), a gate insulating film, and a semiconductor substrate. The capacitance value Cg of the charge storage unit 124 can be made larger than the capacitance Cp of the first photodiode 120 of the high sensitivity pixel 110. In addition, since the voltage Vg applied to the electrode portion 124a can be arbitrarily controlled, it is easy to increase the charge accumulation amount of the low sensitivity pixel 111 as compared to the high sensitivity pixel 110. Thereby, the low-sensitivity pixel 111 can obtain an image in which the flicker phenomenon of the LED light source is suppressed by ensuring a wide dynamic range and always performing an exposure operation.

FIG. 6 is a diagram illustrating a second example of the pixel layout configuration in the solid-state imaging device 100 according to the embodiment. In addition, the description of the part of the same number as FIG. 3 mentioned above is abbreviate | omitted, and only a difference is described. The difference from FIG. 3 is the shape of the electrode part 124a of the charge storage part 124. The electrode portion 124a of the charge storage portion 124 is formed along the boundary between the second photodiode 122 and the element isolation region 130, and is concave (that is, U-shaped) toward the gate electrode 123a side of the second transfer transistor. Is formed. In other words, the electrode portion 124a includes first, second, and third electrode portions 124a1 to 124a3 that form a U-shape. Here, the first electrode portion 124a1 does not cover the second photoelectric conversion unit 122 in plan view. The second electrode portion 124a2 covers a part of the outer periphery of the second photoelectric conversion unit 122 in plan view. The third electrode portion 124a3 covers the other part of the outer periphery of the second photoelectric conversion unit 122 in plan view. As a result, the area of the electrode portion 124a of the charge storage portion 124 can be increased without affecting the sensitivity of the second photodiode 122, and the charge storage amount can be increased.

FIG. 7 is a diagram illustrating a third example of the pixel layout configuration in the solid-state imaging device 100 according to the embodiment. In addition, the description of the part of the same number as FIG. 3 mentioned above is abbreviate | omitted, and only a difference is described. The difference from FIG. 3 is the shape of the electrode part 124a of the charge storage part 124. The electrode part 124 a of the charge storage part 124 is formed so as to cover the upper part of the second photodiode 122. Thereby, the area of the electrode part 124a of the charge storage part 124 can be increased, and the charge storage amount can be increased. However, as described above, the short wavelength blue light is absorbed by the electrode portion 124a of the charge storage portion 124, so that the sensitivity reduction with respect to the blue light becomes a problem. Therefore, this configuration is applied to the pixel cell 101 in which a green filter that transmits green light or a red filter that transmits red light is arranged, and the second pixel cell 101 in which a blue filter that transmits blue light is arranged. It is preferable to suppress a decrease in sensitivity to blue light with the shape shown in FIG. 3 or FIG. 6 that is not covered with the electrode part 124a of the charge storage part 124 on the photodiode 122.

FIG. 8 is a diagram illustrating an example of a schematic cross section of the solid-state imaging device 100 according to the embodiment. This figure shows a cross section taken along line VIII-VIII shown in FIG. 3 and FIG. An insulating film 141 and an element isolation region 130 that isolates elements of the amplification transistor 127 and the charge storage unit 124 are provided on the semiconductor substrate 140. On the insulating film 141, the gate electrode 126a of the reset transistor, the gate electrode 123a of the second transfer transistor 123 of the low-sensitivity pixel 111, the electrode portion 124a of the charge storage unit 124, the gate electrode 127a of the amplification transistor 127, An insulating film 144. In addition, the second photodiode 122 of the low sensitivity pixel 111 is provided in the semiconductor substrate 140. In addition, a copper wiring 143 is connected to the electrode part 124 a of the charge storage part 124 through a contact 142. Copper wiring 143 transmits control pulse φCG as control line CG.

Here, in order to increase the capacitance value Cg of the charge storage unit 124, the charge storage unit 124 has a thickness Tox 1 of the insulating film 141 (that is, the gate insulating film) under the gate electrode 123 a of the second transfer transistor 123. The insulating film 141 (for example, a gate insulating film when the charge storage portion 124 is a MOS capacitor) under the electrode portion 124a may be formed to have a small thickness Tox2. As a result, the distance between the electrode portion 124a and the semiconductor substrate 140 becomes smaller, so that the capacitance value Cg of the charge storage portion 124 can be increased without increasing the area of the electrode portion 124a of the charge storage portion 124, and charge storage. It is possible to increase the amount.

Further, when the contact 142 is formed in the electrode portion 124a of the charge storage portion 124, a process of opening a hole in the insulating film 144 by etching in the insulating film 144 and filling the material of the contact 142, for example, tungsten W, is necessary. At this time, a contamination source such as a metal diffuses from the contact 142 forming portion to the electrode portion 124 a of the charge storage portion 124, and the contamination source also propagates to the insulating film 141 and the semiconductor substrate 140 below the electrode portion 124 a of the charge storage portion 124. . As a result, a defect may occur in the semiconductor substrate 140 that accumulates charges under the electrode portion 124 a of the charge accumulation portion 124. Defects in the semiconductor substrate 140 cause noise that causes image quality degradation such as dark current and white scratches. In order to avoid this, the contact 142 is preferably formed on the gate electrode on the element isolation region 130. The reason for this will be described below. Since the charge accumulation unit 124 accumulates charges in the semiconductor substrate 140 closer to the electrode unit 124a of the charge accumulation unit 124, the charges accumulate on the semiconductor substrate 140 below the Tox 2 where the insulating film 141 is thin. On the other hand, when the lower part of the electrode part 124a of the charge storage part 124 is the element isolation region 130, the semiconductor substrate 140 below the element isolation region 130 is much thicker than the thickness Tox2 of the gate insulating film, so that charge is hardly stored. . For this reason, by forming the contact 142 in the electrode portion 124a of the charge storage portion 124 on the element isolation region 130, noise that causes image quality deterioration such as dark current and white scratches due to defects can be suppressed.

Note that the element isolation region 130 may be formed deeper than illustrated. If the semiconductor substrate 140 is made of silicon, for example, the refractive index of silicon at a wavelength of 400 to 1000 nm is 3.5 to 6.0. On the other hand, if the element isolation region 130 is formed of, for example, silicon oxide, the refractive index is 1.4 to 1.5, and light incident on the first photodiode 120 is reflected by the element isolation region 130, so Can be prevented from entering the pixel portion.

FIG. 9 is a diagram illustrating another example of a schematic cross section of the solid-state imaging device 100 according to the embodiment. This figure shows a cross section taken along the line IX-IX shown in FIG. It should be noted that the description of the same numbered parts as in FIG. 8 described above is omitted, and only the difference is described. The difference from FIG. 8 is that the thickness of the insulating film 141 below the electrode portion 124a of the charge storage portion 124 is the same as that of Tox1, and the shape of the electrode portion 124a of the charge storage portion 124. The electrode part 124a of the charge storage part 124 is formed so as to cover the second photodiode 122, and the thickness Tgate1 of the electrode part 124a of the charge storage part 124 on the second photodiode 122 is a contact. It is characterized by being thinner than the thickness Tgate2 of the electrode part 124a of the charge storage part 124 to which 142 is connected. This is because by reducing the thickness Tgate1 of the electrode portion 124a of the charge storage portion 124 on the second photodiode 122, absorption of blue light by the electrode portion 124a of the charge storage portion 124 can be suppressed. Further, the thickness Tgate2 of the electrode portion 124a of the charge storage portion 124 to which the contact 142 is connected is set to be the same as that of the gate of another transistor, for example, the gate electrode 123a of the second transfer transistor 123. Compared with Tgate1, the thickness of the portion 124a can suppress propagation of a contamination source such as metal to the semiconductor substrate 140 when the contact 142 is formed.

FIG. 10 is a diagram illustrating a first example of a schematic cross section of (a) the high sensitivity pixel 110 and (b) the low sensitivity pixel 111 in the solid-state imaging device 100 according to the embodiment. FIG. 2A shows a schematic cross section of the high-sensitivity pixel 110. The high-sensitivity pixel 110 is formed on the semiconductor substrate 140, and includes a first photodiode 120, an insulating film 141, and a first transfer transistor. 121, a gate electrode 121a, an insulating film 144, a copper wiring 143, a liner film 145, a copper wiring 146, a liner film 147, a high refractive insulating film 148, a color filter 149, and a first planarizing film. 1 transmission filter 150 and microlens 151.

As described above, the first photodiode 120 that accumulates electric charge for each pixel is configured in the imaging region serving as the light receiving surface in the semiconductor substrate 140, and further, the semiconductor is adjacent to the first photodiode 120. A gate electrode 121a of the first transfer transistor 121 is formed on the substrate 140 as an example of a gate.

In the semiconductor substrate 140, a signal reading unit that reads a signal charge generated or accumulated in the first photodiode 120 or a voltage corresponding to the signal charge is formed in the first FD unit 128. The signal charge is transferred by applying a voltage to the gate electrode 121a of the transfer transistor 121.

In addition, the first photodiode 120 is covered, and an insulating film 144 made of, for example, silicon oxide, for example, silicon carbide (refractive index 1.7 to 1.9), or silicon nitride (refractive) is formed on the semiconductor substrate 140. A liner film 145 having a ratio of 1.9 to 2.1) and a liner film 147 are laminated to form an insulating film.

Also, the

copper wirings

143 and 146 are copper wirings formed in different metal wiring layers. However, for example, a barrier metal layer made of tantalum / tantalum nitride formed by a damascene process may be formed on the outer periphery of the copper wiring.

The

liner films

145 and 147 are etch stop films at the time of forming vias and are films for preventing diffusion of copper constituting the metal wiring layer.

As described above, the wiring layer is embedded in the laminated insulating film. Each of the copper wiring 143 and the copper wiring 146 may have a wiring structure formed integrally with the via portion in the opening from the bottom surface of the wiring groove to the lower layer wiring by, for example, a dual damascene process.

In the upper part of the first photodiode 120, recesses are formed with respect to the insulating film 144 and the

liner films

145 and 147 formed by stacking as described above. A high-refractive insulating film 148 having a refractive index higher than that of silicon oxide (refractive index: 1.4 to 1.5) is formed on the side wall and bottom surface of the recess. The high refractive insulating film 148 is formed of a silicon nitride film (refractive index 1.9 to 2.0) or the like. In the cross section, the high refractive insulating film 148 is narrow on the semiconductor substrate 140 side and wide on the microlens 151 side. That is, in the cross section shown in FIG. 10A, the width of the high-refractive insulating film 148 decreases as it approaches the semiconductor substrate 140 side. At this time, if the angle between the bottom surface and the side wall surface of the high refractive insulating film 148 is α, the angle α is greater than 90 degrees.

As described above, by using the high refractive insulating film 148 having a refractive index higher than that of the insulating film 144, the insulating film 144 serves as a cladding layer and the high refractive insulating film 148 serves as a core layer. Thus, it has a function as an optical waveguide leading to one photodiode 120. A portion of the high-refractive insulating film 148 formed in a recess formed in the insulating film 144 above the first photoelectric conversion unit 120 is referred to as a first core layer 1480. In other words, a portion of the insulating film 144 adjacent to the sidewall surface of the high refractive insulating film 148 (first core layer 1480) is used as a cladding layer, and the high refractive insulating film 148 (first core layer 1480) is An optical waveguide that guides light by reflection of incident light on the cladding layer is formed.

The color filter 149 selects light incident on the first photodiode 120 according to wavelength (for example, RGB color). The color filter 149 is formed, for example, by mixing a pigment for each color into an organic material (for example, an acrylic resin). In this case, the refractive index of the color filter 149 is 1.5 to 1.7. The color filter 149 is formed in an island shape (in a state of being formed individually corresponding to each pixel portion). The microlens 151 focuses light on the first photodiode 120 in the pixel portion corresponding to light incident from above. The microlens 151 is a convex lens that protrudes away from the semiconductor substrate 140.

10B is a schematic cross-sectional view of the low-sensitivity pixel 111. FIG. In addition, description is abbreviate | omitted about the location of the same number as Fig.10 (a) mentioned above in the figure, and only a difference is described. The low-sensitivity pixel 111 is reduced in size in the horizontal direction, and the second photodiode 122 of the low-sensitivity pixel 111 and a charge accumulation unit that accumulates signal charges from the second photodiode 122 (for example, a MOS capacitor) ) 124, the electrode portion 124 a of the charge storage portion 124, and the gate electrode 123 a of the second transfer transistor 123 that transfers to the second FD portion 129. A portion of the high-refractive insulating film 148 formed in a recess formed in the insulating film 144 above the second photoelectric conversion unit 122 is referred to as a second core layer 1481. The second core layer 1481 forms an optical waveguide that guides light by reflection of incident light on the side wall surface adjacent to the insulating film 144.

Here, when the width of the bottom of the second core layer 1481 is D1, and the distance between the electrode portion 124a of the charge storage portion 124 and the gate electrode 123a of the second transfer transistor 123 is D2, the relationship of D1 <D2 is established. is there. The second core layer 1481 functions as an optical waveguide that guides the light that has passed through the color filter 149 to the second photodiode 122, and thus the light is collected with a width of D1. Therefore, it is possible to suppress the occurrence of vignetting caused by the light condensed to the width D1 by the optical waveguide hitting the gate electrode 123a of the second transfer transistor 123 and the electrode portion 124a of the charge storage portion 124.

Further, when the angle between the bottom surface and the side wall surface of the second core layer 1481 is β, the angle β is larger than 90 degrees, and the angle β is larger than the angle α in the first core layer 1480. It has become. Thereby, since light is condensed more, it is possible to suppress color mixing due to leakage of light into the adjacent pixel cell 101.

FIG. 11 is a diagram illustrating a relationship between the optical waveguide width and the light collection efficiency in the solid-state imaging device 100 according to the embodiment. This relationship is a result calculated by optical simulation. As a premise of the simulation, the optical waveguide is formed of a silicon nitride film with a high refractive insulating film 148, and is a red component which is a component on the long wavelength side, and has a wavelength of 600 to 650 nm. The time when the maximum wavelength λ = 650 nm is irradiated is shown. The light collection efficiency is defined as the ratio of the intensity of light transmitted through the optical waveguide to the intensity of light irradiated onto the optical waveguide. In the graph of the figure, it is shown that the light collection efficiency sharply decreases with the optical waveguide width being about 340 nm as a boundary. This is because if the width of the optical waveguide that guides light is equal to or smaller than the wavelength, the corresponding light cannot pass and the sensitivity is lowered. Specifically, the wavelength of light changes depending on the refractive index of the material that passes through, and the light wavelength when passing through the air (refractive index is 1.0) is λ1, and passes through the material of refractive index n. The wavelength λ2 of the light at this time is expressed as λ2 = λ1 / n. For this reason, the minimum width for passing the wavelength 600 to 650 nm of red light, which is a component on the long wavelength side, through the high refractive insulating film 148 is that the high refractive insulating film 148 is a silicon nitride film (refractive index 1.9 to 2.0). For example, the wavelength of red light is 300 to 340 nm, and the width of the optical waveguide needs to be at least 340 nm.

FIG. 12 is a diagram illustrating a second example of a schematic cross section of (a) the high sensitivity pixel 110 and (b) the low sensitivity pixel 111 in the solid-state imaging device 100 according to the embodiment. FIG. 6A shows a schematic cross-sectional view of the high-sensitivity pixel 110, which is the same as FIG. 10A described above, and is shown as a comparison target in FIG. FIG. 5B shows a schematic cross-sectional view of the low-sensitivity pixel 111, the description of the portions having the same numbers as those in FIG. The difference from FIG. 10B is that the bottom surface of the high refractive insulating film 148 is shifted away from the semiconductor substrate 140 more than the bottom surface of the high refractive insulating film 148 of the high sensitivity pixel 110 and is closest to the semiconductor substrate 140. It is a point located above the copper wiring 143 and the liner film 145. This is because the light condensing efficiency can be changed by changing the position of the bottom surface of the high refractive insulating film 148. For example, by shifting the position of the bottom side of the high refractive insulating film 148 to the microlens 151 side, the light condensing efficiency is lowered, and the amount of light irradiated to the second photodiode 122 is reduced. Thereby, the sensitivity of the low-sensitivity pixel 111 is lowered, the slope of the graph in FIG. 5 can be made gentle, and the range of the subject illuminance L3 that can be imaged can be adjusted.

In addition, when forming recesses in the insulating film 144 and

liner films

145 and 147 formed by stacking, the insulating film 144 and liner film 147 are removed by etching. At this time, by using the liner film 145 of the low sensitivity pixel 111 as an etch stop film, variation in the distance D3 between the bottom surface of the high refractive insulating film 148 of the low sensitivity pixel 111 and the semiconductor substrate 140 due to the variation in etching is suppressed. Can do. Thereby, the sensitivity variation of the low sensitivity pixel 111 can be reduced.

FIG. 13 is a diagram illustrating a third example of a schematic cross section of (a) the high sensitivity pixel 110 and (b) the low sensitivity pixel 111 in the solid-state imaging device 100 according to the embodiment. (A) of the figure shows a schematic cross-sectional view of the high-sensitivity pixel 110, and description of the portions having the same numbers as those in FIG. 10 (a) is omitted, and only the differences are described. 10A is different from FIG. 10A in that there is a recess formed in an interlayer insulating film (second interlayer insulating film) above the insulating film 144 (first interlayer insulating film). A partition wall 152 is provided by forming the filter 149 and the first transmission filter 150. As a result, the color filter 149 is formed so that the semiconductor substrate 140 side is narrow and the microlens 151 side is wide in the cross section. That is, the bottom side on the semiconductor substrate 140 side has a trapezoidal shape with a smaller width than the upper side on the microlens 151 side. The partition wall 152 prevents light incident from the microlens 151 or the color filter 149 from entering the adjacent pixel portion. The partition wall 152 has a lattice shape (mesh shape) in which a portion corresponding to the color filter 149 is opened in plan view. In addition, in the cross section of Fig.13 (a), each partition 152 seems to be independent. Here, the sectional shape of the partition wall 152 is trapezoidal as a whole. The trapezoidal shape here is a shape in which the bottom side on the semiconductor substrate 140 side is longer than the upper side on the microlens 151 side. That is, the width becomes narrower as the distance from the semiconductor substrate 140 increases. The partition wall 152 is made of a material having a lower refractive index than the material constituting the color filter 149, for example, a silicon oxide film (TEOS (TetraTeEthyl Ortho Silicate) film, refractive index 1.4 to 1.5). For this reason, the light traveling in the oblique direction in the color filter 149 is reflected when it reaches the surface of the partition wall 152. At this time, since the partition wall 152 has a shape that becomes narrower as the distance from the semiconductor substrate 140 increases, the reflected light travels toward the first photodiode 120 side.

FIG. 13B shows a schematic cross section of the low-sensitivity pixel 111. It should be noted that the description of the portions having the same numbers as in FIG. 10B described above in FIG. 10B is different from FIG. 10B in that a second transmission filter 153 is provided above the color filter 149, and a partition wall is formed on the layers of the color filter 149, the second transmission filter 153, and the first transmission filter 150. 152 is provided. Here, the second transmission filter 153 is a gray filter that transmits light with a lower transmittance than that of the first transmission filter 150, and is a material whose light transmittance decreases as the thickness of the film increases. . Further, as a material constituting the second transmission filter 153, for example, a mixture of organic materials is mixed with organic pigments of various colors, fine particles of carbon or metal oxide, and the like. In this case, the refractive index of the second transmission filter 153 is 1.5 to 1.7, and in the wavelength region of 400 nm to 1000 nm, the transmittance is in the range of 5 to 20% compared to the transparent filter. . The partition wall 152 is made of a material having a lower refractive index than the material constituting the second transmission filter 153, for example, a silicon oxide film (TEOS (TetraTeEthyl Ortho Silicate), refractive index 1.4 to 1.5). . For this reason, the light traveling in the oblique direction in the second transmission filter 153 is reflected when it reaches the surface of the partition wall 152.

Note that the upper part of the recess formed in the interlayer insulating film, that is, the upper part of the partition wall 152 is arranged at a position higher than the upper part of the color filter 149, and the upper part of the second transmission filter 153 is higher than the upper part of the partition wall 152. You may arrange in. This is because when the partition wall 152 is formed, the aspect ratio of the concave portion formed in the interlayer insulating film (ratio of the bottom side to the height of the concave portion) is limited, while the second transmission filter 153 is used to reduce the transmittance. This is because it may be thicker.

By arranging the second transmission filter 153 in the low sensitivity pixel 111, the sensitivity of the low sensitivity pixel 111 can be lowered. Thereby, the subject illuminance L3 that can be captured by the low-sensitivity pixel 111 can be increased. This is an effective means for reducing the sensitivity of the low-sensitivity pixel 111 because the low-sensitivity pixel 111 always performs an exposure operation, and the amount of signal charge accumulated in the second photodiode 122 cannot be adjusted by the electron SHT. is there.

As described above, the solid-state imaging device 100 according to the present embodiment has a plurality of pixel cells 101 arranged on a matrix. Each of the plurality of pixel cells 101 has a first photoelectric conversion unit 120, a first FD unit 128, and a signal charge photoelectrically converted by the first photoelectric conversion unit 120 formed on the semiconductor substrate 140. The first transfer transistor 121 that transfers to one FD unit 128, the second photoelectric conversion unit 122 that has a light receiving area smaller than that of the first photoelectric conversion unit 120, and the second photoelectric conversion unit 122 performs photoelectric conversion. A charge accumulation unit 124 that accumulates signal charges, a second FD unit 129, and a second transfer transistor 123 that transfers signal charges accumulated in the charge accumulation unit 124 to the second FD unit 129 are provided. The charge storage unit 124 includes an insulating film 141 on the semiconductor substrate 140 and an electrode unit 124 a formed on the insulating film 141.

According to this, an image in which the flicker phenomenon is suppressed can be obtained. More specifically, the charge storage unit 124 is added to the second photoelectric conversion unit 122 having a light receiving area smaller than that of the first photoelectric conversion unit 120. As a result, the second photoelectric conversion unit 122 can substantially increase the saturation charge amount while having lower sensitivity. Therefore, the second photoelectric conversion unit 122 can configure a low sensitivity pixel that can realize a wide dynamic range. Here, an image in which the flicker phenomenon of the LED light source is suppressed can be obtained by always exposing the low-sensitivity pixels.

Further, since the light-receiving area of the first photoelectric conversion unit 120 is larger than that of the second photoelectric conversion unit 122, the high-sensitivity pixel 110 that secures the saturation charge amount can be configured, and thus an image that secures the dynamic range. Can be obtained. In other words, a dynamic range in which the flicker phenomenon is suppressed is secured by combining the image in which the LED photoelectric flicker phenomenon is suppressed in the low sensitivity pixel 111 including the first photoelectric conversion unit 120 and the captured image of the high sensitivity pixel 110. An image can be obtained.

Here, the electrode part 124a may be configured not to cover the second photoelectric conversion part 122 in a plan view.

According to this, attenuation of light incident on the second photoelectric conversion unit 122, particularly blue light, can be suppressed.

Here, the electrode part 124a may be configured to cover at least a part of the second photoelectric conversion part 122 in plan view.

According to this, the area of the electrode part 124a of the charge storage part 124 can be increased, and the charge storage amount can be easily increased. However, since the short wavelength blue light is absorbed by the electrode portion 124a, the above configuration is applied to the pixel cell 101 in which a filter that transmits green light is disposed or the pixel cell 101 in which a filter that transmits red light is disposed. However, the electrode portion 124 a may not be covered with the second photodiode 122 without being applied to the pixel cell 101 in which a filter that transmits blue light is arranged.

Here, the electrode portion 124a includes first, second, and third electrode portions 124a1 to 124a3 that form a U-shape, and the first electrode portion 124a1 has the second photoelectric conversion portion 122 in plan view. The second electrode portion 124a2 covers a part of the outer periphery of the second photoelectric conversion unit 122 in plan view, and the third electrode portion 124a3 is the outer periphery of the second photoelectric conversion unit 122 in plan view. You may cover other part of.

According to this, it is possible to increase the area of the electrode part 124a of the charge storage part 124 without affecting the sensitivity of the second photoelectric conversion part 122, and to increase the charge storage amount of the charge storage part 124. it can.

Here, the second photoelectric conversion unit 122 may be disposed between the charge storage unit 124 and the second transfer transistor 123 in a plan view.

According to this, the shape of the second photodiode 122 and the gate electrode 123a of the second transfer transistor is maintained, and the efficiency (sensitivity) of photoelectric conversion and the transfer of signal charges (for example, afterimage characteristics) are affected. This can be suppressed.

Here, the electrode part 124a may have a convex shape in a direction opposite to the direction in which the second transfer transistor 123 is arranged in a plan view.

According to this, the shape of the second photodiode 122 and the gate electrode 123a of the second transfer transistor is maintained, and the efficiency (sensitivity) of photoelectric conversion and the transfer of signal charges (for example, afterimage characteristics) are affected. Therefore, the charge accumulation amount (saturation charge amount) of the charge accumulation unit 124 can be easily increased.

Here, in a plan view, the first photoelectric conversion unit 120 and the second photoelectric conversion unit 122 are adjacent to each other in an oblique direction with respect to the row direction, and the first photoelectric conversion unit 120 and the first photoelectric conversion unit 120 in the same pixel cell. A color filter 149 having the same spectral characteristics is stacked on each of the two photoelectric conversion units 122, and the transfer direction in which the first transfer transistor 121 transfers signal charges in plan view is the second transfer transistor 123. It may be the same as the transfer direction in which signal charges are transferred.

According to this, by making the transfer directions the same, it is possible to suppress a difference in characteristics due to transfer variations between the first transfer transistor 121 and the second transfer transistor 123. The characteristic difference due to transfer variation includes, for example, an afterimage characteristic in which signal charges remain in the first photodiode 120 and / or the second photodiode 122 during transfer.

Here, the pixel cell 101 includes a switch transistor 125 that electrically connects the first FD 128 and the second FD 129, and an amplification transistor 127 having a gate electrode that is electrically connected to the first FD 128. It may be.

According to this, one amplification transistor 127 can be shared by the first photoelectric conversion unit 120 and the second photodiode 122.

Here, the pixel cell 101 is formed in a recess formed in the insulating film 144 above the insulating film 144 formed on the semiconductor substrate 140 and the first photoelectric conversion unit 120, and is higher than the insulating film 144. A first core layer 1480 having a refractive index and a second core layer having a refractive index higher than that of the insulating film 144 and formed in a recess formed in the insulating film 144 above the second photoelectric conversion unit 122. 1481 may be provided.

According to this, the first core layer 1480 and the second core layer 1481 can be waveguides. That is, light incident on the first core layer 1480 can be reflected on the boundary surface between the first core layer 1480 and the insulating film 144 and guided to the first photoelectric conversion unit 120. Light incident on the second core layer 1481 can be reflected by the boundary surface between the second core layer 1481 and the insulating film 144 and guided to the second photoelectric conversion unit 122. As a result, the light collection efficiency of the first photoelectric conversion unit 120 and the second photoelectric conversion unit 122 can be increased, and color mixing due to leakage of light to adjacent pixel cells can be reduced.

Here, the angle formed between the bottom surface of the first core layer 1480 and the side wall surface is a first angle α larger than 90 degrees, and the angle formed between the bottom surface of the second core layer 1481 and the side wall surface is 90 °. The second angle β is larger than the second angle β, and the second angle β may be larger than the first angle α.

Thereby, since the light incident on the second core layer 1481 is collected more, color mixing due to light leakage into the adjacent pixel cell 101 can be further suppressed.

Here, the second transfer transistor 123 includes a gate electrode 123a, and the distance D2 between the electrode portion 124a and the gate electrode 123a of the second transfer transistor 123 is the width D1 of the bottom surface of the second core layer 1481. May be longer.

Thereby, since the second core layer 1481 has a function as an optical waveguide for guiding the light that has passed through the color filter 149 to the second photodiode 122, the light is condensed with a width of D1. Since D2> D1, it is possible to suppress the occurrence of vignetting caused by the light condensed to the width D1 by the optical waveguide hitting the gate electrode 123a of the transfer transistor 123 and the electrode portion 124a of the charge storage unit 124.

Here, the second core layer 1481 may be made of silicon nitride, and the width D1 of the bottom surface of the second core layer 1481 may be 340 nm or more.

According to this, the minimum width for passing the wavelength of red light of 600 to 650 nm through the high refractive insulating film 148 is such that the high refractive insulating film 148 is formed of a silicon nitride film (refractive index 1.9 to 2.0). In this case, the wavelength of red light is 300 to 340 nm, and the width of the optical waveguide may be at least 340 nm.

Here, the distance D3 between the conductor substrate 140 and the bottom surface of the second core layer 1481 is larger than the distance between the semiconductor substrate 140 and the bottom surface of the first core layer 1480, and the bottom surface of the second core layer 1481 is The metal wiring layer may be positioned on the metal wiring layer closest to the semiconductor substrate 140 among the plurality of metal wiring layers.

According to this, by using an insulating layer (for example, liner film 145) immediately above the metal wiring layer on which the copper wiring 143 is formed as an etch stop film, the bottom surface of the second core layer 1481 and the semiconductor due to etching variations Variation in the distance D3 from the substrate 140 can be suppressed. Thereby, the sensitivity variation of the 2nd photoelectric conversion part 122 can be reduced.

Here, the first transfer transistor 121 has a first gate electrode 121 a, the second transfer transistor 123 has a second gate electrode 123 a, and an electrode portion on the second photoelectric conversion unit 122. The film thickness Tgate1 of 124a may be thinner than the film thickness Tgate2 of the first gate electrode and may be thinner than the film thickness Tgate2 of the second gate electrode 123a.

According to this, by reducing the thickness Tgate1 of the electrode part 124a, the absorption of blue light by the electrode part 124a can be suppressed.

Here, the pixel cell 101 includes a first wiring (for example, a copper wiring 143) that transmits a control pulse to the electrode portion 124a, and a contact 142 that connects the first wiring and the electrode portion 124a. Of 124a, the thickness Tgate1 of the portion on the second photoelectric conversion unit 122 may be smaller than the thickness Tgate2 of the portion to which the contact 142 is connected.

According to this, by setting the thickness Tgate2 of the electrode part 124a to which the contact 142 is connected to the same thickness as the gate of another transistor, for example, the gate electrode 123a of the transfer transistor, the thickness of the electrode part 124a. However, it is possible to suppress the propagation of a contamination source such as metal to the semiconductor substrate 140 when the contact 142 is formed, as compared with Tgate1.

Here, the electrode part 124a may have a contact 142 that covers a part of the element isolation region formed in the semiconductor substrate 140 and contacts a part of the electrode part 124a that covers the element isolation region.

According to this, by forming the contact 142 in the electrode part 124a on the element isolation region 130, noise that causes image quality degradation such as dark current and white scratches caused by defects can be suppressed.

Here, the film thickness Tox2 of the insulating film 141 under the electrode portion 124a may be smaller than the film thickness Tox1 of the gate insulating film of the second transfer transistor 123.

According to this, the maximum capacity of the charge storage unit 124 can be increased without increasing the area of the electrode part 124a of the charge storage unit 124, and the charge storage amount can be increased.

Here, the pixel cell 101 transmits the first transmission filter 150 that transmits incident light incident on the first photoelectric conversion unit 120 and the incident light incident on the second photoelectric conversion unit 122. A second transmission filter 153, and the second transmission filter 153 may have a transmittance lower than that of the first transmission filter 150.

According to this, the sensitivity of the low-sensitivity pixel 111 can be reduced by disposing the second transmission filter 153. Thereby, the subject illuminance L3 that can be captured by the low-sensitivity pixel 111 can be increased. This is effective as an adjusting means for lowering the sensitivity of the low-sensitivity pixel 111 because the low-sensitivity pixel 111 always performs an exposure operation and the signal charge amount stored in the second photodiode 122 is not adjusted by the electron SHT.

Here, the pixel cell 101 may include a partition wall 152 surrounding the first transmission filter 150 and the second transmission filter 153 or the color filter 149 in a plan view.

According to this, the light traveling in the oblique direction in the first transmission filter 150 and the second transmission filter 153 or the color filter 149 is reflected when it reaches the surface of the partition wall 152. The reflected light travels toward the first photoelectric conversion unit 120 or the second photoelectric conversion unit 122. Thereby, light collection efficiency can be increased and color mixing can be reduced.

Here, the pixel cell 101 may include a partition wall 152 surrounding the first transmission filter 150, the second transmission filter 153, and the color filter 149 in a plan view.

According to this, the light traveling in the oblique direction in the first transmission filter 150, the second transmission filter 153, and the color filter 149 is reflected when reaching the surface of the partition wall 152. The reflected light travels toward the first photoelectric conversion unit 120 or the second photoelectric conversion unit 122. Thereby, light collection efficiency can be increased and color mixing can be reduced.

As mentioned above, although the solid-state imaging device concerning the present invention was explained based on an embodiment, this indication is not limited to an embodiment. Unless departing from the gist of the present disclosure, various modifications conceived by those skilled in the art have been made in the present embodiment, and other forms constructed by arbitrarily combining some components in the embodiment and the modified examples are also possible. Are included within the scope of this disclosure.

Note that the present disclosure is effective regardless of the pixel structure, and can be used for, for example, a back-illuminated type, a stacked type solid-state imaging device, and the like.

The present disclosure can be used for a solid-state imaging device, and is suitable for, for example, a video camera or a digital camera.

DESCRIPTION OF SYMBOLS 100 Solid-state imaging device 101 Pixel cell 102 Pixel array part 103 Driver circuit 104 Vertical scanning circuit 105 Constant current source circuit 106 Column readout circuit 107 Horizontal scanning circuit 110 High sensitivity pixel 111 Low sensitivity pixel 120 1st photodiode (1st photoelectric device) Conversion part)
121

First transfer transistor

121a, 123a, 125a, 126a, 127a Gate electrode 122 Second photodiode (second photoelectric conversion unit)
123 Second transfer transistor 124 Charge storage unit 124a Electrode unit 125 Switch transistor 126 Reset transistor 127 Amplification transistor 128 First FD unit 129 Second FD unit 130 Element isolation region 140 Semiconductor substrate 141 Insulating film 142

Contacts

143 and 146 Copper Wiring 144

Insulating films

145, 147 Liner film 148 High refractive insulating film 149 Color filter 150 First transmission filter 151 Micro lens 152 Partition 153 Second transmission filter 1480 First core layer 1481 Second core layer VL Vertical signal line VDDC Pixel power supply voltage Qs1, Qs2, Qs3 Signal charge amounts L1, L2, L3 Subject illuminance Tox1, Tox2 Gate oxide film thickness Tgate1, Tgate2 Gate film thickness

Claims

A solid-state imaging device having a plurality of pixel cells arranged on a matrix,
Each of the plurality of pixel cells includes
A first photoelectric conversion unit formed on a semiconductor substrate;
A first floating diffusion section;
A first transfer transistor that transfers the signal charge photoelectrically converted by the first photoelectric conversion unit to the first floating diffusion unit;
A second photoelectric conversion unit having a light receiving area smaller than that of the first photoelectric conversion unit;
A charge storage unit that stores the signal charges photoelectrically converted by the second photoelectric conversion unit;
A second floating diffusion section;
A second transfer transistor for transferring the signal charge stored in the charge storage section to the second floating diffusion section,
The solid-state imaging device, wherein the charge storage unit includes an insulating film on the semiconductor substrate and an electrode unit formed on the insulating film.
The solid-state imaging device according to claim 1, wherein the electrode unit does not cover the second photoelectric conversion unit in plan view.
The solid-state imaging device according to claim 1, wherein the electrode unit covers at least a part of the second photoelectric conversion unit in a plan view.
The electrode portion has first, second and third electrode portions constituting a U-shape,
The first electrode portion does not cover the second photoelectric conversion unit in plan view,
The second electrode portion covers a part of the outer periphery of the second photoelectric conversion unit in plan view,
The solid-state imaging device according to claim 1, wherein the third electrode portion covers another part of the outer periphery of the second photoelectric conversion unit in plan view.
The solid-state imaging device according to any one of claims 1 to 4, wherein the second photoelectric conversion unit is arranged between the charge storage unit and the second transfer transistor in a plan view.
The solid-state imaging device according to claim 5, wherein the electrode portion has a convex shape in a direction opposite to a direction in which the second transfer transistor is arranged in a plan view.
In plan view, the first photoelectric conversion unit and the second photoelectric conversion unit are adjacent to each other in an oblique direction with respect to a row direction,
A color filter having the same spectral characteristics is stacked on each of the first photoelectric conversion unit and the second photoelectric conversion unit in the same pixel cell,
The transfer direction in which the first transfer transistor transfers a signal charge in a plan view is the same as the transfer direction in which the second transfer transistor transfers a signal charge. Solid-state imaging device.
Each of the plurality of pixel cells includes
A switch transistor for electrically connecting the first floating diffusion portion and the second floating diffusion portion;
The solid-state imaging device according to any one of claims 1 to 7, further comprising: an amplification transistor having a gate electrode electrically connected to the first floating diffusion portion.
An insulating film formed on the semiconductor substrate;
Above the first photoelectric conversion part, a first core layer formed in a recess formed in the insulating film and having a higher refractive index than the insulating film;
9. The method according to claim 1, further comprising: a second core layer formed in a recess formed in the insulating film above the second photoelectric conversion portion and having a higher refractive index than the insulating film. The solid-state imaging device according to item.
The angle formed by the bottom surface and the side wall surface of the first core layer is a first angle greater than 90 degrees,
The angle formed by the bottom surface and the side wall surface of the second core layer is a second angle larger than 90 degrees,
The solid-state imaging device according to claim 9, wherein the second angle is larger than the first angle.
The second transfer transistor has a gate electrode;
The solid-state imaging device according to claim 9 or 10, wherein a distance between the electrode portion and the gate electrode of the second transfer transistor is longer than a width of a bottom surface of the second core layer.
The solid-state imaging device according to any one of claims 9 to 11, wherein the second core layer is made of silicon nitride, and a width of a bottom surface of the second core layer is 340 nm or more.
The distance between the semiconductor substrate and the bottom surface of the second core layer is greater than the distance between the semiconductor substrate and the bottom surface of the first core layer,
The solid-state imaging device according to any one of claims 9 to 12, wherein the bottom surface of the second core layer is located on a metal wiring layer closest to the semiconductor substrate among a plurality of metal wiring layers.
The first transfer transistor has a first gate electrode;
The second transfer transistor has a second gate electrode;
The film thickness of the electrode part on the second photoelectric conversion part is thinner than the film thickness of the first gate electrode and thinner than the film thickness of the second gate electrode. The solid-state imaging device described.
A first wiring for transmitting a control pulse to the electrode portion;
A contact connecting the first wiring and the electrode portion;
The solid-state imaging device according to claim 14, wherein a film thickness of a portion of the electrode unit in the second photoelectric conversion unit is thinner than a film thickness of a portion to which the contact is connected.
The electrode portion covers a part of an element isolation region formed in the semiconductor substrate,
The solid-state imaging device according to any one of claims 1 to 14, further comprising a contact that contacts a portion of the electrode portion that covers the element isolation region.
The solid-state imaging device according to any one of claims 1 to 16, wherein a film thickness of the insulating film under the electrode portion is smaller than a film thickness of a gate insulating film of the second transfer transistor.
A first transmission filter that transmits incident light incident on the first photoelectric conversion unit;
A second transmission filter that transmits incident light incident on the second photoelectric conversion unit;
The solid-state imaging device according to any one of claims 1 to 6, and 8 to 17, wherein the transmittance of the second transmission filter is lower than the transmittance of the first transmission filter.
A color filter having the same spectral characteristics is stacked on each of the first photoelectric conversion unit and the second photoelectric conversion unit in the same pixel cell,
The solid-state imaging device according to claim 18, further comprising a partition wall surrounding the first transmission filter and the second transmission filter or the color filter in a plan view.
A color filter having the same spectral characteristics is stacked on each of the first photoelectric conversion unit and the second photoelectric conversion unit in the same pixel cell,
The solid-state imaging device according to claim 18, further comprising a partition wall that surrounds the first transmission filter, the second transmission filter, and the color filter in a plan view.