WO2018143986A1

WO2018143986A1 - Quantum dot array devices

Info

Publication number: WO2018143986A1
Application number: PCT/US2017/016130
Authority: WO
Inventors: Hubert C. GEORGE; James S. Clarke; Ravi Pillarisetty; Jeanette M. Roberts; Nicole K. THOMAS; Zachary R. YOSCOVITS; Roman CAUDILLO; Payam AMIN
Original assignee: Intel Corporation
Priority date: 2017-02-02
Filing date: 2017-02-02
Publication date: 2018-08-09

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a plurality of pillars, wherein individual pillars include a quantum well layer, at least two of the pillars are spaced apart in a first dimension, at least two of the pillars are spaced apart in a second dimension, and the first and second dimensions are perpendicular; an insulating material between at least two of the pillars spaced apart in the first dimension and at least two of the pillars spaced apart in the second dimension; and a plurality of gates disposed above corresponding individual ones of the pillars.

Description

QUANTUM DOT ARRAY DEVICES

Background

[0001] Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

Brief Description of the Drawings

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0003] FIGS. 1A-D are cross-sectional views of a quantum dot device, in accordance with various embodiments.

[0004] FIGS. 2-4, 5A-C, 6, 7A-B, 8-20, 21A-B, and 22-25 illustrate various example stages in the manufacture of a quantum dot device, in accordance with various embodiments.

[0005] FIGS. 26, 27A-B, 28A-B, 29A-B, 30A-B, 31A-B, 32A-B, 33A-B, 34A-B, 35A-B, 36A-B, 37A-B,

38A-B, 39A-B, and 40A-B illustrate various example patterning techniques that may be used in the manufacture of a quantum dot device, in accordance with various embodiments.

[0006] FIGS. 41A-B, 42A-B, 43A-B, 44A-B, 45A-B, 46A-B, 47A-B, 48A-B, 49A-B, and 50A-B illustrate various example patterning techniques that may be used in the manufacture of a quantum dot device, in accordance with various embodiments.

[0007] FIGS. 51A-B, 52A-B, 53A-B, 54A-B, 55A-B, 56A-B, and 57A-B illustrate various example patterning techniques that may be used in the manufacture of a quantum dot device, in accordance with various embodiments.

[0008] FIGS. 58-70 illustrate various example pitch-quartering patterning techniques that may be used in the manufacture of a quantum dot device, in accordance with various embodiments.

[0009] FIGS. 71-75 are cross-sectional views of various examples of quantum well stacks that may be used in a quantum dot device, in accordance with various embodiments.

[0010] FIGS. 76A-B are cross-sectional views of a quantum dot device including magnet lines, in accordance with various embodiments.

[0011] FIG. 77 is a cross-sectional view of a quantum dot device with multiple interconnect layers, in accordance with various embodiments. [0012] FIG. 78 is a cross-sectional view of a quantum dot device package, in accordance with various embodiments.

[0013] FIGS. 79A-B are top views of a wafer and dies that may include any of the quantum dot devices disclosed herein.

[0014] FIG. 80 is a cross-sectional side view of a device assembly that may include any of the quantum dot devices disclosed herein.

[0015] FIGS. 81 and 82 are flow diagrams of illustrative methods of manufacturing a quantum dot device, in accordance with various embodiments.

[0016] FIG. 83 is a flow diagram of an illustrative method of operating a quantum dot device, in accordance with various embodiments.

[0017] FIG. 84 is a block diagram of an example quantum computing device that may include any of the quantum dot devices disclosed herein, in accordance with various embodiments.

Detailed Description

[0018] Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a plurality of pillars, wherein individual pillars include a quantum well layer, at least two of the pillars are spaced apart in a first dimension, at least two of the pillars are spaced apart in a second dimension, and the first and second dimensions are perpendicular; an insulating material between at least two of the pillars spaced apart in the first dimension and at least two of the pillars spaced apart in the second dimension; and a plurality of gates disposed above corresponding individual ones of the pillars.

[0019] The quantum dot devices disclosed herein may enable the formation of quantum dots to serve as quantum bits ("qubits") in a quantum computing device, as well as the control of these quantum dots to perform quantum logic operations. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein provide strong spatial localization of the quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

[0020] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. [0021] Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0022] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

[0023] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. As used herein, a "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide.

[0024] FIGS. 1A-D are cross-sectional views of a quantum dot device 100, in accordance with various embodiments. In particular, FIG. IB illustrates the quantum dot device 100 taken along the section A-A of FIGS. 1A and ID, FIG. 1C illustrates the quantum dot device 100 taken along the section B-B of FIGS. 1A and ID (while FIG. 1A illustrates the quantum dot device 100 taken along the section C-C of FIGS. IB and 1C), and FIG. ID illustrates the quantum dot device taken along the section D-D of FIGS. IB and 1C. FIGS. 1A and ID may be considered "top" cross-sectional views and FIGS. IB and 1C may be considered "side" cross-sectional views, although as noted above, such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments.

[0025] The quantum dot device 100 may include one or more quantum dot pillars 104 spaced apart by insulating material 128 (e.g., silicon oxide). Individual ones of the quantum dot pillars 104 may have at least one associated gate. In "double-sided" embodiments of the quantum dot devices 100 disclosed herein (e.g., as shown in FIGS. 1A-D), a quantum dot pillar may be bookended by a gate 108-1 and a gate 108-2. In "single-sided" embodiments the quantum dot devices 100 disclosed herein, only a single gate 108 may be disposed on a quantum dot pillar 104. Although a particular number of quantum dot pillars 104 are shown in FIGS. 1A-D, this is simply for ease of illustration, and any number of quantum dot pillars 104 may be included in the quantum dot device 100. The quantum dot pillars 104 may include one or more quantum well layers 152. In the embodiment illustrated in FIGS. 1A-D, the quantum dot pillars 104 are illustrated as including two quantum well layers, 152-1 and 152-2, but in some embodiments (as discussed further herein), a quantum dot pillar 104 may include one quantum well layer 152 or three or more quantum well layers 152. In the embodiment illustrated in FIGS. 1A-D, the quantum well layer 152-1 and the quantum well layer 152-2 are spaced apart by a barrier layer 154. Examples of quantum well stacks 146 (and the quantum dot pillars 104 that may be formed from such quantum well stacks 146) are discussed in detail below with reference to FIGS. 71-75. The quantum dot device 100 may, in some

embodiments, include a support 103 to provide mechanical support for the quantum dot device 100 (e.g., in the form of a carrier or other structure). In some embodiments, the quantum dot device 100 may not include a support 103.

[0026] As noted above, each of the quantum dot pillars 104 may include one or more quantum well layers 152. The quantum well layers 152 included in the quantum dot pillars 104 may be arranged normal to the z-direction, and may provide layers in which a two-dimensional electron gas (2DEG) may form to enable the generation of a quantum dot during operation of the quantum dot device 100, as discussed in further detail below. The quantum well layers 152 themselves may provide a geometric constraint on the z-location of quantum dots in the quantum dot pillars 104, and the limited x- and y-dimensions of the quantum dot pillars 104 may provide a geometric constraint on the x- and y-locations of quantum dots in the quantum dot pillars 104. To further control the x- location and the y-location of quantum dots in the quantum dot pillars 104 (and to control the energy of the quantum dots), voltages may be applied to gates disposed on the quantum dot pillars 104 to adjust the energy profile along the quantum dot pillars 104 in the x-direction and the y- direction and thereby constrain the x-location and y-location of quantum dots within quantum wells (discussed in detail below with reference to the gates 108).

[0027] The quantum dot device 100 may include one or more sets of gates 105. In particular, in some embodiments, a first set of gates 105-1 may be disposed at the "bottom" of the quantum dot pillars 104, and a second set of gates 105-2 may be disposed at the "top" of the quantum dot pillars 104. In the embodiment illustrated in FIGS. 1A-D, the first set of gates 105-1 includes four gates 108- 1 (corresponding to the four quantum dot pillars 104), and the second set of gates 105-2 includes four gates 108-2 (corresponding to the four quantum dot pillars 104). This particular number of gates is simply illustrative, and any suitable number and arrangement of gates may be used. For example, a set of gates 105 may include three or more gates 108, arranged in any desired arrangement (e.g., as vertices of triangles or other polygons, in a rectangular or other array, in an irregular arrangement on the quantum well stack 146, etc.) and corresponding to a similar arrangement of quantum dot formation pillars 104.

[0028] As shown in FIGS. 1A-D, the gate 108-11 may be disposed in an opening 111-1 in an insulating material 110-1, and the gate 108-12 may be disposed in a different opening 111-1 in the insulating material 110-1. The gates 108-21 and 108-22 (of the set of gates 105-2) are arranged above corresponding quantum dot formation pillars 104 analogously to the arrangement of the gates 108-11 and 108-12 (of the set of gates 105-1). References to a "gate 108" herein may refer to any of the gates 108. Reference to the "gates 108-1" herein may refer to any of the gates 108 of the first set of gates 105-1 (and analogously for the "gates 108-2").

[0029] A set of gates 105 may include multiple gates 108 that include at least one pair of gates 108 spaced apart from each other in a first dimension (e.g., spaced apart from each other in the x- dimension), and at least one pair of gates 108 spaced apart from each other in a second dimension perpendicular to the first dimension (e.g., spaced apart from each other in the y-dimension). A two- dimensional regular array of spaced-apart gates 108 is one example of such an arrangement (e.g., as illustrated in FIGS. 1A-D), but many others exist (e.g., an irregular array or other distribution). These pairs may share a gate 108; for example, three gates 108 may satisfy this description if arranged accordingly. In the embodiment illustrated in FIGS. 1A-D, the gates 108 in a set 105 are spaced apart by intervening portions of the insulating material 110; in other embodiments, other materials or structures may be disposed between pairs of gates 108 in a set 105. The insulating material 110 may have any suitable material composition. For example, in some embodiments, the insulating material 110 may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride. The arrangement of quantum dot pillars 104 may follow the arrangement of the gates 108 in a set 105 such that a gate 108 is disposed "on" an associated quantum dot pillar 104.

[0030] In the embodiment illustrated in FIGS. 1A and ID, from a top view, the insulating material 110 around each set of gates 105 may be shaped substantially as a "grid" or "cross-grating," having openings 111 in which the gate metal 112 of the gates 108 are at least partially disposed. Such a grid may have one or more cross-shaped portions (between a set of four adjacent openings 111) and a perimeter portion (extending around the collection of openings 111). As noted elsewhere herein, the insulating material 110 may be patterned in any suitable way to define the location and shape of the gates 108. A number of examples of techniques for patterning the insulating material 110, and thereby establishing the footprints of the gates 108, are discussed below. For example, in some embodiments, the gates 108 may have footprints that are substantially rectangular (e.g., as discussed below with reference to FIGS. 26-40B) or footprints that have two linear opposing sides and two semicircular opposing sides (e.g., as discussed below with reference to FIGS. 41A-50B). In some embodiments, the insulating material 110-1 may be a mirror image of the insulating material 110-2 around the quantum well stack 146; in other embodiments, the insulating material 110-1 may not be a mirror image of the insulating material 110-2. Similarly, the gates 108-1 may be a mirror image of the gates 108-2 around the quantum well stack 146; in other embodiments, the gates 108- 1 may not be a mirror image of the gates 108-2.

[0031] As noted above, the arrangement of quantum dot pillars 104 may follow the arrangement of the gates 108 in a set 105 such that a gate 108 is disposed "on" an associated quantum dot pillar 104 (thus, for example, the quantum dot pillars 104 may be arranged in a rectangular array, and the insulating material 128 may be shaped as a cross-grating and have one or more cross-shaped portions). The techniques discussed below for patterning the insulating material 110 to establish the footprints of the gates 108 may be used to pattern the quantum dot pillars 104, as discussed below.

[0032] Each of the gates 108 may include a gate dielectric 114 (e.g., the gate dielectric 114-1 for the gates 108-1, and the gate dielectric 114-2 for the gates 108-2). Separate portions of the gate dielectric 114 may be provided for each of the gates 108, and in some embodiments, the gate dielectric 114 may extend at least partially up the side walls of the openings 111 in the proximate insulating material 110. In such embodiments, the gate metal 112 may extend between the portions of the associated gate dielectric 114 on the side walls of the openings 111, and thus may have a U- shape in cross section (as illustrated in FIG. IB and discussed below with reference to FIG. 8). In some embodiments, the gate dielectric 114 may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the associated quantum dot pillar 104 and the gate metal 112). The gate dielectric 114 may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric 114 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that may be used in the gate dielectric 114 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric 114 to improve the quality of the gate dielectric 114. The gate dielectric 114-1 may be a same material as the gate dielectric 114-2, or a different material. [0033] Each of the gates 108-1 may include a gate metal 112-1, and a hardmask 118-1 may be disposed above the gate metal 112-1. The hardmask 118-1 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 112-1 may be disposed between the hardmask 118-1 and the gate dielectric 114-1, and the gate dielectric 114-1 may be disposed between the gate metal 112-1 and the associated quantum dot pillar 104. In some embodiments, the gate metal 112- 1 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride. In some embodiments, the hardmask 118-1 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 118-1 may be removed during processing, as discussed below).

[0034] Each of the gates 108-2 may include a gate metal 112-2, and a hardmask 118-2 may be disposed above the gate metal 112-2. The hardmask 118-2 may be formed of any of the materials discussed above with reference to the hardmask 118-1. The gate metal 112-2 may be disposed between the hardmask 118-2 and the gate dielectric 114-2, and the gate dielectric 114-2 may be disposed between the gate metal 112-2 and the associated quantum dot pillar 104. In some embodiments, the gate metal 112-2 may be a different metal from the gate metal 112-1; in other embodiments, the gate metal 112-2 and the gate metal 112-1 may have the same material composition. In some embodiments, the gate metal 112-2 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride. In some embodiments, the hardmask 118-2 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 118-2 may be removed during processing, as discussed below).

[0035] The dimensions of the insulating material 110 and the gates 108 may take any suitable values. For example, in some embodiments, the z-height 166 of the insulating material 110 and the gate metal 112 may be between 40 and 75 nanometers (e.g., approximately 50 nanometers). In some embodiments, the x-distance 168 between adjacent portions of the gate metal 112 in the cross section of FIG. IB (and therefore the x-length of the portion of the insulating material 110 disposed between adjacent gates 108) may be less than 100 nanometers (e.g., between 20 and 100 nanometers, between 20 and 40 nanometers, between 30 and 40 nanometers, between 20 and 30 nanometers, approximately 30 nanometers, or approximately 50 nanometers). In some

embodiments, the x-length 170 of the openings 111 in the insulating material 110 (and therefore the x-length of the gates 108) may be between 40 and 60 nanometers (e.g., 50 nanometers) or between 20 and 40 nanometers (e.g., 30 nanometers); the y-length 171 of the openings 111 may take any of the values described herein for the x-length 170, for example.

[0036] The x- and y-dimensions of the quantum dot pillars 104 may take values corresponding to any of the x- and y-dimensions of the associated gates 108. In some embodiments, the x-y area of the quantum dot pillars 104 may be the same as the x-y area of the associated gates 108 (e.g., the x- and y-limits of the quantum dot pillars 104 may be aligned with the x- and y-limits of the associated gates 108, as shown in FIG. IB). In some embodiments, the x-y area of the quantum dot pillars 104 may be larger than the x-y area of the associated gates 108; in other embodiments, the x-y area of the quantum dot pillars 104 may be smaller than the x-y area of the associated gates 108. In some embodiments, the z-length 164 of the quantum dot pillars 104 may be between 200 and 400 nanometers (e.g., between 250 and 350 nanometers, or equal to 300 nanometers).

[0037] During operation of the quantum dot device 100, voltages may be applied to the gates 108-1 to adjust the potential energy in the quantum well layer 152-1 in the quantum dot pillars 104 to create quantum wells of varying depths in which quantum dots may form. Similarly, voltages may be applied to the gates 108-2 to adjust the potential energy in the quantum well layer 152-2 in the quantum dot pillars 104 to create quantum wells of varying depths in which quantum dots may form. As noted above, in some embodiments, the set 105-1 and/or the quantum well layer 152-1 may be omitted from the quantum dot device 100 (e.g., in a single-sided device embodiment). In some embodiments, the set 105-2 and/or the quantum well layer 152-2 may be omitted from the quantum dot device 100.

[0038] The portions of insulating material 110 disposed between adjacent gates 108 may themselves provide "passive" barriers between quantum wells under the gates 108 in the associated quantum well layer 152, and the voltages applied to different ones of the gates 108 may adjust the potential energy under the gates 108 in the quantum well layer 152; decreasing the potential energy may form quantum wells, while increasing the potential energy may form quantum barriers. The discussion below may generally refer to gates 108 and quantum well layers 152. This discussion may apply to the gates 108-1 and quantum well layer 152-1, respectively; to the gates 108-2 and quantum well layer 152-2, respectively; or to both.

[0039] The quantum dot pillar 104 may include doped regions 140 that may serve as a reservoir of charge carriers for the quantum dot device 100. In particular, the doped regions 140-1 may provide carriers to the quantum well layer 152-1, and the doped regions 140-2 may provide carriers to the quantum well layer 152-2. For example, an n-type doped region 140 may supply electrons for electron-type quantum dots, and a p-type doped region 140 may supply holes for hole-type quantum dots. In some embodiments, an interface material 141 may be disposed at a surface of a doped region 140, as shown by the interface material 141-1 at the surface of the doped regions 140- 1 and the interface material 141-2 at the surface of the doped regions 140-2. The interface material 141 may facilitate electrical coupling between a conductive contact (e.g., a conductive via 136, as discussed below) and the doped region 140. The interface material 141 may be any suitable metal- semiconductor ohmic contact material; for example, in embodiments in which the doped region 140 includes silicon, the interface material 141 may include nickel silicide, aluminum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tungsten silicide, or platinum silicide (e.g., as discussed below with reference to FIGS. 22-23). In some embodiments, the interface material 141 may be a non-silicide compound, such as titanium nitride. In some embodiments, the interface material 141 may be a metal (e.g., aluminum, tungsten, or indium). In some embodiments, a quantum dot device 100 may include doped layers in the quantum dot pillars 104, instead of or in addition to the doped regions 104, as discussed below with reference to FIGS. 73-75.

[0040] In some embodiments, the quantum dot devices 100 disclosed herein may include additional bridge pillars under the regions of insulating material 110 between the quantum dot pillars 104 and the doped regions 140. These bridge pillars may take the form of the quantum dot pillars 104 (and, in particular, may have bridge layers that correspond to the quantum dot layers 152), and may be fabricated simultaneously with the fabrication of the quantum dot pillars 104. During operation of the quantum dot device 100, the bridge layers of the bridge pillars may serve as conduits for carriers to flow between the doped regions 140 and the quantum dot layers 152 in the quantum dot pillars 104; thus, the bridge pillars may help to "bridge" any spatial gap between the quantum dot pillars 104 and the doped regions 140.

[0041] The quantum dot devices 100 disclosed herein may be used to form electron-type or hole- type quantum dots. Note that the polarity of the voltages applied to the gates 108 to form quantum wells/barriers depend on the charge carriers used in the quantum dot device 100. In embodiments in which the charge carriers are electrons (and thus the quantum dots are electron-type quantum dots), amply negative voltages applied to a gate 108 may increase the potential barrier under the gate 108, and amply positive voltages applied to a gate 108 may decrease the potential barrier under the gate 108 (thereby forming a potential well in the associated quantum well layer 152 in which an electron-type quantum dot may form). In embodiments in which the charge carriers are holes (and thus the quantum dots are hole-type quantum dots), amply positive voltages applied to a gate 108 may increase the potential barrier under the gate 108, and amply negative voltages applied to a gate 108 may decrease the potential barrier under the gate 108 (thereby forming a potential well in the associated quantum well layer 152 in which a hole-type quantum dot may form). The quantum dot devices 100 disclosed herein may be used to form electron-type or hole-type quantum dots.

[0042] Voltages may be applied to each of the gates 108 separately to adjust the potential energy in the quantum well layer under the gates 108, and thereby control the formation of quantum dots under each of the gates 108. Additionally, the relative potential energy profiles under different ones of the gates 108 allow the quantum dot device 100 to tune the potential interaction between quantum dots under adjacent gates 108. For example, if two adjacent quantum dots (e.g., one quantum dot under a gate 108 in one quantum dot pillar 104 and another quantum dot under an adjacent gate 108 in another quantum dot pillar 104) are separated by only a short potential barrier, the two quantum dots may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each gate 108 may be adjusted by adjusting the voltages on the respective gates 108 and neighboring gates, the differences in potential between various gates 108 may be adjusted, and thus the interaction tuned. In some applications, the gates 108 may be used as plunger gates to enable the formation of quantum dots under the gates 108.

[0043] Conductive vias and lines may make contact with the gates 108, and with the doped regions 140, to enable electrical connection to the gates 108 and the doped regions 140/quantum well layers 152 to be made in desired locations. As shown in FIG. IB, the gates 108-1 may extend away from the associated quantum dot pillars 104, and conductive vias 122-1 may extend through insulating material 130-1 to contact the gate metal 112-1 of the gates 108-1. The conductive vias 122-1 may extend through the hardmask 118-1 to contact the gate metal 112-1 of the gates 108-1. Conductive lines 123-1 may contact the conductive vias 122-1, and may extend "laterally" away from the conductive vias 122-1 to make contact with conductive vias 125-1 that extend through the insulating material 130-1, the insulating material 128, and insulating material 130-2.

[0044] The gates 108-2 may extend away from the associated quantum dot pillars 104, and conductive vias 122-2 may contact the gates 108-2. The conductive vias 122-2 may extend through the hardmask 118-2 to contact the gate metal 112-2 of the gates 108-2. The insulating material 130- 1 and the insulating material 130-2 may have different material compositions, or the same material composition. Examples of materials that may be used for the insulating materials 130 are discussed below.

[0045] Conductive vias 136 may contact the interface material 141 and may thereby make electrical contact with the doped regions 140. In particular, the conductive vias 136-1 may extend through the insulating material 130 and make contact with the doped regions 140-1, and the conductive vias 136-2 may extend through the insulating material 130 and make contact with the doped regions 140-2. The quantum dot device 100 may include further conductive vias and/or lines (not shown) to make electrical contact to the gates 108 and/or the doped regions 140, as desired. The conductive vias and lines included in a quantum dot device 100 may include any suitable materials, such as copper, tungsten (deposited, e.g., by CVD), or a superconductor (e.g., aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium).

[0046] As illustrated in FIGS. IB and 1C, in some embodiments, the insulating material 128 may include recesses 107 that extend down to the interface material 141-1 to make conductive contact with the doped regions 140-1. The recesses 107 may be filled with the insulating material 130, and the bottoms of the recesses 107 may be doped to provide the doped regions 140-1.

[0047] During operation, a bias voltage may be applied to the doped regions 140 (e.g., via the conductive vias 136 and the interface material 141) to cause current to flow through the doped regions 140. When the doped regions 140 are doped with an n-type material, this voltage may be positive; when the doped regions 140 are doped with a p-type material, this voltage may be negative. The magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts).

[0048] The conductive vias 122, 125, and 136 may be electrically isolated from each other by various insulating materials, including the insulating materials 130-1 and 130-2, and the insulating material 128, as shown. The insulating material 130 may be any suitable material, such as an interlayer dielectric (ILD). Examples of the insulating material 130 may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride. As known in the art of integrated circuit manufacturing, conductive vias and lines may be formed in an iterative process in which layers of structures are formed on top of each other. In some embodiments, the conductive vias 122/125/136 may have a width that is 20 nanometers or greater at their widest point (e.g., 30 nanometers), and a pitch of 80 nanometers or greater (e.g., 100 nanometers). In some

embodiments, conductive lines (e.g., the conductive lines 123) included in the quantum dot device 100 may have a width that is 100 nanometers or greater, and a pitch of 100 nanometers or greater. The particular arrangement of conductive vias and lines shown in FIGS. 1A-D is simply illustrative, and any electrical routing arrangement may be implemented.

[0049] In some embodiments, the quantum dots in the quantum well layer 152-2 may be used as "active" quantum dots in the sense that these quantum dots act as qubits and are controlled (e.g., by voltages applied to the gates 108-2) to perform quantum computations. The quantum dots in the quantum well layer 152-1 may be used as "read" quantum dots in the sense that a quantum dot in the quantum well layer 152-1 of a quantum dot pillar 104 may sense the quantum state of the quantum dot in the quantum well layer 152-2 of the same quantum dot pillar 104 by detecting the electric field generated by the charge in the quantum dot of the quantum well layer 152-2, and may convert the quantum state of the quantum dot in the quantum well layer 152-2 into electrical signals that may be detected by the associated gate 108-1. In some embodiments, each quantum dot in the quantum well layer 152-1 may be read by its corresponding quantum dot in the quantum well layer 152-2. In some other embodiments, the "active" and "read" roles of the quantum dots in the quantum well layers 152-1 and 152-2 may be switched. Thus, the quantum dot device 100 enables both quantum computation and the ability to read the results of a quantum computation within a single quantum dot pillar, if desired. In other embodiments, one or more of the quantum well layers 152 and associated set of gates 105 may be omitted. In some such embodiments, the quantum dots formed in the remaining quantum well layer(s) 152 may be "read" by other devices (not shown), if appropriate (e.g., single electron transistors (SETs)).

[0050] The quantum dot devices 100 disclosed herein may be manufactured using any suitable techniques. FIGS. 2-25 illustrate various example stages in the manufacture of the quantum dot device 100 of FIGS. 1A-D, in accordance with various embodiments. Further, FIGS. 26-33B, FIGS. 34A-40B, FIGS. 41A-50B, FIGS. 51A-57B, and FIGS. 58-70 illustrate various sets of techniques for patterning the quantum dot pillars 104 and the gates 105; any of the techniques disclosed herein may be used in any combination to pattern the quantum dot pillars 104 and the sets of gates 105 in accordance with the process discussed with reference to FIGS. 2-25. Although the particular manufacturing operations discussed below with reference to FIGS. 2-25 are illustrated as manufacturing a particular embodiment of the quantum dot device 100, these operations may be applied to manufacture many different embodiments of the quantum dot device 100, as discussed herein. Any of the elements discussed below with reference to FIGS. 2-25 may take the form of any of the embodiments of those elements discussed above (or otherwise disclosed herein). For ease of illustration, not all elements in each of FIGS. 2-25 are expressly labeled with reference numerals, but reference numerals for each element are included among the drawings of FIGS. 2-25.

[0051] FIG. 2 illustrates a cross-sectional view of an assembly 202 including a base 102. The base 102 may include any suitable semiconductor material or materials, or any other suitable structure on which to perform the subsequent operations. In some embodiments, the base 102 may include a semiconductor material. For example, the base 102 may include silicon (e.g., may be formed from a silicon wafer).

[0052] FIG. 3 illustrates a cross-sectional view of an assembly 204 subsequent to providing a quantum well stack 146 on the base 102 of the assembly 202 (FIG. 2). The quantum well stack 146 may include at least one quantum well layer 152. For example, the quantum well stack 146 illustrated in FIG. 3 includes a quantum well layer 152-1, a quantum well layer 152-2, and a barrier layer 154 disposed therebetween. As discussed above, a 2DEG may form in the quantum well layer 152-1 and/or the quantum well layer 152-2 during operation of the quantum dot device 100.

Various embodiments of the quantum well stack 146 are discussed below with reference to FIGS. 71- 75. As noted above, in some embodiments, the quantum well stack 146 may include only a single quantum well layer 152 (and in some such embodiments, only a single set of gates 105, as discussed below).

[0053] FIG. 4 illustrates a cross-sectional view of an assembly 206 subsequent to patterning the quantum well stack 146 of the assembly 204 (FIG. 3) into multiple quantum dot pillars 104. The size and shape of the quantum dot pillars 104 may take any suitable form (e.g., the substantially rectangular solid form illustrated in FIGS. 1A-D, or pillars with more rounded peaks and sides). The quantum well stack 146 may be patterned and etched using any suitable technique known in the art to form the quantum dot pillars 104. For example, a combination of dry and wet etch chemistry may be used to shape the quantum well stack 146 into the quantum dot pillars 104, and the appropriate chemistry may depend on the materials included in the assembly 204, as known in the art. Any of the techniques illustrated in FIGS 26-33B, FIGS. 34A-40B, FIGS. 41A-50B, FIGS. 51A-57B, and/or FIGS. 58-70 may be used to pattern the quantum well stack 146 into the quantum dot pillars 104, as discussed below.

[0054] FIG. 5A illustrates a cross-sectional view of an assembly 208 subsequent to providing an insulating material 128 around the quantum dot pillars 104 of the assembly 206 (FIG. 4), then planarizing the resulting assembly to remove the insulating material 128 above the quantum dot pillars 104 (or, more generally, the material above a certain height). Any suitable material may be used as the insulating material 128 to electrically insulate the quantum dot pillars 104. As noted above, in some embodiments, the insulating material 128 may be a dielectric material, such as silicon oxide. In some embodiments, the assembly 208 may be planarized using a chemical mechanical polishing (CMP) technique.

[0055] FIG. 5B is a perspective view of at least a portion of the assembly 208, showing the quantum dot pillars 104 extending from the base 102 and laterally insulated by the insulating material 128. FIG. 5C is another cross-sectional view of the assembly 208, illustrating the quantum dot pillars 104 without any internal detail, for ease of illustration; the cross-sectional view of FIG. 5C corresponds to the cross-sectional view of FIG. IB. The views illustrated in FIGS. 6-13 maintain the perspective of FIG. 5C, while the cross-sectional views illustrated in FIGS. 14-25 are "zoomed out" relative to the view of FIG. 5C.

[0056] FIG. 6 is a cross-sectional view of an assembly 210 subsequent to providing an insulating material 110-1 on the quantum well stack 146 of the assembly 208 (FIGS. 5A-C). The insulating material 110-1 may take any of the forms disclosed herein, and may be deposited using any suitable technique. [0057] FIG. 7A is a cross-sectional view of an assembly 228 subsequent to patterning the insulating material 110-1 of the assembly 210 (FIG. 6) to form openings 111-1. Any of the techniques illustrated in FIGS 26-33B, FIGS. 34A-40B, FIGS. 41A-50B, FIGS. 51A-57B, and/or FIGS. 58-70 may be used to pattern the openings 111-1 into the insulating material 110-1. FIG. 7B is a top view of the assembly 228; the cross-sectional view of FIG. 7A is taken along the section A-A of FIG. 7B. In the assembly 228, the insulating material 110-1 may have a grid or cross-grating shape around the rectangular openings 111-1, and the quantum dot pillars 104 may be exposed through these openings. As noted above, although only four openings 111-1 arranged in a 2x2 array are illustrated in FIGS. 7A-B, any array of openings 111-1 of any desired number and size may be formed using the techniques disclosed herein.

[0058] FIG. 8 is a cross-sectional view of an assembly 230 subsequent to providing a gate dielectric 114-1 on the quantum well stack 146 in the openings 111-1 between portions of the insulating material 110-1 of the assembly 228 (FIGS. 7A-B). In some embodiments, the gate dielectric 114-1 of the assembly 230 may be formed by atomic layer deposition (ALD) and, as illustrated in FIG. 8, may cover the exposed quantum dot pillars 104 in the openings 111-1 and may extend onto the adjacent insulating material 110-1.

[0059] FIG. 9 is a cross-sectional view of an assembly 232 subsequent to providing the gate metal 112-1 on the assembly 230 (FIG. 8). The gate metal 112-1 may fill the openings 111-1 between the gate dielectric 114-1 disposed on adjacent side walls of the insulating material 110-1, and may extend over the insulating material 110-1. The gate metal 112-1 may be provided using any suitable technique.

[0060] FIG. 10 is a cross-sectional view of an assembly 234 subsequent to planarizing the assembly 232 (FIG. 9) to remove the gate metal 112-1 and the gate dielectric 114-1 above the insulating material 110-1. In some embodiments, the assembly 232 may be planarized to form the assembly 234 using a CMP technique. The remaining gate metal 112-1 may fill the openings 111-1 in the insulating material 110-1.

[0061] FIG. 11 is a cross-sectional view of an assembly 236 subsequent to providing a hardmask 118-1 on the planarized surface of the assembly 234 (FIG. 10). The hardmask 118-1 may be formed of an electrically insulating material, such as silicon nitride or carbon-doped nitride, or any of the other materials discussed above.

[0062] FIG. 12 is a cross-sectional view of an assembly 238 subsequent to patterning the hardmask 118-1 of the assembly 236 (FIG. 11). The pattern applied to the hardmask 118-1 may extend over the gate metal 112-1 and onto adjacent portions of the insulating material 110-1. The hardmask 118-1 may be patterned by applying a resist, patterning the resist using lithography, and then etching the hardmask (using dry etching or any appropriate technique).

[0063] FIG. 13 is a cross-sectional view of an assembly 240 subsequent to etching the assembly 238 (FIG. 12) to remove the portions of insulating material 110-1 that are not protected by the patterned hardmask 118-1. The patterned hardmask 118-1 may remain on top of the insulating material 110-1 and gates 108-1, as shown.

[0064] FIG. 14 is a cross-sectional view of an assembly 242 subsequent to providing an insulating material 130-1 on the assembly 240 (FIG. 13). As noted above, FIGS. 14-25 represent a "zoomed out" view, showing additional insulating material 128 disposed at the side faces of the quantum dot pillars 104. The insulating material 130-1 may take any of the forms discussed above. For example, the insulating material 130-1 may be a dielectric material, such as silicon oxide. The insulating material 130-1 may be provided on the assembly 242 using any suitable technique, such as spin coating, chemical vapor deposition (CVD), or plasma-enhanced CVD (PECVD). In some

embodiments, the insulating material 130-1 may be polished back after deposition, and before further processing. In some embodiments, the assembly 242 may be planarized to remove the hardmask 118-1, then additional insulating material 130-1 may optionally be provided on the planarized surface; in such an embodiment, the hardmask 118-1 would not be present in the quantum dot device 100.

[0065] FIG. 15 is a cross-sectional view of an assembly 244 subsequent to forming conductive vias 122-1 and conductive lines 123-1 in electrical contact with the gate metal 112-1 of the gates 108-1 of the assembly 242 (FIG. 14). The conductive vias and lines may be formed using any conventional interconnect technique (e.g., depositing the insulating material 130-1, forming cavities for the vias, filling the cavities with conductive material for the vias, polishing back the conductive material overburden, depositing additional insulating material 130-1, forming trenches for the lines, filling the trenches with conductive material for the lines, etc.). Generally, conductive vias and lines included in the quantum dot devices 100 disclosed herein may be formed using any suitable additive, subtractive, semi-additive/subtractive, or other known interconnect formation technique.

[0066] FIG. 16 is a cross-sectional view of an assembly 246 subsequent to attaching a support 103 to the insulating material 130-1 of the assembly 244 (FIG. 15). The support 103 may take any suitable form for providing mechanical support for the operations discussed below. For example, in some embodiments, the support 103 may be a carrier wafer and may be secured to the insulating material 130-1 using an adhesive. In some embodiments, the support 103 may be a mechanical fixture that may be temporarily secured to the insulating material 130-1 (e.g., by clamping or using a fastener), and removed when no longer needed. [0067] FIG. 17 is a cross-sectional view of an assembly 248 subsequent to removing the base 102 from the assembly 246 (FIG. 16). The quantum dot pillars 104 may remain secured to the gates 108- 1, the insulating material 110-1, and the insulating material 130-1 (which may be mechanically supported by the support 103). Any suitable technique may be used to separate the base 102 from the rest of the assembly 246. For example, in some embodiments, an ion implantation and wafer bonding technique may be used in which the support 103 is adhered to the assembly 244 (as discussed above with reference to FIG. 16) and then the base 102 is polished or etched away. In some embodiments, the base 102 may be mechanically separated from the rest of the assembly 246, and then the "broken" surface of the assembly 246 may be polished or etched.

[0068] FIG. 18 is a cross-sectional view of an assembly 250 subsequent to turning the assembly 248 (FIG. 17) "upside down" so that further processing may be performed on the exposed quantum dot pillars 104. In some embodiments, the assembly 248 need not be physically reoriented (as illustrated in FIG. 18) in order for subsequent processing operations to be performed.

[0069] FIG. 19 is a cross-sectional view of an assembly 252 subsequent to forming a patterned insulator material 110-2 and gates 108-2 with a gate dielectric 114-2 on the quantum well stack 146 proximate to the quantum well layer 152-2. The patterned insulator material 110-2 and the gates 108-2 may be formed using any of the techniques discussed above with reference to the formation of the patterned insulator material and the gates 108-1 (e.g., discussed above with reference to FIGS. 6-13). Any of the techniques illustrated in FIGS 26-33B, FIGS. 34A-40B, FIGS. 41A-50B, FIGS. 51A-57B, and/or FIGS. 58-70 may be used to pattern the insulating material 110-2. For example, as shown in FIG. 19, a hardmask 118-2 may be disposed on the gate metal 112-2 of the gates 108-2, analogously to the hardmask 118-1 of the gates 108-1.

[0070] FIG. 20 is a cross-sectional view of an assembly 254 subsequent to forming recesses 107 in the insulating material 128 outside the perimeter of the area including the quantum dot pillars 104 of the assembly 252 (FIG. 19). The recesses 107 may be formed using any of the patterning techniques discussed above with reference to FIG. 4, and may extend down to any desired depth. For example, in some embodiments, the recesses 107 may extend down to a depth of the quantum well layer 152-1. In embodiments in which the quantum well stack 146 includes a single quantum well layer 152, the recesses 107 may not be formed.

[0071] FIG. 21A is a cross-sectional view of an assembly 256 subsequent to doping the quantum well stack 146 of the assembly 254 (FIG. 20) to form doped regions 140-1 at the bottoms of the recesses 107, and doped regions 140-2 adjacent to the insulating material 110-2. The doped regions 140-1 may be disposed proximate to the quantum well layer 152-1 so that carriers in the doped regions 140-1 may travel into the quantum well layer 152-1 or proximate quantum dot pillars 104 (e.g., by direct contact or by tunneling). The doped regions 140-2 may be disposed proximate to the quantum well layer 152-2 so that carriers in the doped regions 140-2 may travel into the quantum well layer 152-2 of proximate quantum dot pillars 104 (e.g., by direct contact or by tunneling). FIG. 21B is a top view of the assembly 256, showing the doped regions 140-1 and 140-2.

[0072] The type of dopant used to form the doped regions 140 may depend on the type of quantum dot desired, as discussed above. In some embodiments, the doping may be performed by ion implantation. For example, when a quantum dot is to be an electron-type quantum dot, the doped regions 140 may be formed by ion implantation of phosphorous, arsenic, or another n-type material. When a quantum dot is to be a hole-type quantum dot, the doped regions 140 may be formed by ion implantation of boron or another p-type material. An annealing process that activates the dopants and causes them to diffuse farther into the quantum well stack 146 may follow the ion implantation process. The depth of the doped regions 140 may take any suitable value; for example, in some embodiments, the doped regions 140 may each have a depth 115 between 500 and 1000 Angstroms. The doping concentration of the doped regions 140 may, in some embodiments, be between 1017/cm3 and 1020/cm3.

[0073] FIG. 22 is a cross-sectional side view of an assembly 258 subsequent to providing a layer of nickel or other material 143 over the assembly 256 (FIGS. 21A-B). The nickel or other material 143 may be deposited on the assembly 256 using any suitable technique (e.g., a plating technique, chemical vapor deposition, or atomic layer deposition).

[0074] FIG. 23 is a cross-sectional side view of an assembly 260 subsequent to annealing the assembly 258 (FIG. 22) to cause the material 143 to interact with the doped regions 140 to form the interface material 141, then removing the unreacted material 143. When the doped regions 140 include silicon and the material 143 includes nickel, for example, the interface material 141 may be nickel silicide. Materials other than nickel may be deposited in the operations discussed above with reference to FIG. 22 in order to form other interface materials 141, including titanium, aluminum, molybdenum, cobalt, tungsten, or platinum, for example. More generally, the interface material 141 of the assembly 260 may include any of the materials discussed herein with reference to the interface material 141.

[0075] FIG. 24 is a cross-sectional view of an assembly 262 subsequent to providing an insulating material 130-2 on the assembly 260 (FIG. 23). The insulating material 130-2 may take any of the forms discussed above. For example, the insulating material 130-2 may be a dielectric material, such as silicon oxide. The insulating material 130-2 may be provided on the assembly 260 using any suitable technique, such as spin coating, chemical vapor deposition (CVD), or plasma-enhanced CVD (PECVD). In some embodiments, the insulating material 130-2 may be polished back after deposition, and before further processing.

[0076] FIG. 25 is a cross-sectional view of an assembly 264 subsequent to forming, in the assembly 262 (FIG. 24), conductive vias 122-2 through the insulating material 130-2 (and the hardmask 118-2) to contact the gate metal 112-2 of the gates 108-2, conductive vias 136-2 through the insulating material 130-2 to contact the interface material 141-2 of the doped regions 140-2, conductive vias 136-1 through the insulating material 130-2 to contact the interface material 141-1 of the doped regions 140-1, and conductive vias 125-1 through the insulating material 130-2, the insulating material 128, and the insulating material 130-1 to contact the conductive lines 123-1 (to make electrical contact with the gate metal 112-1 of the gates 108-1). Further conductive vias and/or lines may be formed on the assembly 264 using conventional interconnect techniques, if desired. The resulting assembly 264 may take the form of the quantum dot device 100 discussed above with reference to FIGS. 1A-D. In some embodiments, the assembly 262 may be planarized to remove the hardmask 118-2, then additional insulating material 130-2 may be provided on the planarized surface before forming the conductive vias 122, 125, and 136; in such an embodiment, the hardmask 118-2 would not be present in the quantum dot device 100.

[0077] As noted above, different patterning techniques may be used to form the various structures of the quantum dot devices 100 disclosed herein. These different patterning techniques may achieve different dimensions (e.g., pitches) or result in structures with different shapes, for example. FIGS. 26-33B, FIGS. 34A-40B, FIGS. 41A-50B, FIGS. 51A-57B, and FIGS. 58-70 each illustrate different techniques that may be used to pattern various elements in a quantum dot device 100, and are illustrated and discussed as patterning a material 1219 on a material 1221. The materials 1219 and 1221 may take any of the forms disclosed herein; for example, the material 1219 may be the insulating material 110 and the material 1221 may be the assembly 208 (e.g., when forming openings 111, as discussed above with reference to FIG. 7). In some embodiments, when any of these techniques are used to form the quantum dot pillars 104, the material 1219 may be a template material (not shown) and the material 1221 may be the quantum well stack 146 of FIG. 3; the openings 1223 formed in the template material using these techniques may be filled with a protective material, the template material may be etched away, and the exposed quantum well stack 146 may then be etched, leaving the quantum dot pillars 104 (protected by the protective material and taking the shape of the openings 1223).

[0078] FIG. 26 is a cross-sectional view of an assembly 212 subsequent to providing a hardmask 201 on the material 1219 (e.g., the quantum well stack 146 of the assembly 204 of FIG. 3, or the insulating material 110-1 of the assembly 210 of FIG. 6). The hardmask 201 may be formed of an electrically insulating material, such as silicon nitride or carbon-doped nitride. The etch selectivity of the hardmask 201, as well as the other masks (e.g., hardmasks) disclosed herein, may be chosen to achieve the patterning results described, and may take any suitable form.

[0079] FIG. 27A is a cross-sectional view of an assembly 214 subsequent to providing a resist material 203 on the hardmask 201 of the assembly 212 (FIG. 26). FIG. 27B is a top view of the assembly 214; the cross-sectional view of FIG. 27 A is taken along the section A-A of FIG. 27B. In some embodiments, the resist material 203 may be a photoresist, and when patterned, may serve as a mask for subsequent operations, as discussed below. The resist material 203, and any of the resist materials discussed herein, may be applied using any suitable technique, such as coating or casting processes (e.g., spin coating).

[0080] FIG. 28A is a cross-sectional view of an assembly 216 subsequent to patterning trenches 205 in the resist material 203 of the assembly 214 (FIGS. 27A-B). FIG. 28B is a top view of the assembly 216; the cross-sectional view of FIG. 28A is taken along the section A-A of FIG. 28B. In particular, the view of FIG. 28A is taken along a trench 205. The trenches 205 may be parallel, and when patterned using conventional lithography, may have a width between 20 and 150 nanometers (e.g., between 30 and 80 nanometers) and a pitch between 60 and 300 nanometers (e.g., between 80 and 160 nanometers). Only two trenches 205 are illustrated in FIG. 28B for economy of illustration, but any desired number of trenches 205 may be formed. The resist material 203 may be patterned using any suitable technique (e.g., any suitable lithographic technique).

[0081] FIG. 29A is a cross-sectional view of an assembly 218 subsequent to patterning the hardmask 201 in accordance with the pattern of the resist material 203 of the assembly 216 (FIGS. 28A-B), and then removing the remaining resist material 203. FIG. 29B is a top view of the assembly 218; the cross-sectional view of FIG. 29A is taken along the section A-A of FIG. 29B. The resulting patterned hardmask 201 may include trenches 277 corresponding to the trenches 205 in the resist material 203. The hardmask 201 may be patterned using any suitable technique (such as dry etching).

[0082] FIG. 30A is a cross-sectional view of an assembly 220 subsequent to providing a hardmask 207 on the material 1219 and the patterned hardmask 201 of the assembly 218 (FIGS. 29A-B). FIG. 30B is a top view of the assembly 220; the cross-sectional view of FIG. 30A is taken along the section A-A of FIG. 30B. The hardmask 207 may be formed of any suitable material, such as any of the materials discussed above with reference to the hardmask 201.

[0083] FIG. 31A is a cross-sectional view of an assembly 222 subsequent to providing a resist material 275 on the hardmask 207 of the assembly 220 (FIGS. 30A-B), and patterning trenches 209 in the resist material 275. FIG. 31B is a top view of the assembly 222; the cross-sectional view of FIG. 31A is taken along the section A-A of FIG. 31B. The resist material 275 may take any suitable form (e.g., a photoresist). The trenches 209 in the resist material 275 may be oriented differently than the trenches 205 in the assembly 216 (FIGS. 28A-B); for example, as illustrated in FIGS. 31A-B, the trenches 209 may be perpendicular to, and overlap with, the trenches 205. The trenches 209 may be parallel, and may have any of the widths and spacings discussed above with reference to the trenches 205. Only two trenches 209 are illustrated in FIGS. 31A-B for economy of illustration, but any desired number of trenches 209 may be formed. The resist material 275 may be patterned using any suitable technique (e.g., any suitable lithographic technique).

[0084] FIG. 32A is a cross-sectional view of an assembly 224 subsequent to patterning the hardmask 207 in accordance with the pattern of the resist material 275 of the assembly 222 (FIGS. 31A-B), and then removing the remaining resist material 275. FIG. 32B is a top view of the assembly 224; the cross-sectional view of FIG. 32A is taken along the section A-A of FIG. 32B. The resulting patterned hardmask 207 may include trenches 211 corresponding to the trenches 209 in the resist material 275. The hardmask 207 may be patterned using any suitable technique (such as dry etching). As illustrated in FIGS. 32A-B, rectangular portions of the surface of the material 1219 may be exposed in the assembly 224, while the remainder of the material 1219 is covered by the hardmask 201 and/or the hardmask 207.

[0085] FIG. 33A is a cross-sectional view of an assembly 226 subsequent to patterning the material 1219 in accordance with the pattern of the hardmask 201 and the hardmask 207 of the assembly 224 (FIGS. 32A-B) so as to etch away the portions of the material 1219 that are not covered by at least one of the hardmasks 201 and 207. FIG. 33B is a top view of the assembly 226; the cross- sectional view of FIG. 33A is taken along the section A-A of FIG. 33B. The resulting patterned material 1219 may include openings 1223 that have rectangular footprints (corresponding to the areas where the trenches 277 of the hardmask 201 "overlapped" with the trenches 211 of the hardmask 207 to expose the material 1219). The hardmasks 201 and 207 of the assembly 226 may then be removed.

[0086] FIGS. 34A-40B illustrate another set of techniques for patterning a material 1219. In some embodiments, these techniques may be used instead of the techniques illustrated in FIGS. 27A-33B.

[0087] FIG. 34A is a cross-sectional view of an assembly 1214 subsequent to providing a resist material 1203 on the hardmask 201 of the assembly 212 (FIG. 26). FIG. 34B is a top view of the assembly 1214; the cross-sectional view of FIG. 34A is taken along the section A-A of FIG. 34B. The resist material 1203 may be a photoresist, and may be pre-baked after deposition. Any ones of the resist materials disclosed herein may be pre-baked after deposition, as appropriate.

[0088] FIG. 35A is a cross-sectional view of an assembly 1216 subsequent to exposing the resist material 1203 to form unexposed resist material 1203a and strips of exposed resist material 1203b in the resist material 1203 of the assembly 1214 (FIGS. 34A-B). FIG. 35B is a top view of the assembly 1216; the cross-sectional view of FIG. 35A is taken along the section A-A of FIG. 35B. In particular, the view of FIG. 35A is taken along a strip of exposed resist material 1203b. Only two strips of exposed resist material 1203b are illustrated in FIG. 35B for economy of illustration, but any desired number of strips of exposed resist material 1203b may be formed. The resist material 1203 of the assembly 1216 may be subject to a post-exposure bake, in some embodiments. Any of the resist materials disclosed herein may be subject to a post-exposure bake, as appropriate.

[0089] FIG. 36A is a cross-sectional view of an assembly 1218 subsequent to developing the resist material 1203 of the assembly 1216 (FIGS. 35A-B) to remove the strips of exposed resist material 1203b to form trenches 1277 in the resist material 1203. FIG. 36B is a top view of the assembly 1218; the cross-sectional view of FIG. 36A is taken along the section A-A of FIG. 36B. The remaining unexposed resist material 1203a may be hard-baked, in some embodiments. Any of the resist materials disclosed herein may be hard-baked, as appropriate.

[0090] FIG. 37A is a cross-sectional view of an assembly 1220 subsequent to providing another layer of resist material 1207 on the assembly 1218 (FIGS. 36A-B). FIG. 37B is a top view of the assembly 1220; the cross-sectional view of FIG. 37A is taken along the section A-A of FIG. 37B. The resist material 1207 may take any of the forms discussed above with reference to the resist material 1203, for example. In some embodiments, the resist material 1207 may be pre-baked after deposition.

[0091] FIG. 38A is a cross-sectional view of an assembly 1222 subsequent to exposing and developing the resist material 1207 of the assembly 1220 (FIGS. 37A-B) to form trenches 1209 in the resist material 1207. FIG. 38B is a top view of the assembly 1222; the cross-sectional view of FIG. 38A is taken along the section A-A of FIG. 38B. The resist material 1207 may be exposed in accordance with any of the embodiments discussed above with reference to FIGS. 35A-B (leaving unexposed resist material 1207a in which the trenches 1209 are defined), and may be developed in accordance with any of the embodiments discussed above with reference to FIGS. 36A-B. The trenches 1209 in the resist material 1207 may be oriented differently than the trenches 1277 in the assembly 1218 (FIGS. 36A-B); for example, as illustrated in FIGS. 38A-B, the trenches 1209 may be perpendicular to, and overlap with, the trenches 1277 to expose the hardmask 201. The trenches 1209 may be parallel, and may have any of the widths and spacings discussed above with reference to the trenches 1277. Only two trenches 1209 are illustrated in FIGS. 38A-B for economy of illustration, but any desired number of trenches 1209 may be formed.

[0092] FIG. 39A is a cross-sectional view of an assembly 1224 subsequent to etching the hardmask 201 of the assembly 1222 (FIGS. 38A-B) to remove portions of the hardmask 201 that are not covered by the unexposed resist material 1207a or the unexposed resist material 1203a. FIG. 39B is a top view of the assembly 1224; the cross-sectional view of FIG. 39A is taken along the section A-A of FIG. 39B. The resulting patterned hardmask 201 may include trenches 1211 corresponding to the areas of overlap between the trenches 1209 and the trenches 1277. The hardmask 201 may be patterned using any suitable technique (such as dry etching). As illustrated in FIGS. 39A-B, rectangular portions of the surface of the material 1219 may be exposed in the assembly 1224, while the remainder of the material 1219 may be covered by the hardmask 201.

[0093] FIG. 40A is a cross-sectional view of an assembly 1226 subsequent to patterning the material 1219 in accordance with the pattern of the hardmask 201 of the assembly 1224 (FIGS. 39A-B) so as to etch away the portions of the material 1219 that are not covered by the hardmask 201. FIG. 40B is a top view of the assembly 1226; the cross-sectional view of FIG. 40A is taken along the section A- A of FIG. 40B. The resulting patterned material 1219 may include openings 1223 that have rectangular footprints (corresponding to the areas where the trenches 1209 "overlapped" with the trenches 1277 to expose the material 1219). The layers resist material 1203 and 1207 and the hardmask 201 may then be removed.

[0094] In some embodiments, alternative patterning techniques may be used, resulting in openings 1223 that have a different shape from what would be achievable using the technique of FIGS. 26-33B and 34A-40B. FIGS. 41A-50B illustrate an example of such an alternative technique that may be used instead of the patterning techniques of FIGS. 26-33B or 34A-40B.

[0095] FIG. 41A is a cross-sectional view of an assembly 266 subsequent to providing a hardmask 201 and a hardmask 207 on the material 1219 (e.g., a template material on the quantum well stack 146 of the assembly 204 of FIG. 3, or the insulating material 110-1 of the assembly 210 (of FIG. 6). FIG. 41B is a top view of the assembly 266; the cross-sectional view of FIG. 41A is taken along the section A-A of FIG. 41B. The hardmasks 201 and 207 may take the form of any of the embodiments discussed above.

[0096] FIG. 42A is a cross-sectional view of an assembly 268 subsequent to providing a resist material 279 on the hardmask 207 of the assembly 266 (FIGS. 41A-B), and patterning trenches 215 in the resist material 279. FIG. 42B is a top view of the assembly 268; the cross-sectional view of FIG. 42A is taken along the section A-A of FIG. 42B. The resist material 279 may take any suitable form (e.g., a photoresist). The trenches 215 in the resist material 279 may be parallel, and may have any of the widths and spacings discussed above with reference to the trenches 205. Only two trenches 215 are illustrated in FIGS. 42A-B for economy of illustration, but any desired number of trenches 215 may be formed. The resist material 279 may be patterned using any suitable technique (e.g., any suitable lithographic technique). [0097] FIG. 43A is a cross-sectional view of an assembly 270 subsequent to patterning the hardmask 207 in accordance with the pattern of the resist material 279 of the assembly 268 (FIGS. 42A-B), and then removing the remaining resist material 279. FIG. 43B is a top view of the assembly 270; the cross-sectional view of FIG. 43A is taken along the section A-A of FIG. 43B. The resulting patterned hardmask 207 may include trenches 217 corresponding to the trenches 215 in the resist material 279. The hardmask 207 may be patterned using any suitable technique (such as dry etching).

[0098] FIG. 44A is a cross-sectional view of an assembly 272 subsequent to filling the trenches 217 in the hardmask 207 of the assembly 270 (FIGS. 43A-B) with a fill material 219. FIG. 44B is a top view of the assembly 272; the cross-sectional view of FIG. 44A is taken along the section A-A of FIG. 44B. The fill material 219 may be a material that may be etched away without etching the hardmask 207, as discussed below. In some embodiments, the fill material 219 may be an amorphous material, such as amorphous silicon or a bottom antireflective coating (BA C). The fill material 219 may be provided in the trenches 217 using any suitable technique (e.g., plasma-enhanced chemical vapor deposition for amorphous silicon, or spin-on for BARC).

[0099] FIG. 45A is a cross-sectional view of an assembly 274 subsequent to providing a resist material 281 on the hardmask 207 and the fill material 219 of the assembly 272 (FIGS. 44A-B). FIG. 45B is a top view of the assembly 274; the cross-sectional view of FIG. 45A is taken along the section A-A of FIG. 45B. In some embodiments, the resist material 281 may be a photoresist, and when patterned, may serve as a mask for subsequent operations, as discussed below.

[0100] FIG. 46A is a cross-sectional view of an assembly 276 subsequent to patterning holes 221 in the resist material 281 of the assembly 274 (FIGS. 45A-B). FIG. 46B is a top view of the assembly 276; the cross-sectional view of FIG. 46A is taken along the section A-A of FIG. 46B. The holes 221 may be formed using any suitable technique, such as extreme ultraviolet (EUV) lithography. As shown in FIGS. 46A-B, the holes 221 may be substantially circular, and may be provided in a regular array or any other desired pattern in the resist material 281. In particular, the holes 221 may overlap with the segments of the fill material 219, and as illustrated, may extend beyond the fill material 219 and may expose at least some of the hardmask 207 proximate to the fill material 219. Only four holes 221 are illustrated in FIG. 46B for economy of illustration, but any desired number of holes 221 may be formed. The dimensions of the holes 221 may be selected to limit the likelihood that adjacent holes 221 will inadvertently merge (e.g., due to process variation).

[0101] FIG. 47A is a cross-sectional view of an assembly 278 subsequent to patterning the fill material 219 in accordance with the pattern of the resist material 281 of the assembly 276 (FIGS. 46A-B), and then removing the remaining resist material 281. FIG. 47B is a top view of the assembly 278; the cross-sectional view of FIG. 47A is taken along the section A-A of FIG. 47B. The resulting patterned fill material 219 may include openings 223 corresponding to areas in which the holes 221 and the fill material 219 overlapped in the assembly 276 (FIGS. 46A-B); the etching of the fill material 219 may not etch the hardmask 207, and thus the holes 221 may not be transferred in their entireties to the underlying layers. In particular, the openings 223 may have two opposing sides that are substantially flat or linear (corresponding to the border between the hardmask 207 and the fill material 219) and two opposing sides that are curved or semicircular (corresponding to the edges of the holes 221 that entirely overlap the fill material 219). The fill material 219 may be patterned using any suitable technique (such as dry etching). As illustrated in FIGS. 47A-B, the openings 223 may expose portions of the surface of the hardmask 201 in the assembly 278, while the remainder of the hardmask 201 is covered by the hardmask 207 and/or the fill material 219.

[0102] In some embodiments, the fill material 219 may be a photoresist material. In some such embodiments, the fill material 219 may be patterned directly (e.g., using EUV) instead of applying the resist material 281, patterning the resist material 281, and transferring that pattern to the fill material 219. Thus, in such embodiments, the operations discussed above with reference to FIGS. 46A-B may not be performed; instead, the fill material 219 may be directly patterned to form the assembly 278.

[0103] FIG. 48A is a cross-sectional view of an assembly 280 subsequent to patterning the hardmask 201 in accordance with the pattern of the hardmask 207 and the fill material 219 of the assembly 278 (FIGS. 47A-B). FIG. 48B is a top view of the assembly 280; the cross-sectional view of FIG. 48A is taken along the section A-A of FIG. 48B. The resulting patterned hardmask 201 may include openings 225 corresponding to the openings 223, and thus the openings 225 may have two opposing sides that are substantially flat or linear (corresponding to the border between the hardmask 207 and the fill material 219) and two opposing sides that are curved or semicircular (corresponding to the edges of the holes 221 that entirely overlap the fill material 219). As illustrated in FIGS. 48A-B, the openings 225 may expose portions of the surface of the material 1219 in the assembly 280, while the remainder of the material 1219 may be covered by the hardmask 201, the hardmask 207, and/or the fill material 219.

[0104] FIG. 49A is a cross-sectional view of an assembly 282 subsequent to patterning the material 1219 in accordance with the pattern of the hardmask 201 of the assembly 280 (FIGS. 48A-B) so as to etch away the portions of the material 1219 that are not covered by the hardmask 201. FIG. 49B is a top view of the assembly 282; the cross-sectional view of FIG. 49A is taken along the section A-A of FIG. 49B. The resulting patterned material 1219 may include openings 1223 corresponding to the openings 225, and thus the openings 1223 may have two opposing sides that are substantially flat or linear (corresponding to the border between the hardmask 207 and the fill material 219) and two opposing sides that are curved or semicircular (corresponding to the edges of the holes 221 that entirely overlap the fill material 219). The material 1221 may be exposed through the openings 1223.

[0105] FIG. 50A is a cross-sectional view of an assembly 284 subsequent to removing the hardmasks 201 and 207, as well as the fill material 219, of the assembly 282 (FIGS. 49A-B). FIG. 50B is a top view of the assembly 284; the cross-sectional view of FIG. 50A is taken along the section A-A of FIG. 50B. In the assembly 284, the material 1219 may have a grid or cross-grating shape around the openings 1223, and the material 1221 may be exposed through these openings. As noted above, although only four openings 1223 arranged in a 2x2 array are illustrated in FIG. 50B, any array of openings 1223 of any desired number and size may be formed using the techniques disclosed herein.

[0106] In some embodiments, the technique discussed above with reference to FIGS. 41A-50B may be performed without the use of the hardmask 201; instead, the material 1219 may be directly patterned when the hardmask 207 and fill material 219 have been patterned. However, as noted above with reference to FIGS. 33A-B, including the intervening hardmask 201 may improve the tailoring of etch selectivity and reduce potential damage to the material 1219.

[0107] In some embodiments, alternative patterning techniques may be used, resulting in openings 1223 that have a different shape from what would be achievable using the technique of FIGS. 26-33B and 34A-40B. FIGS. 41A-50B illustrate an example of such an alternative technique that may be used instead of the patterning techniques of FIGS. 26-33B or 34A-40B.

[0108] As noted above, FIGS. 51A-57B illustrate alternative patterning techniques that may be used instead of the patterning techniques illustrated in FIGS. 26-33B, FIGS. 34A-40B, or FIGS. 41A-50B. The "photobucket" techniques described with reference to FIGS. 51A-57B (which utilize spacer- based pitch-quartering or pitch-halving, as discussed below with reference to FIGS. 58-70) may enable greater control and smaller pitch than achievable using conventional lithography.

[0109] FIG. 51A is a cross-sectional view of an assembly 2214 subsequent to providing a hardmask 2203 on the hardmask 201 of the assembly 212 (FIG. 26). FIG. 51B is a top view of the assembly 2214; the cross-sectional view of FIG. 51A is taken along the section A-A of FIG. 51B. The hardmask 2203 may take the form of any of the hardmasks disclosed herein, for example.

[0110] FIG. 52A is a cross-sectional view of an assembly 2216 subsequent to patterning the hardmask 2203 to form trenches 2277 in the hardmask 2203 of the assembly 2214 (FIGS. 51A-B) using a pitch-quartering or pitch-halving technique, as discussed below with reference to FIGS. 58- 70. FIG. 52B is a top view of the assembly 2216; the cross-sectional view of FIG. 52A is taken along the section A-A of FIG. 52B. In particular, the view of FIG. 52A is taken along a trench 2277. The trenches 2277 may be parallel, and may have any suitable dimensions in accordance with the spacer-based patterning technique applied. Only two trenches 2277 are illustrated in FIG. 52B for economy of illustration, but any suitable number of trenches 2277 may be formed.

[0111] FIG. 53A is a cross-sectional view of an assembly 2218 subsequent to filling the trenches 2277 of the assembly 2216 (FIGS. 52A-B) with a resist material 2204. FIG. 53B is a top view of the assembly 2218; the cross-sectional view of FIG. 53A is taken along the section A-A of FIG. 53B. The resist material 2204 may be, for example, a photoresist. The resist material 2204 may be provided in the trenches 2277 using any suitable technique.

[0112] FIG. 54A is a cross-sectional view of an assembly 2220 subsequent to providing another hardmask 2207 on the assembly 2218 (FIGS. 53A-B). FIG. 54B is a top view of the assembly 2220; the cross-sectional view of FIG. 54A is taken along the section A-A of FIG. 54B. The hardmask 2207 may take the form of any of the hardmasks disclosed herein, for example.

[0113] FIG. 55A is a cross-sectional view of an assembly 2222 subsequent to patterning the hardmask 2207 to form trenches 2209 in the hardmask 2207 of the assembly 2220 (FIGS. 54A-B), and filling the trenches 2209 with resist material 2219. FIG. 55B is a top view of the assembly 2222; the cross-sectional view of FIG. 55A is taken along the section A-A of FIG. 55B. The hardmask 2207 may be patterned in accordance with any of the embodiments discussed above with reference to the patterning of the hardmask 2203 (e.g., using a pitch-quartering or pitch-halving technique), and the resist material 2219 may be provided in accordance with any of the embodiments discussed above with reference to the provision of the resist material 2204. The trenches 2209 in the hardmask 2207 may be oriented differently than the trenches 2277 in the assembly 2218 (FIGS. 53A- B); for example, as illustrated in FIGS. 55A-B, the trenches 2209 may be perpendicular to, and overlap with, the trenches 2277. The resist material 2204 in the trenches 2277 are shown with dashed lines in FIG. 55B to illustrate the areas of overlap with the resist material 2219 in the trenches 2209. Only two trenches 2209 are illustrated in FIGS. 55A-B for economy of illustration, but any suitable number of trenches 2209 may be formed.

[0114] FIG. 56A is a cross-sectional view of an assembly 2224 subsequent to exposing at least some of the areas of overlap between the resist material 2219 and the resist material 2204 of the assembly 2222 (FIGS. 55A-B), and then developing the exposed resist material 2219 and resist material 2204 to "uncover" areas of the hardmask 201 that are not covered by the undeveloped resist material 2204, the undeveloped resist material 2219, or either of the hardmasks 2203 and 2207. FIG. 56B is a top view of the assembly 2224; the cross-sectional view of FIG. 56A is taken along the section A-A of FIG. 56B. In the embodiment illustrated in FIGS. 56A-B, all four areas of overlap between the resist material 2204 and the resist material 2219 are shown as developed, uncovering four rectangular areas of the hardmask 201. In other embodiments, fewer than all of the areas of overlap between the resist material 2204 and the resist material 2219 may be developed, in any desired pattern.

[0115] FIG. 57A is a cross-sectional view of an assembly 2226 subsequent to patterning the hardmask 201 of the assembly 2224 (FIGS. 56A-B) to etch away portions of the hardmask 201 that are not covered by the undeveloped resist material 2204, the undeveloped resist material 2219, or either of the hardmasks 2203 and 2207. FIG. 57B is a top view of the assembly 2226; the cross- sectional view of FIG. 57A is taken along the section A-A of FIG. 57B. The resulting patterned hardmask 201 may include openings 2211 that have rectangular footprints (corresponding to the areas where the trenches 2209 and the trenches 2277 "overlapped"). The patterned hardmask 201 may be used to analogously pattern the material 1219 with openings 1223, as discussed above with reference to several of the preceding embodiments, and further processing may be performed as disclosed herein.

[0116] As noted above, in some embodiments, spacer-based pitch-halving or pitch-quartering techniques may be used to pattern a material, instead of or in addition to photolithographic techniques. In particular, any suitable ones of the materials described herein may be patterned using pitch-halving or pitch-quartering techniques. FIGS. 58-70 illustrate a technique for patterning a material 1219 (which may be a hardmask, or a layer of resist material, for example) using pitch- quartering. Such pitch-quartering techniques may be used to pattern any suitable material discussed herein. For example, pitch-quartering techniques may be used to pattern the hardmask 201 of the assembly 212 of FIG. 26 to form the assembly 216 of FIGS. 28A-B (instead of using the photoresist patterning technique illustrated in FIGS. 27A-B). In another example, pitch-quartering techniques may be used to pattern the hardmask 207 of the assembly 220 of FIGS. 30A-B to form the assembly 224 of FIGS. 32A-B (instead of using the photoresist patterning technique illustrated in FIGS. 31A-B). In another example, pitch-quartering techniques may be used to pattern the resist material 1203 of the assembly 1214 (FIGS. 34A-B) to form the assembly 1218 of FIGS. 36A-B. In another example, pitch-quartering techniques may be used to pattern the resist material 1207 of the assembly 1220 (FIGS. 37A-B) to form the assembly 1222 of FIGS. 38A-B.

[0117] FIG. 58 is a cross-sectional view of an assembly 285 subsequent to providing a hardmask 188 and an antireflective coating 186 on the material 1219. The material used for the hardmask 188 may be selected so that the hardmask 188 may be etched without etching the material 1219; any suitable material may be used. The antireflective coating 186 may mitigate optical interference effects during lithography and may be a sacrificial light absorbing material (SLAM), for example. [0118] FIG. 59 is a cross-sectional view of an assembly 286 subsequent to providing a resist material 190 on the antireflective coating 186 of the assembly 285 (FIG. 58). In some embodiments, the resist material 190 may be a photoresist.

[0119] FIG. 60 is a cross-sectional view of an assembly 287 subsequent to etching the resist material 190 to pattern the resist material 190 of the assembly 286 (FIG. 59). The pattern formed in the resist material 190 may be selected based on the final desired patterning of the material 1219, as illustrated in FIGS. 62-70 and discussed below.

[0120] FIG. 61 is a cross-sectional view of an assembly 288 subsequent to providing a template material 192 on the patterned resist material 190 (and the exposed antireflective coating 186) of the assembly 287 (FIG. 60). The template material 192 may be conformal on the patterned resist material 190, and the thickness of the template material 192 may be selected based on the final desired patterning of the material 1219, as illustrated in FIGS. 62-70 and discussed below. The template material 192 may be formed of any suitable material, and may be provided using any suitable technique. For example, the template material 192 may be a nitride material (e.g., silicon nitride), an oxide material, or polysilicon, and may be deposited by ALD.

[0121] FIG. 62 is a cross-sectional view of an assembly 289 subsequent to etching the template material 192 of the assembly 288 (FIG. 61) to pattern the template material 192. The template material 192 may be anisotropically etched, etching the template material 192 "downward" to remove the template material 192 on top of the patterned resist material 190 and in some of the area between the patterned resist material 190, leaving the patterned template material 192 on the sides of the patterned resist material 190. In some embodiments, the anisotropic etch may be a dry etch. The thickness of the template material 192 when provided (as illustrated in FIG. 61), and the dimensions of the patterned resist material 190, may dictate the dimensions of the patterned template material 192.

[0122] FIG. 63 is a cross-sectional view of an assembly 290 subsequent to removing the patterned resist material 190 of the assembly 289 (FIG. 62). In some embodiments, the patterned resist material 190 may be removed with a solvent, or with an oxygen plasma ash. The patterned template material 192 may remain in the assembly 290.

[0123] FIG. 64 is a cross-sectional view of an assembly 291 subsequent to etching the antireflective coating 186 and the hardmask 188 in accordance with the pattern provided by the patterned template material 192 of assembly 290 (FIG. 63). In particular, portions of the antireflective coating 186 and the hardmask 188 not covered by the patterned template material 192 may be etched away, and the etch may stop upon reaching the material 1219. This etching may result in a patterned antireflective coating 186 and a patterned hardmask 188, having dimensions that depend on the dimensions of the patterned template material 192, as discussed. In some embodiments, the antireflective coating 186 and the hardmask 188 may be removed with a solvent, or with an oxygen plasma ash.

[0124] FIG. 65 is a cross-sectional view of an assembly 292 subsequent to removing the patterned template material 192 and the antireflective coating 186 of the assembly 291 (FIG. 64). The patterned hardmask 188 may remain in the assembly 292. In some embodiments, the patterned template material 192 and the antireflective coating 186 may be removed with a solvent, or with an oxygen plasma ash.

[0125] FIG. 66 is a cross-sectional view of an assembly 293 subsequent to providing a template material 194 on the patterned hardmask 188 of the assembly 292 (FIG. 65). In some embodiments, the template material 194 (and its provision) may take the form of any of the embodiments of the template material 192 discussed above. In some embodiments, the template material 194 may have the same material composition as the template material 192; in other embodiments, the template material 194 may have a different material composition from the template material 192.

[0126] FIG. 67 is a cross-sectional view of an assembly 294 subsequent to etching the template material 194 of the assembly 293 (FIG. 66) to pattern the template material 194. The patterned template material 194 may be disposed on the sides of the patterned hardmask 188, analogously to the etching of the template material 192 discussed above with reference to FIG. 62. In particular, the template material 194 may be etched in accordance with any of the techniques for etching the template material 192 discussed above. The thickness of the template material 194 when provided (as illustrated in FIG. 66), and the dimensions of the patterned hardmask 188, may dictate the dimensions of the patterned template material 194.

[0127] FIG. 68 is a cross-sectional view of an assembly 295 subsequent to removing the patterned hardmask 188 of the assembly 294 (FIG. 67). The patterned template material 194 may remain in the assembly 295. In some embodiments, the patterned hardmask 188 may be removed with a solvent, or with an oxygen plasma ash.

[0128] FIG. 69 is a cross-sectional view of an assembly 296 subsequent to etching the material 1219 in accordance with the pattern provided by the patterned template material 194 of the assembly 295 (FIG. 68). In particular, portions of the material 1219 not covered by the patterned template material 194 may be etched away. The etch may stop upon reaching an underlying material (not shown). This etching may result in a patterned material 1219, having dimensions that depend on the dimensions of the patterned template material 194.

[0129] FIG. 70 is a cross-sectional view of an assembly 297 subsequent to removing the patterned template material 194 of the assembly 296 (FIG. 69). The patterned material 1219 may remain in the assembly 297, and the template material 194 may be removed in accordance with any of the embodiments discussed above with reference to the removal of the template material 192. The patterned material 1219 may be further processed in accordance with any of the embodiments disclosed herein.

[0130] In the assembly 297, the distances between adjacent ones of the portions of the material 1219 may vary along an array of the gates 108. For example, the distance 231 may be equal to the distance 191 between adjacent portions of the patterned resist material 190 of the assembly 287 (FIG. 60) minus twice the thickness 193 of the patterned template material 192 of the assembly 289 (FIG. 62) minus twice the thickness 195 of the patterned template material 194 of the assembly 294 (FIG. 67), as illustrated. The distance 233 may be equal to the thickness 193 of the patterned template material 192 of the assembly 289 (FIG. 62), as illustrated. The distance 235 may be equal to the length 197 of a portion of the patterned template material 190 of the assembly 287 (FIG. 60) minus twice the thickness 195 of the patterned template material 194 of the assembly 294 (FIG. 67), as illustrated. When the material 1219 is the insulating material 110 (or a material used to pattern the insulating material 110), the dimension of the corresponding gates 108 may vary like the distances in the assembly 297. Similarly, when the material 1219 is a template material on the quantum well stack 146, the dimension of the quantum dot pillars 104 may vary like the distances in the assembly 297.

[0131] Suitable values of the distance 231, the distance 233, and the distance 235 may be achieved by appropriate selection of the distance 191, length 197, and thicknesses 193 and 195. As illustrated in FIG. 70, if the patterned resist material 190 has a regular pattern, and the gates 108 are partially formed by "filling in" between the portions of the patterned insulating material 110 (e.g., as discussed above with reference to FIGS. 3-10), the lengths of adjacent ones of the gates 108 in the assembly 297 (i.e., the x-lengths 170 illustrated in FIGS. 1 and 2) will also follow a regular pattern: distance 233-distance 235-distance 233-distance 231-distance 233-distance 235-distance 233- distance 235-distance 233-distance 231, etc. A similar pattern in the dimensions of the quantum dot pillars 104 may be followed if the pitch quartering techniques disclosed herein are used to pattern the quantum well stack 146.

[0132] References made herein to "pitch-quartering techniques" and "pitch-quartering" also include the use of pitch-halving techniques. In a pitch-halving approach, the hardmask 188 (and optionally the antireflective coating 186) may not be used; instead, the resist material 190 may be applied on the material 1219 as discussed above with reference to FIG. 59, the resist material 190 may be patterned as discussed above with reference to FIG. 60, a template material 192 may be provided as discussed above with reference to FIG. 61, the template material 192 may be etched as discussed above with reference to FIG. 62, the resist material 190 may be removed as discussed above with reference to FIG. 63, and then the material 1219 may be etched as discussed above with reference to FIG. 69 but in accordance with the pattern of the template material 192 (instead of the patterned template material 194). Any of the embodiments discussed herein may be patterned according to such a pitch-halving approach. In some embodiments, using pitch-halving techniques may enable features (e.g., trenches) to be patterned into the material 1219 with a pitch between 40 and 200 nanometers (e.g., between 50 and 70 nanometers) and a width between 15 and 100 nanometers (e.g., between 20 and 35 nanometers). In some embodiments, using pitch-quartering techniques may enable features (e.g., trenches) to be patterned into the material 1219 with a pitch between 15 and 100 nanometers (e.g., between 25 and 35 nanometers) and a width between 5 and 50 nanometers (e.g., between 10 and 18 nanometers).

[0133] FIGS. 71-75 illustrate various examples of quantum well stacks 146 that may provide the quantum well stacks 146 of any of the embodiments of the quantum dot devices 100 disclosed herein. In some embodiments, the layers of the quantum well stacks 146 may be grown on a substrate (e.g., a silicon or germanium wafer) (and on each other) by epitaxy. Although the quantum well stacks 146 illustrated in FIGS. 71-75 each include two quantum well layers 152 (e.g., as appropriate for a double-sided device, as discussed above), in some embodiments, the quantum well stack 146 included in a quantum dot device 100 may include one quantum well layer 152 or more than two quantum well layers 152; elements may be omitted from the quantum well stacks 146, or added to the quantum well stacks 146 to achieve such embodiments, as appropriate. Layers other than the quantum well layer(s) 152 in a quantum well stack 146 may have higher threshold voltages for conduction than the quantum well layer(s) 152 so that when the quantum well layer(s) 152 are biased at their threshold voltages, the quantum well layer(s) 152 conduct and the other layers of the quantum well stack 146 do not. This may avoid parallel conduction in both the quantum well layer(s) 152 and the other layers, and thus avoid compromising the strong mobility of the quantum well layer(s) 152 with conduction in layers having inferior mobility.

[0134] FIG. 71 is a cross-sectional view of a quantum well stack 146 including only a quantum well layer 152-1, a barrier layer 154, and a quantum well layer 152-2. In some embodiments, the quantum well layers 152 of FIG. 71 may be formed of intrinsic silicon, and the gate dielectrics 114 (not shown in FIG. 71, but as discussed above with reference to FIG. 1) may be formed of silicon oxide; in such an arrangement, during use of the quantum dot device 100, a 2DEG may form in the intrinsic silicon at the interface between the intrinsic silicon and the proximate silicon oxide.

Embodiments in which the quantum well layers 152 of FIG. 71 are formed of intrinsic silicon may be particularly advantageous for electron-type quantum dot devices 100. In some embodiments, the quantum well layers 152 of FIG. 71 may be formed of intrinsic germanium, and the gate dielectrics 114 may be formed of germanium oxide; in such an arrangement, during use of the quantum dot device 100, a 2DEG may form in the intrinsic germanium at the interface between the intrinsic germanium and the proximate germanium oxide. Such embodiments may be particularly advantageous for hole-type quantum dot devices 100. In some embodiments, the quantum well layers 152 may be strained, while in other embodiments, the quantum well layers 152 may not be strained.

[0135] The barrier layer 154 of FIG. 71 may provide a potential barrier between the quantum well layer 152-1 and the quantum well layer 152-2. In some embodiments in which the quantum well layers 152 of FIG. 71 are formed of silicon, the barrier layer 154 may be formed of silicon germanium. The germanium content of this silicon germanium may be 20-80% (e.g., 30%). In some embodiments in which the quantum well layers 152 are formed of germanium, the barrier layer 154 may be formed of silicon germanium (with a germanium content of 20-80% (e.g., 70%)).

[0136] The thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 71 may take any suitable values. For example, in some embodiments, the thickness of the barrier layer 154 (e.g., silicon germanium) may be between 0 and 400 nanometers. In some embodiments, the thickness of the quantum well layers 152 (e.g., silicon or germanium) may be between 5 and 30 nanometers.

[0137] FIG. 72 is a cross-sectional view of a quantum well stack 146 including quantum well layers 152-1 and 152-2, a barrier layer 154-2 disposed between the quantum well layers 152-1 and 152-2, and additional barrier layers 154-1 and 154-3. In the quantum dot device 100, the barrier layer 154- 1 may be disposed between the quantum well layer 152-1 and the gate dielectric 114-1 (not shown in FIG. 71, but as discussed above with reference to FIG. 1). The barrier layer 154-3 may be disposed between the quantum well layer 152-2 and the gate dielectric 114-2 (not shown in FIG. 71, but as discussed above with reference to FIG. 1). In some embodiments, the barrier layer 154-3 may be formed of a material (e.g., silicon germanium), and when the quantum well stack 146 is being grown on the substrate 144, the barrier layer 154-3 may include a buffer region of that material. This buffer region may trap defects that form in this material as it is grown on the substrate 144, and in some embodiments, the buffer region may be grown under different conditions (e.g., deposition temperature or growth rate) from the rest of the barrier layer 154-3. In particular, the rest of the barrier layer 154-3 may be grown under conditions that achieve fewer defects than the buffer region. In some embodiments, the buffer region may be lattice mismatched with the quantum well layer(s) 152 in a quantum well stack 146, imparting biaxial strain to the quantum well layer(s) 152. [0138] The barrier layers 154-1 and 154-3 may provide potential energy barriers around the quantum well layers 152-1 and 152-2, respectively, and the barrier layer 154-1 may take the form of any of the embodiments of the barrier layer 154-3 discussed herein. In some embodiments, the barrier layer 154-1 may have a similar form as the barrier layer 154-3, but may not include a "buffer region" as discussed above; in the quantum dot device 100, the barrier layer 154-3 and the barrier layer 154-1 may have substantially the same structure. The barrier layer 154-2 may take the form of any of the embodiments of the barrier layer 154 discussed above with reference to FIG. 71. The thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 72 may take any suitable values. For example, in some embodiments, the thickness of the barrier layers 154-1 and 154-3 (e.g., silicon germanium) in the quantum dot device 100 may be between 0 and 400 nanometers. In some embodiments, the thickness of the quantum well layers 152 (e.g., silicon or germanium) may be between 5 and 30 nanometers (e.g., 10 nanometers). In some embodiments, the thickness of the barrier layer 154-2 (e.g., silicon germanium) may be between 25 and 75 nanometers (e.g., 32 nanometers).

[0139] FIGS. 73-75 illustrate examples of quantum well stacks 146 including doped layer(s) 137. Doped layer(s) 137 may be included in a quantum well stack 146 instead of or in addition to doped regions 140.

[0140] FIG. 73 is a cross-sectional view of a quantum well stack 146 including a buffer layer 176, a barrier layer 155-2, a quantum well layer 152-2, a barrier layer 154-2, a doped layer 137, a barrier layer 154-1, a quantum well layer 152-1, and a barrier layer 155-1.

[0141] The buffer layer 176 may be formed of the same material as the barrier layer 155-2, and may be present to trap defects that form in this material as it is grown. In some embodiments, the buffer layer 176 may be grown under different conditions (e.g., deposition temperature or growth rate) from the barrier layer 155-2. In particular, the barrier layer 155-2 may be grown under conditions that achieve fewer defects than the buffer layer 176. In some embodiments in which the buffer layer 176 includes silicon germanium, the silicon germanium of the buffer layer 176 may have a germanium content that varies to the barrier layer 155-2; for example, the silicon germanium of the buffer layer 176 may have a germanium content that varies from zero percent to a nonzero percent (e.g., 30%) at the barrier layer 155-2. The buffer layer 176 may be grown beyond its critical layer thickness such that it is substantially free of stress from the underlying base (and thus may be referred to as "relaxed"). In some embodiments, the thickness of the buffer layer 176 (e.g., silicon germanium) may be between 0.3 and 4 microns (e.g., 0.3-2 microns, or 0.5 microns). In some embodiments, the buffer layer 176 may be lattice mismatched with the quantum well layer(s) 152 in a quantum well stack 146, imparting biaxial strain to the quantum well layer(s) 152. [0142] The barrier layer 155-2 may provide a potential energy barrier proximate to the quantum well layer 152-2. The barrier layer 155-2 may be formed of any suitable materials. For example, in some embodiments in which the quantum well layer 152 is formed of silicon or germanium, the barrier layer 155-2 may be formed of silicon germanium. In some embodiments, the thickness of the barrier layer 155-2 may be between 0 and 400 nanometers (e.g., between 25 and 75 nanometers).

[0143] The quantum well layer 152-2 may be formed of a different material than the barrier layer 155-2. Generally, a quantum well layer 152 may be formed of a material such that, during operation of the quantum dot device 100, a 2DEG may form in the quantum well layer 152. Embodiments in which the quantum well layer 152 is formed of intrinsic silicon may be particularly advantageous for electron-type quantum dot devices 100. Embodiments in which a quantum well layer 152 is formed of intrinsic germanium may be particularly advantageous for hole-type quantum dot devices 100. In some embodiments, a quantum well layer 152 may be strained, while in other embodiments, a quantum well layer 152 may not be strained. The thickness of a quantum well layer 152 may take any suitable values; in some embodiments, a quantum well layer 152 may have a thickness between 5 and 30 nanometers.

[0144] In the quantum well stack 146 of FIG. 73, the doped layer 137 may be "shared" by the two quantum well layers 152 in the quantum well stack 146, in that the doped layer 137 provides carriers to the quantum well layer 152-1 and the quantum well layer 152-2 during use. In the quantum dot device 100, the quantum well layer 152-1 may be disposed between the doped layer 137 and the gate dielectric 114-1, while the quantum well layer 152-2 may be disposed between the doped layer 137 and the gate dielectric 114-2. The doped layer 137 of FIG. 73 may be doped with an n-type material (e.g., for an electron-type quantum dot device 100) or a p-type material (e.g., for a hole- type quantum dot device 100). In some embodiments, the doping concentration of the doped layer 137 may be between 10¹⁷/cm³ and 10²⁰/cm³ (e.g., between 10¹⁷/cm³ and 10¹⁸/cm³). The thickness (i.e., z-height) of the doped layer 137 may depend on the doping concentration, among other factors, and in some embodiments, may be between 5 and 50 nanometers (e.g., between 20 and 30 nanometers).

[0145] A doped layer 137 may be formed using any of a number of techniques. In some embodiments, a doped layer 137 may be formed of an undoped base material (e.g., silicon germanium) that is doped in situ during growth of the base material by epitaxy. In some embodiments, a doped layer 137 may initially be fully formed of an undoped base material (e.g., silicon germanium), then a layer of dopant may be deposited on this base material (e.g., a monolayer of the desired dopant), and an annealing process may be performed to drive the dopant into the base material. In some embodiments, a doped layer 137 may initially be fully formed of an undoped base material (e.g., silicon germanium), and the dopant may be implanted into the lattice (and, in some embodiments, may be subsequently annealed). In some embodiments, a doped layer 137 may be provided by a silicon germanium layer (e.g., with 90% germanium content) doped with an n-type dopant. In general, any suitable technique may be used to form a doped layer 137.

[0146] The barrier layer 154-2 may not be doped, and thus may provide a barrier to prevent impurities in the doped layer 137 from diffusing into the quantum well layer 152-2 and forming recombination sites or other defects that may reduce channel conduction and thereby impede performance of the quantum dot device 100. In some embodiments of the quantum well stack 146 of FIG. 73, the doped layer 137 may include a same material as the barrier layer 154-2, but the barrier layer 154-2 may not be doped. For example, in some embodiments, the doped layer 137 and the barrier layer 154-2 may both be silicon germanium. In some embodiments in which the quantum well layer 152-2 is formed of silicon, the barrier layer 154-2 may be formed of silicon germanium. The germanium content of this silicon germanium may be 20-80% (e.g., 30%). In some embodiments in which the quantum well layer 152-2 is formed of germanium, the barrier layer 154- 2 may be formed of silicon germanium (with a germanium content of 20-80% (e.g., 70%)). The thickness of the barrier layer 154-2 may depend on the doping concentration of the doped layer 137, among other factors discussed below, and in some embodiments, may be between 5 and 50 nanometers (e.g., between 20 and 30 nanometers).

[0147] The barrier layer 154-1 may provide a barrier to prevent impurities in the doped layer 137 from diffusing into the quantum well layer 152-1, and may take any of the forms described herein for the barrier layer 154-2. Similarly, the quantum well layer 152-1 may take any of the forms described herein for the quantum well layer 152-2. The barrier layer 155-1 may provide a potential energy barrier proximate to the quantum well layer 152-1 (as discussed above with reference to the barrier layer 155-2 and the quantum well layer 152-2), and may take any of the forms described herein for the barrier layer 155-2.

[0148] The thickness of a barrier layer 154 may impact the ease with which carriers in the doped layer 137 can move into a quantum well layer 152 disposed on the other side of the barrier layer 154. The thicker the barrier layer 154, the more difficult it may be for carriers to move into the quantum well layer 152; at the same time, the thicker the barrier layer 154, the more effective it may be at preventing impurities from the doped layer 137 from moving into the quantum well layer 152. Additionally, the diffusion of impurities may depend on the temperature at which the quantum dot device 100 operates. Thus, the thickness of the barrier layer 154 may be adjusted to achieve a desired energy barrier and impurity screening effect between the doped layer 137 and the quantum well layer 152 during expected operating conditions. [0149] In some embodiments of the quantum well stack 146 of FIG. 73 (e.g., those included in "single-sided" quantum dot devices 100), only a single quantum well layer 152 may be included. For example, the quantum well stack 146 may include (from top to bottom in the frame of reference of the figure), layers 155-1, 137, 154-2, 152-2, 155-2, and 176; in such an embodiment, gates may be formed proximate to the barrier layer 155-1 such that the doped layer 137 is disposed between the gates and the quantum well layer 152-2. In another example, the quantum well stack 146 may include (from top to bottom in the frame of reference of the figure), layers 155-1, 152-1, 154-1, 137, and 176; in such an embodiment, gates may be formed proximate to the barrier layer 155-1 such that the quantum well layer 152-1 is disposed between the gates and the doped layer 137. In some embodiments, the buffer layer 176 and/or the barrier layer 155-2 may be omitted from the quantum well stack 146 of FIG. 73.

[0150] FIG. 74 is a cross-sectional view of a quantum well stack 146 that is similar to the quantum well stack 146 of FIG. 73, except that in the place of the single doped layer 137 shared by two quantum well layers 152, the quantum well stack 146 of FIG. 74 includes two different doped layers 137-2 and 137-1 (spaced apart by a barrier layer 155-3). In such an embodiment, the doped layer 137-2 may provide a source of carriers for the quantum well layer 152-2, and the doped layer 137-1 may provide a source of carriers for the quantum well layer 152-1. The barrier layer 155-3 may provide a potential barrier between the two doped layers 137, and may take any suitable form. Generally, the elements of the quantum well stack 146 of FIG. 74 may take the form of any of the corresponding elements of the quantum well stack 146 of FIG. 73. The doped layers 137-1 and 137- 2 may have the same geometry and material composition, or may have different geometries and/or material compositions.

[0151] FIG. 75 is a cross-sectional view of a quantum well stack 146 in which two doped layers 137- 1 and 137-2 are disposed toward the "outside" of the quantum well stack 146, rather than the "inside" of the quantum well stack 146, as illustrated in FIGS. 73 and 74. In particular, the quantum well layer 152-2 is disposed between the doped layer 137-2 and the quantum well layer 152-1, and the quantum well layer 152-1 is disposed between the doped layer 137-1 and the quantum well layer 152-2. In the quantum dot device 100, the doped layer 137-1 may be disposed between the quantum well layer 152-1 and the gate dielectric 114-1 (not shown in FIG. 75, but discussed above with reference to FIG. 1), while the doped layer 137-2 may be disposed between the quantum well layer 152-2 and the gate dielectric 114-2 (not shown in FIG. 75, but discussed above with reference to FIG. 1). In the quantum well stack 146 of FIG. 75, a barrier layer 155-3 provides a potential barrier directly between the quantum well layers 152-1 and 152-2 (rather than directly between the doped layers 137-1 and 137-2, as illustrated in the quantum well stack 146 of FIG. 74). Generally, the elements of the quantum well stack 146 of FIG. 75 may take the form of any of the corresponding elements of the quantum well stack 146 of FIGS. 71-75.

[0152] In some particular embodiments in which the quantum dot device 100 is a "single-sided" device with only one set of gates, the quantum well stack 146 may include a silicon base, a buffer layer 176 of silicon germanium (e.g., with 30% germanium content), then a doped layer 137 formed of silicon germanium doped with an n-type dopant, a thin barrier layer 154 formed of silicon germanium (e.g., silicon germanium with 70% germanium content), a silicon quantum well layer 152, and a barrier layer 155 formed of silicon germanium (e.g., with 30% germanium content); in such an embodiment, the gates may be disposed on the barrier layer 155. In some other particular embodiments in which the quantum dot device 100 is a "single-sided" device with only one set of gates, the quantum well stack 146 may include a silicon base, a doped layer 137 formed of silicon doped with an n-type dopant, a thin barrier layer 154 formed of silicon germanium, and a silicon quantum well layer 152; in such an embodiment, the gates may be disposed on the silicon quantum well layer 152.

[0153] Although the quantum dot pillars 104 have been illustrated in many of the preceding figures as substantially rectangular with parallel side walls (e.g., as illustrated in FIGS. 1B-C), this is simply for ease of illustration, and the quantum dot pillars 104 may have any suitable shape (e.g., a shape appropriate to the manufacturing processes used to shape the quantum dot pillars 104 from the quantum well stacks 146). For example, in some embodiments, the quantum dot pillars 104 may be tapered, narrowing as they extend away from the base 102 (FIG. 4). In some embodiments, the quantum dot pillars 104 may taper by 3-10 nanometers in x-width for every 100 nanometers in z- height (e.g., 5 nanometers in x-width for every 100 nanometers in z-height).

[0154] Any of the quantum dot devices 100 disclosed herein may include one or more magnet lines. As used herein, a "magnet line" refers to a magnetic-field-generating structure to influence (e.g., change, reset, scramble, or set) the spin states of quantum dots. One example of a magnet line, as discussed herein, is a conductive pathway that is proximate to an area of quantum dot formation and selectively conductive of a current pulse that generates a magnetic field to influence a spin state of a quantum dot in the area.

[0155] For example, FIGS. 76A and 76B are side and top views, respectively, of a quantum dot device 100 including multiple magnet lines 121. In particular, FIG. 76B illustrates the quantum dot device 100 taken along the section C-C of FIG. 76A (while FIG. 76A illustrates the quantum dot device 100 taken along the section D-D of FIG. 76B). A magnet line 121-1 is disposed proximate to the quantum well layer 152-1 (not shown), and a magnet line 121-2 is disposed proximate to the quantum well layer 152-2 (not shown). [0156] A magnet line 121 may be formed of a conductive material, and may be used to conduct current pulses that generate magnetic fields to influence the spin states of one or more of the quantum dots that may form in the quantum dot device 100. In some embodiments, a magnet line 121 may conduct a pulse to reset (or "scramble") nuclear and/or quantum dot spins. In some embodiments, a magnet line 121 may conduct a pulse to initialize an electron in a quantum dot in a particular spin state. In some embodiments, a magnet line 121 may conduct current to provide a continuous, oscillating magnet field to which the spin of a qubit may couple. A magnet line 121 may provide any suitable combination of these embodiments, or any other appropriate functionality.

[0157] In some embodiments, a magnet line 121 may be formed of copper. In some embodiments, a magnet line 121 may be formed of a superconductor, such as aluminum. In some embodiments, a magnet line 121 may be spaced apart from proximate gates 108 by a distance 175. The distance 175 may take any suitable value (e.g., based on the desired strength of magnetic field interaction with the quantum dots); in some embodiments, the distance 175 may be between 25 nanometers and 1 micron (e.g., between 50 nanometers and 200 nanometers). In embodiments in which a quantum dot device 100 includes multiple magnet lines 121, the distances 175 between the multiple magnet lines 121 and proximate gates 108 may be the same or different.

[0158] In some embodiments, a magnet line 121 may be formed of a magnetic material. For example, a magnetic material (such as cobalt) may be deposited in a trench in the insulating material

130 to provide a permanent magnetic field in the quantum dot device 100.

[0159] A magnet line 121 may have any suitable dimensions. For example, the magnet line 121 may have a thickness 169 between 25 and 100 nanometers. A magnet line 121 may have a width 177 between 25 and 100 nanometers. In some embodiments, the width 177 and thickness 169 of a magnet line 121 may be equal to the width and thickness, respectively, of other conductive lines in the quantum dot device 100 used to provide electrical interconnects (e.g., the conductive lines 393 and 396, discussed below with reference to FIGS. 77 and 78), as known in the art, and may be formed using any processes known for forming conductive lines (e.g., plating in a trench, followed by planarization, or a semi-additive process). A magnet line 121 may have a length 173 that may depend on the number and dimensions of the gates 108 that are to form quantum dots with which the magnet line 121 is to interact. The magnet lines 121 illustrated in FIGS. 76A-B are substantially linear, but this need not be the case; magnet lines 121 may take any suitable shape. Conductive vias

131 may contact the magnet lines 121.

[0160] In some embodiments, a quantum dot device 100 may include one magnet line 121, or no magnet lines 121; in other embodiments, a quantum dot device 100 may include two, three, four, or more magnet lines 121. Magnet lines 121 included in a quantum dot device 100 may be oriented in any desired manner relative to the gates 108 or other structural features of the quantum dot device 100; for example, one or more magnet lines 121 may be oriented from left to right according to the perspective of FIG. 76B, in addition to or instead of one or more magnet lines 121 oriented up and down according to the perspective of FIG. 76B (as illustrated).

[0161] In some embodiments, the quantum dot device 100 may be included in a die and coupled to a package substrate to form a quantum dot device package. For example, FIG. 77 is a side cross- sectional view of a die 302 including the quantum dot device 100 of FIG. IB and conductive pathway layers 303 disposed thereon, while FIG. 78 is a side cross-sectional view of a quantum dot device package 300 in which the die 302 is coupled to a package substrate 304. Details of the quantum dot device 100 are omitted from FIG. 78 for economy of illustration. As noted above, the particular quantum dot device 100 illustrated in FIG. 78 may take the form of the quantum dot device 100 illustrated in FIG. IB, but any of the quantum dot devices 100 disclosed herein may be included in a die (e.g., the die 302) and coupled to a package substrate (e.g., the package substrate 304). In particular, any number of quantum dot pillars 104, gates 108, and other components discussed herein with reference to various embodiments of the quantum dot device 100 may be included in the die 302.

[0162] The die 302 may include a first face 320 and an opposing second face 322. The support 103 may be proximate to the second face 322, and conductive pathways 315 from various components of the quantum dot device 100 may extend to conductive contacts 365 disposed at the first face 320. The conductive pathways 315 may include conductive vias, conductive lines, and/or any combination of conductive vias and lines. For example, FIG. 77 illustrates an embodiment in which a conductive pathway 315-1 (extending between a gate 108-1 and associated conductive contact 365) includes a conductive via 122-1, a conductive line 123-1, a conductive via 125-1, a conductive line 393, a conductive via 398, and a conductive line 396. In the embodiment of FIG. 77, a conductive pathway 315-2 (extending between a gate 108-2 and an associated conductive contact 365) include a conductive via 122-2, a conductive line 393, a conductive via 398, and a conductive line 396. More or fewer structures may be included in the conductive pathways 315, and analogous conductive pathways 315 may be provided between ones of the conductive contacts 365 and the doped regions 140 (and any other components, such as magnet lines, included in the quantum dot device 100). In some embodiments, conductive lines of the die 302 (and the package substrate 304, discussed below) may extend into and out of the plane of the drawing, providing conductive pathways to route electrical signals to and/or from various elements in the die 302.

[0163] The conductive vias and/or lines that provide the conductive pathways 315 in the die 302 may be formed using any suitable techniques. Examples of such techniques may include subtractive fabrication techniques, additive or semi-additive fabrication techniques, single Damascene fabrication techniques, dual Damascene fabrication techniques, or any other suitable technique. In some embodiments, layers of oxide material 390 and layers of nitride material 391 may insulate various structures in the conductive pathways 315 from proximate structures, and/or may serve as etch stops during fabrication. In some embodiments, an adhesion layer (not shown) may be disposed between conductive material and proximate insulating material of the die 302 to improve mechanical adhesion between the conductive material and the insulating material.

[0164] The gates 108, the doped regions 140, and the quantum well stack 146 (as well as the proximate conductive vias/lines) may be referred to as part of the "device layer" of the quantum dot device 100. The conductive lines 393 may be referred to as a Metal 1 or "Ml" interconnect layer, and may couple the structures in the device layer to other interconnect structures. The conductive vias 398 and the conductive lines 396 may be referred to as a Metal 2 or "M2" interconnect layer, and may be formed directly on the Ml interconnect layer.

[0165] A solder resist material 367 may be disposed around the conductive contacts 365, and in some embodiments may extend onto the conductive contacts 365. The solder resist material 367 may be a polyimide or similar material, or may be any appropriate type of packaging solder resist material. In some embodiments, the solder resist material 367 may be a liquid or dry film material including photoimageable polymers. In some embodiments, the solder resist material 367 may be non-photoimageable (and openings therein may be formed using laser drilling or masked etch techniques). The conductive contacts 365 may provide the contacts to couple other components (e.g., a package substrate 304, as discussed below, or another component) to the conductive pathways 315 in the quantum dot device 100, and may be formed of any suitable conductive material (e.g., a superconducting material). For example, solder bonds may be formed on the one or more conductive contacts 365 to mechanically and/or electrically couple the die 302 with another component (e.g., a circuit board), as discussed below. The conductive contacts 365 illustrated in FIG. 77 take the form of bond pads, but other first level interconnect structures may be used (e.g., posts) to route electrical signals to/from the die 302, as discussed below.

[0166] The combination of the conductive pathways and the proximate insulating material (e.g., the insulating material 130, the oxide material 390, and the nitride material 391) in the die 302 may provide an interlayer dielectric (ILD) stack of the die 302. As noted above, interconnect structures may be arranged within the quantum dot device 100 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures depicted in FIG. 77 or any of the other accompanying figures, and may include more or fewer interconnect structures). During operation of the quantum dot device 100, electrical signals (such as power and/or input/output (I/O) signals) may be routed to and/or from the gates 108 and/or the doped regions 140 (and/or other components) of the quantum dot device 100 through the interconnects provided by conductive vias and/or lines, and through the conductive pathways of the package substrate 304 (discussed below).

[0167] Example superconducting materials that may be used for the structures in the conductive pathways 313 (discussed below) and 315, and/or conductive contacts of the die 302 and/or the package substrate 304, may include aluminum, niobium, tin, titanium, osmium, zinc, molybdenum, tantalum, vanadium, or composites of such materials (e.g., niobium-titanium, niobium-aluminum, or niobium-tin). In some embodiments, the conductive contacts 365, 379, and/or 399 may include aluminum, and the first level interconnects 306 and/or the second level interconnects 308 may include an indium-based solder.

[0168] In the quantum dot device package 300 (FIG. 78), first level interconnects 306 may be disposed between the first face 320 of the die 302 and the second face 326 of a package substrate 304. Having first level interconnects 306 disposed between the first face 320 of the die 302 and the second face 326 of the package substrate 304 (e.g., using solder bumps as part of flip chip packaging techniques) may enable the quantum dot device package 300 to achieve a smaller footprint and higher die-to-package-substrate connection density than could be achieved using conventional wirebond techniques (in which conductive contacts between the die 302 and the package substrate 304 are constrained to be located on the periphery of the die 302). For example, a die 302 having a square first face 320 with side length N may be able to form only 4N wirebond interconnects to the package substrate 304, versus N² flip chip interconnects (utilizing the entire "full field" surface area of the first face 320). Additionally, in some applications, wirebond interconnects may generate unacceptable amounts of heat that may damage or otherwise interfere with the performance of the quantum dot device 100. Using solder bumps as the first level interconnects 306 may enable the quantum dot device package 300 to have much lower parasitic inductance relative to using wirebonds to couple the die 302 and the package substrate 304, which may result in an

improvement in signal integrity for high-speed signals communicated between the die 302 and the package substrate 304.

[0169] The package substrate 304 may include a first face 324 and an opposing second face 326. Conductive contacts 399 may be disposed at the first face 324, and conductive contacts 379 may be disposed at the second face 326. Solder resist material 314 may be disposed around the conductive contacts 379, and solder resist material 312 may be disposed around the conductive contacts 399; the solder resist materials 314 and 312 may take any of the forms discussed above with reference to the solder resist material 367. In some embodiments, the solder resist material 312 and/or the solder resist material 314 may be omitted. Conductive pathways 313 may extend through insulating material 310 between the first face 324 and the second face 326 of the package substrate 304, electrically coupling various ones of the conductive contacts 399 to various ones of the conductive contacts 379, in any desired manner. The insulating material 310 may be a dielectric material (e.g., an I LD), and may take the form of any of the embodiments of the insulating material 130 disclosed herein, for example. The conductive pathways 313 may include one or more conductive vias 395 and/or one or more conductive lines 397, for example.

[0170] In some embodiments, the quantum dot device package 300 may be a cored package, one in which the package substrate 304 is built on a carrier material (not shown) that remains in the package substrate 304. In such embodiments, the carrier material may be a dielectric material that is part of the insulating material 310; laser vias or other through-holes may be made through the carrier material to allow conductive pathways 313 to extend between the first face 324 and the second face 326.

[0171] In some embodiments, the package substrate 304 may be or may otherwise include a silicon interposer, and the conductive pathways 313 may be through-silicon vias. Silicon may have a desirably low coefficient of thermal expansion compared with other dielectric materials that may be used for the insulating material 310, and thus may limit the degree to which the package substrate 304 expands and contracts during temperature changes relative to such other materials (e.g., polymers having higher coefficients of thermal expansion). A silicon interposer may also help the package substrate 304 achieve a desirably small line width and maintain high connection density to the die 302.

[0172] Limiting differential expansion and contraction may help preserve the mechanical and electrical integrity of the quantum dot device package 300 as the quantum dot device package 300 is fabricated (and exposed to higher temperatures) and used in a cooled environment (and exposed to lower temperatures). In some embodiments, thermal expansion and contraction in the package substrate 304 may be managed by maintaining an approximately uniform density of the conductive material in the package substrate 304 (so that different portions of the package substrate 304 expand and contract uniformly), using reinforced dielectric materials as the insulating material 310 (e.g., dielectric materials with silicon dioxide fillers), or utilizing stiffer materials as the insulating material 310 (e.g., a prepreg material including glass cloth fibers).

[0173] The conductive contacts 365 of the die 302 may be electrically coupled to the conductive contacts 379 of the package substrate 304 via the first level interconnects 306. In some

embodiments, the first level interconnects 306 may include solder bumps or balls (as illustrated in FIG. 78); for example, the first level interconnects 306 may be flip chip (or controlled collapse chip connection, "C4") bumps disposed initially on the die 302 or on the package substrate 304. Second level interconnects 308 (e.g., solder balls or other types of interconnects) may couple the conductive contacts 399 on the first face 324 of the package substrate 304 to another component, such as a circuit board (not shown). Examples of arrangements of electronics packages that may include an embodiment of the quantum dot device package 300 are discussed below with reference to FIG. 80. The die 302 may be brought in contact with the package substrate 304 using a pick-and-place apparatus, for example, and a reflow or thermal compression bonding operation may be used to couple the die 302 to the package substrate 304 via the first level interconnects 306.

[0174] The conductive contacts 365, 379, and/or 399 may include multiple layers of material that may be selected to serve different purposes. In some embodiments, the conductive contacts 365, 379, and/or 399 may be formed of aluminum, and may include a layer of gold (e.g., with a thickness of less than 1 micron) between the aluminum and the adjacent interconnect to limit the oxidation of the surface of the contacts and improve the adhesion with adjacent solder. In some embodiments, the conductive contacts 365, 379, and/or 399 may be formed of aluminum, and may include a layer of a barrier metal such as nickel, as well as a layer of gold, wherein the layer of barrier metal is disposed between the aluminum and the layer of gold, and the layer of gold is disposed between the barrier metal and the adjacent interconnect. In such embodiments, the gold may protect the barrier metal surface from oxidation before assembly, and the barrier metal may limit the diffusion of solder from the adjacent interconnects into the aluminum.

[0175] In some embodiments, the structures and materials in the quantum dot device 100 may be damaged if the quantum dot device 100 is exposed to the high temperatures that are common in conventional integrated circuit processing (e.g., greater than 100 degrees Celsius, or greater than 200 degrees Celsius). In particular, in embodiments in which the first level interconnects 306 include solder, the solder may be a low-temperature solder (e.g., a solder having a melting point below 100 degrees Celsius) so that it can be melted to couple the conductive contacts 365 and the conductive contacts 379 without having to expose the die 302 to higher temperatures and risk damaging the quantum dot device 100. Examples of solders that may be suitable include indium-based solders (e.g., solders including indium alloys). When low-temperature solders are used, however, these solders may not be fully solid during handling of the quantum dot device package 300 (e.g., at room temperature or temperatures between room temperature and 100 degrees Celsius), and thus the solder of the first level interconnects 306 alone may not reliably mechanically couple the die 302 and the package substrate 304 (and thus may not reliably electrically couple the die 302 and the package substrate 304). In some such embodiments, the quantum dot device package 300 may further include a mechanical stabilizer to maintain mechanical coupling between the die 302 and the package substrate 304, even when solder of the first level interconnects 306 is not solid. Examples of mechanical stabilizers may include an underfill material disposed between the die 302 and the package substrate 304, a corner glue disposed between the die 302 and the package substrate 304, an overmold material disposed around the die 302 on the package substrate 304, and/or a mechanical frame to secure the die 302 and the package substrate 304.

[0176] FIGS. 79A-B are top views of a wafer 450 and dies 452 that may be formed from the wafer 450; the dies 452 may be included in any of the quantum dot device packages (e.g., the quantum dot device package 300) disclosed herein. The wafer 450 may include semiconductor material and may include one or more dies 452 having conventional and quantum dot device elements formed on a surface of the wafer 450. Each of the dies 452 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum dot device. After the fabrication of the semiconductor product is complete, the wafer 450 may undergo a singulation process in which each of the dies 452 is separated from one another to provide discrete "chips" of the semiconductor product. A die 452 may include one or more quantum dot devices 100 and/or supporting circuitry to route electrical signals to the quantum dot devices 100 (e.g., interconnects including conductive vias and lines), as well as any other IC components. In some embodiments, the wafer 450 or the die 452 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 452. For example, a memory array formed by multiple memory devices may be formed on a same die 452 as a processing device (e.g., the processing device 2002 of FIG. 84) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0177] FIG. 80 is a cross-sectional side view of a device assembly 400 that may include any of the embodiments of the quantum dot device packages 300 disclosed herein. The device assembly 400 includes a number of components disposed on a circuit board 402. The device assembly 400 may include components disposed on a first face 440 of the circuit board 402 and an opposing second face 442 of the circuit board 402; generally, components may be disposed on one or both faces 440 and 442.

[0178] In some embodiments, the circuit board 402 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 402. In other embodiments, the circuit board 402 may be a package substrate or flexible board. [0179] The device assembly 400 illustrated in FIG. 80 includes a package-on-interposer structure 436 coupled to the first face 440 of the circuit board 402 by coupling components 416. The coupling components 416 may electrically and mechanically couple the package-on-interposer structure 436 to the circuit board 402, and may include solder balls (as shown in FIG. 78), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0180] The package-on-interposer structure 436 may include a package 420 coupled to an interposer 404 by coupling components 418. The coupling components 418 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 416. For example, the coupling components 418 may be the second level interconnects 308. Although a single package 420 is shown in FIG. 80, multiple packages may be coupled to the interposer 404; indeed, additional interposers may be coupled to the interposer 404. The interposer 404 may provide an intervening substrate used to bridge the circuit board 402 and the package 420. The package 420 may be a quantum dot device package 300 or may be a conventional IC package, for example. In some embodiments, the package 420 may take the form of any of the embodiments of the quantum dot device package 300 disclosed herein, and may include a quantum dot device die 302 coupled to a package substrate 304 (e.g., by flip chip connections). Generally, the interposer 404 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 404 may couple the package 420 (e.g., a die) to a ball grid array (BGA) of the coupling components 416 for coupling to the circuit board 402. In the embodiment illustrated in FIG. 80, the package 420 and the circuit board 402 are attached to opposing sides of the interposer 404; in other embodiments, the package 420 and the circuit board 402 may be attached to a same side of the interposer 404. In some embodiments, three or more components may be

interconnected by way of the interposer 404.

[0181] The interposer 404 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 404 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 404 may include metal interconnects 408 and vias 410, including but not limited to through-silicon vias (TSVs) 406. The interposer 404 may further include embedded devices 414, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency ( F) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 404. The package-on-interposer structure 436 may take the form of any of the package-on- interposer structures known in the art.

[0182] The device assembly 400 may include a package 424 coupled to the first face 440 of the circuit board 402 by coupling components 422. The coupling components 422 may take the form of any of the embodiments discussed above with reference to the coupling components 416, and the package 424 may take the form of any of the embodiments discussed above with reference to the package 420. The package 424 may be a quantum dot device package 300 or may be a conventional IC package, for example. In some embodiments, the package 424 may take the form of any of the embodiments of the quantum dot device package 300 disclosed herein, and may include a quantum dot device die 302 coupled to a package substrate 304 (e.g., by flip chip connections).

[0183] The device assembly 400 illustrated in FIG. 80 includes a package-on-package structure 434 coupled to the second face 442 of the circuit board 402 by coupling components 428. The package- on-package structure 434 may include a package 426 and a package 432 coupled together by coupling components 430 such that the package 426 is disposed between the circuit board 402 and the package 432. The coupling components 428 and 430 may take the form of any of the embodiments of the coupling components 416 discussed above, and the packages 426 and 432 may take the form of any of the embodiments of the package 420 discussed above. Each of the packages 426 and 432 may be a quantum dot device package 300 or may be a conventional IC package, for example. In some embodiments, one or both of the packages 426 and 432 may take the form of any of the embodiments of the quantum dot device package 300 disclosed herein, and may include a die 302 coupled to a package substrate 304 (e.g., by flip chip connections).

[0184] As noted above, any suitable techniques may be used to manufacture the quantum dot devices 100 disclosed herein. FIGS. 81 and 82 are flow diagrams of illustrative methods 1000 and 1010, respectively, of manufacturing a quantum dot device, in accordance with various

embodiments. Although the operations discussed below with reference to the methods 1000 and 1010 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the methods 1000 and 1010 may be illustrated with reference to one or more of the embodiments discussed above, but the methods 1000 and 1010 may be used to manufacture any suitable quantum dot device (including any suitable ones of the embodiments disclosed herein).

[0185] Turning to the method 1000 of FIG. 81, at 1002, a support may be provided. For example, a base 102 may be provided (e.g., as discussed above with reference to FIG. 2). [0186] At 1004, a plurality of quantum dot pillars may be formed above the support. The plurality of quantum dot pillars may include at least two quantum dot pillars spaced apart in a first dimension and at least two quantum dot pillars spaced apart in a second dimension perpendicular to the first dimension. For example, the quantum dot pillars 104 may be formed (e.g., as discussed above with reference to FIGS. 3-4, and in accordance with any of the patterning techniques disclosed herein).

[0187] At 1006, individual gates may be formed above corresponding individual ones of the quantum dot pillars. For example, a gate 108-1 may be formed above each of the quantum dot pillars 104 (e.g., as discussed above with reference to FIGS. 6-13, and in accordance with any of the patterning techniques disclosed herein).

[0188] Turning to the method 1010 of FIG. 82, at 1012, a quantum well stack may be provided. For example, a quantum well stack 146 may be provided (e.g., on the base 102), and may include the quantum well layers 152-1 and/or the quantum well layer 152-2 (e.g., as discussed above with reference to FIG. 3).

[0189] At 1014, a patterned template material may be formed above the quantum well stack. The patterned template material may include a plurality of openings having a footprint shape with two opposing linear faces and two opposing curved faces, or a substantially rectangular footprint shape. For example, the material 1219 may be disposed on the quantum well stack 146, and may include openings 1221 shaped as illustrated in FIGS. 50A-B (e.g., using the technique discussed above with reference to FIGS. 41A-50B).

[0190] At 1016, the patterned template material may be used as a negative pattern to pattern the quantum well stack into a plurality of quantum dot pillars having footprints corresponding to the footprints of the openings in the patterned template material. For example, the quantum dot pillars 104 may be formed from the quantum well stack 146 (e.g., as discussed above with reference to FIG. 4).

[0191] A number of techniques are disclosed herein for operating a quantum dot device 100. FIG. 83 is a flow diagram of a particular illustrative method 1020 of operating a quantum dot device, in accordance with various embodiments. Although the operations discussed below with reference to the method 1020 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 1020 may be illustrated with reference to one or more of the embodiments discussed above, but the method 1020 may be used to operate any suitable quantum dot device (including any suitable ones of the embodiments disclosed herein). [0192] At 1022, electrical signals may be applied to multiple gates disposed above corresponding multiple quantum dot pillars in a quantum dot device to cause quantum dots to form in quantum well layers in the quantum dot pillars. The quantum dot device may take any of the forms disclosed herein. For example, in some embodiments, the quantum dot pillars may have footprint shapes with two opposing linear faces and two opposing curved faces. In some embodiments, the multiple quantum dot pillars may include at least three quantum dot pillars and an insulating material extending between at least two different pairs of the quantum dot pillars. For example, one or more voltages may be applied to the gates 108-1 on corresponding quantum dot pillars 104 to cause quantum dots to form in the quantum well layers 152-1 of one or more of the quantum dot pillars 104.

[0193] At 1024, quantum states of the quantum dots may be sensed. For example, a quantum state of a quantum dot in the quantum well layer 152-1 may be sensed by a quantum dot in the quantum well layer 152-2 of the same quantum dot pillar 104 (or vice versa), or a quantum dot in a quantum dot pillar 104 may be sensed by another device (e.g., a SET).

[0194] FIG. 84 is a block diagram of an example quantum computing device 2000 that may include any of the quantum dot devices disclosed herein. A number of components are illustrated in FIG. 84 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device 2000 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the

components illustrated in FIG. 84, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the quantum computing device 2000 may not include an audio input device 2024 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2024 or audio output device 2008 may be coupled.

[0195] The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include one or more of the quantum dot devices 100 disclosed herein, and may perform data processing by performing operations on the quantum dots that may be generated in the quantum dot devices 100, and monitoring the result of those operations. For example, as discussed above, different quantum dots may be allowed to interact, the quantum states of different quantum dots may be set or transformed, and the quantum states of quantum dots may be read (e.g., by another quantum dot). The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.

[0196] As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[0197] The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-M AM).

[0198] The quantum computing device 2000 may include a cooling apparatus 2030. The cooling apparatus 2030 may maintain the quantum processing device 2026 at a predetermined low temperature during operation to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less. In some embodiments, the non- quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature. The cooling apparatus 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.

[0199] In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0200] The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless

communications (such as AM or FM radio transmissions).

[0201] In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.

[0202] The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).

[0203] The quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0204] The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0205] The quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above). The audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). [0206] The quantum computing device 2000 may include a global positioning system (GPS) device 2018 (or corresponding interface circuitry, as discussed above). The GPS device 2018 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.

[0207] The quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0208] The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0209] The quantum computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0210] Although various ones of the embodiments illustrated in the accompanying drawings may include exactly two quantum well layers 152, this is simply for illustrative purposes, and any of the quantum dot devices 100 (or associated methods or devices) discussed herein may include three or more quantum well layers 152, in accordance with the teachings of the present disclosure. Thus, various ones of the quantum dot devices 100 disclosed herein may be regarded as stacked quantum well structures including two or more quantum well layers 152. For example, a double quantum well structure in a quantum dot device 100 may include two or more quantum well layers 152.

[0211] The following paragraphs provide examples of various ones of the embodiments disclosed herein.

[0212] Example 1 is a quantum dot device, including: a plurality of pillars, wherein individual pillars include a quantum well layer, at least two of the pillars are spaced apart in a first dimension, at least two of the pillars are spaced apart in a second dimension, and the first and second dimensions are perpendicular; an insulating material between at least two of the pillars spaced apart in the first dimension and at least two of the pillars spaced apart in the second dimension; and a plurality of gates disposed above corresponding individual ones of the pillars.

[0213] Example 2 may include the subject matter of Example 1, and may further specify that individual pillars have a substantially rectangular footprint.

[0214] Example 3 may include the subject matter of any of Examples 1-2, and may further specify that the plurality of pillars are distributed in a regular rectangular array.

[0215] Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the insulating material includes a region shaped as a cross-grating.

[0216] Example 5 may include the subject matter of any of Examples 1-4, and may further specify that the plurality of pillars includes at least three pillars.

[0217] Example 6 may include the subject matter of any of Examples 1-5, and may further specify that the plurality of pillars are arranged in an nxm array, n is greater than 1, and m is greater than 1.

[0218] Example 7 may include the subject matter of any of Examples 1-6, and may further specify that the insulating material includes a cross-shaped portion.

[0219] Example 8 may include the subject matter of any of Examples 1-7, and may further specify that the insulating material includes a perimeter portion extending around the plurality of pillars.

[0220] Example 9 may include the subject matter of any of Examples 1-8, and may further specify that the insulating material is a first insulating material, the quantum dot device includes a second insulating material, and the second insulating material includes a plurality of individual openings in which individual ones of the gates are disposed.

[0221] Example 10 may include the subject matter of any of Examples 1-9, and may further specify that the plurality of gates is a plurality of first gates, the quantum well layers are first quantum well layers, individual pillars include a second quantum well layer different from the first quantum well layer, and the quantum dot device further includes a plurality of second gates disposed below corresponding individual ones of the pillars, wherein the second quantum well layer in an individual pillar is disposed between the associated second gate and the first quantum well layer in the individual pillar.

[0222] Example 11 may include the subject matter of Example 10, and may further specify that at least two of the second gates are spaced apart in the first dimension, and at least two of the second gates are spaced apart in the second dimension.

[0223] Example 12 may include the subject matter of Example 11, and may further specify that an arrangement of the second gates below the quantum well stack is a same arrangement as an arrangement of the first gates above the quantum well stack. [0224] Example 13 may include the subject matter of any of Examples 11-12, and may further specify that individual ones of the first gates correspond to individual ones of the second gates below the quantum well stack.

[0225] Example 14 may include the subject matter of any of Examples 11-13, and may further specify that an arrangement of the second gates is a mirror image of an arrangement of the first gates.

[0226] Example 15 may include the subject matter of any of Examples 10-14, and may further specify that a barrier layer is disposed between the first and second quantum well layers.

[0227] Example 16 may include the subject matter of any of Examples 1-15, and may further specify that adjacent ones of the pillars are spaced apart by a distance of 100 nanometers or less.

[0228] Example 17 may include the subject matter of any of Examples 1-16, and may further specify that adjacent ones of the pillars are spaced apart by a distance between 20 and 40 nanometers.

[0229] Example 18 may include the subject matter of any of Examples 1-17, and may further specify that the quantum well layer includes silicon or germanium.

[0230] Example 19 may include the subject matter of any of Examples 1-18, and may further specify that individual pillars include a doped layer.

[0231] Example 20 may include the subject matter of any of Examples 1-19, and may further include a doped region proximate to the plurality of pillars.

[0232] Example 21 may include the subject matter of Example 20, and may further specify that the doped region extends around a perimeter of a region including the plurality of pillars.

[0233] Example 22 may include the subject matter of any of Examples 1-21, and may further specify that the insulating material is a shallow trench isolation material.

[0234] Example 23 may include the subject matter of any of Examples 1-22, and may further specify that adjacent ones of the gates are spaced apart by a distance of 100 nanometers or less.

[0235] Example 24 may include the subject matter of any of Examples 1-23, and may further specify that adjacent ones of the gates are spaced apart by a distance between 20 and 100 nanometers.

[0236] Example 25 may include the subject matter of any of Examples 1-24, and may further specify that the plurality of gates includes a first gate having a first length, two second gates arranged such that the first gate is disposed between the second gates, wherein the second gates have a second length different from the first length, and two third gates arranged such that the second gates are disposed between the third gates, wherein the third gates have a third length different from the first length and different from the second length. [0237] Example 26 may include the subject matter of any of Examples 1-25, and may further specify that individual gates of the plurality of gates include a gate dielectric having a U-shaped cross section.

[0238] Example 27 is a method of operating a quantum dot device, including: applying electrical signals to one or more first gates disposed proximate to a first face of a plurality of quantum dot pillars to cause a first quantum dot to form in a first quantum well layer in a first quantum dot pillar of the plurality of quantum dot pillars, wherein the plurality of quantum dot pillars includes at least three quantum dot pillars, and wherein an insulating material is between at least two different pairs of the quantum dot pillars; and sensing a quantum state of the first quantum dot.

[0239] Example 28 may include the subject matter of Example 27, and may further specify that sensing the quantum state of the first quantum dot includes applying electrical signals to one or more second gates disposed proximate to a second face of the plurality of quantum dot pillars to cause a second quantum dot to form in a second quantum well layer in the first quantum dot pillar, wherein the first and second faces of the plurality of quantum dot pillars are opposing faces.

[0240] Example 29 may include the subject matter of any of Examples 27-28, and may further specify that sensing the quantum state of the first quantum dot includes sensing a spin state of the first quantum dot.

[0241] Example 30 may include the subject matter of any of Examples 27-29, and may further specify that applying the electrical signals to the one or more first gates is to cause a second quantum dot to form in a first quantum well layer of a second quantum dot pillar of the plurality of quantum dot pillars, and wherein the first quantum dot pillar is different from the second quantum dot pillar.

[0242] Example 31 may include the subject matter of any of Examples 27-30, and may further specify that the insulating material includes a region shaped as a cross-grating.

[0243] Example 32 is a method of manufacturing a quantum dot device, including: providing a quantum well stack; providing a template material above the quantum well stack; patterning the template material, wherein the patterned template material includes at least two openings spaced apart in a first dimension and at least two openings spaced apart in a second dimension

perpendicular to the first dimension; patterning the quantum well stack to form a plurality of quantum dot pillars, wherein the quantum dot pillars are aligned with the openings; and forming individual gates above individual ones of the quantum dot pillars.

[0244] Example 33 may include the subject matter of Example 32, and may further specify that the individual gates are first gates, and the method further includes forming individual gates below individual ones of the quantum dot pillars. [0245] Example 34 may include the subject matter of any of Examples 32-33, and may further specify that providing the quantum well stack includes providing the quantum well stack on a support, and the method further includes, after forming the gates, removing the support.

[0246] Example 35 may include the subject matter of any of Examples 32-34, and may further specify that an insulating material extends around the quantum dot pillars, and the method further includes providing a dopant in a portion of the insulating material.

[0247] Example 36 may include the subject matter of any of Examples 32-35, and may further specify that patterning the template material includes: providing a first hardmask above the template material; forming a first plurality of parallel trenches oriented in a first direction in the first hardmask; providing a second hardmask above the template material; forming a second plurality of parallel trenches oriented in a second direction in the first hardmask, wherein the second direction is perpendicular to the first direction; and patterning the template material to form the patterned template material by removing the template material in areas in which the first plurality of trenches and the second plurality of trenches overlap.

[0248] Example 37 may include the subject matter of Example 36, and may further include:

providing a third hardmask above the template material; and patterning the third hardmask by removing areas in which the first plurality of trenches and the second plurality of trenches overlap; wherein patterning the template material includes patterning the template material in accordance with the patterned third hardmask.

[0249] Example 38 may include the subject matter of any of Examples 36, and may further specify that patterning the template material includes using a spacer-based pitch-quartering technique or a spacer-based pitch-halving technique.

[0250] Example 39 is a quantum computing device, including: a quantum processing device, wherein the quantum processing device includes a quantum dot device, wherein the quantum dot device includes a plurality of quantum dot pillars and a plurality of gates above corresponding ones of the quantum dot pillars; a non-quantum processing device, coupled to the quantum processing device, to control electrical signals applied to the gates; and a memory device to store quantum data generated during operation of the quantum processing device; wherein the quantum dot pillars include at least three quantum dot pillars and an insulating material extending between at least two different pairs of the quantum dot pillars.

[0251] Example 40 may include the subject matter of Example 39, and may further include a cooling apparatus to maintain the temperature of the quantum processing device below 5 degrees Kelvin.

[0252] Example 41 may include the subject matter of Example 40, and may further specify that the cooling apparatus includes a dilution refrigerator. [0253] Example 42 may include the subject matter of any of Examples 40-41, and may further specify that the cooling apparatus includes a liquid helium refrigerator.

[0254] Example 43 may include the subject matter of any of Examples 39-42, and may further specify that the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

[0255] Example 44 may include the subject matter of any of Examples 39-43, and may further specify that the quantum dot pillars are arranged in a two-dimensional array.

[0256] Example 45 may include the subject matter of any of Examples 39-44, and may further specify that a single gate is disposed on each of the quantum dot pillars.

[0257] Example 46 may include the subject matter of any of Examples 39-45, and may further specify that adjacent quantum dot pillars are spaced apart by a distance between 20 and 100 nanometers.

[0258] Example 47 may include the subject matter of any of Examples 39-46, and may further specify that the insulating material includes a portion shaped as a grid.

Claims

Claims:

1. A quantum dot device, comprising:

a plurality of pillars, wherein individual pillars include a quantum well layer, at least two of the pillars are spaced apart in a first dimension, at least two of the pillars are spaced apart in a second dimension, and the first and second dimensions are perpendicular;

an insulating material between at least two of the pillars spaced apart in the first dimension and at least two of the pillars spaced apart in the second dimension; and

a plurality of gates disposed above corresponding individual ones of the pillars.

2. The quantum dot device of claim 1, wherein individual pillars have a substantially rectangular footprint.

3. The quantum dot device of claim 1, wherein the plurality of pillars are distributed in a regular rectangular array.

4. The quantum dot device of claim 1, wherein the insulating material includes a region shaped as a cross-grating.

5. The quantum dot device of claim 1, wherein the plurality of pillars includes at least three pillars.

6. The quantum dot device of claim 1, wherein the plurality of pillars are arranged in an nxm array, n is greater than 1, and m is greater than 1.

7. The quantum dot device of claim 1, wherein the insulating material includes a cross-shaped portion.

8. The quantum dot device of claim 1, wherein the insulating material is a first insulating material, the quantum dot device includes a second insulating material, and the second insulating material includes a plurality of individual openings in which individual ones of the gates are disposed.

9. The quantum dot device of any of claims 1-8, wherein the plurality of gates is a plurality of first gates, the quantum well layers are first quantum well layers, individual pillars include a second quantum well layer different from the first quantum well layer, and the quantum dot device further includes:

a plurality of second gates disposed below corresponding individual ones of the pillars, wherein the second quantum well layer in an individual pillar is disposed between the associated second gate and the first quantum well layer in the individual pillar.

10. The quantum dot device of any of claims 1-8, wherein adjacent ones of the pillars are spaced apart by a distance of 100 nanometers or less.

11. The quantum dot device of any of claims 1-8, wherein adjacent ones of the pillars are spaced apart by a distance between 20 and 40 nanometers.

12. The quantum dot device of any of claims 1-8, wherein the quantum well layer includes silicon or germanium.

13. The quantum dot device of any of claims 1-8, wherein individual pillars include a doped layer.

14. The quantum dot device of any of claims 1-8, wherein the insulating material is a shallow trench isolation material.

15. The quantum dot device of any of claims 1-8, wherein adjacent ones of the gates are spaced apart by a distance of 100 nanometers or less.

16. The quantum dot device of any of claims 1-8, wherein the plurality of gates includes:

a first gate having a first length,

two second gates arranged such that the first gate is disposed between the second gates, wherein the second gates have a second length different from the first length, and

two third gates arranged such that the second gates are disposed between the third gates, wherein the third gates have a third length different from the first length and different from the second length.

17. A method of operating a quantum dot device, comprising:

applying electrical signals to one or more first gates disposed proximate to a first face of a plurality of quantum dot pillars to cause a first quantum dot to form in a first quantum well layer in a first quantum dot pillar of the plurality of quantum dot pillars, wherein the plurality of quantum dot pillars includes at least three quantum dot pillars, and wherein an insulating material is between at least two different pairs of the quantum dot pillars; and

sensing a quantum state of the first quantum dot.

18. The method of claim 17, wherein sensing the quantum state of the first quantum dot includes: applying electrical signals to one or more second gates disposed proximate to a second face of the plurality of quantum dot pillars to cause a second quantum dot to form in a second quantum well layer in the first quantum dot pillar, wherein the first and second faces of the plurality of quantum dot pillars are opposing faces.

19. The method of claim 17, wherein sensing the quantum state of the first quantum dot includes sensing a spin state of the first quantum dot.

20. A method of manufacturing a quantum dot device, comprising:

providing a quantum well stack;

providing a template material above the quantum well stack;

patterning the template material, wherein the patterned template material includes at least two openings spaced apart in a first dimension and at least two openings spaced apart in a second dimension perpendicular to the first dimension; patterning the quantum well stack to form a plurality of quantum dot pillars, wherein the quantum dot pillars are aligned with the openings; and

forming individual gates above individual ones of the quantum dot pillars.

21. The method of claim 20, wherein the individual gates are first gates, and the method further comprises:

forming individual gates below individual ones of the quantum dot pillars.

22. A quantum computing device, comprising:

a quantum processing device, wherein the quantum processing device includes a quantum dot device, wherein the quantum dot device includes a plurality of quantum dot pillars and a plurality of gates above corresponding ones of the quantum dot pillars;

a non-quantum processing device, coupled to the quantum processing device, to control electrical signals applied to the gates; and

a memory device to store quantum data generated during operation of the quantum processing device;

wherein the quantum dot pillars include at least three quantum dot pillars and an insulating material extending between at least two different pairs of the quantum dot pillars.

23. The quantum computing device of claim 22, wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

24. The quantum computing device of any of claims 22-23, wherein the quantum dot pillars are arranged in a two-dimensional array.

25. The quantum computing device of any of claims 22-23, wherein a single gate is disposed on each of the quantum dot pillars.