WO2018127948A1 - Système informatique - Google Patents

Système informatique Download PDF

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Publication number
WO2018127948A1
WO2018127948A1 PCT/JP2017/000054 JP2017000054W WO2018127948A1 WO 2018127948 A1 WO2018127948 A1 WO 2018127948A1 JP 2017000054 W JP2017000054 W JP 2017000054W WO 2018127948 A1 WO2018127948 A1 WO 2018127948A1
Authority
WO
WIPO (PCT)
Prior art keywords
heap
area
nvram
memory
computer system
Prior art date
Application number
PCT/JP2017/000054
Other languages
English (en)
Japanese (ja)
Inventor
明男 島田
アビシェク ジョーリ
光雄 早坂
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to PCT/JP2017/000054 priority Critical patent/WO2018127948A1/fr
Publication of WO2018127948A1 publication Critical patent/WO2018127948A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

L'invention concerne un système informatique qui comprend un processeur et une mémoire vive non volatile. Le processeur : fixe un premier tas pour un programme pour utiliser une région de mémoire de la mémoire vive non volatile; exécute une attribution et une libération de régions d'utilisation dans le premier tas; exécute un traitement pour consolider les régions d'utilisation séparées en une région continue unique, dans le premier tas; met à jour des premières informations de gestion indiquant la relation entre une région d'utilisation dans le premier tas et une clé qui identifie la région de mémoire attribuée à la région d'utilisation, cette mise à jour étant conforme à l'attribution, la libération, et le traitement; et recherche le premier tas pour l'adresse d'une région de mémoire cible en utilisant la clé pour la région de mémoire cible dans les premières informations de gestion.
PCT/JP2017/000054 2017-01-04 2017-01-04 Système informatique WO2018127948A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/000054 WO2018127948A1 (fr) 2017-01-04 2017-01-04 Système informatique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/000054 WO2018127948A1 (fr) 2017-01-04 2017-01-04 Système informatique

Publications (1)

Publication Number Publication Date
WO2018127948A1 true WO2018127948A1 (fr) 2018-07-12

Family

ID=62789225

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/000054 WO2018127948A1 (fr) 2017-01-04 2017-01-04 Système informatique

Country Status (1)

Country Link
WO (1) WO2018127948A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11436256B2 (en) 2020-01-20 2022-09-06 Fujitsu Limited Information processing apparatus and information processing system
US11846003B2 (en) 2018-10-31 2023-12-19 Jfe Steel Corporation High-strength steel sheet and method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6282605B1 (en) * 1999-04-26 2001-08-28 Moore Computer Consultants, Inc. File system for non-volatile computer memory
JP2010277268A (ja) * 2009-05-27 2010-12-09 Kyocera Mita Corp メモリ管理装置及びこれを備えたワンチップマイクロコンピュータ並びに組込システム
JP2013222310A (ja) * 2012-04-17 2013-10-28 Hitachi Ltd 業務継続方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6282605B1 (en) * 1999-04-26 2001-08-28 Moore Computer Consultants, Inc. File system for non-volatile computer memory
JP2010277268A (ja) * 2009-05-27 2010-12-09 Kyocera Mita Corp メモリ管理装置及びこれを備えたワンチップマイクロコンピュータ並びに組込システム
JP2013222310A (ja) * 2012-04-17 2013-10-28 Hitachi Ltd 業務継続方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11846003B2 (en) 2018-10-31 2023-12-19 Jfe Steel Corporation High-strength steel sheet and method for manufacturing the same
US11436256B2 (en) 2020-01-20 2022-09-06 Fujitsu Limited Information processing apparatus and information processing system

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