WO2018125238A1

WO2018125238A1 - Systems, methods, and apparatus for semiconductor memory with porous active layer

Info

Publication number: WO2018125238A1
Application number: PCT/US2016/069619
Authority: WO
Inventors: Jeffery D. Bielefeld; Sean W. King; Elijah V. KARPOV; James S. Clarke
Original assignee: Intel Corporation
Priority date: 2016-12-30
Filing date: 2016-12-30
Publication date: 2018-07-05

Abstract

In various embodiments, low-density dielectrics (for example, interlayer dielectrics, ILDs) can be used as the active layer in conduction bridging random access memory (CBRAM) devices. Further, such low-density dielectrics may permit a predetermined level of metal migration in the active layer of the device. In one embodiment, the density and/or porosity of the active layer can be adjusted to affect the performance of the device. In various embodiments, the disclosure describes the use of such porous and/or low-density dielectric layers (for example, silicon oxycarbide, SiOC, silicon carbide, SiC, silicon carbon nitride, SiCN, silicon oxycarbonitride, SiOCN, silicon nitride, SiNx, and the like) as the solid electrolyte comprising the active layer in CBRAM devices. In an embodiment, the use of these porous and/or low-density backend dielectric materials as the active layer can permit filament formation voltages less than approximately 2 V.

Description

SYSTEMS, METHODS, AND APPARATUS FOR SEMICONDUCTOR MEMORY

WITH POROUS ACTIVE LAYER

TECHNICAL FIELD

[0001] This disclosure generally relates to semiconductor memory devices, and more particularly to semiconductor memory device with porous active layers.

BACKGROUND

[0002] Depending on the applications and the performance specifications, various types of memories can be used in connection with semiconductor devices and technologies. For example, static random access memory (SRAM) can have rapid write times that may be needed, for example, for computations by a microprocessor. One disadvantage of SRAM is that they may be volatile. Dynamic random access memory (DRAM) can store electrical charges in capacitors, providing a large storage capacity. However, DRAM can have higher write times (for example, several tens of nanoseconds) than SRAM, and can also be volatile. Finally, for applications needing storage of information even when the power is cut, non-volatile memories such as electrically erasable programmable read-only memory (EEPROM), which store charges on floating grids of field effect transistors, can be used. However, EEPROM can have other disadvantages, including: long write times (for example, several microseconds), limited density, a reduction of the information retention time, and limited number of write cycles. Other types of rewritable non-volatile memories exist, for example, rewritable non-volatile memories based on active materials such as ferroelectric materials (FERAM), magnetic materials (MRAM), phase-change materials (PC-RAM), and ion-conduction materials, that is, conduction bridging materials (CBRAM).

BRIEF DESCRIPTION OF THE FIGURES [0003] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein: [0004] FIG. 1 shows an example cross-sectional view of an exemplary conduction bridging random access memory (CBRAM) device, in accordance with one or more example embodiments of the disclosure.

[0005] FIG. 2 shows a plot of a cumulative failure rate for a plurality of single-layer devices (based on the CBRAM device structure) having different active layers, with respect to different breakdown voltages, in accordance with one or more example embodiments of the disclosure.

[0006] FIG. 3 shows a plot of a cumulative device performance for a plurality of CBRAM devices having different active layers with respect to a formation voltage, in accordance with example embodiments of the disclosure.

[0007] FIG. 4 shows an example processing sequence for the fabrication of a CBRAM device, in accordance with example embodiments of the disclosure.

[0008] FIG. 5 depicts an example of a system, in accordance with one or more embodiments of the disclosure. DETAILED DESCRIPTION

[0009] Embodiments of the disclosure are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0010] The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure. [0011] In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical.

[0012] The term "horizontal" as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation. The term "vertical," as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as "on," "above," "below," "bottom," "top," "side" (as in "sidewall"), "higher," "lower," "upper," "over," and "under," may be referenced with respect to a horizontal plane, where the horizontal plane can include an x- y plane, a x-z plane, or a y-z plane, as the case may be. The term "processing" as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation a described structure.

[0013] Conducting Bridge Resistive Memory (CBRAM) devices (alternatively or additionally referred to as programmable metallization cell (PMC) devices) can refer to memory devices that can provide a combination of longer lifetimes, lower power, and better memory density as compared with other memory technologies. The design of CBRAM devices may involve implementing metal-solid electrolyte layers that yield both low formation voltage and stable filament retention. In various embodiments, disclosed herein are systems, methods, and apparatus that are directed to the use of dielectric materials with predetermined porosity as a solid electrolyte in CBRAM devices. In one embodiment, the disclosed systems, methods, and apparatus may permit a relatively low and controllable formation voltage (for example, of approximately 2 volts ("V") or less) for one or more filaments in a CBRAM device. In another embodiment, the disclosed systems, methods, and apparatus may permit the use of CBRAM memory cells or switches at such lower formation voltages (for example, approximately 2 V or less).

[0014] One challenge in integrating interlayer dielectric (ILD) layers (also referred to as dielectric materials herein) with metal electrodes (for example, Cu metal electrodes) in a CBRAM device can involve the reduction of metal migration from the metal electrodes into the active layer(s) of the CBRAM device. In various embodiments, various properties of the dielectric materials, for example, the porosity and/or the density of the active layer comprising an ILD can be adjusted and/or preselected in order to control the metal diffusion within the dielectric layer. In one embodiment, the formation voltage (for example, the formation voltage for the generation of filaments in the CBRAM device) can also be adjusted and/or preselected in order to control metal diffusion within the dielectric layer.

[0015] In one embodiment, one or more solid electrolytes can be used as part of the active layer of CBRAM devices, including dense metal oxides such as tantalum oxides (Ta_xO_y), hafnium oxides (HfO_x), titanium oxides, (TiO_x), and tungsten oxides (WO_x). In one embodiment, the formation voltage can be influenced by the thickness of the active layer, the active layer including solid electrolytes comprising dense metal oxides. In one embodiment, the film thicknesses of such dense metal oxides may need to be reduced for use in connection with CBRAM devices. In another embodiment, by using porous and low density dielectric layers (for example, dielectric layers having a density below a first threshold and/or porosity above a first threshold, see discussion herein) as the solid electrolyte, the number of tunable parameters in the fabrication of the CBRAM for adjusting the formation voltage of the CBRAM device can be increased. For example, the number of parameters in the fabrication of the CBRAM for adjusting the formation voltage of the CBRAM can be increased to include the thickness, porosity, and/or density parameters of the dielectric layers comprising the active layer. In one embodiment, porosity of dielectric layer can include pore diameters between approximately 1 nm to approximately 8 nm.

[0016] In one embodiment, an example CBRAM device as described herein can include: a first electrode that is a reactive electrode (serving, for example, as an anode), a second electrode that is an inert electrode (serving, for example, as a cathode), an active layer comprising an electrolyte (for example, a solid electrolyte comprising a dielectric layer), and a sieve and/or screen layer.

[0017] In various embodiments, the disclosure is directed to using metal oxide films in CBRAM devices. In an embodiment, oxygen vacancies in the active layer of the device can be used as a transport method, for example, for ion transport. In one embodiment, low- density backend dielectrics (for example, ILDs) can be used as the active layer, and such low-density backend dielectrics may permit a predetermined level of metal migration in the active layer of the device. In another embodiment, as the density of the active layer decreases and/or the porosity of the active layer increases, metal migration and/or metal mobility in the active layer may increase. Accordingly, the density and/or porosity of the active layer can be adjusted to affect the performance of the device. Some examples of active layers that can be used in connection with the disclosure include, but may not be limited to, dielectric layers, oxide-like layers, porous layers, and non-porous layers.

[0018] In various embodiments, the systems, methods, and apparatus herein can use porous and/or low-density backend dielectric layers (for example, silicon oxy carbide, SiOC, silicon carbide, SiC, silicon carbon nitride, SiCN, silicon oxycarbonitride, SiOCN, silicon nitride, SiNx, and the like) as the solid electrolyte, that is, the dielectric comprising the active layer. In another embodiment, the porous and/or low-density backend dielectric layers can further include porous carbon and porous high-k dielectrics such as porous AI2O₃, HfCh, and the like. In one embodiment, the use of these porous and/or low-density backend dielectric materials as the active layer can permit filament formation voltages less than approximately TV.

[0019] In various embodiments, in devices similar but not identical to the CBRAM device structure (shown and described in connection with FIG. 1, below) but not having a sieve and/or screen layer, the dielectric breakdown voltage of an active layer at fixed active layer thicknesses can be influenced by changes in the density and/or porosity of the active layer. In one embodiment, porosity of active layer can include pore diameters between approximately 1 nm to approximately 8 nm.

[0020] In one embodiment, the chemical nature (for example, oxide, nitride, carbide, and the like), the density, porosity, and/or the thickness of the active layer to produce CBRAM devices with formation voltages less than approximately 2 V. In one embodiment, an active layer including a dielectric layer comprising SiOC-1 (low density) having approximately 6% to approximately 8% porosity can be compared against a dense aluminum oxide electrolyte serving as an active layer. In one embodiment, the filament formation voltage can be reduced from a range of approximately 4 V-4.5 V to approximately 1.5 V by using the SiOC-1 (low density) layer having an approximately 4 nm thickness (as compared to control devices having an approximately 3 nm aluminum oxide film). In one embodiment, formation voltages less than approximately 2 V may facilitate integration of the CBRAM devices into standard semiconductor processes. [0021] In one embodiment, to use thicker active layers in devices disclosed herein while maintaining the formation voltage, the active layer can be made more porous to increase the metal mobility and/or migration through the various layers of the device. Alternatively, a thinner active layer that is less porous can be used to achieve a similar affect in terms of the metal mobility and/or migration through the various layers of the device. [0022] In various embodiments, a temperature and time of a cure of the active layer can affect the final density of the active layer. In one embodiment, the higher the density of the active layer, the lower the metal mobility in the active layer can become.

[0023] In one embodiment, an active layer of SiOC-1 (low density) can be deposited at approximately 200-300C degrees centigrade. In one embodiment, no porogens may be added to SiOC-1 (low density) during the deposition of SiOC-1 (low density), for example, to make the active layer have as reduced porosity. In another embodiment, the deposition of SiOC-1 (low density) at approximately 200-300C degrees centigrade can allow the SiOC-1 (low density) to have a lower density than if the layer were deposited at a higher temperature. [0024] In one embodiment, the second electrode (for example, the cathode of the device) can also include an inert electrode that can be composed at least partially of titanium nitride and/or tungsten. In another embodiment, the device can include a screen and/or sieve layer, to reduce the migration and/or mobility of copper. In one embodiment, the screen and/or sieve layer can be an approximately 1 nm to an approximately 3 nm metal oxide, for example, a titanium oxide. Further, in devices having the screen and/or sieve layer, a thicker electrode (for example, an approximately 10 nm to approximately 20 nm thick copper electrode) can be used. Alternatively or additionally, for devices not having a screen and/or sieve layer, a thinner electrode (for example, an approximately 1 nm to approximately 3 nm copper electrode) can be used. [0025] In another embodiment, one or more inert metal layers (for example, inert metal layers composed at least partially of palladium or titanium nitride as the bulk of the inert metal layers), can be fabricated in contact with the first electrode (that is, the anode or the reactive electrode). This can be done, such that, if the amount of metal migration and/or mobility in the device is limited. Alternatively or additionally, a screen and/or sieve layer can be used in combination with the inert metal layer to control the metal migration and/or mobility.

[0026] FIG. 1 shows an example cross-sectional view of an exemplary CBRAM device 100 in accordance with one or more example embodiments of the disclosure. In one embodiment, the device 100 can include a first electrode 102. The first electrode 102 can alternatively be referred to as an anode and/or an active electrode in this disclosure. Accordingly, the first electrode 102 can serve as an anode in the device 100. In another embodiment, the device 100 can further include a screen layer and/or a sieve layer 104. In one embodiment, the screen and/or sieve layer 104 can be deposited on the first electrode 102. The device 100 can further include an active layer 106. In one embodiment, the active layer may be a solid, a partially solid, and/or a partially liquid electrolyte layer. In one embodiment the active layer can be deposited on the screen and/or sieve layer 104. Finally, the device 100 can further include a second electrode 108. The second electrode 108 can alternatively be referred to as a cathode and/or an inert electrode in this disclosure. Accordingly the second electrode 108 can serve as a cathode in the device 100. [0027] In one embodiment, the device 100 can be fabricated on a substrate (not shown). In another embodiment, the substrate can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. The substrate can be a thin slice of material such as silicon, silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide(GaAs), an alloy of silicon and germanium, or indium phosphide (InP). [0028] In various embodiments, the first electrodes 102 and/or the second electrode 108 can comprise a metallic, semi-metallic, or intermetallic material. In various embodiments, the first electrodes 102 and/or the second electrode 108 can comprise a metallic material. Non-limiting examples include gold, copper, silver, aluminum, zinc, tin, platinum, and any of the like. Metallic materials may also be any alloys of such materials.

[0029] In various embodiments, the first electrodes 102 and/or the second electrode 108 can comprise a semi-metallic material. Non-limiting examples include arsenic, antimony, bismuth, a-tin (gray tin) and graphite, and mercury telluride (HgTe). Semi-metallic materials may also be any mixtures of such materials. [0030] In various embodiments, the first electrodes 102 and/or the second electrode 108 can comprise an intermetallic material. Non-limiting examples include gold and aluminum intermetallics, copper and tin intermetallics, tin and nickel intermetallics, tin and silver intermetallics, tin and zinc intermetallics, and any of the like. Intermetallic materials may also be any alloys of such materials. [0031] The first electrodes 102 and/or the second electrode 108 may be deposited by any suitable mechanism including, but not limited to, metal foil lamination, physical vapor deposition, chemical vapor deposition, sputtering, metal paste deposition, combinations thereof, or the like.

[0032] As mentioned, the first electrode 102 can represent the anode of the device 100. In yet another embodiment, the first electrode 102 can be approximately 1 nm to approximately 1000 nm thick, with example thicknesses of approximately 10 nm to approximately 20 nm. In one embodiment, if the device 100 has no screen and/or sieve layer 106, the first electrode 102 may then be approximately 1 nm to approximately 3 nm thick and may include copper; further, the device 100 can have a second electrode 108 including palladium (Pd) and/or titanium nitride (TiN). In various embodiments, the first electrode 102 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), and/or atomic layer deposition (ALD).

[0033] In one embodiment, the screen and/or sieve layer 104 can be made of a metal oxide, for example, titanium oxide (TiOx). In one embodiment, when a voltage is applied from the first electrode 102 (the anode) to the second electrode (the cathode) of the device 100, metal can migrate through the device from the first electrode 102 to the second electrode 108. In one embodiment, the screen and/or sieve layer 104 can be used to reduce metal mobility and/or metal migration through the device 100, when the device 100 has a voltage bias. In various embodiments, the screen and/or sieve layer 104 can be optionally included in the device 100. In another embodiment, the screen and/or sieve layer 104 can have a thickness of approximately 1 nm to approximately 100 nm with example thicknesses of approximately 1 nm to approximately 3 nm. In various embodiments, the screen and/or sieve layer 104 can be deposited using CVD, PVD, and/or ALD.

[0034] In various embodiments, the active layer 106 can be deposited on the screen and/or sieve layer 104. In another embodiment, if the screen and/or sieve layer 104 is not present in the device 100, then the active layer 106 can be deposited on the first electrode 104. In one embodiment, the active layer 106 can have a thickness of approximately 5 nm to approximately 10,000 nm with example thicknesses of approximately 50 nm to approximately 200 nm. In one embodiment, an active layer 106 having a thickness greater than a predetermined threshold can be used for the device 100 if the active layer 106 also has a porosity and/or density greater than a predetermined threshold. Alternatively, an active layer 106 having a thickness less than a predetermined threshold can be used in the device 100 if the active layer 106 has a porosity and/or density lower than a predetermined threshold. In various embodiments, a processing parameter, for example, a deposition temperature, a thermal curing temperature, and/or a thermal curing duration maybe used to change the porosity of the active layer 106. In one embodiment, porosity of the active layer 106 can include pore diameters between approximately 1 nm to approximately 8 nm. In various embodiments, the active layer 106 can include a solid electrolyte, for example, including by not limited to SiOC-2 (high porosity), SiOC-1 (low density), and/or any composition thereof.

[0035] In various embodiments, the active layer 106 can be deposited using plasma- enhanced chemical vapor deposition (PECVD). In such a technique, the active layer 106 can be deposited by first depositing two separate materials (not shown), a pre-cursor material and a sacrificial material, for example, a porogen material. Example porogen materials can include, but not be limited to, bicycloheptadiene (BCHD), limonene (LIMO) and alpha-terpinene (ATRP). The two materials may be deposited simultaneously and/or substantially at the same time. After deposition, the composition of the two materials can be thermally cured at a pre-determined temperature to remove the sacrificial material (for example, the porogen material) and thereby generate pores in the active layer 106. As such, the amount of sacrificial material used during deposition can influence the porosity and/or density of the active layer 106. [0036] In one embodiment, the deposition of the active layer 106 (the active layer 106 including SiOC-1 (low density)) can first include the deposition of a sacrificial material comprising a pre-determined amount of a porogen. The active layer 106 can then be thermally cured at a predetermined temperature (for example, at approximately 200-300° C) in order to generate the final active layer. [0037] As mentioned, in one embodiment, a second electrode 108 can be deposited on the active layer 106 in the device 100. The second electrode 108 can be designated as the cathode in the device 100 and as such, the second electrode 108 may be grounded during operation of the device 100. In contrast, the first electrode 102, can serve as the anode and/or the active electrode and the first electrode 102 can have a positive voltage applied thereon during device 100 operation, as described further below.

[0038] In various embodiments, the second electrode 108 can include an inert electrode. That is, the second electrode 108 can be made substantially of a compound that is not reactive. For example, the second electrode 108 can include tungsten, nickel, titanium nitride, and/or palladium. In various embodiments, the second electrode may have a thickness of approximately 5 nm to approximately 500 nm, with example thicknesses of approximately 20 nm to approximately 50 nm. In one embodiment, the second electrode can be deposited using any suitable technique, including but not limited to, CVD, PVD, and/or ALD.

[0039] Various aspects of the operation of the device 100 are described below. In one embodiment, prior to the application of voltage to the first electrode 102, the device 100 can be in a state of high resistance, often referred to as a high-resistance state, HRS. In such an HRS state, the resistance between the first electrode 102 and the second electrode 108, can be, for example, in the range of several mega-ohms to several giga-ohms. By applying a positive voltage to the first electrode 102 (for example, while the second electrode 108 is grounded) and by increasing the applied voltage past a first threshold ( known as the formation voltage), a conductive filament 110 can form between the first electrode 102 and the second electrode 108. In one embodiment, the conductive filament 110 can be formed between the first electrode 102 and the second electrode 108 including at least portions of the screen and/or sieve layer 104 and/or the active layer 106. In another embodiment, the conductive filament 1 10 can electrically connect the first electrode 102 to the second electrode 108 and may form, for example, on the order of several nanoseconds.

[0040] In one embodiment, the application of the positive voltage bias to the first electrode 102 can electrochemically oxidize the first electrode 102. That is, the application of the positive voltage bias to the first electrode 102 can lead to the formation of metal ions on the first electrode 102. These metal ions can travel through the intervening layers between the first electrode 102 and the second electrode 108, including the screen and/or sieve layer 104 and the active layer 106. The metal ions can then reach the second electrode 108 where the metal ions may be electrochemically reduced. Upon the continuous application of the applied voltage to the first electrode 102, metal ions can continue to be electrochemically reduced at the second electrode 108, leading to the growth of the conductive filament 110. Once the applied voltage is removed from the first electrode 102, the conductive filament may remain, leaving the device 100 in a low- resistance state, LRS. In various embodiments, the conductive filament 110 may not be continuous but may include a chain of electrodeposit islands and/or nano-crystals. [0041] In one embodiment, the device 100 can revert back to a HRS, for example, by the application of a negative voltage bias to the first electrode 102. In such a situation, the redox process used to generate the conductive filament 1 10 may be reversed. As such, the metal ions residing on the second electrode 108 can migrate along the reverse electric field, from the second electrode 108 to the first electrode 102, where the metal ions can be reduced at the first electrode 102. Accordingly, the conductive filament 1 10 is removed, and the device 100 can revert back to a HRS of, for example, several mega-ohms to several giga-ohms between the first electrode 102 and the second electrode 108.

[0042] FIG. 2 shows a plot 200 of a cumulative failure rate for a plurality of single-layer devices (based on the CBRAM device structure), having different active layers, with respect to different breakdown voltages, in accordance with one or more example embodiments of the disclosure. In particular, the single-layer devices represent devices lacking a screen and/or sieve layer, as shown and described in an illustrative context in the context of FIG. 1. In particular, the single-layer devices of FIG. 2 may have a device structure of a first electrode, followed by an active layer, and then followed by a second electrode. As such, in one embodiment, the single-layer devices can provide data with regards to the active layers in more controlled experiments than in CBRAM devices including the screen and/or sieve layer. In one embodiment, the cumulative failure rate 202 of the plurality of devices having different active layers can provide an indication of how consistently the single-layer devices break down. In various embodiments, the breakdown voltage 204 can refer a voltage at which the active layer becomes electrically conductive. For example, at the breakdown voltage or at voltages exceeding the breakdown voltage, a weakened path for electrical conduction within the material comprising the active layer can be created. This can occur, for example, due to permanent molecular and/or physical changes in the active layer as a result of electric fields and/or current conduction through the layer. [0043] Plot 200 also shows the breakdown voltage 204 of different active layers in single- layer devices, in accordance with example embodiments of the disclosure. In one embodiment, the breakdown voltage 204 can be used as indication of how metal can move through the active layer. In another embodiment, the breakdown voltage 204 can be modulated by the density and the active layer type. Shown in FIG. 2 are four curves (curves 206, 207, 209, and 211) that can represent different active layers: porous active layers(206, 209), non-porous active layers(207, 211), etch-stop active layers (209), and ILD active layers (206, 209, 21 1).

[0044] In one embodiment, the breakdown voltage 204 of the active layer can represent a parameter related to the active layer not physically breaking down before the metal moves through the active layer. In another embodiment, when a voltage having a magnitude lower than the breakdown voltage is applied across the active layer, the active layer does not change the bulk of its chemical, physical, and/or electronic properties before the metal moves through the film. In one embodiment, various backend dielectric films having high breakdown voltages can be used as the active layer in devices disclosed herein. [0045] In one embodiment, plot 200 shows device data resulting from applying an increasing voltage across a set of devices having a device structure comprising: a first electrode comprising copper, different active layers comprising an electrolyte, and a second inert electrode. In particular, curve 206 represents devices having an active layer comprising SiOC-2 (high porosity), curve 207 represents devices having an active layer comprising SiOC-1 (low density), curve 209 represents devices having an active layer comprising a screen and/or sieve layer, curve 211 represents devices having an active layer comprising SiOC-3 (Dense). The breakdown voltage of the devices can be determined from the data.

[0046] The y-axis 202 of the plot 200 represents the cumulative failure rate, which can represent the how consistently the devices in a given group of tested devices break down. As such, several devices can be tested simultaneously to obtain a statistical representation of how consistently the devices break down. For example, at approximately 0.5 V on the y-axis of the plot shown in FIG. 3, corresponds to approximately 50% of the devices having broken down. In one embodiment, the steepness or slope of the curves (curves 206, 207, 209, and 211) can indicate the uniformity of devices having a given active layer. For example, for devices having a SiOC-2 (high porosity) active layer (curve 206), at approximately 3.2 V a steep increase in the slope of curve 206 can be observed where, within a small amount of voltage increase (less than 1 V), many devices break down (that is, the cumulative failure rate increases to greater than 0.9 below 3.5 V. For the devices having a SiOC-1 (low density) active layer (curve 207), a less steep increase in the slope of the curve 207 is observed with respect to the curve 206 representing devices having the SiOC-2 (high porosity) active layer. However, for the devices having a SiOC-1 (low density) active layer (curve 207), an increase in the breakdown voltages in comparison to devices having the aluminum oxide active layer (curve 206) can additionally be observed.

[0047] In one embodiment, the curves representing devices having active layers comprising SiOC-1 (low density) (curve 206), SiOC-2 (high porosity) (curve 207), and

SiOC-3 (Dense) (curve 211), indicate that such devices have a more consistent failure rate.

That is, for devices having active layers comprising SiOC-1 (low density) (curve 206),

SiOC-2 (high porosity) (curve 207), and SiOC-3 (Dense) (curve 211), the curves have a more even slope throughout the voltage range tested for each group of devices. For example, for devices having active layers comprising SiOC-2 (high porosity) (curve 207), the curve may have two sloping regions (as represented by the group of device failures,

210, and another group of device failures, 208). However, the two distinct sloping regions (as represented by the group of device failures, 210, and another group of device failures, 208) are not substantially different, and can be considered within the margin of statistical variation between devices. In contrast, for devices having active layers comprising the SiC (Porous)(curve 209), the curve has two distinct sloping regions (as represented by the group of device failures, 212, and another group of device failures, 214), the two sloping regions having a more pronounced distinction, for example, than that the group of device failures, 210, and another group of device failures, 208 of curve 207.

[0048] In one embodiment, the silicon carbide, SiC (Porous), can be used in devices represented by curve 209. In one embodiment, silicon carbide can have a higher breakdown voltage, for example, in comparison with the SiOC-2 (high porosity) and/or the SiOC-1 (low density) layer. However, in an embodiment, the SiC Porous layer represented by curve 209 can have a predetermined level of porosity. In one embodiment, the SiC Porous layer can include a material having a predetermined backbone molecular structure, where the layer of the material is further chemically or physically altered to have a predetermined porosity. The porosity can permit the SiC Porous layer to have a path to diffuse metal and form the switching mechanism of the device. In one embodiment, the density and/or the porosity of the SiC Porous layer can be altered to tune how the metal mobility and/or migration rate through the SiC (Porous) layer.

[0049] In one embodiment, SiOC-1 (low density) (represented by curve 207) can be considered a better active layer than SiOC-2 (high porosity) (represented by curve 206), for example, because the SiOC-1 (low density) film can be a porous film. That is, while the SiOC-1 (low density) can be a low density film, SiOC-1 (low density) may not be as porous as the SiOC-2 (high porosity). As such, metal from the electrodes can have a sufficiently large mobility and/or migration rate in devices having SiOC-2 (high porosity), that it may be difficult to turn such devices off. That is, after applying a positive bias to the anode of the device, the metal may migrate in a difficult-to-control manner. In one embodiment, the material parameters can be tuned between to have a more suitable metal mobility and/or metal migration rate, for example, by using an active layer having both SiOC-1 (low density) and SiOC-2 (high porosity). In one embodiment, devices with such a hybrid active layer can be used to avoid a low (for example, an approximately 0.1 V) formation voltage. [0050] In various embodiments, several parameters of the active layer can be modified to affect the performance parameters (for example, the formation voltage, cumulative failure rate, breakdown voltage, and the like) of the device. For example, such parameters can include the density, porosity, thickness, and composition of the active layer. [0051] In one embodiment, the SiOC-2 (high porosity) film and the SiOC-1 (low density) film can be at least partially composed of silicon oxy carbides. In another embodiment, the screen and/or sieve layer can be composed at least partially of silicon carbide. In various embodiments, similar layers, such as layers comprising materials that have higher dielectric constants or have higher break down voltages (for example, layers that are at least partially composed of silicon nitride and/or silicon carbon nitride) can be used in connection with the disclosure. Accordingly, in various embodiments the thickness, porosity, density, and chemical composition of the materials and layers used in connection with the disclosure can be tuned to fabricate the devices. In another embodiment, the porous and/or low-density backend dielectric layers used in connection with the systems, methods, and apparatus herein can further include porous carbon and porous high-k dielectrics such as porous AI2O3, HfC , and the like.

[0052] In one embodiment, the chemical composition of the films can modulate the breakdown strength of the backbone of the chemical compounds that compose the bulk of the film. For example, a denser silicon carbide or silicon nitride film can be harder to break down than a silicon oxide or a silicon oxy carbide film.

[0053] In one embodiment, the films can be deposited with chemical vapor deposition (CVD). The films may optionally be thermally cured after deposition. For the generation of a porous film, the backbone of the film can first be deposited along with a porogen. The porogen can later be removed, for example, using the thermal curing process. Alternatively or additionally, the films can be deposited using physical chemical vapor deposition (PCVD). The films may optionally be thermally cured after deposition, for example, to tune the porosity of the films.

[0054] To fabricate porous films, at least two elements can be first formed, for example, a backbone and a sacrificial material (for example, a porogen), followed by selectively removing the sacrificial material, for example, using an etching process. In one embodiment, the sacrificial material such as the progen can be used to make a plurality of voids in the film, giving rise to the porosity of the film.

[0055] In one embodiment, the amount of the porogen can be tuned to make a range of different film porosities that can thereby impact the formation voltage of the film. The porosity of the film can impact the way that the metal can move through the film. In one embodiment, the SiOC-1 (low density) can be about 5% to about 10% porous, where the SiOC-2 (high porosity) can be about 20-30% porous. In one embodiment (not shown), the formation voltage for devices having SiOC-1 (low density) as the active layer can be about 1.2 V, but the formation voltage of devices having a SiOC-2 (high porosity) active layer can be in the millivolt range.

[0056] In one embodiment, to use thicker active layers in devices disclosed herein while maintaining the formation voltage, the active layer can be made more porous to increase the metal mobility. Alternatively, a thinner active layer that is less porous can be used.

[0057] In various embodiments, the temperature and time of the cure can affect the final density of the active layer. The higher the density of the active layer, the lower the metal mobility in the active layer can be.

[0058] In one embodiment, the SiOC-1 (low density) can be deposited at approximately 200-300C degrees centigrade. In one embodiment, no porogens can be added to the SiOC-1 (low density), for example, to make the active layer have as little porosity as possible. The deposition at approximately 200-300 degrees centigrade can allow the SiOC-1 (low density) to have a lower density than if the layer were deposited at a higher temperature. In one embodiment, the SiOC-1 (low density) can be deposited using PCVD using a silicon oxy carbide (SiOC) liquid precursor. The deposition of the SiOC-1 (low density) at a higher temperature may yield active layers that are denser. [0059] In one embodiment, the second electrode (for example, the cathode of the device) can include an inert electrode that can be composed at least partially of titanium nitride and/or tungsten. In one embodiment, the thicknesses of the first electrode or the second electrode can be approximately 20 to approximately 50 nm. For the screen and/or sieve layer, for example, a screen and/or sieve layer to reduce the migration and/or mobility of copper, an approximately 1 nm to an approximately 3 nm metal oxide, for example, a titanium oxide, can be used. Further, in devices having the screen and/or sieve layer, a thicker electrode (for example, an approximately 10 nm to approximately 20 nm thick copper electrode) can be used. Alternatively or additionally, for devices not having a screen and/or sieve layer, a thinner electrode (for example, an approximately 1 nm to approximately 3 nm copper electrode) can be used.

[0060] In another embodiment, one or more inert metal layers (for example, inert metal layers composed at least partially of palladium or titanium nitride as the bulk of the inert metal layers), can be fabricated in contact with the first electrode (that is, the anode or the reactive electrode). This can be done, such that, if the amount of metal migration and/or mobility in the device is limited. Alternatively or additionally, a screen and/or sieve layer can be used in combination with the inert metal layer to control the metal migration and/or mobility.

[0061] FIG. 3 shows a plot 300 of a cumulative device performances (in units of percent) 302 for a plurality of CBRAM devices having different active layers with respect to a formation voltage 304, in accordance with example embodiments of the disclosure. In particular, plot 300 shows the formation voltage of CBRAM devices having a device structure of a first electrode, followed by a screen and/or sieve layer, followed by an active layer, followed by a second electrode.

[0062] In one embodiment, plot 300 shows performance data for devices having two different active layers: the first active layer comprising an aluminum oxide active layer, which can be approximately 3 nm thick, and the second active layer comprising an SiOC-1 (low density) active layer, which can be approximately 4 nm thick. In one embodiment, as shown in curve 303, devices having the aluminum oxide active layer can take, on average, between approximately 3.5 V and approximately 4.5 V to form a LRS, as represented by portion of the curve 308. (In one embodiment, the portion of the curve 307 can be considered statistical variations in the devices, showing lower formation voltages below approximately 3.5 V.) In another embodiment, for devices having the SiOC-1 (low density) (a siloxi-carbide material) active layer (as represented by curve 301), a thicker layer than the aluminum oxide active layer can be deposited (for example, 4 nm for the SiOC-1 (low density) active layer versus 3 nm for the aluminum oxide active layer). Further, for devices having the SiOC-1 (low density) active layer (as represented by curve 301) lower formation voltages can be obtained as compared with devices having aluminum oxide active layers. In summary, for devices having active layers comprising an SiOC-1 (low density) active layer and using, for example, copper as the mobile metal, a slightly thicker active layer (for example, approximately 1 nm thicker active layer) can be used in devices, while simultaneously lowering the formation voltage.

[0063] In one embodiment, plot 300 can further represent the statistical variability of device performance for a group of devices. In one embodiment, the steeper the slope of a given curve (that is curves 301 and 303), the more consistent the device performance for the group of devices represented in the curves. [0064] In one embodiment, for curve 301 representing devices including the approximately 4 nm thick SiOC-1 (low density) active layer, a couple of devices have a relatively low formation voltage, as represented by the group of tested devices 304. As seen in the group of tested devices 304, one device has a formation voltage of approximately 0.5 V and another device has a formation voltage of approximately 1.0 V. However, as shown in curve 301, the majority of the devices having the SiOC-1 (low density) active layer (curve 301) demonstrated a formation voltage of approximately 1.2 V to approximately 1.3 V, as represented by the group of tested devices 306. Further, towards the higher end of the formation voltage rage represented in curve 301 (that is, as represented by the group of tested devices 308) a few devices have a higher formation voltage of approximately 1.5 V.

[0065] In one embodiment, curve 301 can represents a cumulative plot of device performance for devices having a SiOC-1 (low density) active layer. In another embodiment, curve 301 can indicate that, of the group of devices tested, approximately 50% of the devices had a formation voltage of approximately 1.35 V. Further, approximately 80% of the devices in curve 301 showed a formation voltage of approximately 1.45 V. At a voltage of approximately 1.4 V, approximately 50% of the devices represented by the curve 301 have already formed. Accordingly, at a voltage of approximately 1.45 V, approximately 90% of the tested devices in curve 301 have formed.

[0066] Similar remarks can be made regarding device formation for devices including an aluminum oxide active layer as represented by curve 303. In particular, in one embodiment, for the curve 303 representing devices including approximately 3 nm thick aluminum oxide active layers, a greater spread in the failure rates for such devices can be observed. That is, excluding the group of devices 307 at the lower formation voltage range between approximately 3 V and approximately 3.5 V, the formation voltage range for devices represented by curve 303 is greater than the formation voltage range for devices represented by curve 301. For example, comparing group of tested devices 308 in curve 303 with the group of tested devices 306 in curve 301, it can be observed that there is a formation voltage spread in the group of devices 308 in curve 303. That is, because curve 303 does not have an average slope that is as steep as curve 301, the spread of formation voltage in curve 303 is greater (between approximately 3.5 V and approximately 4.6 V, whereas the spread in curve 301 is tighter (between approximately 1 V and approximately 1.5 V, excluding the two devices having formation voltages below 1 V, in group 304).

[0067] In one embodiment, the data shown in plot 300 can indicate that with a physically thicker active layer (that is, for devices having a 4 nm thick SiOC-1 (low density) active layer as represented by curve 301 versus devices having a 3 nm thick aluminum oxide active layer as represented by curve 302), an LRS can be obtained at lower formation voltages in the group of devices tested. Further, in another embodiment, a higher repeatability for devices having the SiOC-1 (low density) active layer (as represented by curve 301) can be obtained versus devices having the aluminum oxide active layer (as represented by curve 302).

[0068] FIG. 4 shows an example processing sequence for the fabrication of a CBRAM device in accordance with example embodiments of the disclosure. The fabrication of a device can be for a device similar but not necessarily identical to the device 100 of FIG. 1.

[0069] In block 402, a first electrode, acting as an anode, can be deposited on a substrate using a suitable mechanism. The substrate can be a sacrificial carrier, for example, made of a semiconductor (such as silicon, Si), and/or glass. The first electrode can be considered an active electrode and/or an anode. The first electrode can be at least partially composed of copper, silver, and/or any other suitable metal.

[0070] In another embodiment, the substrate can be a thin slice of material such as silicon, silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide(GaAs), an alloy of silicon and germanium, or indium phosphide (InP). These serve as the foundation upon which electronic devices such as transistors, diodes, and especially integrated circuits (ICs) are deposited.

[0071] In one embodiment, the thickness of the first electrode may be approximately 5 nm to approximately 1000 nm with example thicknesses of approximately 10 nm to approximately 20 nm. In one embodiment, if the device 100 has no screen and/or sieve layer 106, the first electrode 102 may be approximately 1 nm to approximately 3 nm thick and may include copper, and the device 100 can have a second electrode 108 including palladium (Pd) and/or titanium nitride (TiN). In various embodiments, the first electrode may be deposited by any suitable technique, including but not limited to, ALD, CVD, and/or PVD.

[0072] In block 404, a screen and/or a sieve layer can optionally be deposited onto the first electrode using a suitable mechanism. In one embodiment, the screen and/or sieve layer may be at least partially composed of a metal oxide, for example, titanium oxide (TiOx). The screen and/or sieve layer can serve to reduce the electromigration of metal (for example, copper and/or silver) from the first electrode and/or any other metal from which the first electrode is composed of. In various embodiments, the screen and/or sieve layer may be approximately 1 nm to approximately 100 nm thick with example thicknesses of approximately 1 nm to approximately 3 nm thick. In various embodiments, the screen and/or the sieve layer can be deposited using any suitable technique, including but not limited to, ALD, CVD, and/or PVD.

[0073] In block 406, an active layer having a first porosity and first thickness can be deposited on the screen and/or sieve layer (or on the first electrode, for example, if a screen and/or sieve layer is not present in the device) using a suitable mechanism. In various embodiments, the active layer can be at least partially comprised of SiOC-2 (high porosity), SiOC-1 (low density) and/or any composition of thereof. In another embodiment, the active layer can further include porous carbon and porous high-k dielectrics such as porous AI2O₃, HfC>2, and the like. In various embodiments, the density and/or porosity, the thickness, and/or the composition of the active layer can be controlled by the parameters of the deposition and fabrication of the active layer. [0074] In block 408, optionally, a porogen can be deposited at a first weight percentage during the deposition of the active layer, and the active layer can be thermally annealed at a first temperature and at a first duration. As mentioned, in various embodiments, the density and/or porosity, the thickness, and/or the composition of the active layer can be controlled by the parameters of the deposition and fabrication of the active layer. For example, the active layer may be deposited as a combination of two constituent materials, the first being a precursor material and the second being a sacrificial material, for example, a porogen. In one embodiment, the porosity and/or density of the active layer can be controlled, for example, based on the amount of sacrificial material, and/or the ratio of the sacrificial material to the precursor material. Further, the active layer may be thermally cured at a predetermined temperature after a deposition of the two constituent materials. The thermal cure may serve to remove the sacrificial material (for example, the porogen), leaving behind a porous material comprising the active layer. As one example, for the case of an active layer including SiOC-1 (low density), no sacrificial material (for example, porogen) may be used, but a thermal cure of 325° C may be employed to fabricate the active layer. As another example, for SiOC-2 (high porosity), a predetermined amount of sacrificial material, for example, approximately 20-30% of a porogen material, can be deposited simultaneously and/or substantially at the same time as the precursor material; further, a thermal cure may be performed in order to generate a final active layer of having a predetermined porosity such as, for example, 5% porosity. In various embodiments, the active layer can be deposited using any suitable technique, including but not limited to PECVD.

[0075] In various embodiments, the thickness of the active layer may affect the formation of the filaments in the device and/or the electrical performance of the device. In one embodiment, the thickness of the active layer may be approximately 5 nm to approximately 1,000 nm with example thicknesses of approximately 50 nm to approximately 100 nm.

[0076] In various embodiments, the composition of the active layer may be controlled in order to tune the film formation properties of the active layer and of the device, incorporating the active layer. For example, an active layer that is approximately 25% SiOC-2 (high porosity) can be used in conjunction with the device, having approximately 80% SiOC-1 (low density). Other ratios of two or more materials such as SiOC-2 (high porosity) and SiOC-1 (low density), can be used in order to optimize a device for a particular application. For example, various ratios of two or more materials such as SiOC- 2 (high porosity) and SiOC-1 (low density), can be used to generate an active layer for a device such that the device has a predetermined formation voltage, predetermined breakdown voltage, a high-resistance state, a low-resistance state, and/or any other relevant device parameter.

[0077] In block 410, a second electrode can be deposited at least partially on the active layer, using a suitable mechanism. The second electrode can include an inert electrode and can be considered a cathode of the device, comprising the first electrode, the screen/sieve layer, the active layer, and the second electrode. In one embodiment, the second electrode can include any suitable material including, but not limited to, tungsten, nickel, titanium nitride, palladium, including combinations and/or alloys thereof.

[0078] In various embodiments, the second electrode can have any suitable thickness, including but not limited to, approximately 5 nm thick to approximately 2,000 nm thick, with example thicknesses of approximately 20 nm to approximately 50 nm thick. In one embodiment, the second electrode can be deposited using any suitable technique, including ALD, CVD, and/or PVD.

[0079] FIG. 5 depicts an example of a system 500 according to one or more embodiments of the disclosure. In one embodiment, the systems, methods, and apparatus disclosed herein, including for example, the CBRAM devices described herein can be used in connection with system 500. For example, the CBRAM devices described herein can be used in connection with system 500 to improve the performance of system 500 or to provide memory capabilities to one or more devices of system 500. In one embodiment, system 500 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 500 can include a system on a chip (SOC) system.

[0080] In one embodiment, system 500 includes multiple processors including processor 510 and processor N 505, where processor N 505 has logic similar or identical to the logic of processor 510. In one embodiment, processor 510 has one or more processing cores (represented here by processing core 1 512 and processing core N 512N, where 512N represents the Nth processor core inside processor 510, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 5). In some embodiments, processing core 512 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 510 has a cache memory 516 to cache instructions and/or data for system 500. Cache memory 516 may be organized into a hierarchical structure including one or more levels of cache memory.

[0081] In some embodiments, processor 510 includes a memory controller (MC) 514, which is configured to perform functions that enable the processor 510 to access and communicate with memory 530 that includes a volatile memory 532 and/or a non-volatile memory 534. In some embodiments, processor 510 can be coupled with memory 530 and chipset 520. Processor 510 may also be coupled to a wireless antenna 578 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna 578 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol. [0082] In some embodiments, volatile memory 532 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 534 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0083] Memory device 530 stores information and instructions to be executed by processor 510. In one embodiment, memory 530 may also store temporary variables or other intermediate information while processor 510 is executing instructions. In the illustrated embodiment, chipset 520 connects with processor 510 via Point-to-Point (PtP or P-P) interface 517 and P-P interface 522. Chipset 520 enables processor 510 to connect to other elements in system 500. In some embodiments of the disclosure, P-P interface 517 and P-P interface 522 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used. [0084] In some embodiments, chipset 520 can be configured to communicate with processor 510, the processor N 505, display device 540, and other devices 572, 576, 574, 560, 562, 564, 566, 577, etc. Chipset 520 may also be coupled to the wireless antenna 578 to communicate with any device configured to transmit and/or receive wireless signals.

[0085] Chipset 520 connects to display device 540 via interface 526. Display 540 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 510 and chipset 520 are integrated into a single SOC. In addition, chipset 520 connects to bus 550 and/or bus 555 that interconnect various elements 574, 560, 562, 564, and 566. Bus 550 and bus 555 may be interconnected via a bus bridge 572. In one embodiment, chipset 520 couples with a non-volatile memory 560, a mass storage device(s) 562, a keyboard/mouse 564, and a network interface 566 via interface 524 and/or 504, smart TV 576, consumer electronics 577, etc.

[0086] In one embodiment, mass storage device(s) 552 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 566 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0087] While the modules shown in FIG. 5 are depicted as separate blocks within the system 500, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 516 is depicted as a separate block within processor 510, cache memory 516 or selected elements thereof can be incorporated into processor core 512.

[0088] It is noted that the system 500 described herein may be any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor packages (for example, the semiconductor packages described in connection with any of FIGS. 1-5), as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[0089] In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0090] Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0091] In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0092] According to example embodiments of the disclosure, there may be a memory device. The device may comprise: a first electrode as an anode and disposed on a substrate; a screening layer disposed on the first electrode; an active layer disposed on the first screening layer having a first porosity and a first thickness to yield a formation voltage below about 2 volts; and a second electrode as a cathode and disposed on the active layer.

[0093] Implementation may include one or more of the following features. The active layer of the device may be based on a porogen at a first weight percentage and may be based on a thermal anneal at a first temperature and a first duration. The active layer may be deposited at about 200 degrees centigrade to about 300 degrees centigrade. The first thickness may be about 1 nanometer to about 5 nanometers. The pores of the active layer may have a pore diameter of about 1 nanometer to about 8 nanometers. The active layer may comprise a silicon oxide material or a silicon oxycarbide material, the silicon oxycarbide material comprising a SiOC-1 (low density) material, SiOC-2 (high porosity) material, or a combination of SiOC-1 (low density) material and a SiOC-2 (high porosity) material. The SiOC-1 (low density) material may have a porosity of about 6% to about 8% by weight. The screening layer may have a thickness of about 1 nanometers to about 3 nanometers and may comprise a metal oxide material. The first electrode may comprise copper or silver and the second electrode may comprise tungsten, nickel, titanium, nitride, and/or palladium.

[0094] According to example embodiments of the disclosure, there may be a method. The method may comprise: depositing a first electrode on a substrate; depositing a screening layer on the first electrode; depositing, on the screening layer, an active layer having a first porosity and a first thickness to yield a formation voltage below about 2 volts; and depositing a second electrode on the active layer.

[0095] Implementation may include one or more of the following features. The method of depositing the active layer may further comprise depositing an active layer having pores with pore diameters of about 1 nanometer to about 8 nanometers. The first thickness may be about 1 nanometer to about 5 nanometers. The method of depositing the second electrode may further comprise depositing tungsten, nickel, titanium nitride, and/or palladium. The method of depositing the screening layer may comprise depositing a metal oxide material. Depositing the active layer may further comprise depositing a silicon oxide material or a silicon oxycarbide material, the materials may comprise depositing a SiOC-1

(low density) layer, a SiOC-2 (high porosity) layer, or a combination of the SiOC-1 (low density) layer and the SiOC-2 (high porosity) layer. The SiOC-1 (low density) layer may be deposited at a porosity of about 6% to about 8% by volume and may be deposited at about 200 degrees centigrade to about 300 degrees centigrade. The method may further comprise depositing a porogen at a first weight percentage during the deposition of the active layer, and thermally annealing the active layer at a first temperature and at a first duration. The method of depositing the first electrode or depositing the second electrode may further comprise a metal foil lamination technique, a physical vapor deposition technique, a chemical vapor deposition technique, a sputtering technique, or a metal paste deposition technique. The method of depositing either the active layer and/or the screening layer may further comprise a physical vapor deposition technique, a chemical vapor deposition technique, or a plasma-enhanced chemical vapor deposition technique. [0096] According to example embodiments of the disclosure, there may be an electronic device. The device may comprise a memory device, the memory device further comprising: a first electrode as an anode and disposed on a substrate; a screening layer disposed on the first electrode; an active layer disposed on the first screening layer having a first porosity and a first thickness to yield a formation voltage below about 2 volts; and a second electrode as a cathode and disposed on the active layer.

[0097] Implementation may include one or more of the following features. The active layer of the device may be based on a porogen at a first weight percentage and may be based on a thermal anneal at a first temperature and a first duration. The active layer may be deposited at about 200 degrees centigrade to about 300 degrees centigrade. The first thickness may be about 1 nanometer to about 5 nanometers. The pores of the active layer may have a pore diameter of about 1 nanometer to about 8 nanometers. The active layer may comprise a silicon oxide material or a silicon oxycarbide material, the silicon oxy carbide material comprising a SiOC-1 (low density) material, SiOC-2 (high porosity) material, or a combination of SiOC-1 (low density) material and a SiOC-2 (high porosity) material. The SiOC-1 (low density) material may have a porosity of about 6% to about 8% by weight. The screening layer may have a thickness of about 1 nanometers to about 3 nanometers and may comprise a metal oxide material. The first electrode may comprise copper or silver and the second electrode may comprise tungsten, nickel, titanium, nitride, and/or palladium.

[0098] According to example embodiments of the disclosure, there may be a semiconductor package. The semiconductor package may comprise: a substrate, a first electrode, a screening layer, an active layer, and a second electrode, wherein: the first electrode as an anode and disposed on the substrate; the screening layer disposed on the first electrode; the active layer disposed on the first screening layer having a first porosity and a first thickness to yield a formation voltage below about 2 volts; and the second electrode as a cathode and disposed on the active layer. In one embodiment, the active layer can include a silicon oxide material or a silicon oxy carbide material. In another embodiment, the silicon oxy carbide material can include a SiOC-1 (low density) material, SiOC-2 (high porosity) material, or a combination of SiOC-1 (low density) material and a SiOC-2 (high porosity) material. [0099] Implementation may include one or more of the following features.

[00100] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.

[00101] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.

[00102] While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non- limiting sense.

[00103] This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and performing any incorporated methods and processes. The patentable scope of certain embodiments of the invention is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

Claims

CLAIMS The claimed invention is:

1. A device comprising:

a substrate;

a first electrode as an anode and disposed on the substrate;

a screening layer disposed on the first electrode;

an active layer disposed on the first screening layer and having a first porosity and a first thickness to yield a formation voltage below about 2 volts; and

a second electrode as a cathode and disposed on the active layer.

2. The device of claim 1 , wherein the active layer is based on a porogen at a first weight percentage and is based on a thermal anneal at a first temperature and a first duration.

3. The device of claim 1, wherein the active layer is based on a deposition at about 200 degrees centigrade to about 300 degrees centigrade.

4. The device of claim 1 , wherein the first thickness is about 1 nanometer to about 5 nanometers.

5. The device of claim 1 , wherein the active layer has pores with pore diameters of about 1 nanometer to about 8 nanometers.

6. The device of claim 1, wherein the screening layer comprises a metal oxide material.

7. The device of claim 1, wherein the screening layer has a thickness of about 1 nanometer to about 3 nanometers.

8. The device of claim 1 , wherein the active layer comprises a silicon oxide material or a silicon oxy carbide material.

9. The device of claim 8, wherein the silicon oxycarbide material comprises a SiOC-1 (low density) material, SiOC-2 (high porosity) material, or a combination of SiOC-1 (low density) material and a SiOC-2 (high porosity) material.

10. The device of claim 9, wherein the SiOC-1 (low density) material has an porosity of about 6% to about 8% by weight.

11. The device of claim 1, wherein the second electrode comprises tungsten, nickel, titanium nitride, and/or palladium.

12. The device of claim 1, wherein the first electrode comprises copper or silver.

13. A method for fabricating a memory device, the method comprising:

depositing a first electrode on a substrate;

depositing a screening layer on the first electrode;

depositing, on the screening layer, an active layer having a first porosity and a first thickness to yield a formation voltage below about 2 volts; and

depositing a second electrode on the active layer.

14. The method of claim 13, wherein depositing the active layer further comprising depositing an active layer having pores with pore diameters of about 1 nanometer to about 8 nanometers.

15. The method of claim 13, wherein the first thickness is about 1 nanometer to about 5 nanometers.

16. The method of claim 13, wherein depositing the second electrode further comprises depositing tungsten, nickel, titanium nitride, and/or palladium.

17. The method of claim 13, wherein depositing the active layer further comprises depositing a silicon oxide material or a silicon oxycarbide material.

18. The method of claim 13, wherein depositing the screening layer comprises depositing a metal oxide material.

19. The method of claim 13, wherein depositing the active layer comprises depositing a SiOC-1 (low density) layer, a SiOC-2 (high porosity) layer, or a combination of the SiOC-

1 (low density) layer and the SiOC-2 (high porosity) layer.

20. The method of claim 19, wherein depositing a SiOC-1 (low density) layer comprises depositing the SiOC-1 (low density) layer at a porosity of about 6% to about 8% by volume.

21. The method of claim 19, wherein depositing a SiOC-1 (low density) layer comprises depositing the SiOC-1 (low density) layer at about 200 degrees centigrade to about 300 degrees centigrade.

22. The method of claim 13, further comprising depositing a porogen at a first weight percentage during the deposition of the active layer, and thermally annealing the active layer at a first temperature and at a first duration.

23. A semiconductor package, comprising:

a substrate, a first electrode, a screening layer, an active layer, and a second electrode, wherein:

the first electrode as an anode and disposed on the substrate;

the screening layer disposed on the first electrode;

the active layer disposed on the first screening layer having a first porosity and a first thickness to yield a formation voltage below about 2 volts; and

the second electrode as a cathode and disposed on the active layer.

24. The semiconductor package of claim 23, wherein the active layer comprises a silicon oxide material or a silicon oxy carbide material.

25. The semiconductor package of claim 24, wherein the silicon oxycarbide material comprises a SiOC-1 (low density) material, SiOC-2 (high porosity) material, or a combination of SiOC-1 (low density) material and a SiOC-2 (high porosity) material.