WO2018125079A1

WO2018125079A1 - Systems, methods and devices for creating alignment features or registration features

Info

Publication number: WO2018125079A1
Application number: PCT/US2016/068874
Authority: WO
Inventors: Kevin E. HUGGINS
Original assignee: Intel Corporation
Priority date: 2016-12-28
Filing date: 2016-12-28
Publication date: 2018-07-05

Abstract

An alignment mark or a registration mark can be formed from a combination of Self-Aligned Via patterns interacting with a pre-patterned and unfilled grating. During etch, the via pattern edge parallel to the long axis of the pre-patterned and unfilled grating is formed by the grating pattern, making this edge suitable for a grating alignment mark. Post via etch processing and metalization of the vias and grating pattern, the position of an array of the metal filled vias can be detected optically with standard alignment and metrology optics using visible light. The metalized Self-Aligned Via pattern is formed below the metalized grating where the vias are protected from integrated process interactions with polish and spin-on coat process variations.

Description

SYSTEMS, METHODS AND DEVICES FOR CREATING ALIGNMENT FEATURES OR

REGISTRATION FEATURES

Technical Field

[0001] The present disclosure relates to semiconductor construction and more specifically creating alignment features or registration features.

Brief Description of the Drawings

[0002] FIG. 1 is a top down schematic of a wide gap within a uniform grating formed in resist consistent with embodiments disclosed herein.

[0003] FIG. 2 is a side view schematic post etch of the pattern transferred into the underlying film forming a wide trench consistent with embodiments disclosed herein.

[0004] FIG. 3 is a side view schematic of spin-on film thickness variation across a wide trench consistent with embodiments disclosed herein.

[0005] FIG. 4 is a side view schematic of post metalization and polish non-uniformity across the wide metal filled trench consistent with embodiments disclosed herein.

[0006] FIG. 5 a top down schematic of a wide wall within a uniform grating formed in resist consistent with embodiments disclosed herein.

[0007] FIG. 6 is a side view schematic post etch of a pattern transferred into the underlying film to form a wide wall consistent with embodiments disclosed herein.

[0008] FIG. 7 is a side view schematic of spin-on film thickness variation across the wide wall consistent with embodiments disclosed herein.

[0009] FIG. 8 is a side view schematic post metalization and polish of film thickness non- uniformity across the wide non-metalized wall consistent with embodiments disclosed herein.

[0010] FIG. 9 is a top down schematic of a uniform grating etched into an oxide film consistent with embodiments disclosed herein.

[0011] FIG. 10 is top down schematic of vias patterned over a small area of grating which will form a mark of submerged Self-Aligned Vias consistent with embodiments disclosed herein. [0012] FIG. 11 is a top down schematic of the Self-Aligned Via pattern post via etch consistent with embodiments disclosed herein.

[0013] FIG. 12 is a top down schematic post metalization of the Self-Aligned Vias and metal grating forming a mark comprised by columns of vias consistent with embodiments disclosed herein.

[0014] FIG. 13 is a side view schematic of vias patterned over a small span of grating which will form a mark comprised of submerged Self-Aligned Vias consistent with embodiments disclosed herein.

[0015] FIG. 14 is a side view schematic of the vias shown in FIG. 13 post via etch consistent with embodiments disclosed herein.

[0016] FIG. 15 is a side view schematic post metalization of the Self- Aligned Vias and metal grating forming a mark comprised of columns of vias consistent with embodiments disclosed herein.

[0017] FIG. 16 is a top down schematic of vias patterned over a wide area of grating to form a mark from a void of submerged Self-Aligned Vias consistent with embodiments disclosed herein.

[0018] FIG. 17 is a top down schematic of the Self- Aligned Via pattern post via etch consistent with embodiments disclosed herein.

[0019] FIG. 18 is a top down schematic post metalization of the Self-Aligned Vias and metal grating forming a mark comprised by the absence of vias consistent with embodiments disclosed herein.

[0020] FIG. 19 is a side view schematic of vias patterned over a large span of grating (except the center) forming a mark comprised of the absence of submerged Self-Aligned Vias consistent with embodiments disclosed herein.

[0021] FIG. 20 is a side view schematic of the vias shown in FIG. 19 post via etch consistent with embodiments disclosed herein.

[0022] FIG. 21 is a side view schematic post metalization of the Self- Aligned Vias and metal grating forming a mark comprised by the absence of vias consistent with embodiments disclosed herein.

[0023] FIG. 22 is a top view schematic of a grating for use with a Self-Aligned Via pattern with dual damascene patterning with pitch division consistent with embodiments disclosed herein.

[0024] FIG. 23 is a top view schematic of a grating with pitch division spacer around resist consistent with embodiments disclosed herein. [0025] FIG. 24 is a top view schematic of a grating after the resist has been removed consistent with embodiments disclosed herein.

[0026] FIG. 25 is a top view schematic of via selection over a grating consistent with embodiments disclosed herein.

[0027] FIG. 26 is a top view schematic of the metal filled vias and metal filled grating consistent with embodiments disclosed herein.

[0028] FIG. 27 is a flow chart illustrating a method for creating an alignment mark or a registration mark using Self-Aligned Vias within a uniform grating consistent with embodiments disclosed herein.

[0029] FIG. 28 illustrates an interposer that includes one or more embodiments of the disclosed herein.

[0030] FIG. 29 is a diagram of a computing device consistent with embodiments disclosed herein.

Detailed Description

[0031] Described herein are systems and methods of creating an alignment mark or a registration mark using Self-Aligned Vias within a uniform grating. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the embodiments may be practiced with some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0032] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the embodiments; however, the order of description should not be construed to imply that these operations are order dependent. In particular, these operations need not be performed in the order of presentation.

[0033] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0034] Implementations of the embodiments may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present

embodiments.

[0035] A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the embodiments, the MOS transistors may be planar transistors, non- planar transistors, or a combination of both. Non-planar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all- around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate planar transistors, it should be noted that the embodiments may also be carried out using non-planar transistors.

[0036] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si02) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0037] The gate electrode layer is formed on the gate dielectric layer and may include at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer may include a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

[0038] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0039] In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may include a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the embodiments, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0040] In some implementations of the embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0041] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0042] One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si02), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as

silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[0043] Optical alignment mark designs are susceptible to local process variations on the micron scale which can impact local pattern defect formation and optical alignment performance especially for spin-on coat integrated processing and polishing. The process sensitivity of alignment marks designs can be addressed with Self-Aligned Via (SAV) patterning.

[0044] It should be noted that the description below describes marks, features, alignment marks, alignment features, registration marks and/or registration features. The process and/or product formed from a combination of Self-Aligned Via patterns interacting with a pre- patterned and unfilled grating can be used to create such marks, features, alignment marks, alignment features, registration marks and/or registration features. For clarity, the description may call out a single use. However, it should be recognized that marks or features can be used for alignment or registration depending on the application. For example, registration can be a process to find common features for placing a body in a coordinate system, such as centerline to centerline comparisons within an array of targets of a wafer. In another example, alignment can be a process to match two coordinate systems, such as placement of a wafer and its wafer pattern with respect to a lithography printer. For example, the entire wafer pattern, often referred to as "a grid," can be displaced relative the wafer center. In some embodiments, the lithography printer aligns in three operations: i) coarse alignment to the wafer perimeter to within about 10 micrometers and ii) search alignment using an alignment mark to within about 1 micrometer and iii) fine alignment to the wafer pattern or "grid" to within several nanometers. In many examples, an alignment of the lithography printer's coordinate system to the wafer grid is more important rather than to the wafer center.

[0045] An alignment mark (also known as an alignment feature) or a registration mark (also known as a registration feature) is formed from a combination of Self-Aligned Via patterns interacting with a pre-patterned and unfilled grating. During etch, the via pattern edge parallel to the long axis of the pre-patterned and unfilled grating is formed by the grating pattern, making this edge suitable for a grating alignment mark. Post via etch processing and metalization of the vias and grating pattern, the position of an array of the metal filled vias can be detected optically with standard alignment and metrology optics in visible, near infrared and/or infra-red light spectrum. An optical difference between the via pattern within the uniform grating and uniform grating outside of the via pattern is detectable. The metalized Self-Aligned Via pattern is formed below the metalized grating where the vias are protected from integrated process interactions with polish and spin-on coat process variations.

[0046] This process for forming alignment and/or registration marks can be more robust to process interactions such as polish and local spin-on coat thickness variation than other processes such as wide walls or wide trenches within a grating. A feature (e.g., alignment feature or registration feature) has a uniform metalized grating pattern at its top surface which polishing cannot locally distinguish as unique above the alignment mark and polish differently than the surroundings. Additionally, a substrate having undergone this process has a uniform thickness from spin-coated films above the alignment mark compared other processes such as wide walls or wide trenches within a grating. An improved process uniformity of the alignment mark can improve an optical quality of the alignment signal over a wider range of process variation compared to other processes such as wide walls or wide trenches within a grating.

[0047] Optical alignment marks are created by forming a pattern disruption (or a mark) from a uniform background pattern as shown. In FIGs. 1-8, examples of mark thickness non- uniformity is shown on semiconductor substrates 100, 200, 300, 400, 500, 600, 700 and 800. For instance, in FIG. 1 a wide gap 106 in a uniform grating is shown, disrupting the uniform background grating (including a resist grating 104 and trenches or spaces 102) to create an optical alignment mark. Post etch in FIG. 2, the resist pattern is transferred into an underlying film 208, forming the wide gap 106 (or trench). Post spin-on film processing (shown in FIG. 3), spin-on film 311 thickness is non-uniform across the mark (e.g., dip 310) due to local volumetric differences in the mark compared to the surrounding uniform grating. FIG. 3 shows the spin-on film 311 thinning in the dip 310 above the wide trench 106. In results from post metalization (e.g., metal fill 412 in the spaces 102) and polish processing shown in FIG. 4, the final mark (or the wide gap 106) shows non-uniformities 410 in the mark film thickness. When imaged by an optical alignment system, this mark thickness non- uniformity 410 across the mark (or the wide gap 106) can deceive the optical alignment system finding a true position of the mark, resulting in overlay error.

[0048] In another example in FIG. 5, a wide wall 506 having a width 510 in a uniform grating is shown, disrupting the uniform background grating (including the resist grating 104 and the trenches or spaces 102) to create an optical alignment mark. Post etch, the resist pattern is transferred into an underlying film 608, forming the wide wall 506 as in FIG. 6. Post spin-on film processing (shown in FIG. 7), spin-on film 711 thickness is non-uniform across the mark (e.g., bump 712) due to local volumetric differences in the mark compared to the surrounding uniform grating. The spin-on film 711 thickening occurs in the bump 712 above the wide wall 506 in FIG. 7. Post metalization (e.g., metal fill 812 in the spaces 102) and polish processing (shown in FIG. 8), the final mark shows non-uniformities 814 in the mark film thickness. When imaged by an optical alignment system, this mark thickness non- uniformity 814 across the mark can deceive the optical alignment system finding a true position of the mark, resulting in overlay error.

[0049] FIGs. 9-26 describe using patterning Self-Aligned Vias (SAV) into a uniform background grating to form an alignment or a registration mark in a film 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500 and 2600. Although the via marks are submerged below a metal grating, a film thickness of the metal and via layers is sufficiently thin that visible wavelength light can penetrate the metal and/or oxide pattern below the surface allowing the via arrays to be detected optically and useful for optical alignment or registration measurements. An advantage is that a top surface of the mark includes a uniform grating, making the alignment or registration mark less susceptible and/or immune to localized spin-on film thickness variation and localized polish sensitivity. This process benefits from greater process robustness with little to no optical edge detection deception compared to other methods including wide gap or wide trench patterns. Inclusions of vias in an area form a deeper trench, whereas exclusions of vias from an area form a shallower trench. The film 900,1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500 and 2600 can be an oxide layer or optically transparent dielectric layer. In some embodiments, the vias form a grid or an array.

[0050] For example in FIG. 9, which shows an inclusive pattern of vias in an area, a uniform background grating is shown post etch, where the uniform grating pattern has been transferred into an underlying film 900 with a formally resist grating 904 and a formally resist space 902. In FIG. 10, vias are patterned in resist (e.g., a via pattern 1006) for a Self- Aligned Via process as shown forming a narrow via array in FIG. 10. In FIG. 11 and post etch, the via patterns 1006 are transferred into the substrate where the vertical edges of the etched via patterns (i.e., vias 1108) are defined by the uniform background grating formed from the formally resist grating 904 and the formally resist space 902. These via arrays (formed from the vias 1108) form alignment marks within the background grating mask layer. In FIG. 12 and post metalization, the marks (e.g., metal filled vias 1208 within metal filled grating 1210) have a localized increase in metal depth and metal density that form optical alignment structures.

[0051] Side view schematics of the inclusive process are shown in FIGs. 13-15. FIG. 13 shows via patterning using the inclusive via pattern 1006 that places resist around an area to receive vias in an underlying film 1308. FIG. 14 shows the vias 1108 having been etched in the area, while the grating remains outside of the area. FIG. 15 shows the metal filled vias 1208 and the metal filled grating 1210 after metalization, which includes a planar or approximately planar surface and a uniform or approximately uniform surface.

[0052] In another example starting in FIG. 16, the uniform grating (shown in FIG. 9) has vias that are patterned in resist (e.g., the via pattern 1006) outside of an area for a Self-Aligned Via process as shown forming a via array. In FIG. 17 and post etch, the via patterns 1006 are transferred into the substrate where the vertical edges of the etched via patterns (i.e., the vias 1108) are defined by the uniform background grating formed from the formally resist grating 904 and the formally resist space 902. The absence of these via arrays (formed from the vias 1108) within an area forms alignment marks within the background grating mask layer. In FIG. 18 and post metalization, the marks (e.g., the metal filled vias 1208 within the metal filled grating 1210) have a localized difference (i.e., less) in metal depth and metal density that form optical alignment structures.

[0053] Side view schematics of the exclusive process are shown in FIGs. 19-21. FIG. 19 shows via patterning using the exclusive via pattern 1006 that places resist within an area to receive vias (to mask the area from receiving vias). FIG. 20 shows the vias 1108 having been etched outside the area, while the grating remains inside of the area. FIG. 21 shows the metal filled vias 1208 and the metal filled grating 1210 after metalization, which includes a planar or approximately planar surface and a uniform or approximately uniform surface.

[0054] FIGs. 22-26 show a dual damascene process with pitch division that uses Self- Aligned Vias to form alignment marks and/or registration marks. In FIG. 22, a resist grating 2204 is deposited on a film to form resist spaces 2202 between the resist grating 2204. In FIG. 23, a spacer 2306 is grown next to the resist grating 2204. In FIG. 24, the resist grating 2204 is removed while leaving the spacer 2306 to form a backbone 2408 space and a complement 2410 space between the spacers 2306. In FIG. 25, a via selection 2510 is performed, such that a via edge 2512 lies on the spacer 2306. By placing the via edge 2512 on the spacer 2306, the via is forced to align with the edge of the spacer 2306, as a via cannot be formed on the spacer 2306. This results in a Self-Aligned Via. In FIG. 26, post metalization is shown (which occurs post etch). The backbone 2408 space and the complement 2410 space are filled with metal. The via selection 2510 is filled with metal to form metal filled vias 2614 with a via edge 2618 that is defined by the spacer 2306.

Alignment marks or registration marks (e.g., the metal filled vias 2614 within metal filled grating 2616) have a localized difference (i.e., more) in metal depth and metal density that form optical alignment structures.

[0055] FIG. 27 shows a method 2700 for creating an alignment mark or a registration mark using Self- Aligned Vias within a uniform grating. The method 2700 can be performed by an etching and deposition system, such as a semiconductor processing system used to prepare silicon wafers. In block 2702, a substrate has a uniform grating etched with it. In block 2704, a feature area is selected within the uniform grating, the feature area comprising the alignment feature or the registration feature. In block 2706, the system performs a via pattern at the selected feature area. In block 2708, the system etches the via pattern. In block 2710, the system fills the via pattern and grating with metal to form the alignment feature or the registration feature.

[0056] It should be recognized that alignment or registration marks can be uniform or nonuniform. In alignment mark design, marks can be formed using pitch division that results in a non-uniform grating. In a uniform final pitch division grating example, a resist backbone of 40 nm width pitched at 120 nm is drawn. The pitch division spacer width is 20 nm, which grows about the resist backbone. After resist removal, the final pitch division grating sequence would be the following where "sr" = spacer: 20 nm sr, 40 nm space formally backbone, 20 nm sr, 40 nm remaining space. 20+40+20+40 = 120 nm pitch. The final grating is simply expressed as 20 nm sr @ 60 nm pitch. In a nonuniform final pitch division grating example, a resist backbone of 40 nm with pitch at 160 nm with a pitch division spacer width = 20 nm is drawn. Then the final pitch division grating sequence would be: 20 nm sr, 40 nm space formally backbone, 20 nm sr, and 80 nm remaining space. 20+40+20+80 = 160 nm pitch. The final grating forms a compound structure of 20 sr / 40 space / 20 sr / 80 space.

[0057] FIG. 28 illustrates an interposer 2800 that includes one or more embodiments described herein. The interposer 2800 is an intervening substrate used to bridge a first substrate 2802 to a second substrate 2804. The first substrate 2802 may be, for instance, an integrated circuit die. The second substrate 2804 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 2800 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, the interposer 2800 may couple an integrated circuit die to a ball grid array (BGA) 2806 that can subsequently be coupled to the second substrate 2804. In some embodiments, the first and second substrates 2802/2804 are attached to opposing sides of the interposer 2800. In other embodiments, the first and second substrates 2802/2804 are attached to the same side of the interposer 2800. And in further embodiments, three or more substrates are interconnected by way of the interposer 2800.

[0058] The interposer 2800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further

implementations, the interposer 2800 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[0059] The interposer 2800 may include metal interconnects 2808 and vias 2810, including but not limited to through-silicon vias (TSVs) 2812. The interposer 2800 may further include embedded devices 2814, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 2800.

[0060] In accordance with some embodiments, apparatuses or processes disclosed herein may be used in the fabrication of the interposer 2800.

[0061] FIG. 29 illustrates a computing device 2900 in accordance with one or more embodiments. The computing device 2900 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices. The components in the computing device 2900 include, but are not limited to, an integrated circuit die 2902 and at least one

communications logic unit 2908. In some implementations the communications logic unit 2908 is fabricated within the integrated circuit die 2902 while in other implementations the communications logic unit 2908 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 2902. The integrated circuit die 2902 may include a CPU 2904 as well as on-die memory 2906, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT- MRAM). In one embodiment, the integrated circuit die 2902 is formed from silicon from a silicon wafer. The silicon wafer can include registration features and/or alignment features.

[0062] Computing device 2900 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die.

These other components include, but are not limited to, volatile memory 2910 (e.g., DRAM), non-volatile memory 2912 (e.g., ROM or flash memory), a graphics processing unit 2914 (GPU), a digital signal processor 2916, a crypto processor 2942 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 2920, at least one antenna 2922 (in some implementations two or more antennas may be used), a display or a touchscreen display 2924, a touchscreen controller 2926, a battery 2929 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 2928, a compass 2930, a motion coprocessor or sensors 2932 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 2934, a camera 2936, user input devices 2938 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 2940 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 2900 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 2900 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 2900 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

[0063] The communications logic unit 2908 enables wireless communications for the transfer of data to and from the computing device 2900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The

communications logic unit 2908 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 2900 may include a plurality of communications logic units 2908. For instance, a first communications logic unit 2908 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and

Bluetooth and a second communications logic unit 2908 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0064] The processor 2904 of the computing device 2900 includes one or more alignment or registration features that are formed in accordance with embodiments described herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0065] The communications logic unit 2908 may also include one or more alignment or registration features that are formed in accordance with embodiments described herein.

[0066] In further embodiments, another component housed within the computing device 2900 may contain one or more alignment or registration features that are formed in accordance with embodiments described herein. [0067] In various embodiments, the computing device 2900 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a

dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 2900 may be any other electronic device that processes data.

Examples

[0068] The following examples pertain to further embodiments.

[0069] Example 1 is a substrate. The substrate has an alignment feature or a registration feature including a grating etched on the substrate, and a via pattern forming the alignment feature or the registration feature within the grating, the via pattern defining a grid of vias. The substrate has an alignment feature or a registration feature including metal within the via pattern and grating providing an optical difference between the via pattern within the grating and grating outside of the via pattern.

[0070] Example 2 is the substrate of Example 1, where the grating is a uniform grating.

[0071] Example 3 is the substrate of Example 1, where the grating is a non-uniform grating.

[0072] Example 4 is the substrate of Example 1, where the substrate is an oxide film.

[0073] Example 5 is the substrate of Example 1, where the substrate is an optically transparent dielectric film.

[0074] Example 6 is the substrate of Example 1, where the via pattern results in a metal depth and metal density difference between the via pattern and grating.

[0075] Example 7 is the substrate of Example 6, where the via pattern is an inclusion of vias for a deeper trench for the metal within the via pattern than the grating.

[0076] Example 8 is the substrate of Example 6, where the via pattern is an exclusion of vias for a more shallow trench for the metal within the via pattern than the grating.

[0077] Example 9 is the substrate of Example 1, where the substrate with the alignment feature further includes an approximately planar surface.

[0078] Example 10 is the substrate of Example 1, further including a spin-on coat deposited on the substrate, the spin-on coat having an approximately uniform thickness.

[0079] Example 11 is the substrate of Example 10, where the spin-on coat deposited on the substrate has been polished and forms a second approximately uniform thickness. [0080] Example 12 is the substrate of any of Examples 1-11, where the optical difference between the grating and is detectable using visible, near infra-red and infra-red light spectrum.

[0081] Example 13 is a method. The method forms an alignment feature or a registration feature including etching a grating in a substrate, selecting a feature area within the grating, the feature area including the alignment feature or the registration feature, and performing a via pattern at the selected feature area. The method forms an alignment feature or a registration feature including etching the via pattern, and filling the via pattern and grating with metal to form the alignment feature or the registration feature.

[0082] Example 14 is the method of Example 13, where performing the via pattern further includes using a Self-Aligned Via patterning process.

[0083] Example 15 is the method of Example 13, where performing the via pattern further includes excluding vias from the feature area while including vias within the grating.

[0084] Example 16 is the method of Example 15, where excluding the vias from the feature area while including the vias within the grating further includes masking the feature area.

[0085] Example 17 is the method of Example 13, where performing the via pattern further includes including the vias within the feature area while excluding vias within the grating.

[0086] Example 18 is the method of Example 17, where including the vias within the feature area while excluding the vias within the grating further includes masking the grating outside of the feature area.

[0087] Example 19 is the method of Example 13, where filling the via pattern and grating with the metal further includes forming an approximately planar surface.

[0088] Example 20 is the method of Example 19, further including depositing an oxide layer or an optically transparent dielectric film on the approximately planar surface using a spin process.

[0089] Example 21 is the method of Example 20, where the approximately planar surface enables depositing an approximately uniform oxide layer or an optically transparent dielectric film.

[0090] Example 22 is the method of Example 13, further including using an optical metrology to align a system with the alignment feature or the registration feature.

[0091] Example 23 is the method of Example 13, where filling the via pattern further includes using a dual damascene process to fill vias from the via pattern and grating with the metal. [0092] Example 24 is an apparatus including a manner to perform a method as exemplified in any of Examples 13-23.

[0093] Example 25 is a machine readable medium including code, when executed, to cause a machine to perform the method of any one of Examples 13-23.

[0094] Example 26 is a computing device. The computer device includes a processor mounted on a substrate, a memory unit capable of storing data, a graphics processing unit, and an antenna within the computing device. The computer device includes a display on the computing device, a battery within the computing device, a power amplifier within the processor. The computer device includes a voltage regulator within the processor, where the processor includes a grating etched on a layer, a via pattern forming an alignment feature or registration feature within the grating, and metal within the via pattern and grating providing an optical difference between the via pattern within the grating and grating outside of the via pattern.

[0095] Example 27 is the computing device of Example 26,. where the layer is an oxide layer of a silicon die of the processor.

[0096] Example 28 is the computing device of Example 26, where via pattern is a self- aligned via pattern forming a grid of vias.

[0097] Example 29 is the computing device of Example 26, where the metal is deposited using a dual damascene process.

[0098] Embodiments and implementations of the systems and methods described herein may include various operations, which may be embodied in machine-executable instructions to be executed by a computer system. A computer system may include one or more general- purpose or special-purpose computers (or other electronic devices). The computer system may include hardware components that include specific logic for performing the operations or may include a combination of hardware, software, and/or firmware.

[0099] Various techniques, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD- ROMs, hard drives, magnetic or optical cards, solid-state memory devices, a nontransitory computer-readable storage medium, or any other machine-readable storage medium wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the various techniques. In the case of program code execution on programmable computers, the computing device may include a processor, a storage medium readable by the processor (including volatile and nonvolatile memory and/or storage elements), at least one input device, and at least one output device. The volatile and nonvolatile memory and/or storage elements may be a RAM, an EPROM, a flash drive, an optical drive, a magnetic hard drive, or other medium for storing electronic data. One or more programs that may implement or utilize the various techniques described herein may use an application programming interface (API), reusable controls, and the like. Such programs may be implemented in a high-level procedural or an object-oriented programming language to communicate with a computer system. However, the program(s) may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language, and combined with hardware implementations.

[00100] Each computer system includes one or more processors and/or memory; computer systems may also include various input devices and/or output devices. The processor may include a general purpose device, such as an Intel®, AMD®, or other "off-the-shelf microprocessor. The processor may include a special purpose processing device, such as ASIC, SoC, SiP, FPGA, PAL, PLA, FPLA, PLD, or other customized or programmable device. The memory may include static RAM, dynamic RAM, flash memory, one or more flip-flops, ROM, CD-ROM, DVD, disk, tape, or magnetic, optical, or other computer storage medium. The input device(s) may include a keyboard, mouse, touch screen, light pen, tablet, microphone, sensor, or other hardware with accompanying firmware and/or software. The output device(s) may include a monitor or other display, printer, speech or text synthesizer, switch, signal line, or other hardware with accompanying firmware and/or software.

[00101] It should be understood that many of the functional units described in this specification may be implemented as one or more components, which is a term used to more particularly emphasize their implementation independence. For example, a component may be implemented as a hardware circuit comprising custom very large scale integration (VLSI) circuits or gate arrays, or off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like.

[00102] Components may also be implemented in software for execution by various types of processors. An identified component of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions, which may, for instance, be organized as an object, a procedure, or a function. Nevertheless, the executables of an identified component need not be physically located together, but may comprise disparate instructions stored in different locations that, when joined logically together, comprise the component and achieve the stated purpose for the component. [00103] Indeed, a component of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Similarly, operational data may be identified and illustrated herein within components, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network. The components may be passive or active, including agents operable to perform desired functions.

[00104] Several aspects of the embodiments described will be illustrated as software modules or components. As used herein, a software module or component may include any type of computer instruction or computer-executable code located within a memory device. A software module may, for instance, include one or more physical or logical blocks of computer instructions, which may be organized as a routine, program, object, component, data structure, etc., that perform one or more tasks or implement particular data types. It is appreciated that a software module may be implemented in hardware and/or firmware instead of or in addition to software. One or more of the functional modules described herein may be separated into sub-modules and/or combined into a single or smaller number of modules.

[00105] In certain embodiments, a particular software module may include disparate instructions stored in different locations of a memory device, different memory devices, or different computers, which together implement the described functionality of the module. Indeed, a module may include a single instruction or many instructions, and may be distributed over several different code segments, among different programs, and across several memory devices. Some embodiments may be practiced in a distributed computing environment where tasks are performed by a remote processing device linked through a communications network. In a distributed computing environment, software modules may be located in local and/or remote memory storage devices. In addition, data being tied or rendered together in a database record may be resident in the same memory device, or across several memory devices, and may be linked together in fields of a record in a database across a network.

[00106] Reference throughout this specification to "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment described herein. Thus, appearances of the phrase "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment.

[00107] As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on its presentation in a common group without indications to the contrary. In addition, various embodiments and examples may be referred to herein along with alternatives for the various components thereof. It is understood that such embodiments, examples, and alternatives are not to be construed as de facto equivalents of one another, but are to be considered as separate and autonomous representations.

[00108] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of materials, frequencies, sizes, lengths, widths, shapes, etc., to provide a thorough understanding of embodiments described herein. One skilled in the relevant art will recognize, however, that the embodiments described herein may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the

embodiments.

[00109] It should be recognized that the systems described herein include descriptions of specific embodiments. These embodiments can be combined into single systems, partially combined into other systems, split into multiple systems or divided or combined in other ways. In addition, it is contemplated that parameters/attributes/aspects/etc. of one embodiment can be used in another embodiment. The parameters/attributes/aspects/etc. are merely described in one or more embodiments for clarity, and it is recognized that the parameters/attributes/aspects /etc. can be combined with or substituted for

parameters/attributes/etc. of another embodiment unless specifically disclaimed herein.

[00110] The above description of illustrated implementations of the embodiments described herein, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. While specific implementations of, and examples for, the embodiments are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the embodiments, as those skilled in the relevant art will recognize. It should be noted that there are many alternative ways of implementing both the processes and apparatuses described herein. Accordingly, the present embodiments are to be considered illustrative and not restrictive, and the embodiments described herein are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

[00111] Those having skill in the art will appreciate that many changes may be made to the details of the above-described embodiments without departing from the underlying principles described herein. The scope of the embodiments should, therefore, be determined only by the following claims.

Claims

Claims:

1. A substrate with an alignment feature or a registration feature comprising:

a grating etched on the substrate;

a via pattern forming the alignment feature or the registration feature within the grating, the via pattern defining a grid of vias; and

metal within the via pattern and grating providing an optical difference between the via pattern within the grating and grating outside of the via pattern.

2. The substrate of claim 1, wherein the grating is a uniform grating.

3. The substrate of claim 1, wherein the grating is a non-uniform grating.

4. The substrate of claim 1, wherein the substrate is an oxide film.

5. The substrate of claim 1, wherein the substrate is an optically transparent dielectric film.

6. The substrate of claim 1, wherein the via pattern results in a metal depth and metal density difference between the via pattern and grating.

7. The substrate of claim 6, wherein the via pattern is an inclusion of vias for a deeper trench for the metal within the via pattern than the grating.

8. The substrate of claim 6, wherein the via pattern is an exclusion of vias for a more shallow trench for the metal within the via pattern than the grating.

9. The substrate of claim 1, wherein the substrate with the alignment feature further comprises an approximately planar surface.

10. The substrate of claim 1, further comprising a spin-on coat deposited on the substrate, the spin-on coat having an approximately uniform thickness.

11. The substrate of claim 10, wherein the spin-on coat deposited on the substrate has been polished and forms a second approximately uniform thickness.

12. The substrate of any of claims 1-11, wherein the optical difference between the grating and is detectable using visible, near infra-red and infra-red light spectrum.

13. A method of forming an alignment feature or a registration feature comprising: etching a grating in a substrate;

selecting a feature area within the grating, the feature area comprising the alignment feature or the registration feature;

performing a via pattern at the selected feature area;

etching the via pattern; and

filling the via pattern and grating with metal to form the alignment feature or the registration feature.

14. The method of claim 13, wherein performing the via pattern further comprises using a Self-Aligned Via patterning process.

15. The method of claim 13, wherein performing the via pattern further comprises excluding vias from the feature area while including vias within the grating.

16. The method of claim 15, wherein excluding the vias from the feature area while including the vias within the grating further comprises masking the feature area.

17. The method of claim 13, wherein performing the via pattern further comprises including the vias within the feature area while excluding vias within the grating.

18. The method of claim 17, wherein including the vias within the feature area while excluding the vias within the grating further comprises masking the grating outside of the feature area.

19. The method of claim 13, wherein filling the via pattern and grating with the metal further comprises forming an approximately planar surface.

20. The method of claim 19, further comprising depositing an oxide layer or an optically transparent dielectric film on the approximately planar surface using a spin process.

21. The method of claim 20, wherein the approximately planar surface enables depositing an approximately uniform oxide layer or an optically transparent dielectric film.

22. The method of claim 13, further comprising using an optical metrology to align a system with the alignment feature or the registration feature.

23. The method of claim 13, wherein filling the via pattern further comprises using a dual damascene process to fill vias from the via pattern and grating with the metal.

24. An apparatus comprising means to perform a method as claimed in any of claims

13-23.

25. A machine readable medium including code, when executed, to cause a machine to perform the method of any one of claims 13-23.

26. A computing device comprising:

a processor mounted on a substrate;

a memory unit capable of storing data;

a graphics processing unit;

an antenna within the computing device;

a display on the computing device;

a battery within the computing device;

a power amplifier within the processor; and

a voltage regulator within the processor; wherein the processor comprises:

a grating etched on a layer;

a via pattern forming an alignment feature or registration feature within the grating; and

27. The computing device of claim 26,. wherein the layer is an oxide layer of a silicon die of the processor.

28. The computing device of claim 26, wherein via pattern is a self-aligned via pattern forming a grid of vias.

29. The computing device of claim 26, wherein the metal is deposited using a dual damascene process.