WO2018125064A1 - Deeply scaled metal interconnects with high aspect ratio - Google Patents

Deeply scaled metal interconnects with high aspect ratio Download PDF

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Publication number
WO2018125064A1
WO2018125064A1 PCT/US2016/068763 US2016068763W WO2018125064A1 WO 2018125064 A1 WO2018125064 A1 WO 2018125064A1 US 2016068763 W US2016068763 W US 2016068763W WO 2018125064 A1 WO2018125064 A1 WO 2018125064A1
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WIPO (PCT)
Prior art keywords
dielectric material
metal
layer
semiconductor fins
interconnects
Prior art date
Application number
PCT/US2016/068763
Other languages
French (fr)
Inventor
En-Shao LIU
Everett S. CASSIDY-COMFORT
Joodong Park
Chen-Guan LEE
Walid M. Hafez
Chia-Hong Jan
Original Assignee
Intel Corporation
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Priority to PCT/US2016/068763 priority Critical patent/WO2018125064A1/en
Publication of WO2018125064A1 publication Critical patent/WO2018125064A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Definitions

  • Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to integrated circuits with deeply scaled metal interconnects having a high aspect ratio.
  • Interconnects are essential components in complementary metal-oxide- semiconductor (CMOS) very large scale integration (VLSI) technology.
  • CMOS complementary metal-oxide- semiconductor
  • VLSI very large scale integration
  • the interconnects provide power and ground connections, as well as carry clock signals, data signals, and other electrical signals to various circuit blocks of the integrated circuit.
  • the dimensions of interconnects must also decrease.
  • Figure 1 is a flow diagram that illustrates a process for forming an interconnect layer of an integrated circuit (IC) structure, in accordance with various embodiments.
  • FIGS 2A-2E illustrate cross-sectional views of an IC structure subsequent to various operations of the process shown in Figure 1 , in accordance with various embodiments.
  • Figures 3A-D illustrate cross-sectional views of another IC structure subsequent to various operations of another process for forming an interconnect layer, in accordance with various embodiments.
  • Figure 4 is a cross-sectional view of another IC structure including an interconnect layer, in accordance with various embodiments.
  • Figure 5 is a cross-sectional view of another IC structure including an interconnect layer, in accordance with various embodiments.
  • Figure 6 is cross-sectional view of an interposer implementing one or more embodiments of the present disclosure.
  • Figure 7 is schematic view of a computing device built in accordance with an embodiment of the present disclosure.
  • Embodiments of the present disclosure describe techniques and configurations associated with an integrated circuit (IC) structure including an interconnect layer.
  • semiconductor fins may be formed on an underlying layer.
  • a first dielectric material may be formed on the sidewalls of the semiconductor fins, and a second dielectric material may be formed between the semiconductor fins and the portions of the first dielectric material.
  • semiconductor fins may be removed and replaced with a metal to form respective interconnects.
  • the first dielectric material may serve as an etch stop layer for removal of the semiconductor fins.
  • the second dielectric material may have a lower dielectric constant than the first dielectric material to reduce capacitance between the interconnects.
  • the process described herein may enable the formation of trenches with a higher aspect ratio than prior techniques.
  • the higher aspect ratio may enable the width of the trenches to be reduced while maintaining a low resistance (the resistance may be based on the cross-sectional area of the trench). That is, compared to prior trenches, the width of the trenches may be reduced and the height may be increased.
  • the reduced width of the trenches may be useful when used with active circuit devices (e.g., transistors) with reduced feature size.
  • over refers to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • Implementations of the invention may be formed or carried out on a substrate, such as a semiconductor substrate.
  • a substrate such as a semiconductor substrate.
  • semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium
  • any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.
  • MOSFET metal-oxide-semiconductor field-effect transistors
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor.
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode when viewed as a cross-section of the transistor along the source-channel-drain direction, may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions.
  • An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process.
  • the substrate may first be etched to form recesses at the locations of the source and drain regions.
  • the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • ILD interlayer dielectrics
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.
  • dielectric materials examples include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.
  • Figure 1 is a flow chart illustrating a process 100 for fabricating an IC structure in accordance with various embodiments.
  • Figures 2A-2E illustrate an IC structure 200 at various stages of the process 100, in accordance with various embodiments. Accordingly, the process 100 will be described with reference to the IC structure 200 shown in Figures 2A-2E. Similar fabrication principles to those described herein may be used to form IC structures with other configurations than that shown in FIGS. 2A-2E.
  • the IC structure 200 may correspond to an interconnect layer that includes one or more interconnect structures (e.g., trenches or vias).
  • the process 100 may include forming semiconductor fins on an underlying layer.
  • the semiconductor fins may be formed of any suitable semiconductor material, such as a semiconductor material including silicon, gallium nitride (GaN), and/or another suitable material.
  • the underlying layer may include one or more active circuitry layers (e.g., including transistor devices and/or other active circuit devices) formed on a substrate.
  • a dielectric layer may be formed on the one or more active circuitry layers, and the semiconductor fins may be formed on the dielectric layer.
  • the semiconductor fins may be used to form interconnect structures of an interconnect layer (e.g., metal layer), as further discussed below.
  • the IC may include multiple interconnect layers stacked on one another, and the process 100 may be used to form one or more of the interconnect layers.
  • the underlying layer may include one or more interconnect layers.
  • Figure 2A illustrates the IC structure 200 subsequent to block 102 of the process 100.
  • the IC structure 200 includes semiconductor fins 202 formed on an underlying layer 204.
  • the semiconductor fins may be replaced with a metal later in the process 100 to form respective trenches of the interconnect layer. Accordingly, the semiconductor fins may be formed with dimensions that correspond to desired dimensions of the respective trenches.
  • the semiconductor fins may have an aspect ratio (ratio of height to width of the fins) of about 6:1 or higher, such as about 8:1 or higher.
  • the width of the fins may be about 5 nanometers to 50 nanometers, and/or the height of the fins may be about 30 nanometers to 500 nanometers.
  • a length of the semiconductor fins may be substantially longer than the height and width (e.g., the semiconductor fins may extend into and/or out of the page as shown in Figure 2A).
  • the process 100 may enable the formation of trenches with a higher aspect ratio than prior techniques.
  • the process 100 may include forming a first dielectric material (also referred to as a first ILD) on sidewalls of the semiconductor fins.
  • the first dielectric material may be used as an etch stop layer for subsequent removal of the semiconductor fins.
  • the first dielectric material may be any suitable material that is suitable for use as an etch stop layer during removal of the material of the semiconductor fins.
  • the first dielectric material may include silicon and nitrogen (e.g., silicon nitride).
  • suitable materials for the first dielectric material may include one or more of silicon oxynitride (SiOxNy), silicon nitride (SixNy) aluminum oxide (AI203), hafnium oxide (Hf02), hafnium aluminum oxide (HfAlxOy), hafnium silicon oxide (HfSixOy), zirconium oxide (Zr02), zirconium silicon oxide (ZrSixOy), lanthanum oxide (La203), yttrium
  • Y203 lanthanum aluminum oxide (LaAlxOy), tantalum oxide (Ta205), titanium oxide (Ti02), barium strontium titanium oxide (BaSrTixOy), barium titanium oxide (BaTixOy), strontium titanium oxide (SrTixOy), lead scandium tantalum oxide (PbScxTayOz), or lead zinc niobate (PbZnxNbyOz), carbon doped oxide (CDO), organic polymers such as perfluorocyclobutane or polytetrafluoroethylene,
  • fluorosilicate glass FSG
  • organosilicates such as silsesquioxane, siloxane, or organosilicate glass, or combinations thereof, where x, y, and z represent suitable quantities of the respective elements.
  • an annealing process may be carried out on the first dielectric material to improve its quality when a high-k material is used.
  • Other materials may be used in other embodiments for the first dielectric material.
  • the first dielectric material may be formed on the sidewalls of the semiconductor fins by any suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • a layer of the first dielectric material may be deposited on the IC structure, and then the first dielectric material may be removed from the top surface of the fins and from the underlying layer between the fins.
  • the layer of the first dielectric material on the first underlying layer between the fins may be maintained, for example as shown in Figures 4 and 5, which are further discussed below.
  • Figure 2B depicts the IC structure 200 with a first dielectric material 206 formed on sidewalls 208 of the semiconductor fins 202.
  • the process 100 may include forming a second dielectric material (also referred to as a second ILD) between the semiconductor fins and between portions of the first dielectric material (e.g., that are on the sidewalls of the semiconductor fins).
  • the second dielectric material may be different from the first dielectric material.
  • the second dielectric material may have a lower dielectric constant (lower K) than the first dielectric material, and/or may have a higher porosity and/or a lower density than the first dielectric material to reduce capacitance between the interconnect trenches.
  • the second dielectric material may include silicon and oxygen (e.g., silicon oxide).
  • the second dielectric material may include a porous, low-K
  • dielectric material such as a carbon-doped oxide (CDO) of silicon with a controllable porosity, e.g., 50% porosity.
  • CDO carbon-doped oxide
  • Other suitable materials for the second dielectric material may include one or more of silicon oxynitride (SiOxNy), silicon nitride (SixNy) aluminum oxide (AI203), hafnium oxide (Hf02), hafnium aluminum oxide (HfAlxOy), hafnium silicon oxide (HfSixOy), zirconium oxide (Zr02), zirconium silicon oxide (ZrSixOy), lanthanum oxide (La203), yttrium oxide (Y203), lanthanum aluminum oxide (LaAlxOy), tantalum oxide (Ta205), titanium oxide (Ti02), barium strontium titanium oxide (BaSrTixOy), barium titanium oxide (BaTixOy), strontium titanium oxide (SrTixOy),
  • perfluorocyclobutane or polytetrafluoroethylene fluorosilicate glass (FSG)
  • organosilicates such as silsesquioxane, siloxane, or organosilicate glass, or combinations thereof, where x, y, and z represent suitable quantities of the respective elements.
  • FSG fluorosilicate glass
  • organosilicates such as silsesquioxane, siloxane, or organosilicate glass, or combinations thereof, where x, y, and z represent suitable quantities of the respective elements.
  • Other materials may be used in other embodiments for the first dielectric material.
  • the second dielectric material may be formed by any suitable process, such as a spin-on process or a deposition process such as chemical vapor deposition (CVD).
  • voiding caused by the CVD process may provide a lower K for the resulting second dielectric material.
  • the first dielectric material may provide an etch stop layer for removal of the semiconductor fins, while the second dielectric material may prevent/reduce capacitance between the metal trenches (interconnects).
  • Figure 2C illustrates the IC structure 200 with a second dielectric material 210 between the semiconductor fins 202 and between the portions of the first dielectric material 206 that are on the sidewalls 208.
  • the second dielectric material 210 may be disposed on the underlying layer 204.
  • the process 100 may include removing the semiconductor fins to form openings (e.g., between the portions of the first dielectric material that were on the sidewalls of the semiconductor fins).
  • the semiconductor fins may be removed by any suitable process, such as an etch process.
  • the first dielectric material may not be significantly removed by the etch process (e.g., may have a low etch rate), and may thus serve as an etch stop layer.
  • a mask e.g., hard mask
  • a capping layer may be formed on the second dielectric material to protect the second dielectric material from being removed by the etch process (e.g., as in the process described below with reference to Figures 3A-3D).
  • Figure 2D illustrates the IC structure 200 subsequent to the semiconductor fins 202 being removed. Accordingly, the IC structure 200 includes openings 212 between the portions of the first dielectric material 206 that were on the sidewalls of the semiconductor fins 202.
  • the process 100 may include forming a metal in the openings to form respective interconnects.
  • the metal may be formed in the trench openings and via openings by any suitable deposition technique, including a conformal and/or selective deposition process.
  • the metal may be formed by CVD, ALD, PVD, electroless, electroplating, or suitable combinations of these deposition techniques.
  • the metal may include one or more metal layers of any suitable metal.
  • the metal may include copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al), or combinations thereof.
  • the metal may include a metal nitride such as, for example, titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), or combinations thereof.
  • the metal may include a metal silicide such as, for example, titanium silicide (TiSi), tungsten silicide (WSi), tantalum silicide (TaSi), cobalt silicide (CoSi), platinum silicide (PtSi), nickel silicide (NiSi), or combinations thereof.
  • the metal may include a metal silicon nitride such as, for example, titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN), or combinations thereof.
  • the metal may include a metal carbide such as, for example, titanium carbide (TiC), zirconium carbide (ZrC), tantalum carbide (TaC), hafnium carbide (HfC), or aluminum carbide (AIC), or combinations thereof.
  • the metal may include a metal carbon nitride such as, for example, tantalum carbon nitride (TaCN), titanium carbon nitride (TiCN), or combinations thereof.
  • the metal may include a conductive metal oxide (e.g., ruthenium oxide).
  • a liner may be formed in the openings prior to forming the metal.
  • the top surface of the IC structure may be polished after forming the metal in the trench openings.
  • the polishing may remove the remaining portions of the hard mask layer (if one was used) and any excess metal disposed above the trench openings.
  • the polishing process may include, for example, chemical mechanical polishing using a slurry solution designed to remove the metals used in the IC structure.
  • Figure 2E shows the IC structure with metal trenches 21 formed in the openings 212, between the portions of the first dielectric material 206.
  • the metal trenches 214 may have a width W and a height H.
  • an aspect ratio of the trenches 214 e.g., a ratio of the height H to the width W
  • the width of the fins may be about 5 nanometers to 50 nanometers, and/or the height of the fins may be about 30 nanometers to 500 nanometers.
  • a length of the semiconductor fins may be substantially longer than the height and width (e.g., the semiconductor fins may extend into and/or out of the page as shown in Figure 2A).
  • the process 100 may enable the formation of trenches with a higher aspect ratio than prior techniques.
  • the higher aspect ratio may enable the width of the trenches to be reduced while maintaining a low resistance (the resistance may be based on the cross-sectional area of the trench).
  • the reduced width of the trenches may be useful when paired with active circuit devices (e.g., transistors) with reduced feature size.
  • Figures 3A-3D illustrate cross-sectional views of an IC structure 300 subsequent to various operations of another process for fabricating an interconnect layer of the IC structure 300, in accordance with various embodiments.
  • Figure 3A illustrates the IC structure 300 with semiconductor fins 302 formed on an underlying layer 304.
  • a first dielectric material 306 may be disposed on the sidewalls 308 of the semiconductor fins 302.
  • the semiconductor fins 302 and first dielectric material 306 may be formed in a similar manner to that described above with respect to the blocks 102 and 104 of process 100.
  • a second dielectric material 310 may be formed between the semiconductor fins 302 and between the portions of the first dielectric material 306 that are on the sidewalls 308 of the semiconductor fins 302.
  • the top surface of the second dielectric material 310 may be lower than the top surface of the first dielectric material 306 and semiconductor fins 302.
  • the second dielectric material 310 may be initially formed with the lower height, or may be filled between the semiconductor fins 302 and then recessed.
  • a capping layer 320 may be formed on the second dielectric material 310.
  • the capping layer 320 may include any suitable material that is resistant to the etching process used to remove the semiconductor fins 302.
  • the capping layer 320 may be composed of the first dielectric material (e.g., silicon nitride). In other embodiments, the capping layer may be a different material than the first dielectric material.
  • the semiconductor fins 302 may be removed after formation of the capping layer 320.
  • Figure 3C shows the IC structure 300 subsequent to removal of the semiconductor fins 302, leaving openings 312 between the portions of the first dielectric material 306 that were on the sidewalls 308.
  • the capping layer 320 may protect the second dielectric material 310 from being removed by the process used to remove the semiconductor fins 302.
  • Figure 3D illustrates the IC structure 300 subsequent to formation of metal trenches 314.
  • a layer of the first dielectric material may be formed on the underlying layer between the semiconductor fins, and the second dielectric material may be formed on the first dielectric material.
  • Figure 4 illustrates an IC structure 400 that includes a first dielectric material 406 on the sidewalls of the metal trenches 414, and on the underlying layer 404 between the metal trenches 414 (and between the portions of the first dielectric material 406 that are on the sidewalls of the metal trenches 414).
  • a second dielectric material 410 is on the first dielectric material 406, between the portions of the first dielectric material 406 that are adjacent to the sidewalls of the metal trenches 414.
  • Figure 5 illustrates an IC structure 500 that is similar to the IC structure 400, but includes a capping layer 520 on the second dielectric material 510.
  • a first dielectric material 506 is on the sidewalls of the metal trenches 514, and on the underlying layer 504 between the metal trenches 514 (and between the portions of the first dielectric material 506 that are on the sidewalls of the metal trenches 514).
  • the second dielectric material 510 is on the first dielectric material 506, between the portions of the first dielectric material 506 that are adjacent to the sidewalls of the metal trenches 514.
  • the capping layer 520 is formed on the second dielectric material 510, with a top surface of the capping layer 520 substantially coplanar with a top surface of the metal trenches 514 and a top surface of the first dielectric material 506.
  • the capping layer 520 may be similar to the capping layer 320 described with respect to Figures 3A-3D.
  • FIG 6 illustrates an interposer 1000 that includes one or more embodiments of the IC structure described herein.
  • the interposer 1000 is an intervening substrate used to bridge a first substrate 1002 to a second substrate 1004.
  • the first substrate 1002 may be, for instance, an integrated circuit die.
  • the second substrate 1004 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 1000 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that can subsequently be coupled to the second substrate 1004.
  • BGA ball grid array
  • first and second substrates 1002/1004 are attached to opposing sides of the interposer 1000. In other embodiments, the first and second substrates 1002/1004 are attached to the same side of the interposer 1000. And in further embodiments, three or more substrates are interconnected by way of the interposer 1000.
  • the interposer 1000 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012.
  • TSVs through-silicon vias
  • the interposer 1000 may further include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and
  • ESD electrostatic discharge
  • More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1000.
  • RF radio- frequency
  • interconnects 1008, vias 1010, and/or TSVs 1012 may include aspects of the IC structures described herein (e.g., IC structure 200, 300, 400, and/or 500) and/or be formed using the processes described herein.
  • FIG. 7 illustrates a computing device 1200 in accordance with various embodiments.
  • the computing device 1200 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices.
  • SoC system-on-a-chip
  • the components in the computing device 1200 include, but are not limited to, an integrated circuit die 1202 and at least one communications logic unit 1208.
  • the communications logic unit 1208 is fabricated within the integrated circuit die 1202 while in other implementations the communications logic unit 1208 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1202.
  • the integrated circuit die 1202 may include a CPU 1204 as well as on-die memory 1206, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory
  • Computing device 1200 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1210 (e.g., DRAM), non-volatile memory 1212 (e.g., ROM or flash memory), a graphics processing unit 121 (GPU), a digital signal processor 1216, a crypto processor 1242 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1220, at least one antenna 1222 (in some
  • two or more antenna may be used), a display or a touchscreen display 1224, a touchscreen controller 1226, a battery 1228 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1228, a compass 1230, a motion coprocessor or sensors 1232 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 1234, a camera 1236, user input devices 1238 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1240 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • a display or a touchscreen display 1224, a touchscreen controller 1226 such as a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1228, a compass 1230, a motion coprocessor or sensors 1232 (that may include an accelerometer,
  • the computing device 1200 may incorporate further transmission, telecommunication, or radio functionality not already described herein.
  • the computing device 1200 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the computing device 1200 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the communications logic unit 1208 enables wireless communications for the transfer of data to and from the computing device 1200.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communications logic unit 1208 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 1200 may include a plurality of communications logic units 1208.
  • a first communications logic unit 1208 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 1208 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1204 of the computing device 1200 includes one or more devices, such as metal interconnects, that are formed in accordance with embodiments described herein.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communications logic unit 1208 may also include one or more devices, such as metal interconnects, that are formed in accordance with
  • another component housed within the computing device 1200 may contain one or more devices, such as metal
  • interconnects that are formed in accordance with embodiments described herein.
  • the computing device 1200 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • PDA personal digital assistant
  • the computing device 1200 may be any other electronic device that processes data.
  • Example 1 is an integrated circuit comprising: an underlying layer; and an interconnect layer on the underlying layer.
  • the interconnect layer includes: metal trenches; a first dielectric material on sidewalls of the metal trenches; and a second dielectric material between portions of the first dielectric material that are on the sidewalls of adjacent metal trenches and between the adjacent metal trenches, wherein the second dielectric material is different from the first dielectric material.
  • Example 2 is the integrated circuit of Example 1 , further comprising a capping layer on a top surface of the second dielectric material between the metal trenches.
  • Example 3 is the integrated circuit of Example 1 , further comprising active circuit devices under the underlying layer.
  • Example 4 is the integrated circuit of Example 1 , wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes silicon and oxygen.
  • Example 5 is the integrated circuit of any one of Examples 1 to 4, wherein the metal trenches have a height-to-width ratio of 8:1 or higher.
  • Example 6 is the integrated circuit of Example 5, wherein a width of the metal trenches is 10 nanometers or less.
  • Example 7 is a method for fabricating an integrated circuit (IC) structure, comprising: forming semiconductor fins on an underlying layer; forming a first dielectric material on sidewalls of the semiconductor fins; forming a second dielectric material between the semiconductor fins and between portions of the first dielectric material, wherein the second dielectric material is different from the first dielectric material; removing the semiconductor fins to form respective openings; and forming a metal in the openings to form respective interconnects.
  • IC integrated circuit
  • Example 8 is the method of Example 7, further comprising forming a capping layer on a top surface of the second dielectric material before removing the semiconductor fins.
  • Example 9 is the method of Example 8, wherein the capping layer is formed of the first dielectric material.
  • Example 10 is the method of Example 7, wherein the underlying layer includes a third dielectric material.
  • Example 11 is the method of Example 10, wherein the third dielectric material has a same chemical composition as the first or second dielectric material.
  • Example 12 is the method of Example 7, further comprising forming active circuit devices under the interconnects.
  • Example 13 is the method of Example 7, wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes silicon and oxygen.
  • Example 14 is the method of Example 7, wherein the semiconductor fins are removed by an etch process for which the first dielectric material serves as an etch stop layer.
  • Example 15 is the method of any one of Examples 7 to 14, wherein the forming the metal in the openings to form interconnects includes forming
  • interconnects with a height-to-width ratio of 8:1 or higher.
  • Example 10 is an integrated circuit comprising: an underlying layer; and an interconnect layer on the underlying layer.
  • the interconnect layer includes: metal trenches; a first dielectric material on sidewalls of the metal trenches; and a second dielectric material between portions of the first dielectric material that are on the sidewalls of adjacent metal trenches and between the adjacent metal trenches, wherein the second dielectric material is different from the first dielectric material.
  • Example 11 is the integrated circuit of Example 10, further comprising a capping layer on a top surface of the second dielectric material between the metal trenches.
  • Example 12 is the integrated circuit of Example 10, further comprising active circuit devices under the underlying layer.
  • Example 13 is the integrated circuit of Example 10, wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes silicon and oxygen.
  • Example 1 is the integrated circuit of any one of Examples 10 to 13, wherein the metal trenches have a height-to-width ratio of 8:1 or higher.
  • Example 15 is the integrated circuit of Example 14, wherein a width of the metal trenches is 10 nanometers or less.
  • Example 16 is a computing device comprising: a processor mounted on a substrate; and a memory unit coupled to the processor and capable of storing data.
  • the processor comprises an interconnect layer including: metal interconnects;
  • first dielectric material portions of a first dielectric material adjacent sidewalls of the metal interconnects; and a second dielectric material between the portions of the first dielectric material and between adjacent metal interconnects, wherein the second dielectric material is different from the first dielectric material.
  • Example 17 is the computing device of Example 16, wherein the interconnect layer further includes a capping layer on a top surface of the second dielectric material between the metal interconnects.
  • Example 18 is the computing device of Example 16, wherein the processor further includes active circuit devices under the underlying layer and coupled to the metal interconnects.
  • Example 19 is the computing device of Example 16, wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes silicon and oxygen.
  • Example 20 is the computing device of Example 16, wherein the metal interconnects have a height-to-width ratio of 8:1 or higher.
  • Example 21 is the computing device of any one of Examples 16 to 20, further comprising one or more of: a graphics processing unit coupled to the processor; an antenna within the computing device; a display on the computing device; a battery within the computing device; a power amplifier within the processor; or a voltage regulator within the processor.

Abstract

Embodiments of the present disclosure describe techniques and configurations associated with an integrated circuit (IC) structure including an interconnect layer. Semiconductor fins may be formed on an underlying layer. A first dielectric material may be formed on the sidewalls of the semiconductor fins, and a second dielectric material may be formed between the semiconductor fins and the portions of the first dielectric material. The semiconductor fins may be removed and replaced with a metal to form respective interconnects. The first dielectric material may serve as an etch stop layer for removal of the semiconductor fins. The second dielectric material may have a lower dielectric constant than the first dielectric material to reduce capacitance between the interconnects. Other embodiments may be described and/or claimed.

Description

DEEPLY SCALED METAL INTERCONNECTS WITH HIGH ASPECT RATIO
Field
Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to integrated circuits with deeply scaled metal interconnects having a high aspect ratio.
Background
Interconnects are essential components in complementary metal-oxide- semiconductor (CMOS) very large scale integration (VLSI) technology. The interconnects provide power and ground connections, as well as carry clock signals, data signals, and other electrical signals to various circuit blocks of the integrated circuit. As semiconductor devices scale down to smaller sizes, the dimensions of interconnects must also decrease.
Brief Description of the Drawings
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements.
Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.
Figure 1 is a flow diagram that illustrates a process for forming an interconnect layer of an integrated circuit (IC) structure, in accordance with various embodiments.
Figures 2A-2E illustrate cross-sectional views of an IC structure subsequent to various operations of the process shown in Figure 1 , in accordance with various embodiments.
Figures 3A-D illustrate cross-sectional views of another IC structure subsequent to various operations of another process for forming an interconnect layer, in accordance with various embodiments.
Figure 4 is a cross-sectional view of another IC structure including an interconnect layer, in accordance with various embodiments.
Figure 5 is a cross-sectional view of another IC structure including an interconnect layer, in accordance with various embodiments.
Figure 6 is cross-sectional view of an interposer implementing one or more embodiments of the present disclosure.
Figure 7 is schematic view of a computing device built in accordance with an embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure describe techniques and configurations associated with an integrated circuit (IC) structure including an interconnect layer. In various embodiments, semiconductor fins may be formed on an underlying layer. A first dielectric material may be formed on the sidewalls of the semiconductor fins, and a second dielectric material may be formed between the semiconductor fins and the portions of the first dielectric material. The
semiconductor fins may be removed and replaced with a metal to form respective interconnects. The first dielectric material may serve as an etch stop layer for removal of the semiconductor fins. The second dielectric material may have a lower dielectric constant than the first dielectric material to reduce capacitance between the interconnects.
The process described herein may enable the formation of trenches with a higher aspect ratio than prior techniques. The higher aspect ratio may enable the width of the trenches to be reduced while maintaining a low resistance (the resistance may be based on the cross-sectional area of the trench). That is, compared to prior trenches, the width of the trenches may be reduced and the height may be increased. The reduced width of the trenches may be useful when used with active circuit devices (e.g., transistors) with reduced feature size.
In the following description, various aspects of the illustrative
implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
Implementations of the invention may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the
semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium
antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.
A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the invention may also be carried out using nonplanar transistors.
Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some implementations of the invention, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.
Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.
Figure 1 is a flow chart illustrating a process 100 for fabricating an IC structure in accordance with various embodiments. Figures 2A-2E illustrate an IC structure 200 at various stages of the process 100, in accordance with various embodiments. Accordingly, the process 100 will be described with reference to the IC structure 200 shown in Figures 2A-2E. Similar fabrication principles to those described herein may be used to form IC structures with other configurations than that shown in FIGS. 2A-2E. In some embodiments, the IC structure 200 may correspond to an interconnect layer that includes one or more interconnect structures (e.g., trenches or vias).
At block 102, the process 100 may include forming semiconductor fins on an underlying layer. The semiconductor fins may be formed of any suitable semiconductor material, such as a semiconductor material including silicon, gallium nitride (GaN), and/or another suitable material. The underlying layer may include one or more active circuitry layers (e.g., including transistor devices and/or other active circuit devices) formed on a substrate. In some embodiments, a dielectric layer may be formed on the one or more active circuitry layers, and the semiconductor fins may be formed on the dielectric layer. Furthermore, the semiconductor fins may be used to form interconnect structures of an interconnect layer (e.g., metal layer), as further discussed below. The IC may include multiple interconnect layers stacked on one another, and the process 100 may be used to form one or more of the interconnect layers. Thus, in some cases, the underlying layer may include one or more interconnect layers.
Figure 2A illustrates the IC structure 200 subsequent to block 102 of the process 100. As shown, the IC structure 200 includes semiconductor fins 202 formed on an underlying layer 204.
As discussed further below, the semiconductor fins may be replaced with a metal later in the process 100 to form respective trenches of the interconnect layer. Accordingly, the semiconductor fins may be formed with dimensions that correspond to desired dimensions of the respective trenches. For example, the semiconductor fins may have an aspect ratio (ratio of height to width of the fins) of about 6:1 or higher, such as about 8:1 or higher. In some embodiments, the width of the fins may be about 5 nanometers to 50 nanometers, and/or the height of the fins may be about 30 nanometers to 500 nanometers. A length of the semiconductor fins may be substantially longer than the height and width (e.g., the semiconductor fins may extend into and/or out of the page as shown in Figure 2A). The process 100 may enable the formation of trenches with a higher aspect ratio than prior techniques.
At block 104, the process 100 may include forming a first dielectric material (also referred to as a first ILD) on sidewalls of the semiconductor fins. The first dielectric material may be used as an etch stop layer for subsequent removal of the semiconductor fins. Accordingly, the first dielectric material may be any suitable material that is suitable for use as an etch stop layer during removal of the material of the semiconductor fins. For example, in some embodiments, the first dielectric material may include silicon and nitrogen (e.g., silicon nitride). Other suitable materials for the first dielectric material may include one or more of silicon oxynitride (SiOxNy), silicon nitride (SixNy) aluminum oxide (AI203), hafnium oxide (Hf02), hafnium aluminum oxide (HfAlxOy), hafnium silicon oxide (HfSixOy), zirconium oxide (Zr02), zirconium silicon oxide (ZrSixOy), lanthanum oxide (La203), yttrium
oxide (Y203), lanthanum aluminum oxide (LaAlxOy), tantalum oxide (Ta205), titanium oxide (Ti02), barium strontium titanium oxide (BaSrTixOy), barium titanium oxide (BaTixOy), strontium titanium oxide (SrTixOy), lead scandium tantalum oxide (PbScxTayOz), or lead zinc niobate (PbZnxNbyOz), carbon doped oxide (CDO), organic polymers such as perfluorocyclobutane or polytetrafluoroethylene,
fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass, or combinations thereof, where x, y, and z represent suitable quantities of the respective elements. In some embodiments, an annealing process may be carried out on the first dielectric material to improve its quality when a high-k material is used. Other materials may be used in other embodiments for the first dielectric material.
The first dielectric material may be formed on the sidewalls of the semiconductor fins by any suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In some embodiments, a layer of the first dielectric material may be deposited on the IC structure, and then the first dielectric material may be removed from the top surface of the fins and from the underlying layer between the fins. In other
embodiments, the layer of the first dielectric material on the first underlying layer between the fins may be maintained, for example as shown in Figures 4 and 5, which are further discussed below.
Figure 2B depicts the IC structure 200 with a first dielectric material 206 formed on sidewalls 208 of the semiconductor fins 202.
At block 106, the process 100 may include forming a second dielectric material (also referred to as a second ILD) between the semiconductor fins and between portions of the first dielectric material (e.g., that are on the sidewalls of the semiconductor fins). The second dielectric material may be different from the first dielectric material. For example, the second dielectric material may have a lower dielectric constant (lower K) than the first dielectric material, and/or may have a higher porosity and/or a lower density than the first dielectric material to reduce capacitance between the interconnect trenches. In some embodiments, the second dielectric material may include silicon and oxygen (e.g., silicon oxide). In some embodiments, the second dielectric material may include a porous, low-K
dielectric material, such as a carbon-doped oxide (CDO) of silicon with a controllable porosity, e.g., 50% porosity. Other suitable materials for the second dielectric material may include one or more of silicon oxynitride (SiOxNy), silicon nitride (SixNy) aluminum oxide (AI203), hafnium oxide (Hf02), hafnium aluminum oxide (HfAlxOy), hafnium silicon oxide (HfSixOy), zirconium oxide (Zr02), zirconium silicon oxide (ZrSixOy), lanthanum oxide (La203), yttrium oxide (Y203), lanthanum aluminum oxide (LaAlxOy), tantalum oxide (Ta205), titanium oxide (Ti02), barium strontium titanium oxide (BaSrTixOy), barium titanium oxide (BaTixOy), strontium titanium oxide (SrTixOy), lead scandium tantalum oxide (PbScxTayOz), or lead zinc niobate (PbZnxNbyOz), carbon doped oxide (CDO), organic polymers such
as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass, or combinations thereof, where x, y, and z represent suitable quantities of the respective elements. Other materials may be used in other embodiments for the first dielectric material.
The second dielectric material may be formed by any suitable process, such as a spin-on process or a deposition process such as chemical vapor deposition (CVD). In some embodiments, voiding caused by the CVD process may provide a lower K for the resulting second dielectric material.
The first dielectric material may provide an etch stop layer for removal of the semiconductor fins, while the second dielectric material may prevent/reduce capacitance between the metal trenches (interconnects).
Figure 2C illustrates the IC structure 200 with a second dielectric material 210 between the semiconductor fins 202 and between the portions of the first dielectric material 206 that are on the sidewalls 208. The second dielectric material 210 may be disposed on the underlying layer 204.
At block 108, the process 100 may include removing the semiconductor fins to form openings (e.g., between the portions of the first dielectric material that were on the sidewalls of the semiconductor fins). The semiconductor fins may be removed by any suitable process, such as an etch process. The first dielectric material may not be significantly removed by the etch process (e.g., may have a low etch rate), and may thus serve as an etch stop layer. In some embodiments, a mask (e.g., hard mask) may be used to etch out the semiconductor fins. Alternatively, or additionally, a capping layer may be formed on the second dielectric material to protect the second dielectric material from being removed by the etch process (e.g., as in the process described below with reference to Figures 3A-3D).
Figure 2D illustrates the IC structure 200 subsequent to the semiconductor fins 202 being removed. Accordingly, the IC structure 200 includes openings 212 between the portions of the first dielectric material 206 that were on the sidewalls of the semiconductor fins 202.
In block 110, the process 100 may include forming a metal in the openings to form respective interconnects. The metal may be formed in the trench openings and via openings by any suitable deposition technique, including a conformal and/or selective deposition process. For example, the metal may be formed by CVD, ALD, PVD, electroless, electroplating, or suitable combinations of these deposition techniques.
The metal may include one or more metal layers of any suitable metal.
For example, in some embodiments, the metal may include copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al), or combinations thereof. In some embodiments, the metal may include a metal nitride such as, for example, titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), or combinations thereof. In some embodiments, the metal may include a metal silicide such as, for example, titanium silicide (TiSi), tungsten silicide (WSi), tantalum silicide (TaSi), cobalt silicide (CoSi), platinum silicide (PtSi), nickel silicide (NiSi), or combinations thereof. In some embodiments, the metal may include a metal silicon nitride such as, for example, titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN), or combinations thereof. In some embodiments, the metal may include a metal carbide such as, for example, titanium carbide (TiC), zirconium carbide (ZrC), tantalum carbide (TaC), hafnium carbide (HfC), or aluminum carbide (AIC), or combinations thereof. In some embodiments, the metal may include a metal carbon nitride such as, for example, tantalum carbon nitride (TaCN), titanium carbon nitride (TiCN), or combinations thereof. In some embodiments, the metal may include a conductive metal oxide (e.g., ruthenium oxide). In some embodiments, a liner may be formed in the openings prior to forming the metal.
In some embodiments, the top surface of the IC structure may be polished after forming the metal in the trench openings. The polishing may remove the remaining portions of the hard mask layer (if one was used) and any excess metal disposed above the trench openings. The polishing process may include, for example, chemical mechanical polishing using a slurry solution designed to remove the metals used in the IC structure.
Figure 2E shows the IC structure with metal trenches 21 formed in the openings 212, between the portions of the first dielectric material 206. The metal trenches 214 may have a width W and a height H. In embodiments, an aspect ratio of the trenches 214 (e.g., a ratio of the height H to the width W) may be about 6:1 or higher, such as about 8:1 or higher. In some embodiments, the width of the fins may be about 5 nanometers to 50 nanometers, and/or the height of the fins may be about 30 nanometers to 500 nanometers. A length of the semiconductor fins may be substantially longer than the height and width (e.g., the semiconductor fins may extend into and/or out of the page as shown in Figure 2A). The process 100 may enable the formation of trenches with a higher aspect ratio than prior techniques. The higher aspect ratio may enable the width of the trenches to be reduced while maintaining a low resistance (the resistance may be based on the cross-sectional area of the trench). The reduced width of the trenches may be useful when paired with active circuit devices (e.g., transistors) with reduced feature size.
Figures 3A-3D illustrate cross-sectional views of an IC structure 300 subsequent to various operations of another process for fabricating an interconnect layer of the IC structure 300, in accordance with various embodiments. Figure 3A illustrates the IC structure 300 with semiconductor fins 302 formed on an underlying layer 304. A first dielectric material 306 may be disposed on the sidewalls 308 of the semiconductor fins 302. The semiconductor fins 302 and first dielectric material 306 may be formed in a similar manner to that described above with respect to the blocks 102 and 104 of process 100.
As shown in Figure 3A, a second dielectric material 310 may be formed between the semiconductor fins 302 and between the portions of the first dielectric material 306 that are on the sidewalls 308 of the semiconductor fins 302. The top surface of the second dielectric material 310 may be lower than the top surface of the first dielectric material 306 and semiconductor fins 302. For example, the second dielectric material 310 may be initially formed with the lower height, or may be filled between the semiconductor fins 302 and then recessed.
As shown in Figure 3B, a capping layer 320 may be formed on the second dielectric material 310. The capping layer 320 may include any suitable material that is resistant to the etching process used to remove the semiconductor fins 302. For example, in some embodiments, the capping layer 320 may be composed of the first dielectric material (e.g., silicon nitride). In other embodiments, the capping layer may be a different material than the first dielectric material.
In various embodiments, the semiconductor fins 302 may be removed after formation of the capping layer 320. Figure 3C shows the IC structure 300 subsequent to removal of the semiconductor fins 302, leaving openings 312 between the portions of the first dielectric material 306 that were on the sidewalls 308. The capping layer 320 may protect the second dielectric material 310 from being removed by the process used to remove the semiconductor fins 302.
After formation of the capping layer 320, a metal may be formed in the openings 312. Figure 3D illustrates the IC structure 300 subsequent to formation of metal trenches 314.
In other embodiments, as mentioned above, a layer of the first dielectric material may be formed on the underlying layer between the semiconductor fins, and the second dielectric material may be formed on the first dielectric material. For example, Figure 4 illustrates an IC structure 400 that includes a first dielectric material 406 on the sidewalls of the metal trenches 414, and on the underlying layer 404 between the metal trenches 414 (and between the portions of the first dielectric material 406 that are on the sidewalls of the metal trenches 414). A second dielectric material 410 is on the first dielectric material 406, between the portions of the first dielectric material 406 that are adjacent to the sidewalls of the metal trenches 414.
Figure 5 illustrates an IC structure 500 that is similar to the IC structure 400, but includes a capping layer 520 on the second dielectric material 510. A first dielectric material 506 is on the sidewalls of the metal trenches 514, and on the underlying layer 504 between the metal trenches 514 (and between the portions of the first dielectric material 506 that are on the sidewalls of the metal trenches 514). The second dielectric material 510 is on the first dielectric material 506, between the portions of the first dielectric material 506 that are adjacent to the sidewalls of the metal trenches 514. The capping layer 520 is formed on the second dielectric material 510, with a top surface of the capping layer 520 substantially coplanar with a top surface of the metal trenches 514 and a top surface of the first dielectric material 506. The capping layer 520 may be similar to the capping layer 320 described with respect to Figures 3A-3D.
Figure 6 illustrates an interposer 1000 that includes one or more embodiments of the IC structure described herein. The interposer 1000 is an intervening substrate used to bridge a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for instance, an integrated circuit die. The second substrate 1004 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1000 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that can subsequently be coupled to the second substrate 1004. In some embodiments, the first and second substrates 1002/1004 are attached to opposing sides of the interposer 1000. In other embodiments, the first and second substrates 1002/1004 are attached to the same side of the interposer 1000. And in further embodiments, three or more substrates are interconnected by way of the interposer 1000.
The interposer 1000 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
The interposer may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012. The interposer 1000 may further include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and
electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1000.
In accordance with various embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1000. For example, the interconnects 1008, vias 1010, and/or TSVs 1012 may include aspects of the IC structures described herein (e.g., IC structure 200, 300, 400, and/or 500) and/or be formed using the processes described herein.
Figure 7 illustrates a computing device 1200 in accordance with various embodiments. The computing device 1200 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices. The components in the computing device 1200 include, but are not limited to, an integrated circuit die 1202 and at least one communications logic unit 1208. In some implementations the communications logic unit 1208 is fabricated within the integrated circuit die 1202 while in other implementations the communications logic unit 1208 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1202. The integrated circuit die 1202 may include a CPU 1204 as well as on-die memory 1206, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM).
Computing device 1200 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1210 (e.g., DRAM), non-volatile memory 1212 (e.g., ROM or flash memory), a graphics processing unit 121 (GPU), a digital signal processor 1216, a crypto processor 1242 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1220, at least one antenna 1222 (in some
implementations two or more antenna may be used), a display or a touchscreen display 1224, a touchscreen controller 1226, a battery 1228 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1228, a compass 1230, a motion coprocessor or sensors 1232 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 1234, a camera 1236, user input devices 1238 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1240 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 1200 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 1200 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 1200 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
The communications logic unit 1208 enables wireless communications for the transfer of data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 1208 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1200 may include a plurality of communications logic units 1208. For instance, a first communications logic unit 1208 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 1208 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 1204 of the computing device 1200 includes one or more devices, such as metal interconnects, that are formed in accordance with embodiments described herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communications logic unit 1208 may also include one or more devices, such as metal interconnects, that are formed in accordance with
embodiments described herein. In further embodiments, another component housed within the computing device 1200 may contain one or more devices, such as metal
interconnects, that are formed in accordance with embodiments described herein.
In various embodiments, the computing device 1200 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further
implementations, the computing device 1200 may be any other electronic device that processes data.
Some non-limiting Examples of various embodiments are provided below.
Example 1 is an integrated circuit comprising: an underlying layer; and an interconnect layer on the underlying layer. The interconnect layer includes: metal trenches; a first dielectric material on sidewalls of the metal trenches; and a second dielectric material between portions of the first dielectric material that are on the sidewalls of adjacent metal trenches and between the adjacent metal trenches, wherein the second dielectric material is different from the first dielectric material.
Example 2 is the integrated circuit of Example 1 , further comprising a capping layer on a top surface of the second dielectric material between the metal trenches.
Example 3 is the integrated circuit of Example 1 , further comprising active circuit devices under the underlying layer.
Example 4 is the integrated circuit of Example 1 , wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes silicon and oxygen.
Example 5 is the integrated circuit of any one of Examples 1 to 4, wherein the metal trenches have a height-to-width ratio of 8:1 or higher.
Example 6 is the integrated circuit of Example 5, wherein a width of the metal trenches is 10 nanometers or less. Example 7 is a method for fabricating an integrated circuit (IC) structure, comprising: forming semiconductor fins on an underlying layer; forming a first dielectric material on sidewalls of the semiconductor fins; forming a second dielectric material between the semiconductor fins and between portions of the first dielectric material, wherein the second dielectric material is different from the first dielectric material; removing the semiconductor fins to form respective openings; and forming a metal in the openings to form respective interconnects.
Example 8 is the method of Example 7, further comprising forming a capping layer on a top surface of the second dielectric material before removing the semiconductor fins.
Example 9 is the method of Example 8, wherein the capping layer is formed of the first dielectric material.
Example 10 is the method of Example 7, wherein the underlying layer includes a third dielectric material.
Example 11 is the method of Example 10, wherein the third dielectric material has a same chemical composition as the first or second dielectric material.
Example 12 is the method of Example 7, further comprising forming active circuit devices under the interconnects.
Example 13 is the method of Example 7, wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes silicon and oxygen.
Example 14 is the method of Example 7, wherein the semiconductor fins are removed by an etch process for which the first dielectric material serves as an etch stop layer.
Example 15 is the method of any one of Examples 7 to 14, wherein the forming the metal in the openings to form interconnects includes forming
interconnects with a height-to-width ratio of 8:1 or higher.
Example 10 is an integrated circuit comprising: an underlying layer; and an interconnect layer on the underlying layer. The interconnect layer includes: metal trenches; a first dielectric material on sidewalls of the metal trenches; and a second dielectric material between portions of the first dielectric material that are on the sidewalls of adjacent metal trenches and between the adjacent metal trenches, wherein the second dielectric material is different from the first dielectric material.
Example 11 is the integrated circuit of Example 10, further comprising a capping layer on a top surface of the second dielectric material between the metal trenches.
Example 12 is the integrated circuit of Example 10, further comprising active circuit devices under the underlying layer.
Example 13 is the integrated circuit of Example 10, wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes silicon and oxygen.
Example 1 is the integrated circuit of any one of Examples 10 to 13, wherein the metal trenches have a height-to-width ratio of 8:1 or higher.
Example 15 is the integrated circuit of Example 14, wherein a width of the metal trenches is 10 nanometers or less.
Example 16 is a computing device comprising: a processor mounted on a substrate; and a memory unit coupled to the processor and capable of storing data. The processor comprises an interconnect layer including: metal interconnects;
portions of a first dielectric material adjacent sidewalls of the metal interconnects; and a second dielectric material between the portions of the first dielectric material and between adjacent metal interconnects, wherein the second dielectric material is different from the first dielectric material.
Example 17 is the computing device of Example 16, wherein the interconnect layer further includes a capping layer on a top surface of the second dielectric material between the metal interconnects.
Example 18 is the computing device of Example 16, wherein the processor further includes active circuit devices under the underlying layer and coupled to the metal interconnects.
Example 19 is the computing device of Example 16, wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes silicon and oxygen. Example 20 is the computing device of Example 16, wherein the metal interconnects have a height-to-width ratio of 8:1 or higher.
Example 21 is the computing device of any one of Examples 16 to 20, further comprising one or more of: a graphics processing unit coupled to the processor; an antenna within the computing device; a display on the computing device; a battery within the computing device; a power amplifier within the processor; or a voltage regulator within the processor.
The above description of illustrated implementations of the various embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. While specific implementations of, and examples for, various embodiments are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the embodiments, as those skilled in the relevant art will recognize.

Claims

Claims
What is claimed is:
1. An integrated circuit comprising:
an underlying layer; and
an interconnect layer on the underlying layer, the interconnect layer including: metal trenches;
a first dielectric material on sidewalls of the metal trenches; and a second dielectric material between portions of the first dielectric material that are on the sidewalls of adjacent metal trenches and between the adjacent metal trenches, wherein the second dielectric material is different from the first dielectric material.
2. The integrated circuit of claim 1 , further comprising a capping layer on a top surface of the second dielectric material between the metal trenches.
3. The integrated circuit of claim 1 , further comprising active circuit devices under the underlying layer. 4. The integrated circuit of claim 1 , wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes silicon and oxygen.
5. The integrated circuit of any one of claims 1 to 4, wherein the metal trenches have a height-to-width ratio of 8:1 or higher.
6. The integrated circuit of claim 5, wherein a width of the metal trenches is 10 nanometers or less.
7. A method for fabricating an integrated circuit (IC) structure, comprising:
forming semiconductor fins on an underlying layer;
forming a first dielectric material on sidewalls of the semiconductor fins; forming a second dielectric material between the semiconductor fins and between portions of the first dielectric material, wherein the second dielectric material is different from the first dielectric material;
removing the semiconductor fins to form respective openings; and
forming a metal in the openings to form respective interconnects.
8. The method of claim 7, further comprising forming a capping layer on a top surface of the second dielectric material before removing the semiconductor fins. 9. The method of claim 8, wherein the capping layer is formed of the first dielectric material.
10. The method of claim 7, wherein the underlying layer includes a third dielectric material.
11. The method of claim 10, wherein the third dielectric material has a same chemical composition as the first or second dielectric material.
12. The method of claim 7, further comprising forming active circuit devices under the interconnects.
13. The method of claim 7, wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes silicon and oxygen. 1 . The method of claim 7, wherein the semiconductor fins are removed by an etch process for which the first dielectric material serves as an etch stop layer.
15. The method of any one of claims 7 to 14, wherein the forming the metal in the openings to form interconnects includes forming interconnects with a height-to-width ratio of 8:1 or higher.
16. A computing device comprising:
a processor mounted on a substrate; and
a memory unit coupled to the processor and capable of storing data;
wherein the processor comprises an interconnect layer including:
metal interconnects;
portions of a first dielectric material adjacent sidewalls of the metal interconnects; and
a second dielectric material between the portions of the first dielectric material and between adjacent metal interconnects, wherein the second dielectric material is different from the first dielectric material.
17. The computing device of claim 16, wherein the interconnect layer further includes a capping layer on a top surface of the second dielectric material between the metal interconnects.
18. The computing device of claim 16, wherein the processor further includes active circuit devices under the underlying layer and coupled to the metal
interconnects.
19. The computing device of claim 16, wherein the first dielectric material includes silicon and nitrogen, and the second dielectric material includes silicon and oxygen.
20. The computing device of claim 16, wherein the metal interconnects have a height-to-width ratio of 8:1 or higher.
21. The computing device of any one of claims 16 to 20, further comprising of:
a graphics processing unit coupled to the processor;
an antenna within the computing device;
a display on the computing device;
a battery within the computing device;
a power amplifier within the processor; or
a voltage regulator within the processor.
PCT/US2016/068763 2016-12-27 2016-12-27 Deeply scaled metal interconnects with high aspect ratio WO2018125064A1 (en)

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