WO2018125060A1

WO2018125060A1 - High density metal-insulator-metal decoupling capacitor

Info

Publication number: WO2018125060A1
Application number: PCT/US2016/068753
Authority: WO
Inventors: Yih Wang
Original assignee: Intel Corporation
Priority date: 2016-12-27
Filing date: 2016-12-27
Publication date: 2018-07-05

Abstract

An apparatus comprises one or more logic circuit blocks coupled between a supply voltage and ground and a decoupling capacitor coupled between the supply voltage and ground in parallel to the one or more logic circuit blocks, comprising a first high-density three-dimensional (3D) metal-insulator-metal (MIM) trench capacitor coupled in series with a second high-density 3D MIM trench capacitor.

Description

HIGH DENSITY METAL-INSULATOR-METAL DECOUPLING CAPACITOR

FIELD

The present disclosure generally relates to de-coupling capacitors.

BACKGROUND

Power supply noise management continues to be a challenge with the scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies. As the supply voltage of circuits continues to decrease with technology scaling, reducing power supply noise has become increasingly important to provide a maximum supply voltage window for robust circuit operation. The most common technique to suppress supply voltage noise is to place a large decoupling capacitor between the supply rails. The decoupling capacitor provides a low impedance path and shunts high-frequency noise on the supply to ground.

Transistors and planar metal-insulator-metal (MIM) capacitors are the typical on- die decoupling capacitors used for decoupling. Capacitance of a decoupling capacitor needs to be high enough (e.g., more than hundreds of nanofarad in modern system on chip (SoC) applications) to be effective in suppressing power supply noise. However, large on-die decoupling capacitors consume a large volume of silicon area (at least a few mm² for embedded Dynamic Random- Access Memory (DRAM) (eDRAM) products) and add leakage power. Further, MIM capacitors require additional process steps and masks to integrate into an interconnect.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A and IB illustrate conventional logic circuits.

Figures 2A and 2B illustrate a MIM capacitor for an eDRAM memory.

Figures 3A and 3B illustrate an embodiment of serially connected MIM capacitors.

Figure 4 illustrates a top view of one embodiment of a de-coupling capacitor.

Figure 5 illustrates a system in which a high Q capacitor may be implemented. DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, various embodiments of the invention may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments of the invention.

Figure 1A illustrates a conventional logic circuit including logic circuit blocks coupled between a power supply (VCC) and ground. Such conventional circuits may suffer from power supply noise that is induced during the dynamic switching of the logic circuit blocks. Thus, one or more decupling capacitors may be added into the power supply network to reduce the noise. Figure IB illustrates a conventional logic circuit including a decoupling capacitor coupled between VCC and ground in parallel to the logic circuit blocks. Conventional decoupling capacitors implement either a gate capacitance of transistor or planar metal-insulator-metal (MIM) capacitor integrated in the interconnect. Both options, however, consume area and increase wafer manufacturing cost.

Three-dimensional (3D) high-density MIM trench capacitors have been developed as charge storage devices for embedded DRAM (eDRAM). Figure 2A illustrates a cross-sectional view, while Figure 2B illustrates a schematic, of a 3D high density MIM trench capacitor implemented in an eDRAM memory array. As shown in Figure 2A, a bottom electrode of each MIM capacitor in the memory cell is connected to access a transistor through a metal 1 (Ml) layer. The top electrode of each MIM capacitor is connected to a common metal plate shared by all of the MIM trench capacitors in the same array. The common metal plate is located in a metal 5 (M5) layer. With the large surface area of deep trench structure, the MIM capacitor provides more than 20 times higher capacitance per unit area than can be achieved by a transistor or planar MIM capacitor. Thus, a 3D MIM trench capacitor makes for a good candidate for implementation of a decoupling capacitor in an eDRAM.

However, a drawback for implementing 3D MIM trench capacitors in such applications is a low dielectric breakdown voltage. For instance, the common plate is biased to a fixed reference voltage to achieve minimum voltage across the dielectric for storage node voltage of either IV for data "1" or 0V for data "0". The reference voltage is typically in the range of 0.4V to 0.6V for supply voltage of 1.1V. Reliability of the dielectric in the 3D MIM capacitor is significantly degraded if the voltage across the dielectric is a full supply voltage. Thus, 3D MIM trench capacitors have not previously been used as decoupling capacitors in products with eDRAM because the dielectric of MIM trench capacitor could not sustain high voltage or meet reliability requirements.

According to one embodiment, high-density 3D MIM trench capacitors in an eDRAM may be implemented as a decoupling capacitor by coupling two or more 3D MIM trench capacitors in series. Figure 3A illustrates one embodiment of a cross-sectional view, while Figure 3B illustrates a schematic, of 3D MIM trench capacitors coupled in series to form a decoupling capacitor in an eDRAM memory array 300. As shown in Figure 3A, a common top plate 305 connect MIM capacitors 310(a) and 310(b) in series. In such an embodiment, capacitors 310(a) and 310(b) each include a group of MIM trench capacitors to achieve sufficient capacitance.

In a further embodiment, the bottom electrodes of capacitors 310(a) and 310(b) capacitors are connected to separate Ml layer interconnects (or busses) 320(a) and 320(b), respectively. Busses 320(a) and 320(b) operate as the two terminals of decoupling capacitor. Bus 320(a) is a high plate that couples to VCC, while bus 320(b) is a plate low that couples to ground. This de-coupling capacitor design reduces voltage droop across each MIM trench capacitor 310 by approximately one-half. The lower voltage across the MIM capacitors 310 significantly improves the reliability of each, thus making it feasible to be used as a de-coupling capacitor.

Figure 4 illustrates one embodiment of a top view of a decoupling capacitor comprised of two MIM trench capacitors 310(a) and 310(b).

Capacitors 310(a) and 310(b) each include MIM trench capacitors 410.

Capacitors 410 in capacitor 310(a) are coupled to the plate high terminal electrode 320(a) through the Ml layer deposited on terminal 320(a). Similarly, capacitors 410 in capacitor 310(b) are coupled to the plate high terminal electrode 320(b) through the Ml layer deposited on terminal 320(b).

The above-described high density decoupling capacitor is implemented using two 3D MIM trench capacitors connected in series through a top electrode plate that is already used in an eDRAM MIM capacitor. Thus, the design is realized

with a layout change of a metal layer below the bottom electrode of each 3D MIM capacitor that is achieved without adding additional process steps and mask.

Figure 5 illustrates one embodiment of a computer system 600 in which a decoupling capacitor may be implemented. The computer system 600 (also referred to as the electronic system 600) as depicted can embody a

semiconductor die packaged with one or more ACIs having metal-density layer units of fractal geometry according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure. The computer system 600 may be a mobile device such as a netbook computer. The computer system 600 may be a mobile device such as a wireless smart phone. The computer system 600 may be a desktop computer. The computer system 600 may be a hand-held reader. The computer system 600 may be a server system. The computer system 600 may be a supercomputer or high-performance computing system.

In an embodiment, the electronic system 600 is a computer system that includes a system bus 620 to electrically couple the various components of the electronic system 600. The system bus 620 is a single bus or any combination of busses according to various embodiments. The electronic system 600 includes a voltage source 630 that provides power to the integrated circuit 610. In some embodiments, the voltage source 630 supplies current to the integrated circuit 610 through the system bus 620.

The integrated circuit 610 is electrically coupled to the system bus 620 and includes any circuit, or combination of circuits according to an

embodiment. In an embodiment, the integrated circuit 610 includes a processor 612 that can be of any type. As used herein, the processor 612 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 612 includes a semiconductor die packaged with one or more ACIs having metal-density layer units of fractal geometry, as disclosed herein. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit 610 are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit 614 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit 610 includes on-die memory 616 such as static random-access memory (SRAM). In an embodiment, the integrated circuit 610 includes embedded on-die memory 616 such as embedded dynamic random- access memory (eDRAM).

In an embodiment, the integrated circuit 610 is complemented with a subsequent integrated circuit 611. Useful embodiments include a dual processor 613 and a dual communications circuit 615 and dual on-die memory 617 such as SRAM. In an embodiment, the dual integrated circuit 610 includes embedded on-die memory 617 such as eDRAM.

In an embodiment, the electronic system 600 also includes an external memory 640 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 642 in the form of RAM, one or more hard drives 644, and/or one or more drives that handle removable media 646, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 640 may also be embedded memory 648 such as the first die in an embedded TSV die stack, according to an embodiment.

In an embodiment, the electronic system 600 also includes a display device 650, an audio output 660. In an embodiment, the electronic system 600 includes an input device such as a controller 670 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 600. In an embodiment, an input device 1070 is a camera. In an embodiment, an input device 670 is a digital sound recorder. In an embodiment, an input device 670 is a camera and a digital sound recorder.

As shown herein, the integrated circuit 610 can be implemented in a number of different embodiments, including a semiconductor die packaged with one or more ACIs having metal-density layer units of fractal geometry according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a semiconductor die packaged with one or more ACIs having metal- density layer units of fractal geometry according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art- recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed semiconductor die packaged with one or more ACIs having metal-density layer units of fractal geometry embodiments and their equivalents. A foundation substrate may be included, as represented by the dashed line of Figure 5. Passive devices may also be included, as is also depicted in Figure 5.

References to "one embodiment", "an embodiment", "example embodiment", "various embodiments", etc., indicate that the embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.

In the following description and claims, the term "coupled" along with its derivatives, may be used. "Coupled" is used to indicate that two or more elements cooperate or interact with each other, but they may or may not have intervening physical or electrical components between them.

As used in the claims, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common element, merely indicate that different instances of like elements are being referred to, and are not intended to imply that the elements so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

The following clauses and/or examples pertain to further embodiments or examples. Specifics in the examples may be used anywhere in one or more embodiments. The various features of the different embodiments or examples may be variously combined with some features included and others excluded to suit a variety of different applications. Examples may include subject matter such as a method, means for performing acts of the method, at least one machine-readable medium including instructions that, when performed by a machine cause the machine to performs acts of the method, or of an apparatus or system for facilitating hybrid communication according to embodiments and examples described herein.

Some embodiments pertain to Example 1 that includes an apparatus comprising one or more logic circuit blocks coupled between a supply voltage and ground and a decoupling capacitor coupled between the supply voltage and ground in parallel to the one or more logic circuit blocks, comprising a first high-density three-dimensional (3D) metal-insulator-metal (MIM) trench capacitor coupled in series with a second high-density 3D MIM trench capacitor

Example 2 includes the subject matter of Example 1, wherein the first high- density 3D MIM trench capacitor and the second high-density 3D MIM trench capacitor each include a plurality of MIM trench capacitors.

Example 3 includes the subject matter of Examples 1 and 2, wherein each of the plurality of MIM trench capacitors comprises electrodes.

Example 4 includes the subject matter of Examples 1-3, further comprising a common plate coupled to a top portion of each of the electrodes in the plurality of MIM trench capacitors in the first high-density 3D MIM trench capacitor and the second high-density 3D MIM trench capacitor.

Example 5 includes the subject matter of Examples 1-4, further comprising a first plate coupled to a lower portion of each of the electrodes in the plurality of MIM trench capacitors in the first high-density 3D MIM trench capacitor and a second plate coupled to a lower portion of each of the electrodes in the plurality of MIM trench capacitors in the second high-density 3D MIM trench capacitor.

Example 6 includes the subject matter of Examples 1-5, wherein the first plate is coupled to the supply voltage and the second plate is coupled to ground.

Example 7 includes the subject matter of Examples 1-6, wherein the first plate and the second plate operate as terminals for the decoupling capacitor.

Example 8 includes the subject matter of Examples 1-7, wherein the first plate and the second plate are located in a first metal layer of the apparatus.

Example 9 includes the subject matter of Examples 1-8, wherein the common plate is located in a fifth metal layer of the apparatus.

Some embodiments pertain to Example 10 that includes an integrated circuit (IC) comprising a decoupling capacitor, including a decoupling capacitor comprising a first high-density three-dimensional (3D) metal-insulator-metal (MIM) trench capacitor coupled in series with a second high-density 3D MIM trench capacitor. Example 11 includes the subject matter of Example 10, wherein the first high- density 3D MIM trench capacitor and the second high-density 3D MIM trench capacitor each include a plurality of MIM trench capacitors.

Example 12 includes the subject matter of Examples 10 and 11, wherein each of the plurality of MIM trench capacitors comprises electrodes.

Example 13 includes the subject matter of Examples 10-12, further comprising a common plate coupled to a top portion of each of the electrodes in the plurality of MIM trench capacitors in the first high-density 3D MIM trench capacitor and the second high-density 3D MIM trench capacitor.

Example 14 includes the subject matter of Examples 10-13, further comprising a first plate coupled to a lower portion of each of the electrodes in the plurality of MIM trench capacitors in the first high-density 3D MIM trench capacitor and a second plate coupled to a lower portion of each of the electrodes in the plurality of MIM trench capacitors in the second high-density 3D MIM trench capacitor.

Example 15 includes the subject matter of Examples 10-14, wherein the first plate is coupled to a supply voltage and the second plate is coupled to ground.

Example 16 includes the subject matter of Examples 10-15, wherein the first plate and the second plate operate as terminals for the decoupling capacitor.

Example 17 includes the subject matter of Examples 10-16, wherein the first plate and the second plate are located in a first metal layer of the IC.

Example 18 includes the subject matter of Examples 10-17, wherein the common plate is located in a fifth metal layer of the IC.

Some embodiments pertain to Example 19 that includes a dynamic random- access memory (DRAM) comprising a memory array including a plurality of high- density three-dimensional (3D) metal-insulator-metal (MIM) trench capacitors and a decoupling capacitor comprising a first of the plurality of the high-density 3D MIM trench capacitors trench capacitor coupled in series with a second of the high-density 3D MIM trench capacitors.

Example 20 includes the subject matter of Example 19, wherein the first high- density 3D MIM trench capacitor and the second high-density 3D MIM trench capacitor each include a plurality of MIM trench capacitors.

Example 21 includes the subject matter of Examples 19 and 20, wherein each of the plurality of MIM trench capacitors comprises electrodes. Example 22 includes the subject matter of Examples 19-21, further comprising a common plate coupled to a top portion of each of the electrodes in the plurality of MIM trench capacitors in the first high-density 3D MIM trench capacitor and the second high-density 3D MIM trench capacitor.

Example 23 includes the subject matter of Examples 19-22, further comprising a first plate coupled to a lower portion of each of the electrodes in the plurality of MIM trench capacitors in the first high-density 3D MIM trench capacitor and a second plate coupled to a lower portion of each of the electrodes in the plurality of MIM trench capacitors in the second high-density 3D MIM trench capacitor.

Example 24 includes the subject matter of Examples 19-23, wherein the first plate is coupled to a supply voltage and the second plate is coupled to ground and operate as terminals for the decoupling capacitor.

Example 25 includes the subject matter of Examples 19-24, wherein the DRAM is an embedded dynamic random- access memory (eDRAM).

Although embodiments of the invention have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.

Claims

CLAIMS What is claimed is:

1. An apparatus comprising:

one or more logic circuit blocks coupled between a supply voltage and ground; and

a decoupling capacitor coupled between the supply voltage and ground in parallel to the one or more logic circuit blocks, comprising a first high-density metal- insulator-metal (MIM) trench capacitor coupled in series with a second high-density 3D MIM trench capacitor.

2. The apparatus of claim 1, wherein the first high-density MIM trench capacitor and the second high-density MIM trench capacitor each include a plurality of MIM trench capacitors.

3. The apparatus of claim 2, wherein each of the plurality of MIM trench capacitors comprises electrodes.

4. The apparatus of claim 3, further comprising a common plate coupled to a top portion of each of the electrodes in the plurality of MIM trench capacitors in the first high-density MIM trench capacitor and the second high-density MIM trench capacitor.

5. The apparatus of claim 4, further comprising:

a first plate coupled to a lower portion of each of the electrodes in the plurality of MIM trench capacitors in the first high-density MIM trench capacitor; and

a second plate coupled to a lower portion of each of the electrodes in the plurality of MIM trench capacitors in the second high-density MIM trench capacitor.

6. The apparatus of claim 5, wherein the first plate is coupled to the supply voltage and the second plate is coupled to ground.

7. The apparatus of claim 6, wherein the first plate and the second plate are terminals for the decoupling capacitor.

8. The apparatus of claim 7, wherein the first plate and the second plate are located in a first metal layer of the apparatus.

9. The apparatus of claim 8, wherein the common plate is located in a fifth metal layer of the apparatus.

10. An integrated circuit (IC) comprising a decoupling capacitor, including a first high-density metal-insulator-metal (MIM) trench capacitor coupled in series with a second high-density MIM trench capacitor.

11. The IC of claim 10, wherein the first high-density 3D MIM trench capacitor and the second high-density MIM trench capacitor each include a plurality of MIM trench capacitors.

12. The IC of claim 11, wherein each of the plurality of MIM trench capacitors comprises electrodes.

13. The IC of claim 12, further comprising a common plate coupled to a top portion of each of the electrodes in the plurality of MIM trench capacitors in the first high-density MIM trench capacitor and the second high-density MIM trench capacitor.

14. The IC of claim 13, further comprising:

a first plate coupled to a lower portion of each of the electrodes in the plurality of MIM trench capacitors in the first high-density MIM trench capacitor; and a second plate coupled to a lower portion of each of the electrodes in the plurality of MIM trench capacitors in the second high-density MIM trench capacitor.

15. The IC of claim 14, wherein the first plate is coupled to a supply voltage and the second plate is coupled to ground.

16. The IC of claim 15, wherein the first plate and the second plate are terminals for the decoupling capacitor.

17. The IC of claim 18, wherein the first plate and the second plate are located in a first metal layer of the IC.

18. The IC of claim 8, wherein the common plate is located in a fifth metal layer of the IC.

19. A dynamic random-access memory (DRAM) comprising:

a memory array including a plurality of high-density metal-insulator-metal (MIM) trench capacitors; and

a decoupling capacitor comprising a first of the plurality of the high-density MIM trench capacitors trench capacitor coupled in series with a second of the high- density MIM trench capacitors.

20. The DRAM of claim 19, wherein the first high-density MIM trench capacitor and the second high-density MIM trench capacitor each include a plurality of MIM trench capacitors.

21. The DRAM of claim 20, wherein each of the plurality of MIM trench capacitors comprises electrodes.

22. The DRAM of claim 21, further comprising a common plate coupled to a top portion of each of the electrodes in the plurality of MIM trench capacitors in the first high-density MIM trench capacitor and the second high-density MIM trench capacitor.

23. The DRAM of claim 22, further comprising:

24. The DRAM of claim 23, wherein the first plate is coupled to a supply voltage and the second plate is coupled to ground and are terminals for the decoupling capacitor.

25. The DRAM of claim 19, wherein the DRAM is an embedded dynamic random-access memory (eDRAM).