WO2018119604A1 - 指纹辨识系统 - Google Patents

指纹辨识系统 Download PDF

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Publication number
WO2018119604A1
WO2018119604A1 PCT/CN2016/112189 CN2016112189W WO2018119604A1 WO 2018119604 A1 WO2018119604 A1 WO 2018119604A1 CN 2016112189 W CN2016112189 W CN 2016112189W WO 2018119604 A1 WO2018119604 A1 WO 2018119604A1
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WO
WIPO (PCT)
Prior art keywords
circuit
top electrode
pixel
peripheral
peripheral top
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PCT/CN2016/112189
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English (en)
French (fr)
Inventor
杨孟达
Original Assignee
深圳市汇顶科技股份有限公司
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Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2016/112189 priority Critical patent/WO2018119604A1/zh
Priority to EP16925153.5A priority patent/EP3401834B1/en
Priority to CN201680002049.8A priority patent/CN106716445B/zh
Publication of WO2018119604A1 publication Critical patent/WO2018119604A1/zh
Priority to US16/055,617 priority patent/US10699096B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display

Definitions

  • the present application relates to a fingerprint identification system, and more particularly to a fingerprint identification system with small circuit area, low cost and low power consumption.
  • the pixel array circuit In the fingerprint identification system, the pixel array circuit is used to accept the contact of the finger, and the pixel array circuit converts the capacitance between the pixel array circuit and the finger into a pixel output signal. Since the pixel output signal is an analog signal, the pixel output signal needs to be converted into a digital signal. Then, the fingerprint judgment module is transmitted to the back end to determine that the pixel array circuit corresponds to a Finger Ridge or a Finger Valley. Wherein, the pixel array circuit in the fingerprint identification system consumes a large amount of power when capturing fingerprints, generally speaking, the pixel array The circuit is normally in the sleep mode, and only enters the normal operation mode for fingerprint recognition when it is touched by the user's finger, so as to achieve power saving effect.
  • a main object of some embodiments of the present invention is to provide a fingerprint identification system with small circuit area, low cost, and low power consumption to improve the shortcomings of the prior art.
  • the present application discloses a fingerprint identification system, which is formed in an integrated circuit, the fingerprint identification system includes a pixel array circuit, and the pixel array circuit determines whether to switch from a sleep mode to a normal operation mode according to a control signal; a first peripheral top electrode disposed on a first side of the pixel array circuit; a first capacitive sensing circuit coupled to the first top electrode for sensing in the sleep mode a capacitance of the first peripheral top electrode and a sensing result; and a logic control circuit coupled to the first capacitive sensing circuit for generating the control signal according to the sensing result; And when the sensing result indicates that the first peripheral top electrode is contacted by a finger, the logic control circuit generates the control signal, so that the pixel array circuit switches from the sleep mode to the normal operation a mode; wherein the pixel array circuit performs fingerprint identification on a finger in the normal operation mode.
  • FIG. 1 is a schematic top plan view of a circuit layout of a fingerprint identification system according to an embodiment of the present application.
  • FIG. 2 is a side view showing the circuit layout of the fingerprint identification system shown in FIG. 1.
  • FIG. 3 is a schematic top plan view of a circuit layout of a fingerprint identification system according to an embodiment of the present application.
  • FIG. 4 is a schematic side view showing the circuit layout side of the fingerprint identification system shown in FIG.
  • FIG. 5 is a schematic top plan view of a circuit layout of a fingerprint identification system according to an embodiment of the present application.
  • FIG. 6 is a side view showing the circuit layout of the fingerprint identification system shown in FIG. 5.
  • FIG. 7 is a schematic top plan view of a circuit layout of a fingerprint identification system according to an embodiment of the present application.
  • FIG. 8 is a side view showing the circuit layout of the fingerprint identification system shown in FIG. 7.
  • FIG. 8 is a side view showing the circuit layout of the fingerprint identification system shown in FIG. 7.
  • the present application proposes a fingerprint recognition system capable of waking up a pixel array circuit of a fingerprint recognition system in a sleep mode, which covers a peripheral top electrode on a peripheral circuit around the pixel array circuit, and senses the capacitance of the peripheral top electrode.
  • the sensing result shows that the fingerprint recognition system generates a control signal to wake up the pixel array circuit when the peripheral top electrode is touched by the user.
  • FIG. 1 is a schematic top view of a circuit layout of the fingerprint identification system 10 according to the embodiment of the present application
  • FIG. 2 is a schematic side view of the circuit layout of the fingerprint identification system 10
  • the fingerprint identification system 10 can be formed in an integrated circuit, and includes a pixel array circuit 12, a peripheral top electrode 14, a driving circuit 15, a capacitance sensing circuit 16, a peripheral circuit 17, and a logic control circuit 18.
  • the pixel array circuit 12 is configured to accept a finger contact of the user and sense the contact capacitance between the pixel array circuit 12 and the finger for fingerprint recognition.
  • the pixel array circuit 12 is usually in a sleep mode, and only when the user wants to use the pixel array circuit 12 When the fingerprint is recognized, the pixel array circuit 12 is awakened to enter a normal operation mode, and the user's finger is fingerprinted.
  • the pixel array circuit 12 can be controlled by a control signal ctrl and decide whether to switch from the sleep mode to the normal operation mode according to the control signal ctrl.
  • the peripheral top electrode 14 is disposed on one side of the pixel array circuit 12, and the peripheral top electrode 14 may be the topmost metal layer in the integrated circuit layout.
  • the capacitive sensing circuit 16 is coupled to the peripheral top electrode 14 for sensing the capacitance of the peripheral top electrode 14 in the sleep mode to determine whether the peripheral top electrode 14 is contacted by a finger and generating a sensing result Rst.
  • the logic control circuit 18 is coupled to the capacitance sensing circuit 16 for generating the control signal ctrl according to the sensing result Rst, that is, when the sensing result Rst indicates that the peripheral top electrode 14 is touched by the finger, the logic control circuit 18 generates control.
  • the signal ctrl causes the pixel array circuit 12 to switch from the sleep mode to the normal mode of operation.
  • the pixel array circuit 12 includes pixel top electrodes PX_1 - PX_N and a capacitance sensing circuit 120.
  • the pixel top electrodes PX_1 - PX_N are located at the uppermost layer of the circuit layout of the fingerprint recognition system 10 (ie, the pixel top electrodes PX_1 - PX_N are also The uppermost metal layer in the integrated circuit layout is used to receive a finger contact, and the pixel top electrodes PX_1 P PX_N may be arranged in an array; and the capacitive sensing circuit 120 is coupled to the pixel top electrodes PX_1 P PX_N for normal use.
  • the contact capacitance between the pixel top layer electrodes PX_1 P PX_N and the finger is sensed, so that the fingerprint identification system 10 can determine the top electrode PX_n of each pixel of the pixel top electrodes PX_1 P PX_N according to the sensing result of the capacitance sensing circuit 120.
  • a Finger Ridge or a Finger Valley corresponding to the finger is generated to produce a fingerprint recognition result corresponding to the finger.
  • the logic control circuit 18 can generate the control signal ctrl to cause the pixel array circuit 12 to switch from the normal operation mode to the sleep mode.
  • the capacitive sensing circuit 120 in the sleep mode, the capacitive sensing circuit 120 is in a Disable state, and in the normal operating mode, The capacitive sensing circuit 120 is in an enable state.
  • the logic control circuit 18 can generate the control signal ctrl, so that the capacitive sensing circuit 120 causes The power state (normal operation mode) is switched to the disabled state (sleep mode).
  • the capacitive sensing circuit 16 senses the capacitance between the peripheral top electrode 14 and a ground.
  • the fingerprint recognition system 10 can generate a driving signal TX1 to the peripheral top electrode 14 at a first time in the sleep mode by the driving circuit 15, and the capacitance sensing circuit 16 can be a second in the sleep mode. Measure the capacitance between the peripheral top electrode 14 and the ground, and generate the sensing result Rst.
  • the logic control circuit 18 can determine whether the peripheral top electrode 14 is in contact with the finger according to the sensing result Rst.
  • the control signal ctrl is generated according to the determination result, wherein the sensing result Rst can be a voltage signal or a current signal.
  • the peripheral top electrode 14 may be located at the periphery of the pixel array circuit 12 and overlying the peripheral circuit 17 (ie, the peripheral circuit 17 is disposed below the peripheral top electrode 14).
  • the peripheral circuit 17 is disposed on the periphery of the pixel array circuit 12, and can supply power to the pixel array circuit 12 or perform data capture on the pixel array circuit 12.
  • the peripheral circuit 17 can include a serial peripheral interface (Serial Peripheral Interface).
  • the Bus, SPI) circuit or a Low Dropout Regulator (LDO) circuit is not limited thereto.
  • FIG. 1 only the pixel array circuit 12 and the peripheral top electrode 14 are indicated by solid lines, and the driving circuit 15, the capacitance sensing circuit 16, the peripheral circuit 17, and the logic control circuit 18 are all indicated by broken lines.
  • the representative pixel array circuit 12 and the peripheral top electrode 14 have an uppermost metal layer, and the driving circuit 15, the capacitance sensing circuit 16, the peripheral circuit 17, and the logic control circuit 18 are The pixel array circuit 12 (and the peripheral top electrode 14) occupy different circuit layout areas (LayoutArea), or the actual circuit layout of the driving circuit 15, the capacitance sensing circuit 16, the peripheral circuit 17, and the logic control circuit 18 may be located at the pixel top electrode PX_1. ⁇ PX_N or below the peripheral top electrode 14 (as shown in Figure 2).
  • the peripheral top electrode 14 and the pixel top electrodes PX_1 to PX_N of the pixel array circuit 12 because the peripheral top electrode 14 and the pixel top electrodes PX_1 to PX_N are the most The upper metal layer
  • the actual circuit layout of the driving circuit 15, the capacitance sensing circuit 16, the peripheral circuit 17, and the logic control circuit 18 can be varied according to actual needs.
  • the fingerprint identification system 10 of the present application is normally in a sleep mode.
  • the user wants to perform fingerprint recognition, the user needs to press his finger on the pixel array circuit 12, and the user's finger will inevitably touch the peripheral top electrode. 14.
  • the capacitance between the peripheral top electrode 14 and the ground is varied, and the capacitance sensing circuit 16 senses a change in the capacitance of the peripheral top electrode 14 and accordingly generates a sensing result Rst.
  • the logic control circuit 18 When the sensing result Rst indicates that the fingerprint recognition system 10 is in contact with a finger, the logic control circuit 18 generates a control signal ctrl to cause the pixel array circuit 12 to switch from the sleep mode to the normal operation mode.
  • conventional techniques utilize additional components (such as electrodes external to the integrated circuit on which the fingerprint recognition system resides and which may be metal rings) to detect whether the fingerprint recognition system is in contact with the user's fingers.
  • the present application can detect whether the fingerprint identification system is touched by the user's finger by using only the peripheral top electrode which is covered in the peripheral circuit and formed in the integrated circuit, without requiring additional circuit layout area (reuse only The circuit layout area occupied by the peripheral circuit does not require additional components such as metal rings to achieve the function of detecting contact with the user's fingers.
  • the present application has the advantages of small circuit area, low cost, and low power consumption.
  • FIG. 3 is a schematic top view of a circuit layout of the fingerprint identification system 30 according to the embodiment of the present application
  • FIG. 4 is a schematic side view of the circuit layout of the fingerprint identification system 30 .
  • the fingerprint identification system 30 is similar to the fingerprint recognition system 10, so the same components follow the same symbols.
  • the fingerprint identification system 30 includes a peripheral top electrode 34a and a peripheral top electrode 34b.
  • the peripheral top electrode 34a and the peripheral top electrode 34b are respectively disposed on a first side and a second of the pixel array circuit 12.
  • the side for example, the second side is the opposite side of the first side.
  • the peripheral top electrode 34a is coupled to a capacitor sensing circuit 36
  • the peripheral top electrode 34b is coupled to a driving circuit 35.
  • the fingerprint recognition system 30 can generate a driving signal TX2 to the peripheral top electrode 34b at a third time in the sleep mode by the driving circuit 35, and the capacitance sensing circuit 36 can be a fourth in the sleep mode.
  • the time measurement measures a capacitance change between the peripheral top electrode 34a and the peripheral top electrode 34b, and generates a sensing result Rst.
  • the logic control circuit 18 can judge according to the sensing result Rst.
  • the fingerprint recognition system 30 Whether or not the fingerprint recognition system 30 is in contact with a finger generates a control signal ctrl accordingly.
  • the operation principle and details of the remaining fingerprint identification system 30 are similar to those of the fingerprint identification system 10, and will not be described herein.
  • the difference from the fingerprint recognition system 10 is that in the fingerprint identification system 10, the capacitance sensing circuit 16 senses the capacitance between the peripheral top electrode 14 and the ground; and in the fingerprint recognition system 30, the capacitance sensing circuit 36 senses The mutual capacitance between the peripheral top electrode 34a and the peripheral top electrode 34b is measured.
  • FIG. 5 is a schematic top view of the circuit layout of the fingerprint identification system 50 according to the embodiment of the present application
  • FIG. 6 is a schematic side view of the circuit layout of the fingerprint identification system 50.
  • the fingerprint identification system 50 includes a pixel array circuit 52, a peripheral top electrode 54, a capacitance sensing circuit 56, and a logic control circuit 18.
  • the pixel array circuit 52 includes pixel top electrodes PX_1 - PX_N and a capacitor.
  • the sensing circuit 520 and a driving circuit 522 is a driving circuit 522.
  • the fingerprint recognition system 50 can generate a driving signal TX3 to the pixel top electrodes PX_1 PPX_N in a fifth time in the sleep mode by using the driving circuit 522, and the capacitive sensing circuit 56 can be in the sleep mode.
  • the sixth time measures the capacitance change of a mutual capacitance between the peripheral top electrode 54 and the pixel top electrodes PX_1 P PX_N, and accordingly generates a sensing result Rst.
  • the logic control circuit 18 can judge according to the sensing result Rst. Whether or not the fingerprint recognition system 50 is in contact with a finger generates a control signal ctrl accordingly.
  • the operation principle and details of the remaining fingerprint identification system 50 are similar to those of the fingerprint identification system 10, 30, and will not be described herein.
  • the difference from the fingerprint recognition system 30 is that in the fingerprint recognition system 30, the capacitance sensing circuit 36 senses the mutual capacitance between the peripheral top electrode 34a and the peripheral top electrode 34b; in the fingerprint identification system 50, the capacitance sensing circuit 56 senses the mutual capacitance between the peripheral top electrode 54 and the pixel top electrodes PX_1 P PX_N.
  • FIG. 7 is a schematic top view of the circuit layout of the fingerprint identification system 70 according to the embodiment of the present application
  • FIG. 8 is a schematic side view of the circuit layout of the fingerprint identification system 70.
  • the fingerprint identification system 70 is similar to the fingerprint recognition system 50, so the same components follow the same symbols.
  • the fingerprint identification system 70 includes peripheral top electrodes 74a, 74b and capacitance sensing circuits 76a, 76b.
  • the peripheral top electrode 74a and the peripheral top electrode 74b are respectively disposed on a first side of the pixel array circuit 52.
  • the side and a third side for example, the third side is the opposite side of the first side.
  • the capacitive sensing circuits 76a, 76b are respectively coupled to the peripheral top electrodes 74a, 74b for measuring the capacitance changes of the mutual capacitance between the peripheral top electrodes 74a, 74b and the pixel top electrodes PX_1 - PX_N, respectively.
  • the operation principle and details of the remaining fingerprint identification system 70 are similar to those of the fingerprint identification system 10, 30, 50, and will not be described herein.
  • the present application utilizes a peripheral top electrode disposed on the periphery of the pixel array circuit, and A capacitance sensing circuit coupled to the peripheral top electrode senses a change in capacitance of the peripheral top electrode in the sleep mode to determine whether the fingerprint recognition system is in contact with the user's finger.
  • the logic control circuit When the fingerprint recognition system is touched by the user's finger, the logic control circuit generates a control signal to cause the pixel array circuit to switch from the sleep mode to the normal operation mode to achieve a power saving effect.

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  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
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Abstract

一种指纹辨识系统(10)，形成于一集成电路中，所述指纹辨识系统包含有一像素阵列电路(12)；一第一外围顶层电极(14)；一第一电容感测电路(16)，用来于所述休眠模式中感测相关于所述第一外围顶层电极(14)的电容，并产生一感测结果；以及一逻辑控制电路(18)，用来根据所述感测结果产生所述控制信号；其中，当所述感测结果显示所述第一外围顶层电极(14)受到一手指的接触时，所述逻辑控制电路(18)产生所述控制信号，使得所述像素阵列电路(12)自一休眠模式切换至一正常操作模式。

Description

指纹辨识系统 技术领域
本申请涉及一种指纹辨识系统，尤其涉及一种电路面积小、成本低且低功耗的指纹辨识系统。
背景技术
随着科技日新月异，移动电话、数字相机、平板计算机、笔记本电脑等越来越多携带型电子装置已经成为了人们生活中必备的工具。由于携带型电子装置一般为个人使用，而具有一定的隐私性，因此其内部储存的数据，例如电话簿、相片、个人信息等等为私人所有。若电子装置一旦丢失，则这些数据可能会被他人所利用，而造成不必要的损失。虽然目前已有利用密码保护的方式来避免电子装置为他人所使用，但密码容易泄露或遭到破解，具有较低的安全性。并且，用户需记住密码才能使用电子装置，若忘记密码，则会带给使用者许多不便。因此，目前发展出利用个人指纹辨识系统的方式来达到身份认证的目的，以提升数据安全性。
指纹辨识系统中利用像素阵列电路接受手指的接触，像素阵列电路将像素阵列电路与手指之间的电容转换成像素输出信号，因像素输出信号为模拟信号，像素输出信号需转换成数字信号后，再传送至后端的指纹判断模块以判断像素数组电路对应于指纹的纹峰(Finger Ridge)或纹谷(Finger Valley)。其中，指纹识别系统中像素阵列电路撷取指纹时功耗较大，一般来说，像素阵列 电路平时处于休眠模式，仅当受到使用者手指接触时，才进入所述正常操作模式进行指纹辨识，以达到省电的功效。
因此，如何判断是否受到使用者手指接触，就成为业界所努力的目标之一。
发明内容
因此，本发明部分实施例主要目的即在于提供一种电路面积小、成本低且低功耗的指纹辨识系统，以改善习知技术的缺点。
本申请揭露一种指纹辨识系统，形成于一集成电路中，所述指纹辨识系统包含有一像素阵列电路，所述像素阵列电路根据一控制信号决定是否自一休眠模式切换至一正常操作模式；一第一外围顶层电极，设置于所述像素阵列电路的一第一侧边；一第一电容感测电路，耦接于所述第一顶层电极，用来于所述休眠模式中感测相关于所述第一外围顶层电极的电容，并产生一感测结果；以及一逻辑控制电路，耦接于所述第一电容感测电路，用来根据所述感测结果产生所述控制信号；其中，当所述感测结果显示所述第一外围顶层电极受到一手指的接触时，所述逻辑控制电路产生所述控制信号，使得所述像素阵列电路自所述休眠模式切换至所述正常操作模式；其中，所述像素阵列电路于所述正常操作模式中，对一手指进行指纹辨识。
附图说明
图1为本申请实施例一指纹辨识系统的电路布局俯视示意图。
图2为图1所示指纹辨识系统的电路布局侧视示意图。
图3为本申请实施例一指纹辨识系统的电路布局俯视示意图。
图4为图3所示指纹辨识系统的电路布局侧示意视图。
图5为本申请实施例一指纹辨识系统的电路布局俯视示意图。
图6为图5所示指纹辨识系统的电路布局侧视示意图。
图7为本申请实施例一指纹辨识系统的电路布局俯视示意图。
图8为图7所示指纹辨识系统的电路布局侧视示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请提出一种可于休眠模式中将指纹识别系统的像素阵列电路唤醒的指纹识别系统，其于像素阵列电路四周的外围电路覆盖一层外围顶层电极，并感测外围顶层电极的电容，当感测结果显示外围顶层电极受到使用者的接触时，指纹识别系统才产生控制信号，以唤醒像素阵列电路。
具体来说，请参考图1及图2，图1为本申请实施例一指纹辨识系统10的电路布局(Layout)俯视示意图，图2为指纹辨识系统10的电路布局侧视示意图。指纹辨识系统10可形成于一集成电路中，其包含一像素阵列电路12、一外围顶层电极14、一驱动电路15、一电容感测电路16、一外围电路17以及一逻辑控制电路18。像素阵列电路12用来接受使用者一手指的接触，并感测像素阵列电路12与手指之间的接触电容，以进行指纹辨识。为了达到省电效果，像素阵列电路12通常处于一休眠模式，而仅当用户欲利用像素阵列电路12进 行指纹辨识时，像素阵列电路12才会被唤醒而进入一正常操作模式，而对用户的手指进行指纹辨识。具体来说，像素阵列电路12可受控于一控制信号ctrl，并根据控制信号ctrl决定是否自休眠模式切换至正常操作模式。另外，外围顶层电极14设置于像素阵列电路12的一侧边，外围顶层电极14可为集成电路布局中最上层的金属层(Top Metal)。电容感测电路16耦接于外围顶层电极14，用来于休眠模式中感测外围顶层电极14的电容，以判断外围顶层电极14是否受到一手指的接触，并产生一感测结果Rst。逻辑控制电路18耦接于电容感测电路16，用来根据感测结果Rst产生控制信号ctrl，也就是说，当感测结果Rst显示外围顶层电极14受到手指接触时，逻辑控制电路18产生控制信号ctrl，使得像素阵列电路12自休眠模式切换至正常操作模式。
更进一步地，像素阵列电路12包含像素顶层电极PX_1～PX_N以及一电容感测电路120，像素顶层电极PX_1～PX_N位于指纹辨识系统10的电路布局的最上层(即像素顶层电极PX_1～PX_N亦为集成电路布局中最上层的金属层)，用来接受一手指的接触，像素顶层电极PX_1～PX_N可排列成一阵列；而电容感测电路120耦接于像素顶层电极PX_1～PX_N，用来于正常操作模式中感测像素顶层电极PX_1～PX_N与手指之间的接触电容，使得指纹辨识系统10可根据电容感测电路120的感测结果，判断像素顶层电极PX_1～PX_N中每一像素顶层电极PX_n对应至手指的一纹峰(Finger Ridge)或一纹谷(Finger Valley)，以产生对应于手指的一指纹辨识结果。另外，于正常操作模式中指纹辨识系统10产生指纹辨识结果后，逻辑控制电路18可产生控制信号ctrl，使得像素阵列电路12自正常操作模式切换至休眠模式。于一实施例中，于休眠模式时，电容感测电路120为一禁能(Disable)状态，而于正常操作模式时， 电容感测电路120为一致能(Enable)状态，换句话说，于正常操作模式中指纹辨识系统10产生指纹辨识结果后，逻辑控制电路18可产生控制信号ctrl，使得电容感测电路120由致能状态(正常操作模式)切换至禁能状态(休眠模式)。
另外，于休眠模式中(电容感测电路120为禁能状态)，电容感测电路16可感测外围顶层电极14与一接地端之间的电容。于一实施例中，指纹辨识系统10可利用驱动电路15于休眠模式中的一第一时间产生一驱动信号TX1至外围顶层电极14，而电容感测电路16可于休眠模式中的一第二时间量测外围顶层电极14与接地端之间的电容，并据以产生感测结果Rst，此时，逻辑控制电路18即可根据感测结果Rst判断外围顶层电极14是否受到手指的接触，进而根据判断结果产生控制信号ctrl，其中，感测结果Rst可为电压信号或是电流信号。
另外，外围顶层电极14可位于像素阵列电路12的外围，且覆盖于外围电路17的上方(即外围电路17设置于外围顶层电极14的下方)。其中，外围电路17设置于像素阵列电路12的外围，其可对像素阵列电路12供电或对像素阵列电路12进行数据撷取，例如，外围电路17可包含一串行外设接口(Serial Peripheral Interface Bus，SPI)电路或是一低压差稳压器(Low Dropout Regulator，LDO)电路，而不限于此。
需注意的是，于图1中，仅像素阵列电路12以及外围顶层电极14为实线标示，而驱动电路15、电容感测电路16、外围电路17以及逻辑控制电路18皆以虚线标示，其代表像素阵列电路12以及外围顶层电极14具有最上层金属层，而驱动电路15、电容感测电路16、外围电路17以及逻辑控制电路18可与 像素阵列电路12(及外围顶层电极14)占用不同电路布局区域(LayoutArea)，或者，驱动电路15、电容感测电路16、外围电路17以及逻辑控制电路18的实际电路布局可位于像素顶层电极PX_1～PX_N或外围顶层电极14的下方(如图2所示)。换句话说，于指纹辨识系统10的电路布局俯视图中，至少会出现外围顶层电极14以及像素阵列电路12的像素顶层电极PX_1～PX_N(因外围顶层电极14及像素顶层电极PX_1～PX_N皆为最上层金属层)，而驱动电路15、电容感测电路16、外围电路17以及逻辑控制电路18的实际电路布局可根据实际需要而变化。
简言之，本申请的指纹辨识系统10平时处于休眠模式，当用户欲进行指纹辨识时，使用者需将其手指按压于像素阵列电路12之上，使用者的手指难免会接触到外围顶层电极14，而使外围顶层电极14与接地端之间的电容产生变化，电容感测电路16可感测外围顶层电极14的电容产生变化，并据以产生感测结果Rst。当感测结果Rst显示指纹辨识系统10受到手指接触时，逻辑控制电路18产生控制信号ctrl，使得像素阵列电路12自休眠模式切换至正常操作模式。
另外，习知技术利用额外的元件(如于指纹辨识系统所在的集成电路外且环绕集成电路的电极，其可为金属环)来侦测指纹辨识系统是否受到用户手指的接触。相较之下，本申请仅利用覆盖于外围电路且形成于集成电路中的外围顶层电极，即可侦测指纹辨识系统是否受到用户手指的接触，而不需要额外的电路布局面积(仅重复利用外围电路所占用的电路布局面积)，亦不需要如金属环之类的额外的元件，即可达到侦测是否受到使用者手指的接触的功效。换句话说，本申请具有电路面积小、成本低且低功耗的优点。
需注意的是，前述实施例用以说明本申请之概念，本领域具通常知识者当可据以做不同之修饰，而不限于此。举例来说，请参考图3及图4，图3为本申请实施例一指纹辨识系统30的电路布局俯视示意图，图4为指纹辨识系统30的电路布局侧视示意图。指纹辨识系统30与指纹辨识系统10类似，故相同组件沿用相同符号。相较于指纹辨识系统10，指纹辨识系统30包含有外围顶层电极34a以及外围顶层电极34b，外围顶层电极34a及外围顶层电极34b分别设置于像素阵列电路12的一第一侧边及一第二侧边，例如，第二侧边为第一侧边的对边。外围顶层电极34a耦接于一电容感测电路36，外围顶层电极34b耦接于一驱动电路35。于一实施例中，指纹辨识系统30可利用驱动电路35于休眠模式中的一第三时间产生一驱动信号TX2至外围顶层电极34b，而电容感测电路36可于休眠模式中的一第四时间量测外围顶层电极34a与外围顶层电极34b之间的一相互电容(Mutual Capacitance)的电容变化，并据以产生感测结果Rst，此时，逻辑控制电路18即可根据感测结果Rst判断指纹辨识系统30是否受到手指的接触，而据以产生控制信号ctrl。其余指纹辨识系统30的操作原理及细节与指纹辨识系统10类似，于此不再赘述。与指纹辨识系统10不同之处在于，于指纹辨识系统10中，电容感测电路16感测外围顶层电极14与接地端之间的电容；而于指纹辨识系统30中，电容感测电路36感测外围顶层电极34a与外围顶层电极34b之间的相互电容。
另外，请参考图5及图6，图5为本申请实施例一指纹辨识系统50的电路布局俯视示意图，图6为指纹辨识系统50的电路布局侧视示意图。指纹辨识系统50包含一像素阵列电路52、一外围顶层电极54、一电容感测电路56以及逻辑控制电路18，像素阵列电路52包含像素顶层电极PX_1～PX_N、一电容 感测电路520以及一驱动电路522。于一实施例中，指纹辨识系统50可利用驱动电路522于休眠模式中的一第五时间产生一驱动信号TX3至像素顶层电极PX_1～PX_N，而电容感测电路56可于休眠模式中的一第六时间量测外围顶层电极54与像素顶层电极PX_1～PX_N之间的一相互电容的电容变化，并据以产生感测结果Rst，此时，逻辑控制电路18即可根据感测结果Rst判断指纹辨识系统50是否受到手指的接触，而据以产生控制信号ctrl。其余指纹辨识系统50的操作原理及细节与指纹辨识系统10、30类似，于此不再赘述。与指纹辨识系统30不同之处在于，于指纹辨识系统30中，电容感测电路36感测外围顶层电极34a与外围顶层电极34b之间的相互电容；于指纹辨识系统50中，电容感测电路56感测外围顶层电极54与像素顶层电极PX_1～PX_N之间的相互电容。
另外，请参考图7及图8，图7为本申请实施例一指纹辨识系统70的电路布局俯视示意图，图8为指纹辨识系统70的电路布局侧视示意图。指纹辨识系统70与指纹辨识系统50类似，故相同组件沿用相同符号。与指纹辨识系统50不同的是，指纹辨识系统70包含外围顶层电极74a、74b以及电容感测电路76a、76b，外围顶层电极74a及外围顶层电极74b分别设置于像素阵列电路52的一第一侧边及一第三侧边，例如，第三侧边为第一侧边的对边。电容感测电路76a、76b分别耦接于外围顶层电极74a、74b，分别用来量测外围顶层电极74a、74b与像素顶层电极PX_1～PX_N之间的相互电容的电容变化。
其余指纹辨识系统70的操作原理及细节与指纹辨识系统10、30、50类似，于此不再赘述。
综上所述，本申请利用设置于像素阵列电路外围的外围顶层电极，并利 用耦接于外围顶层电极的电容感测电路，于休眠模式中感测外围顶层电极的电容变化，以判断指纹辨识系统是否受到用户手指的接触。当指纹辨识系统受到用户手指的接触时，逻辑控制电路产生控制信号，使得像素阵列电路自休眠模式切换至正常操作模式，以达到省电效果。
以上所述仅为本申请的部分实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (13)

  1. 一种指纹辨识系统，形成于一集成电路中，其中，所述指纹辨识系统包含有：
    一像素阵列电路，所述像素阵列电路根据一控制信号切换至一正常操作模式；
    一第一外围顶层电极，设置于所述像素阵列电路的一第一侧边；
    一第一电容感测电路，耦接于所述第一外围顶层电极，用来于所述休眠模式中感测相关于所述第一外围顶层电极的电容，并产生一感测结果；以及
    一逻辑控制电路，耦接于所述第一电容感测电路，用来根据所述感测结果产生所述控制信号；
    其中，当所述感测结果显示所述第一外围顶层电极受到一手指的接触时，所述逻辑控制电路产生所述控制信号，使得所述像素阵列电路自所述休眠模式切换至所述正常操作模式；
    其中，所述像素阵列电路于所述正常操作模式中，对一手指进行指纹辨识。
  2. 如权利要求1所述的指纹辨识系统，其中，另包含一外围电路，所述外围电路设置于所述第一外围顶层电极的下方。
  3. 如权利要求1所述的指纹辨识系统，其中，另包含：
    一第一驱动电路，用来于所述休眠模式中产生一第一驱动信号至所述第一外围顶层电极；
    其中，所述第一电容感测电路于所述休眠模式中量测所述第一外围顶层电极与一接地端之间的电容。
  4. 如权利要求1所述的指纹辨识系统，其中，另包含：
    一第二外围顶层电极，设置于所述像素阵列电路的一第二侧边。
  5. 如权利要求4所述的指纹辨识系统，其中，另包含：
    一第二驱动电路，耦接于所述第二外围顶层电极，用来于所述休眠模式中产生一驱动信号至所述第二外围顶层电极；
    其中，所述第一电容感测电路于所述休眠模式中量测所述第一外围顶层电极与所述第二外围顶层电极之间的一相互电容。
  6. 如权利要求4所述的指纹辨识系统，其中，所述第二侧边为所述第一侧边的一对边。
  7. 如权利要求1所述的指纹辨识系统，其中，所述像素阵列电路包含有：
    复数个像素顶层电极，用来接受一手指的接触，所述复数个像素顶层电极排列成一阵列；以及
    一第三电容感测电路，耦接于所述复数个像素顶层电极，用来于所述正常操作模式中，所述第三电容感测电路感测所述复数个像素顶层电极与所述手指之间的接触电容，使得所述指纹辨识系统判断每一像素顶层电极对应至一纹峰或一纹谷，以产生对应于所述手指的一指纹辨识结果。
  8. 如权利要求7所述的指纹辨识系统，其中，另包含：
    一第三驱动电路，耦接于所述复数个像素顶层电极，用来于所述休眠模式中产生一第三驱动信号至所述复数个像素顶层电极；
    其中，所述第一电容感测电路于所述休眠模式中量测所述第一外围顶层电极与所述复数个像素顶层电极之间的一相互电容。
  9. 如权利要求7所述的指纹辨识系统，其中，于所述指纹辨识系统产生所述指纹辨识结果后，所述像素阵列电路进入所述休眠模式。
  10. 如权利要求7所述的指纹辨识系统，其中，于所述休眠模式中，所述第三电容感测电路为禁能。
  11. 如权利要求7所述的指纹辨识系统，其中，另包含：
    一第三外围顶层电极，设置于所述像素阵列电路的一第三侧边。
  12. 如权利要求11所述的指纹辨识系统，其中，所述第三侧边为所述第一侧边的一对边。
  13. 如权利要求11所述的指纹辨识系统，其中，
    一第四电容感测电路，耦接于所述第三外围顶层电极；
    其中，所述第一电容感测电路于所述休眠模式中量测所述第三外围顶层电极与所述复数个像素顶层电极之间的一相互电容。
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