WO2018118315A1 - Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology - Google Patents

Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology Download PDF

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Publication number
WO2018118315A1
WO2018118315A1 PCT/US2017/062621 US2017062621W WO2018118315A1 WO 2018118315 A1 WO2018118315 A1 WO 2018118315A1 US 2017062621 W US2017062621 W US 2017062621W WO 2018118315 A1 WO2018118315 A1 WO 2018118315A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor die
interposer
major surface
semiconductor
pillar
Prior art date
Application number
PCT/US2017/062621
Other languages
French (fr)
Inventor
Thomas H. Kinsley
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to JP2019531054A priority Critical patent/JP6770648B2/en
Priority to KR1020197019913A priority patent/KR102342690B1/en
Priority to EP17884980.8A priority patent/EP3559987A4/en
Priority to CN201780072758.8A priority patent/CN109983572B/en
Publication of WO2018118315A1 publication Critical patent/WO2018118315A1/en

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    • H—ELECTRICITY
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    • H01L23/367—Cooling facilitated by shape of device
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    • H01L23/367—Cooling facilitated by shape of device
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    • H01L2023/4068—Heatconductors between device and heatsink, e.g. compliant heat-spreaders, heat-conducting bands
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Definitions

  • the present technology is related to semiconductor die assemblies.
  • Packaged semiconductor dies typically include a singulated die containing semiconductor-based integrated circuity, and a plastic protective covering encasing the die.
  • the die includes functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features.
  • the bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry.
  • multiple semiconductor dies are incorporated into a single package. Individual semiconductor dies in a multiple-die package can have some dedicated packaging features and other packaging features shared with other semiconductor dies in the package. This approach increases the processing capacity, memory, etc. that can be contained in a small space.
  • Some multiple-die packages include a single stack of vertically aligned semiconductor dies.
  • Other multiple-die packages include semiconductor dies that are laterally offset from one another at the same or different elevations.
  • heat dissipation is often a significant design constraint.
  • the combined heat generated by semiconductor dies in a multiple-die package can cause the individual dies to reach temperatures above their maximum operating temperatures.
  • the combined heat may also reduce the performance and reliability of electrical interconnects between the dies.
  • These and other heat-related problems typically become more acute as the density of dies in a multiple-die package increases. Accordingly, enhancing heat dissipation from semiconductor dies in multiple-die packages has the potential to improve performance, improve reliability, and allow for further miniaturization to meet market demands.
  • Figure 1 is a side view of the semiconductor die assembly in accordance with an embodiment of the present technology.
  • Figures 2 and 3 are exploded side views of the semiconductor die assembly shown in Figure 1.
  • Figure 4 is a top plan view of a lower subassembly of the semiconductor die assembly shown in Figure 1.
  • Figure 5 is a top plan view of an upper subassembly of the semiconductor die assembly shown in Figure 1.
  • Figure 6 is a flow chart illustrating a method for making the semiconductor die assembly shown in Figure 1 in accordance with an embodiment of the present technology.
  • Figure 7 is a flow chart illustrating a method for operating the semiconductor die assembly shown in Figure 1 in accordance with an embodiment of the present technology.
  • Figure 8 is a side view of a heat spreader of a semiconductor die assembly in accordance with another embodiment of the present technology.
  • Figure 9 is an exploded side view of the heat spreader shown in Figure 8.
  • Figure 10 is a top plan view of the heat spreader shown in Figure 8.
  • Figure 1 1 is a side view of a lower subassembly of a semiconductor die assembly in accordance with another embodiment of the present technology.
  • Figure 12 is a top plan view of the lower subassembly shown in Figure 1 1.
  • Figure 13 is a schematic view of a system that includes a semiconductor die assembly in accordance with an embodiment of the present technology
  • interposers between semiconductor dies at different elevations often interfere with heat dissipation.
  • Conventional interposers are most often made primarily of epoxy resin or another low thermal conductivity material. Therefore, instead of dissipating heat in an upward direction, heat is primarily dissipated from semiconductor dies underlying such interposers in conventional multiple-die packages laterally via relatively thin layers of material overlying and/or underlying the die.
  • capillary underfill material between a package substrate and a die underlying a thermally insulative interposer may serve as the primary pathway for conveying heat away from the die toward a metal casing or another type of external heat spreader.
  • Semiconductor die assemblies and related devices, systems, and methods in accordance with embodiments of the present technology can at least partially address the foregoing and/or other problems associated with conventional technologies.
  • Semiconductor die assemblies in accordance with at least some embodiments of the present technology include a heat spreader having a cap thermally coupled to a die above an interposer, and a pillar thermally coupled to a die below the interposer.
  • the pillar can extend through an opening in the interposer. In this way, vertical heat dissipation from the die below the interposer can be significantly enhanced.
  • Other advantages in addition to or instead of this advantage also may be present.
  • semiconductor die assemblies and related devices, systems, and methods in accordance with embodiments of the present technology can have features in addition to or instead of features associated with heat spreading pillars that pass through openings in the associated interposers.
  • Figure 1 is a side view of a semiconductor die assembly 100 in accordance with an embodiment of the present technology
  • Figure 2 is an exploded side view of the semiconductor die assembly 100.
  • the semiconductor die assembly 100 can include a package substrate 102 carrying an interposer 104 and a heat spreader 106.
  • the package substrate 102 has an upper major surface 108 closer to the interposer 104 and a lower major surface 109 father from the interposer 104.
  • the interposer 104 has an upper major surface 1 10 farther from the package substrate 102 and a lower major surface 1 1 1 closer to the package substrate 102.
  • the semiconductor die assembly 100 can include a plurality of first decoupling capacitors 1 12 (one labeled) electrically connected to the interposer 104, and a plurality of second decoupling capacitors 1 13 (one labeled) electrically connected to the package substrate 102.
  • the interposer 104 and the package substrate 102 can include internal circuitry (not shown) operably connected to the plurality of first decoupling capacitors 1 12 and the plurality of second decoupling capacitors 113, respectively.
  • the semiconductor die assembly 100 can further include laterally spaced apart first solder-ball interconnects 1 14 electrically coupling the interposer 104 (along its lower major surface 1 1 1) to the package substrate 102 (along its upper major surface 108).
  • the first solder-ball interconnects 1 14 are arranged in two peripheral rows 1 16 (individually identified as rows 1 16a, 1 16b in Figure 2) and a central array 1 18 ( Figure 2) between the rows 1 16a, 1 16b.
  • counterparts of the first solder-ball interconnects 1 14 can have other suitable arrangements.
  • the semiconductor die assembly 100 further includes laterally spaced apart second solder-ball interconnects 120 (one labeled) electrically coupled to the package substrate 102 along its lower major surface 109.
  • the second solder-ball interconnects 120 can be configured to electrically connect the overall semiconductor die assembly 100 to higher level circuitry (not shown).
  • the semiconductor die assembly 100 can include a plurality of first semiconductor dies 122 electrically coupled to the interposer 104.
  • the semiconductor die assembly 100 can further include a second semiconductor die 124 electrically coupled to the package substrate 102.
  • the plurality of first semiconductor dies 122 are electrically coupled to both the upper major surface 1 10 and the lower major surface 1 1 1 of the interposer 104.
  • the semiconductor die assembly 100 can include four first semiconductor dies 122 (individually identified as first semiconductor dies 122a-122d), and, at the lower major surface 1 11 of the interposer 104, the semiconductor die assembly 100 can include another four first semiconductor dies 122 (individually identified as first semiconductor dies 122e-122h).
  • first semiconductor dies 122c, 122d, 122g, 122h are hidden behind the first semiconductor dies 122a, 122b, 122e, 122f.
  • the first semiconductor dies 122a-122d can be laterally offset from one another at one elevation
  • the first semiconductor dies 122e-122h can be laterally offset from one another at another elevation.
  • Electrical couplings between the first semiconductor dies 122a- 122h and the interposer 104 and between the second semiconductor die 124 and the package substrate 102 are omitted for clarity of illustration.
  • a counterpart of the semiconductor die assembly 100 can include a different number and/or arrangement of first and second semiconductor dies, such as an arrangement in which first semiconductor dies are electrically connected to only one of two major surfaces of an associated interposer.
  • the first semiconductor dies 122a-122h are memory dies and the second semiconductor die 124 is a logic die.
  • heat generated by the second semiconductor die 124 may be significantly greater than heat generated by the plurality of first semiconductor dies 122 during normal operation of the semiconductor die assembly 100.
  • the semiconductor die assembly 100 can include features that facilitate efficient vertical dissipation of the heat generated by the second semiconductor die 124 when the semiconductor die assembly 100 is in the illustrated orientation (e.g., upward with respect to the horizontal orientation of the package substrate 102 in Figure 1).
  • the heat spreader 106 can include a pillar 126 and a cap 128 extending around the pillar 126 (e.g., extending around at least 75% of a perimeter of the pillar 126).
  • the cap 128 can be positioned to be thermally coupled to the first semiconductor dies 122a- 122d at one elevation, and the pillar 126 can be positioned to be thermally coupled to the second semiconductor die 124 at another elevation.
  • the semiconductor die assembly 100 is in the illustrated orientation, the elevation at which the cap 128 is thermally coupled to the first semiconductor dies 122a- 122d is above the interposer 104, and the elevation at which the pillar 126 is thermally coupled to the second semiconductor die 124 is below the interposer 104.
  • the pillar 126 can extend through a plane occupied by the interposer 104 (e.g., the pillar 126 can extend through an opening in the interposer 104).
  • the pillar 126 and the cap 128 are integral components of the heat spreader 106.
  • a counterpart heat spreader 106 can include a pillar and a cap that are separate components coupled together or are noncontiguous (e.g., spaced apart from each other).
  • a counterpart heat spreader 106 can include a pillar that extends through an opening at least partially defined by a corresponding cap such that the cap extends around at least 75% of a perimeter of the pillar. Other noncontiguous configurations are also possible.
  • the semiconductor die assembly 100 can further include thermal interface features 130 (Figure 2) through which the heat spreader 106 is thermally coupled to the first semiconductor dies 122a- 122d and to the second semiconductor die 124.
  • Some of the thermal interface features 130 can be directly connected to upper surfaces of the first semiconductor dies 122a-122d, respectively, and to corresponding portions of a lower surface of the cap 128 when the semiconductor die assembly 100 is in the illustrated orientation.
  • Another one of the thermal interface features 130 can be directly connected to an upper surface of the second semiconductor die 124 and to a lower surface of the pillar 126 when the semiconductor die assembly 100 is in the illustrated orientation.
  • the heat spreader 106 can be shaped such that an elevation difference between the lower surface of the cap 128 and the lower surface of the pillar 126 corresponds to an elevation difference between the upper surfaces of the first semiconductor dies 122a-122d and the upper surface of the second semiconductor die 124 when the semiconductor die assembly 100 is in the illustrated orientation.
  • the thermal interface features 130 can be configured to fill voids and to smooth irregularities at interfaces between the heat spreader 106 and the first semiconductor dies 122a- 122d and between the heat spreader 106 and the second semiconductor die 124.
  • the thermal interface features 130 are volumes of thermal interface paste, such as silicone -based grease doped with thermally conductive particles.
  • counterparts of one, some, or all of the thermal interface features 130 can be pieces of thermal interface tape or have another suitable form to enhance thermal conductivity and/or to secure the heat spreader 106 to the first semiconductor dies 122a- 122d and to the second semiconductor die 124.
  • Figure 3 is another exploded via of the semiconductor die assembly 100. As shown in Figure 3, the semiconductor die assembly 100 can include a lower subassembly 132 and an upper subassembly 134 configured to be assembled with the heat spreader 106.
  • the lower subassembly 132 can include the package substrate 102, the second decoupling capacitors 1 13, the second solder-ball interconnects 120, the second semiconductor die 124, and the thermal interface feature 130 associated with the second semiconductor die 124.
  • the upper subassembly 134 can include the interposer 104, the first decoupling capacitors 1 12, the first solder-ball interconnects 114, the plurality of first semiconductor dies 122, and the thermal interface features 130 associated with the plurality of first semiconductor dies 122.
  • Figure 4 is a top plan view of the lower subassembly 132. As shown in Figure 4, the package substrate 102 can include bond pads 136 (one labeled) vertically aligned with the first solder-ball interconnects 1 14. The second semiconductor die 124 can be centrally positioned on the package substrate 102.
  • Figure 5 is a top plan view of the upper subassembly 134.
  • the interposer 104 can define an opening 138 configured to be vertically aligned with the second semiconductor die 124 when the lower and upper assemblies 132 and 134 are arranged as shown in Figure 3.
  • the first semiconductor dies 122a, 122c are at one side of the opening 138 and the first semiconductor dies 122b, 122d are at an opposite side of the opening 138.
  • the pillar 126 can extend through the opening 138.
  • the first semiconductor dies 122a, 122c can be laterally spaced apart from the pillar 126 in one direction while the first semiconductor dies 122b, 122d are laterally spaced apart from the pillar 126 in an opposite direction.
  • the interposer 104 is shaped as a rectangular annulus and, therefore, extends around an entire perimeter of the pillar 126.
  • a counterpart of the interposer 104 can extend around less than all (e.g., less than 100%, but greater than 75%) of a perimeter of the pillar 126.
  • a counterpart of the interposer 104 can be U- shaped.
  • FIG. 6 is a flow chart illustrating a method 200 for making the semiconductor die assembly 100 in accordance with an embodiment of the present technology.
  • the method 200 can include electrically coupling the first semiconductor dies 122a-122h to the interposer 104 (block 202) and electrically coupling the second semiconductor die 124 to the package substrate 102 (block 204).
  • Electrically coupling the first semiconductor dies 122a-122h to the interposer 104 can include electrically coupling the first semiconductor dies 122a-122d via the upper major surface 1 10 of the interposer 104 and/or electrically coupling the first semiconductor dies 122e-122h via the lower major surface 11 1 of the interposer 104.
  • the method 200 can further include electrically coupling the interposer 104 to the package substrate 102 (block 206) and disposing the thermal interface features 130 (block 208) in direct contact with respective ones of the first semiconductor dies 122a-122d and the second semiconductor die 124.
  • volumes of thermal interface paste or pieces of thermal interface tape can be disposed at respective upper surfaces of the first semiconductor dies 122a-122d and the second semiconductor die 124.
  • the method 200 can also include locating the heat spreader 106 relative to the interposer 104, which can include extending the pillar 126 through the opening 138 (block 210).
  • the method 200 can include thermally coupling the cap 128 to the first semiconductor dies 122a-122d (block 212) and thermally coupling the pillar 126 to the second semiconductor die 124 (block 214) via the corresponding thermal interface features 130.
  • the thermal interface features 130 include volumes of thermal interface paste
  • the heat spreader 106 can compress and laterally expand the volumes of thermal interface paste. After the heat spreader 106 is suitably positioned, the volumes of thermal interface paste can be cured (e.g., thermally cured) to secure the heat spreader 106.
  • FIG. 7 is a flow chart illustrating a method 300 for operating the semiconductor die assembly 100 in accordance with an embodiment of the present technology.
  • the method 300 can include operating the plurality of first semiconductor dies 122 (block 302).
  • the method 300 can further include transferring heat generated by operating the plurality of first semiconductor dies 122 away from the plurality of first semiconductor dies 122 (block 304). In at least some cases, most (e.g., at least 50% or at least 75%) of the heat generated by operating the first semiconductor dies 122a-122d is dissipated through the cap 128.
  • the method 300 can further include operating the second semiconductor die 124 (block 306).
  • the total heat generated by operating the second semiconductor die 124 can be significantly greater (e.g., at least 4 times greater) than the total heat generated by operating any one of the first semiconductor dies 122a-122h.
  • the method 300 can further include transferring heat generated by operating the second semiconductor die 124 away from the second semiconductor die 124 (block 308). In at least some cases, most (e.g., at least 50% or at least 75%) of the heat generated by operating the second semiconductor die 124 is dissipated through the pillar 126 and through the opening 138.
  • the sequence of die operation may vary, e.g., operation of the plurality of first semiconductor dies 122 and operation of the second semiconductor die 124 die may be in reverse order and/or simultaneous.
  • FIGS 8, 9 and 10 are a side view, an exploded side view, and a top plan view of a heat spreader 400 of a semiconductor die assembly in accordance with another embodiment of the present technology.
  • the heat spreader 400 can include a pillar 402 and a cap 404 having an opening 408 (shown in dashed lines) extending around the pillar 402 (e.g., extending around at least 75% of a perimeter of the pillar 402).
  • the heat spreader 400 can further include fins 406 carried by the pillar 402.
  • the fins 406 can be configured to transfer heat generated by the second semiconductor die 124 by convection.
  • the pillar 402 and the cap 404 of the heat spreader 400 can be noncontiguous.
  • the pillar 402 extends through the opening 408 ( Figure 10) such that a small gap "g" is between the pillar 402 and the cap 404.
  • the heat spreader 400 does not include fins carried by the cap 404.
  • the gap may be useful, for example, to facilitate manufacturing and/or to provide thermal separation between the cap 404 and the pillar 402.
  • a counterpart of the heat spreader 400 can include fins carried by a counterpart of the cap 404 in addition to or instead of the fins 406 carried by the pillar 402.
  • rods or other types of convection enhancing structures can be used in place of fins in other embodiments.
  • FIG 11 is a side view of a lower subassembly 500 of a semiconductor die assembly in accordance with another embodiment of the present technology
  • Figure 12 is a top plan view of the lower subassembly 500.
  • the lower subassembly 500 can include a heat transfer material 502 at the upper major surface 108 of the package substrate 102.
  • the heat transfer material 502 is a metal film overlying the package substrate 102.
  • the heat transfer material 502 can include cutouts 504 ( Figure 12) around the bond pads 136.
  • the lower subassembly 500 can further include additional thermal interface features 130 (e.g., pieces of thermal interface tape or volumes of thermal interface paste) overlying the heat transfer material 502.
  • additional thermal interface features 130 e.g., pieces of thermal interface tape or volumes of thermal interface paste
  • the lower subassembly 500 can be assembled with the upper subassembly 134 and the heat spreader 106.
  • the first semiconductor dies 122e-122h can be thermally coupled to the heat transfer material 502 via the additional thermal interface features 130.
  • the heat transfer material 502 can define a primary pathway for transferring most (e.g., at least 50% or at least 75%) of heat generated by operating the first semiconductor dies 122e-122h away from the first semiconductor dies 122e-122h.
  • the transferred heat can then be dissipated at a peripheral portion of the heat transfer material 502 extending laterally beyond an edge portion of the interposer 104.
  • the lower subassembly 500 does not include convection enhancing structures at its peripheral portion.
  • a counterpart of the lower subassembly 500 can include fins, pillars, or other convection enhancing structures at the peripheral portion of the heat transfer material 502 and/or at another suitable location.
  • the heat transfer material 502 may be used without the heat spreader 106.
  • any one of the semiconductor die assemblies described above with reference to Figures 1-12 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system 600 shown schematically in Figure 13.
  • the system 600 can include a semiconductor die assembly 602, a power source 604, a driver 606, a processor 608, and/or other subsystems or components 610.
  • the semiconductor die assembly 602 can include features generally similar to those of the semiconductor die assemblies described above, and can therefore include a heat spreading pillar that passes through an opening defined by an associated interposer.
  • the resulting system 600 can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions.
  • representative systems 600 can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and appliances. Components of the system 600 may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system 600 can also include remote devices and any of a wide variety of computer readable media.
  • hand-held devices e.g., mobile phones, tablets, digital readers, and digital audio players
  • Components of the system 600 may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network).
  • the components of the system 600 can also include remote devices and any of a wide variety of computer readable media.

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Abstract

A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the first semiconductor die, an interposer between the package substrate and the first semiconductor die, and a second semiconductor die between the package substrate and the interposer. The semiconductor die assembly further comprises a heat spreader including a cap thermally coupled to the first semiconductor die at a first elevation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation. The heat spreader is configured to transfer heat away from the first and second semiconductor dies via the cap and the pillar, respectively. The interposer extends around at least 75% of a perimeter of the pillar in a plane between the first and second elevations.

Description

SEMICONDUCTOR DIE ASSEMBLY HAVING HEAT SPREADER THAT
EXTENDS THROUGH UNDERLYING INTERPOSER AND RELATED
TECHNOLOGY
TECHNICAL FIELD
[0001] The present technology is related to semiconductor die assemblies. BACKGROUND
[0002] Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a singulated die containing semiconductor-based integrated circuity, and a plastic protective covering encasing the die. The die includes functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry. In some cases, multiple semiconductor dies are incorporated into a single package. Individual semiconductor dies in a multiple-die package can have some dedicated packaging features and other packaging features shared with other semiconductor dies in the package. This approach increases the processing capacity, memory, etc. that can be contained in a small space.
[0003] Some multiple-die packages include a single stack of vertically aligned semiconductor dies. Other multiple-die packages include semiconductor dies that are laterally offset from one another at the same or different elevations. In these and other types of multiple- die packages, heat dissipation is often a significant design constraint. The combined heat generated by semiconductor dies in a multiple-die package can cause the individual dies to reach temperatures above their maximum operating temperatures. The combined heat may also reduce the performance and reliability of electrical interconnects between the dies. These and other heat-related problems typically become more acute as the density of dies in a multiple-die package increases. Accordingly, enhancing heat dissipation from semiconductor dies in multiple-die packages has the potential to improve performance, improve reliability, and allow for further miniaturization to meet market demands. BRIEF DESCRIPTION OF THE DRAWINGS
[0004] Figure 1 is a side view of the semiconductor die assembly in accordance with an embodiment of the present technology.
[0005] Figures 2 and 3 are exploded side views of the semiconductor die assembly shown in Figure 1.
[0006] Figure 4 is a top plan view of a lower subassembly of the semiconductor die assembly shown in Figure 1.
[0007] Figure 5 is a top plan view of an upper subassembly of the semiconductor die assembly shown in Figure 1.
[0008] Figure 6 is a flow chart illustrating a method for making the semiconductor die assembly shown in Figure 1 in accordance with an embodiment of the present technology.
[0009] Figure 7 is a flow chart illustrating a method for operating the semiconductor die assembly shown in Figure 1 in accordance with an embodiment of the present technology.
[0010] Figure 8 is a side view of a heat spreader of a semiconductor die assembly in accordance with another embodiment of the present technology.
[0011] Figure 9 is an exploded side view of the heat spreader shown in Figure 8.
[0012] Figure 10 is a top plan view of the heat spreader shown in Figure 8.
[0013] Figure 1 1 is a side view of a lower subassembly of a semiconductor die assembly in accordance with another embodiment of the present technology.
[0014] Figure 12 is a top plan view of the lower subassembly shown in Figure 1 1.
[0015] Figure 13 is a schematic view of a system that includes a semiconductor die assembly in accordance with an embodiment of the present technology
DETAILED DESCRIPTION
[0016] In conventional multiple-die packages, interposers between semiconductor dies at different elevations often interfere with heat dissipation. Conventional interposers are most often made primarily of epoxy resin or another low thermal conductivity material. Therefore, instead of dissipating heat in an upward direction, heat is primarily dissipated from semiconductor dies underlying such interposers in conventional multiple-die packages laterally via relatively thin layers of material overlying and/or underlying the die. For example, capillary underfill material between a package substrate and a die underlying a thermally insulative interposer may serve as the primary pathway for conveying heat away from the die toward a metal casing or another type of external heat spreader. In addition to dissipating heat laterally, it would be desirable to also preferentially dissipate heat vertically.
[0017] Semiconductor die assemblies and related devices, systems, and methods in accordance with embodiments of the present technology can at least partially address the foregoing and/or other problems associated with conventional technologies. Semiconductor die assemblies in accordance with at least some embodiments of the present technology include a heat spreader having a cap thermally coupled to a die above an interposer, and a pillar thermally coupled to a die below the interposer. The pillar can extend through an opening in the interposer. In this way, vertical heat dissipation from the die below the interposer can be significantly enhanced. Other advantages in addition to or instead of this advantage also may be present. Furthermore, as described below, semiconductor die assemblies and related devices, systems, and methods in accordance with embodiments of the present technology can have features in addition to or instead of features associated with heat spreading pillars that pass through openings in the associated interposers.
[0018] Specific details of semiconductor die assemblies and related devices, systems, and methods in accordance with several embodiments of the present technology are disclosed herein with reference to Figures 1-13. Although these embodiments may be disclosed herein primarily or entirely in the context of hybrid assemblies containing logic and memory components, other suitable contexts are within the scope of the present technology. For example, suitable features of disclosed hybrid assemblies can be implemented in the context of memory-only assemblies or in the context of logic -only assemblies. Furthermore, it should understood, in general, that other devices, systems, and methods in addition to those disclosed herein are within the scope of the present technology. For example, devices, systems, and methods in accordance with embodiments of the present technology can have different and/or additional configurations, components, or procedures than those disclosed herein. Moreover, a person of ordinary skill in the art will understand that devices, systems, and methods in accordance with embodiments of the present technology can be without configurations, components, or procedures disclosed herein without deviating from the present technology.
[0019] Figure 1 is a side view of a semiconductor die assembly 100 in accordance with an embodiment of the present technology, and Figure 2 is an exploded side view of the semiconductor die assembly 100. With reference to Figures 1 and 2 together, the semiconductor die assembly 100 can include a package substrate 102 carrying an interposer 104 and a heat spreader 106. In the orientation shown in Figure 1, the package substrate 102 has an upper major surface 108 closer to the interposer 104 and a lower major surface 109 father from the interposer 104. Also in the illustrated orientation, the interposer 104 has an upper major surface 1 10 farther from the package substrate 102 and a lower major surface 1 1 1 closer to the package substrate 102. The semiconductor die assembly 100 can include a plurality of first decoupling capacitors 1 12 (one labeled) electrically connected to the interposer 104, and a plurality of second decoupling capacitors 1 13 (one labeled) electrically connected to the package substrate 102. The interposer 104 and the package substrate 102 can include internal circuitry (not shown) operably connected to the plurality of first decoupling capacitors 1 12 and the plurality of second decoupling capacitors 113, respectively.
[0020] The semiconductor die assembly 100 can further include laterally spaced apart first solder-ball interconnects 1 14 electrically coupling the interposer 104 (along its lower major surface 1 1 1) to the package substrate 102 (along its upper major surface 108). In the illustrated embodiment, the first solder-ball interconnects 1 14 are arranged in two peripheral rows 1 16 (individually identified as rows 1 16a, 1 16b in Figure 2) and a central array 1 18 (Figure 2) between the rows 1 16a, 1 16b. In other embodiments, counterparts of the first solder-ball interconnects 1 14 can have other suitable arrangements. In the illustrated embodiment, the semiconductor die assembly 100 further includes laterally spaced apart second solder-ball interconnects 120 (one labeled) electrically coupled to the package substrate 102 along its lower major surface 109. The second solder-ball interconnects 120 can be configured to electrically connect the overall semiconductor die assembly 100 to higher level circuitry (not shown).
[0021] As shown in Figures 1 and 2, the semiconductor die assembly 100 can include a plurality of first semiconductor dies 122 electrically coupled to the interposer 104. The semiconductor die assembly 100 can further include a second semiconductor die 124 electrically coupled to the package substrate 102. In at least some cases, the plurality of first semiconductor dies 122 are electrically coupled to both the upper major surface 1 10 and the lower major surface 1 1 1 of the interposer 104. For example, at the upper major surface 110 of the interposer 104, the semiconductor die assembly 100 can include four first semiconductor dies 122 (individually identified as first semiconductor dies 122a-122d), and, at the lower major surface 1 11 of the interposer 104, the semiconductor die assembly 100 can include another four first semiconductor dies 122 (individually identified as first semiconductor dies 122e-122h). (In Figures 1 and 2, the first semiconductor dies 122c, 122d, 122g, 122h are hidden behind the first semiconductor dies 122a, 122b, 122e, 122f.) The first semiconductor dies 122a-122d can be laterally offset from one another at one elevation, and the first semiconductor dies 122e-122h can be laterally offset from one another at another elevation. Electrical couplings between the first semiconductor dies 122a- 122h and the interposer 104 and between the second semiconductor die 124 and the package substrate 102 are omitted for clarity of illustration. In other embodiments, a counterpart of the semiconductor die assembly 100 can include a different number and/or arrangement of first and second semiconductor dies, such as an arrangement in which first semiconductor dies are electrically connected to only one of two major surfaces of an associated interposer.
[0022] In some cases, some or all of the first semiconductor dies 122a-122h are memory dies and the second semiconductor die 124 is a logic die. In these and other cases, heat generated by the second semiconductor die 124 may be significantly greater than heat generated by the plurality of first semiconductor dies 122 during normal operation of the semiconductor die assembly 100. The semiconductor die assembly 100 can include features that facilitate efficient vertical dissipation of the heat generated by the second semiconductor die 124 when the semiconductor die assembly 100 is in the illustrated orientation (e.g., upward with respect to the horizontal orientation of the package substrate 102 in Figure 1). As shown in Figure 2, the heat spreader 106 can include a pillar 126 and a cap 128 extending around the pillar 126 (e.g., extending around at least 75% of a perimeter of the pillar 126). The cap 128 can be positioned to be thermally coupled to the first semiconductor dies 122a- 122d at one elevation, and the pillar 126 can be positioned to be thermally coupled to the second semiconductor die 124 at another elevation. When the semiconductor die assembly 100 is in the illustrated orientation, the elevation at which the cap 128 is thermally coupled to the first semiconductor dies 122a- 122d is above the interposer 104, and the elevation at which the pillar 126 is thermally coupled to the second semiconductor die 124 is below the interposer 104. The pillar 126 can extend through a plane occupied by the interposer 104 (e.g., the pillar 126 can extend through an opening in the interposer 104). In the illustrated embodiment, the pillar 126 and the cap 128 are integral components of the heat spreader 106. In other embodiments, a counterpart heat spreader 106 can include a pillar and a cap that are separate components coupled together or are noncontiguous (e.g., spaced apart from each other). For example, a counterpart heat spreader 106 can include a pillar that extends through an opening at least partially defined by a corresponding cap such that the cap extends around at least 75% of a perimeter of the pillar. Other noncontiguous configurations are also possible.
[0023] With reference again to Figures 1 and 2 together, the semiconductor die assembly 100 can further include thermal interface features 130 (Figure 2) through which the heat spreader 106 is thermally coupled to the first semiconductor dies 122a- 122d and to the second semiconductor die 124. Some of the thermal interface features 130 can be directly connected to upper surfaces of the first semiconductor dies 122a-122d, respectively, and to corresponding portions of a lower surface of the cap 128 when the semiconductor die assembly 100 is in the illustrated orientation. Another one of the thermal interface features 130 can be directly connected to an upper surface of the second semiconductor die 124 and to a lower surface of the pillar 126 when the semiconductor die assembly 100 is in the illustrated orientation. The heat spreader 106 can be shaped such that an elevation difference between the lower surface of the cap 128 and the lower surface of the pillar 126 corresponds to an elevation difference between the upper surfaces of the first semiconductor dies 122a-122d and the upper surface of the second semiconductor die 124 when the semiconductor die assembly 100 is in the illustrated orientation. The thermal interface features 130 can be configured to fill voids and to smooth irregularities at interfaces between the heat spreader 106 and the first semiconductor dies 122a- 122d and between the heat spreader 106 and the second semiconductor die 124. In the illustrated embodiment, the thermal interface features 130 are volumes of thermal interface paste, such as silicone -based grease doped with thermally conductive particles. In other embodiments, counterparts of one, some, or all of the thermal interface features 130 can be pieces of thermal interface tape or have another suitable form to enhance thermal conductivity and/or to secure the heat spreader 106 to the first semiconductor dies 122a- 122d and to the second semiconductor die 124. [0024] Figure 3 is another exploded via of the semiconductor die assembly 100. As shown in Figure 3, the semiconductor die assembly 100 can include a lower subassembly 132 and an upper subassembly 134 configured to be assembled with the heat spreader 106. The lower subassembly 132 can include the package substrate 102, the second decoupling capacitors 1 13, the second solder-ball interconnects 120, the second semiconductor die 124, and the thermal interface feature 130 associated with the second semiconductor die 124. The upper subassembly 134 can include the interposer 104, the first decoupling capacitors 1 12, the first solder-ball interconnects 114, the plurality of first semiconductor dies 122, and the thermal interface features 130 associated with the plurality of first semiconductor dies 122. Figure 4 is a top plan view of the lower subassembly 132. As shown in Figure 4, the package substrate 102 can include bond pads 136 (one labeled) vertically aligned with the first solder-ball interconnects 1 14. The second semiconductor die 124 can be centrally positioned on the package substrate 102.
[0025] Figure 5 is a top plan view of the upper subassembly 134. As shown in Figure 5, the interposer 104 can define an opening 138 configured to be vertically aligned with the second semiconductor die 124 when the lower and upper assemblies 132 and 134 are arranged as shown in Figure 3. The first semiconductor dies 122a, 122c are at one side of the opening 138 and the first semiconductor dies 122b, 122d are at an opposite side of the opening 138. When the lower and upper subassemblies 132, 134 and the heat spreader 106 are assembled, the pillar 126 can extend through the opening 138. Thus, the first semiconductor dies 122a, 122c can be laterally spaced apart from the pillar 126 in one direction while the first semiconductor dies 122b, 122d are laterally spaced apart from the pillar 126 in an opposite direction. In the illustrated embodiment, the interposer 104 is shaped as a rectangular annulus and, therefore, extends around an entire perimeter of the pillar 126. In other embodiments, a counterpart of the interposer 104 can extend around less than all (e.g., less than 100%, but greater than 75%) of a perimeter of the pillar 126. As one example, a counterpart of the interposer 104 can be U- shaped.
[0026] Figure 6 is a flow chart illustrating a method 200 for making the semiconductor die assembly 100 in accordance with an embodiment of the present technology. With reference to Figures 1-6 together, the method 200 can include electrically coupling the first semiconductor dies 122a-122h to the interposer 104 (block 202) and electrically coupling the second semiconductor die 124 to the package substrate 102 (block 204). Electrically coupling the first semiconductor dies 122a-122h to the interposer 104 can include electrically coupling the first semiconductor dies 122a-122d via the upper major surface 1 10 of the interposer 104 and/or electrically coupling the first semiconductor dies 122e-122h via the lower major surface 11 1 of the interposer 104. The method 200 can further include electrically coupling the interposer 104 to the package substrate 102 (block 206) and disposing the thermal interface features 130 (block 208) in direct contact with respective ones of the first semiconductor dies 122a-122d and the second semiconductor die 124. For example, volumes of thermal interface paste or pieces of thermal interface tape can be disposed at respective upper surfaces of the first semiconductor dies 122a-122d and the second semiconductor die 124. The method 200 can also include locating the heat spreader 106 relative to the interposer 104, which can include extending the pillar 126 through the opening 138 (block 210). In conjunction with locating the heat spreader 106 relative to the interposer 104, the method 200 can include thermally coupling the cap 128 to the first semiconductor dies 122a-122d (block 212) and thermally coupling the pillar 126 to the second semiconductor die 124 (block 214) via the corresponding thermal interface features 130. When the thermal interface features 130 include volumes of thermal interface paste, the heat spreader 106 can compress and laterally expand the volumes of thermal interface paste. After the heat spreader 106 is suitably positioned, the volumes of thermal interface paste can be cured (e.g., thermally cured) to secure the heat spreader 106.
[0027] Figure 7 is a flow chart illustrating a method 300 for operating the semiconductor die assembly 100 in accordance with an embodiment of the present technology. With reference to Figures 1-5 and 7 together, the method 300 can include operating the plurality of first semiconductor dies 122 (block 302). The method 300 can further include transferring heat generated by operating the plurality of first semiconductor dies 122 away from the plurality of first semiconductor dies 122 (block 304). In at least some cases, most (e.g., at least 50% or at least 75%) of the heat generated by operating the first semiconductor dies 122a-122d is dissipated through the cap 128. The method 300 can further include operating the second semiconductor die 124 (block 306). The total heat generated by operating the second semiconductor die 124 can be significantly greater (e.g., at least 4 times greater) than the total heat generated by operating any one of the first semiconductor dies 122a-122h. The method 300 can further include transferring heat generated by operating the second semiconductor die 124 away from the second semiconductor die 124 (block 308). In at least some cases, most (e.g., at least 50% or at least 75%) of the heat generated by operating the second semiconductor die 124 is dissipated through the pillar 126 and through the opening 138. The sequence of die operation may vary, e.g., operation of the plurality of first semiconductor dies 122 and operation of the second semiconductor die 124 die may be in reverse order and/or simultaneous.
[0028] Figures 8, 9 and 10 are a side view, an exploded side view, and a top plan view of a heat spreader 400 of a semiconductor die assembly in accordance with another embodiment of the present technology. With reference to Figures 8-10 together, the heat spreader 400 can include a pillar 402 and a cap 404 having an opening 408 (shown in dashed lines) extending around the pillar 402 (e.g., extending around at least 75% of a perimeter of the pillar 402). The heat spreader 400 can further include fins 406 carried by the pillar 402. The fins 406 can be configured to transfer heat generated by the second semiconductor die 124 by convection. Unlike the pillar 126 and the cap 128 of the heat spreader 106 (Figures 1-3), the pillar 402 and the cap 404 of the heat spreader 400 can be noncontiguous. For example, the pillar 402 extends through the opening 408 (Figure 10) such that a small gap "g" is between the pillar 402 and the cap 404. In the illustrated embodiment, the heat spreader 400 does not include fins carried by the cap 404. The gap may be useful, for example, to facilitate manufacturing and/or to provide thermal separation between the cap 404 and the pillar 402. In other embodiments, a counterpart of the heat spreader 400 can include fins carried by a counterpart of the cap 404 in addition to or instead of the fins 406 carried by the pillar 402. Furthermore, rods or other types of convection enhancing structures can be used in place of fins in other embodiments.
[0029] Figure 11 is a side view of a lower subassembly 500 of a semiconductor die assembly in accordance with another embodiment of the present technology, and Figure 12 is a top plan view of the lower subassembly 500. With reference to Figures 1 1 and 12 together, the lower subassembly 500 can include a heat transfer material 502 at the upper major surface 108 of the package substrate 102. In at least some cases, the heat transfer material 502 is a metal film overlying the package substrate 102. The heat transfer material 502 can include cutouts 504 (Figure 12) around the bond pads 136. The lower subassembly 500 can further include additional thermal interface features 130 (e.g., pieces of thermal interface tape or volumes of thermal interface paste) overlying the heat transfer material 502. With reference to Figures 3, 1 1 and 12 together, the lower subassembly 500 can be assembled with the upper subassembly 134 and the heat spreader 106. When so assembled, the first semiconductor dies 122e-122h can be thermally coupled to the heat transfer material 502 via the additional thermal interface features 130. The heat transfer material 502 can define a primary pathway for transferring most (e.g., at least 50% or at least 75%) of heat generated by operating the first semiconductor dies 122e-122h away from the first semiconductor dies 122e-122h. The transferred heat can then be dissipated at a peripheral portion of the heat transfer material 502 extending laterally beyond an edge portion of the interposer 104. In the illustrated embodiment, the lower subassembly 500 does not include convection enhancing structures at its peripheral portion. In other embodiments, a counterpart of the lower subassembly 500 can include fins, pillars, or other convection enhancing structures at the peripheral portion of the heat transfer material 502 and/or at another suitable location. In these and other embodiments, the heat transfer material 502 may be used without the heat spreader 106.
[0030] Any one of the semiconductor die assemblies described above with reference to Figures 1-12 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system 600 shown schematically in Figure 13. The system 600 can include a semiconductor die assembly 602, a power source 604, a driver 606, a processor 608, and/or other subsystems or components 610. The semiconductor die assembly 602 can include features generally similar to those of the semiconductor die assemblies described above, and can therefore include a heat spreading pillar that passes through an opening defined by an associated interposer. The resulting system 600 can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems 600 can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and appliances. Components of the system 600 may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system 600 can also include remote devices and any of a wide variety of computer readable media.
[0031] This disclosure is not intended to be exhaustive or to limit the present technology to the precise forms disclosed herein. Although specific embodiments are disclosed herein for illustrative purposes, various equivalent modifications are possible without deviating from the present technology, as those of ordinary skill in the relevant art will recognize. In some cases, well-known structures and functions have not been shown and/or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Although steps of methods may be presented herein in a particular order, in alternative embodiments the steps may have another suitable order. Similarly, certain aspects of the present technology disclosed in the context of particular embodiments can be combined or eliminated in other embodiments. Furthermore, while advantages associated with certain embodiments may have been disclosed in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein to fall within the scope of the present technology.
[0032] Throughout this disclosure, the singular terms "a," "an," and "the" include plural referents unless the context clearly indicates otherwise. Similarly, unless the word "or" is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of "or" in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the terms "comprising" and the like may be used herein to mean including at least the recited feature(s) such that any greater number of the same feature(s) and/or one or more additional types of features are not precluded. Directional terms, such as "upper," "lower," "front," "back," "vertical," and "horizontal," may be used herein to express and clarify the relationship between various elements. It should be understood that such terms do not denote absolute orientation. Reference herein to "one embodiment," "an embodiment," or similar formulations means that a particular feature, structure, operation, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present technology. Thus, the appearances of such phrases or formulations herein are not all referring to the same embodiment. Furthermore, various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments of the present technology.

Claims

CLAIMS I/We claim:
1. A semiconductor die assembly, comprising:
a first semiconductor die;
a package substrate underlying the first semiconductor die when the semiconductor die assembly is in a given orientation;
an interposer between the package substrate and the first semiconductor die;
a second semiconductor die between the package substrate and the interposer; and a heat spreader configured to transfer heat away from the first and second semiconductor dies, wherein the heat spreader includes—
a cap thermally coupled to the first semiconductor die at a first elevation when the semiconductor die assembly is in the given orientation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation when the semiconductor die assembly is in the given orientation, wherein the interposer extends around at least 75% of a perimeter of the pillar in a plane between the first and second elevations.
2. The semiconductor die assembly of claim 1 wherein:
the interposer defines an opening; and
the pillar extends through the opening.
3. The semiconductor die assembly of claim 1 wherein the interposer is shaped as a rectangular annulus in the plane between the first and second elevations.
4. The semiconductor die assembly of claim 1 wherein:
the first semiconductor die is a memory die; and
the second semiconductor die is a logic die.
5. The semiconductor die assembly of claim 1 wherein:
the heat spreader includes fins configured to transfer heat by convection; and the fins are above the pillar when the semiconductor die assembly is in the given orientation.
6. The semiconductor die assembly of claim 1 wherein the cap and the pillar are contiguous components of the heat spreader.
7. The semiconductor die assembly of claim 1 wherein:
the first semiconductor die is a first one of a plurality of first semiconductor dies electrically coupled to the interposer;
the first one of the plurality of first semiconductor dies is laterally spaced apart from the pillar in a first direction;
the semiconductor die assembly further comprises a second one of the plurality of first semiconductor dies; and
the second one of the plurality of first semiconductor dies is laterally spaced apart from the pillar in a second direction opposite to the first direction.
8. The semiconductor die assembly of claim 1 wherein the cap and the pillar are noncontiguous components of the heat spreader.
9. The semiconductor die assembly of claim 8 wherein the cap extends around at least 75% of a perimeter of the pillar at the first elevation.
10. The semiconductor die assembly of claim 1 further comprising:
a first thermal interface feature through which the cap is thermally coupled to the first semiconductor die at the first elevation; and
a second thermal interface feature through which the pillar is thermally coupled to the second semiconductor die at the second elevation.
11. The semiconductor die assembly of claim 10 wherein the first and second thermal interface features are, respectively, first and second pieces of thermal interface tape.
12. The semiconductor die assembly of claim 10 wherein the first and second thermal interface features are, respectively, first and second volumes of thermal interface paste.
13. The semiconductor die assembly of claim 1 wherein:
the first semiconductor die is a first one of a plurality of first semiconductor dies electrically coupled to the interposer;
the interposer has—
a first major surface, and
a second major surface opposite to its first major surface;
the second semiconductor die is closer to the second major surface of the interposer than to the first major surface of the interposer;
the first one of the plurality of first semiconductor dies is electrically coupled to the interposer via the first major surface of the interposer;
the semiconductor die assembly further comprises a second one of the plurality of first semiconductor dies; and
the second one of the plurality of first semiconductor dies is electrically coupled to the interposer via the second major surface of the interposer.
14. The semiconductor die assembly of claim 13 wherein:
the package substrate has—
a first major surface, and
a second major surface opposite to its first major surface;
the first semiconductor die is closer to the first major surface of the package substrate than to the second major surface of the package substrate;
the semiconductor die assembly further comprises heat transfer material at the first major surface of the package substrate; and
the heat transfer material is thermally coupled to the second one of the plurality of first semiconductor dies.
15. The semiconductor die assembly of claim 14 wherein the heat transfer material is a metal film overlying the package substrate when the semiconductor die assembly is in the given orientation.
16. The semiconductor die assembly of claim 14 wherein:
the heat transfer material includes a peripheral portion extending laterally beyond an edge portion of the interposer when the semiconductor die assembly is in the given orientation;
the semiconductor die assembly further comprises fins thermally coupled to the heat transfer material at the peripheral portion of the heat transfer material; and the fins are configured to transfer heat by convection.
17. The semiconductor die assembly of claim 14 further comprising a thermal interface feature through which the heat transfer material is thermally coupled to the first semiconductor die.
18. The semiconductor die assembly of claim 17 wherein the thermal interface feature is a piece of thermal interface tape.
19. The semiconductor die assembly of claim 17 wherein the thermal interface feature is a volume of thermal interface paste.
20. A method for making a semiconductor die assembly, the method comprising: electrically coupling a first semiconductor die to an interposer;
electrically coupling a second semiconductor die to a package substrate;
electrically coupling the interposer to the package substrate;
thermally coupling a cap of a heat spreader to the first semiconductor die, wherein the heat spreader is configured to transfer heat away from the first semiconductor die via the cap;
locating a pillar of the heat spreader relative to the interposer such that the interposer extends around at least 75% of a perimeter of the pillar, wherein the heat spreader is configured to transfer heat away from the second semiconductor die via the pillar; and
thermally coupling the pillar to the second semiconductor die.
21. The method of claim 20 wherein:
the interposer defines an opening; and
locating the pillar relative to the interposer includes extending the pillar through the opening.
22. The method of claim 20 wherein:
the first semiconductor die is a first one of a plurality of first semiconductor dies electrically coupled to the interposer;
electrically coupling the first one of the plurality of first semiconductor dies to the interposer includes electrically coupling the first one of the plurality of first semiconductor dies to the interposer at a portion of the interposer laterally spaced apart from the pillar in a first direction; and
the method further comprises electrically coupling a second one of the plurality of first semiconductor dies to the interposer at a portion of the interposer laterally spaced apart from the pillar in a second direction opposite to the first direction.
23. The method of claim 20, further comprising:
disposing a first thermal interface feature in direct contact with the first semiconductor die; and
disposing a second thermal interface feature in direct contact with the second semiconductor die,
wherein—
thermally coupling the cap to the first semiconductor die includes thermally coupling the cap to the first semiconductor die via the first thermal interface feature, and
thermally coupling the pillar to the second semiconductor die includes thermally coupling the pillar to the second semiconductor die via the second thermal interface feature.
24. The method of claim 23 wherein disposing the first and second thermal interface features includes attaching, respectively, first and second pieces of thermal interface tape.
25. The method of claim 23 wherein disposing the first and second thermal interface features includes depositing, respectively, first and second volumes of thermal interface paste.
26. The method of claim 20 wherein:
the interposer has—
a first major surface, and
a second major surface opposite to its first major surface;
the second semiconductor die is closer to the second major surface of the interposer than to the first major surface of the interposer;
the first semiconductor die is a first one of a plurality of first semiconductor dies electrically coupled to the interposer;
electrically coupling the first one of the plurality of first semiconductor dies to the interposer includes electrically coupling the first one of the plurality of first semiconductor dies to the interposer via the first major surface of the interposer; and
the method further comprises electrically coupling a second one of the plurality of first semiconductor dies to the interposer via the second major surface of the interposer.
27. The method of claim 26 wherein:
the package substrate has—
a first major surface, and
a second major surface opposite to its first major surface;
the first semiconductor die is closer to the first major surface of the package substrate than to the second major surface of the package substrate;
the method further comprises thermally coupling a heat transfer material to the second one of the plurality of first semiconductor dies; and
the heat transfer material is at the first major surface of the package substrate.
28. The method of claim 27, further comprising disposing a thermal interface feature in direct contact with the second one of the plurality of first semiconductor dies, wherein thermally coupling the heat transfer material to the second one of the plurality of first semiconductor dies includes thermally coupling the heat transfer material to the second one of the plurality of first semiconductor dies via the thermal interface feature.
29. The method of claim 28 wherein disposing the thermal interface feature includes attaching a piece of thermal interface tape.
30. The method of claim 28 wherein disposing the thermal interface feature includes depositing a volume of thermal interface paste.
31. A method for operating a semiconductor die assembly, the method comprising: operating a first semiconductor die electrically coupled to an interposer;
operating a second semiconductor die electrically coupled to a package substrate;
transferring at least 50% of total heat generated by operating the first semiconductor die away from the first semiconductor die via a cap of a heat spreader thermally coupled to the first semiconductor die; and
transferring at least 50% of total heat generated by operating the second semiconductor die away from the second semiconductor die via a pillar of the heat spreader thermally coupled to the second semiconductor die and via an opening defined by the interposer, wherein the pillar extends through the opening.
32. The method of claim 31 wherein the total heat generated by operating the first semiconductor die is at most 25% of the total heat generated by operating the second semiconductor die.
33. The method of claim 31 wherein:
the first semiconductor die is a first one of a plurality of first semiconductor dies electrically coupled to the interposer;
the interposer has—
a first major surface, and
a second major surface opposite to its first major surface;
the second semiconductor die is closer to the second major surface of the interposer than to the first major surface of the interposer; the package substrate has—
a first major surface, and
a second major surface opposite to its first major surface;
the first one of the plurality of first semiconductor dies is closer to the first major surface of the package substrate than to the second major surface of the package substrate;
the first one of the plurality of first semiconductor dies is electrically coupled to the interposer via the first major surface of the interposer;
the method further comprises—
operating a second one of the plurality of first semiconductor dies electrically coupled to the interposer via the second major surface of the interposer, and
transferring at least 50% of total heat generated by operating the second one of the plurality of first semiconductor dies away from the second one of the plurality of first semiconductor dies via a heat transfer material thermally coupled to the second one of the plurality of first semiconductor dies; and the heat transfer material is at the first major surface of the package substrate.
PCT/US2017/062621 2016-12-21 2017-11-20 Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology WO2018118315A1 (en)

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JP2019531054A JP6770648B2 (en) 2016-12-21 2017-11-20 Semiconductor die assembly and related technologies with a heat spreader that extends through the interposer below
KR1020197019913A KR102342690B1 (en) 2016-12-21 2017-11-20 Semiconductor die assembly and related art having a heat spreader extending through an underlying interposer
EP17884980.8A EP3559987A4 (en) 2016-12-21 2017-11-20 Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology
CN201780072758.8A CN109983572B (en) 2016-12-21 2017-11-20 Semiconductor die assemblies having heat spreaders extending through an underlying interposer and related techniques

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10062634B2 (en) * 2016-12-21 2018-08-28 Micron Technology, Inc. Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology
KR102451167B1 (en) * 2018-01-23 2022-10-06 삼성전자주식회사 Semiconductor package
KR102705039B1 (en) 2018-12-28 2024-09-10 삼성전자주식회사 ADHESIVE FILM, SEMICONDUCTOR DEVICE USING THE SAME, and SEMICONDUCTOR PACKAGE INCLUDING THE SAME
US11552019B2 (en) * 2019-03-12 2023-01-10 Intel Corporation Substrate patch reconstitution options
US11372043B2 (en) 2019-08-21 2022-06-28 Micron Technology, Inc. Heat spreaders for use in semiconductor device testing, such as burn-in testing
TWI780980B (en) * 2021-11-10 2022-10-11 創意電子股份有限公司 Semiconductor chiplet device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130093074A1 (en) * 2011-10-13 2013-04-18 Xilinx, Inc. Multi-die integrated circuit structure with heat sink
EP2631943A2 (en) * 2012-02-24 2013-08-28 Broadcom Corporation System-in-package with integrated protection socket
KR20150049164A (en) * 2013-10-29 2015-05-08 삼성전자주식회사 Semiconductor Package Device
US20150236002A1 (en) * 2011-04-22 2015-08-20 Tessera, Inc. Multi-chip module with stacked face-down connected dies
US20160254249A1 (en) * 2010-02-26 2016-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. 3D Semiconductor Package Interposer with Die Cavity

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2293487B (en) * 1994-09-21 1998-08-12 Hewlett Packard Co Method and apparatus for attaching a heat sink and a fan to an intergrated circuit package
JP3196762B2 (en) * 1999-04-20 2001-08-06 日本電気株式会社 Semiconductor chip cooling structure
JP2000349178A (en) * 1999-06-08 2000-12-15 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP2001352018A (en) * 2000-06-07 2001-12-21 Tomohiro Kitayama Heat transfer member for semiconductor device and cooling structure thereof
JP2002033411A (en) * 2000-07-13 2002-01-31 Nec Corp Semiconductor device with heat spreader and its manufacturing method
JP2007505478A (en) * 2003-08-29 2007-03-08 サーマルワークス，インコーポレイティド Expansion-constrained die stack
TWI239603B (en) * 2003-09-12 2005-09-11 Advanced Semiconductor Eng Cavity down type semiconductor package
TWI256707B (en) * 2004-10-21 2006-06-11 Advanced Semiconductor Eng Cavity-down multiple chip package
JP4986435B2 (en) * 2005-10-12 2012-07-25 株式会社ソニー・コンピュータエンタテインメント Semiconductor device and method for producing semiconductor device
KR100700936B1 (en) * 2006-01-25 2007-03-28 삼성전자주식회사 Cooling apparatus and memory module having the same
JP5211457B2 (en) * 2006-09-19 2013-06-12 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
JP4870584B2 (en) * 2007-01-19 2012-02-08 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2008218669A (en) * 2007-03-02 2008-09-18 Nec Electronics Corp Semiconductor device
JP2009129960A (en) * 2007-11-20 2009-06-11 Nec Electronics Corp Semiconductor device and its manufacturing method
US20090213541A1 (en) * 2008-02-27 2009-08-27 Matthew Allen Butterbaugh Cooling Plate Assembly with Fixed and Articulated Interfaces, and Method for Producing Same
US8273603B2 (en) * 2008-04-04 2012-09-25 The Charles Stark Draper Laboratory, Inc. Interposers, electronic modules, and methods for forming the same
US7928562B2 (en) * 2008-07-22 2011-04-19 International Business Machines Corporation Segmentation of a die stack for 3D packaging thermal management
KR20120019091A (en) * 2010-08-25 2012-03-06 삼성전자주식회사 Multi-chip package and method of manufacturing the same
US9147085B2 (en) * 2010-09-24 2015-09-29 Blackberry Limited Method for establishing a plurality of modes of operation on a mobile device
US8472190B2 (en) * 2010-09-24 2013-06-25 Ati Technologies Ulc Stacked semiconductor chip device with thermal management
EP2625714A2 (en) * 2010-10-06 2013-08-14 The Charles Stark Draper Laboratory, Inc. Interposers, electronic modules, and methods for forming the same
JP2012114334A (en) * 2010-11-26 2012-06-14 Nec Casio Mobile Communications Ltd Semiconductor module having cavity substrate, failure analysis method for the same, and method of manufacturing the semiconductor module
JP2012129335A (en) * 2010-12-15 2012-07-05 Renesas Electronics Corp Semiconductor device and method of manufacturing semiconductor device
US8674519B2 (en) * 2010-12-17 2014-03-18 Intel Corporation Microelectronic package and method of manufacturing same
TWI475651B (en) * 2011-08-02 2015-03-01 Global Unichip Corp Semiconductor device and associated method
US9269646B2 (en) * 2011-11-14 2016-02-23 Micron Technology, Inc. Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same
KR101894125B1 (en) * 2012-09-14 2018-08-31 르네사스 일렉트로닉스 가부시키가이샤 Method for manufacturing semiconductor device
US9496199B2 (en) * 2012-12-04 2016-11-15 General Electric Company Heat spreader with flexible tolerance mechanism
US9461000B2 (en) * 2013-05-21 2016-10-04 Esilicon Corporation Parallel signal via structure
US9076754B2 (en) * 2013-08-02 2015-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC packages with heat sinks attached to heat dissipating rings
KR102126977B1 (en) * 2013-08-21 2020-06-25 삼성전자주식회사 Semiconductor package
WO2015047350A1 (en) * 2013-09-27 2015-04-02 Intel Corporation Dual-sided die packages
US9269694B2 (en) * 2013-12-11 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with thermal management features for reduced thermal crosstalk and methods of forming same
US9287248B2 (en) * 2013-12-12 2016-03-15 Intel Corporation Embedded memory and power management subpackage
KR20150085384A (en) * 2014-01-15 2015-07-23 삼성전자주식회사 Semiconductor package and method for manufacturing the same
US9269700B2 (en) * 2014-03-31 2016-02-23 Micron Technology, Inc. Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods
US10062634B2 (en) 2016-12-21 2018-08-28 Micron Technology, Inc. Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160254249A1 (en) * 2010-02-26 2016-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. 3D Semiconductor Package Interposer with Die Cavity
US20150236002A1 (en) * 2011-04-22 2015-08-20 Tessera, Inc. Multi-chip module with stacked face-down connected dies
US20130093074A1 (en) * 2011-10-13 2013-04-18 Xilinx, Inc. Multi-die integrated circuit structure with heat sink
EP2631943A2 (en) * 2012-02-24 2013-08-28 Broadcom Corporation System-in-package with integrated protection socket
KR20150049164A (en) * 2013-10-29 2015-05-08 삼성전자주식회사 Semiconductor Package Device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3559987A4 *

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US10062634B2 (en) 2018-08-28
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US20180374774A1 (en) 2018-12-27
US20200013694A1 (en) 2020-01-09
TW201842637A (en) 2018-12-01
KR20190085176A (en) 2019-07-17
CN109983572B (en) 2020-10-16
TWI683404B (en) 2020-01-21
KR102342690B1 (en) 2021-12-24
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JP6770648B2 (en) 2020-10-14
CN109983572A (en) 2019-07-05

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