WO2018118289A1

WO2018118289A1 - Multi-path decoding of a polar code using in parallel permuted graphs of the polar code

Info

Publication number: WO2018118289A1
Application number: PCT/US2017/062092
Authority: WO
Inventors: Eren SASOGLU; Hosein Nikopour; Oner Orhan
Original assignee: Intel Corporation
Priority date: 2016-12-20
Filing date: 2017-11-16
Publication date: 2018-06-28

Abstract

Described is an apparatus comprising an interface to receive channel output; and a decoder to decode the channel output. The decoder may comprise a plurality of decoding paths, wherein a first decoding path and a second decoding path may comprise a common decoding segment.

Description

MULTI-PATH DECODING OF A POLAR CODE USING IN PARALLEL PERMUTED GRAPHS OF THE POLAR CODE

CLAIM OF PRIORITY

[0001] The present application claims priority under 35 U.S.C. § 119(e) to United

States Provisional Patent Application Serial Number 62/436,915, filed December 20, 2016 and entitled "TECHNIQUE TO CONSTRUCT AND ENCODE POLAR CODES," and to United States Provisional Patent Application Serial Number 62/437,375, filed December 21, 2016 and entitled "MULTIPLE-PATH DECODING OF POLAR CODES," which are herein incorporated by reference in their entirety.

BACKGROUND

[0002] Wireless communication may be encoded using one or more appropriate coding techniques. In information theory, a polar code is a linear block error correcting code. The polar code may be constructed, e.g., based on a multiple recursive concatenation of a short kernel code. Polar code may be used for encoding data for wireless communication.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. However, while the drawings are to aid in explanation and understanding, they are only an aid, and should not be taken to limit the disclosure to the specific embodiments depicted therein.

[0004] Fig. 1 illustrates a transmitter and a receiver communicating over a wireless channel, wherein the receiver comprises a multi-path polar code decoder comprising common segments and/or common nodes, according to some embodiments.

[0005] Fig. 2A illustrates an encoding/decoding circuit for length-8 polar codes.

[0006] Figs. 2B and 2C illustrate different representations of the circuit of Fig. 2A.

[0007] Fig. 3 illustrates a section of a decoding circuit.

[0008] Fig. 4A illustrates a circuit that is a compact representation of the circuit of

Fig. 2A, according to some embodiments.

[0009] Fig. 4B illustrates a circuit that is a compact representation of the circuit of

Fig. 2C, according to some embodiments.

[0010] Figs. 5A-5B illustrate compact representations of parallel decoding paths of a decoder, according to some embodiments.

l [0011] Fig. 6A is a compact representation of a decoder comprising multiple parallel paths, according to some embodiments.

[0012] Fig. 6B represents an equivalent compact representation of the compact representation of Fig. 6A, wherein in the compact representation of Fig. 6B, one or more decoding nodes and/or decoding segments are common among two or more decoding paths, according to some embodiments.

[0013] Fig. 7 represents a compact representation of a decoder comprising multiple parallel decoding paths, wherein one or more internal decoding nodes are common among two or more parallel decoding paths, according to some embodiments.

[0014] Fig. 8 illustrates an equivalent representation of the compact representation of the circuit of Fig. 4A, according to some embodiments.

[0015] Figs. 9A-9B illustrate a 3-dimensional hyper-cube to implement a multi-path decoder, according to some embodiments.

[0016] Fig. 10 illustrates a graph depicting example improvement in performance by using multipath decoder with common decoding segments and/or common internal decoding nodes, according to some embodiments.

[0017] Fig. 11 illustrates a graph depicting example improvement in performance by constructing a reliability ranking specifically for multipath decoder with common decoding segments and/or common internal decoding nodes, according to some embodiments.

[0018] Fig. 12 illustrates an eNB and a UE, according to some embodiments.

[0019] Fig. 13 illustrates hardware processing circuitries for an eNB for operating as an encoder and/or operating as a multi-path decoder with common decoding segments and/or common internal decoding nodes, according to some embodiments.

[0020] Fig. 14 illustrates hardware processing circuitries for a UE for operating as an encoder and/or operating as a multi-path decoder with common decoding segments and/or common internal decoding nodes, according to some embodiments.

[0021] Fig. 15 illustrates a method for a receiver to decode polar encoded codewords using multi-path decoder, according to some embodiments.

[0022] Fig. 16 illustrates a method for a computing device to generate a final reliability ranking, according to some embodiments.

[0023] Fig. 17 illustrates an architecture of a system of a network, according to some embodiments.

[0024] Fig. 18 illustrates example components of a device, according to some embodiments. [0025] Fig. 19 illustrates example interfaces of baseband circuitry, according to some embodiments.

DETAILED DESCRIPTION

[0026] Polar codes generally belong to a class of affine codes that may be generated by subsets of the rows of:

rl n-, ®log₂N

[0027] G_N = J Equation 1.

[0028] Here, "(g)" denotes a Kronecker power. In general, a rate K/N code (e.g., not necessarily a polar code) may be generated by selecting any K rows of G_N as a generator matrix. Various codes in this class can be encoded by a matrix multiplication U^G_N , where Ui is set to a data bit if the i^Ath row of G_N is in the code's generator matrix, and otherwise i/j is set to a predetermined fixed frozen value. Thus, input vector to the encoder may comprise a combination of data bits and frozen bits. Such a code may be referred to as a polar code if the corresponding generator matrix consists of K rows of G_N that satisfy Z(W ) < Z(Wj^), if i^th row is in the matrix and j^th row is not. Here, W is the channel, where denotes the output of the channel with input U^G_N. In an example, Z denotes the Bhattacharyya parameter. The order of Z(H^)'s may depend on the underlying channel and thus polar codes may be channel-specific designs. It some examples, these codes may have good performance under successive cancellation (SC) decoding and may achieve channel capacity. Although very few codes may be true polar codes according to this strict definition (in particular, if the order of Z(Wi s is unique for a given W, there is a unique polar code for that channel and given rate), in the literature many codes that do not necessarily adhere to the above rule may also be referred to as polar codes. In general, all of these codes share the property that Z(W ) may be small if the i^Ath row is included in the generator matrix. This disclosure also follows this practice, and thus the codes here may also be referred to as polar codes.

[0029] In some examples, a drawback of known polar codes may be that their performance under SC decoding may be inferior to that of best or better LDPC codes. More involved decoders, e.g., list decoders and maximum likelihood (ML) decoders, may improve known polar codes' performance, but not by too much. In an example, known polar code constructions may become competitive with the alternatives, e.g., when aided by an additional Cyclic Redundancy Cycle (CRC) check. [0030] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0031] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate a greater number of constituent signal paths, and/or have arrows at one or more ends, to indicate a direction of information flow. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0032] Throughout the specification, and in the claims, the term "connected" means a direct electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means either a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0033] The terms "substantially," "close," "approximately," "near," and "about" generally refer to being within +/- 10% of a target value. Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

[0034] It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. [0035] The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0036] For the purposes of the present disclosure, the phrases "A and/or B" and "A or

B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0037] In addition, the various elements of combinatorial logic and sequential logic discussed in the present disclosure may pertain both to physical structures (such as AND gates, OR gates, or XOR gates), or to synthesized or otherwise optimized collections of devices implementing the logical structures that are Boolean equivalents of the logic under discussion.

[0038] In addition, for purposes of the present disclosure, the term "eNB" may refer to a legacy eNB, a next-generation or NR gNB, a 5G eNB, an Access Point (AP), a Base Station or an eNB communicating on the unlicensed spectrum, and/or another base station for a wireless communication system. For purposes of the present disclosure, the term "UE" may refer to a legacy UE, a next-generation or NR UE, a 5G UE, an STA, and/or another mobile equipment for a wireless communication system.

[0039] Various embodiments of eNBs and/or UEs discussed below may process one or more transmissions of various types. Some processing of a transmission may comprise receiving, conducting, and/or otherwise handling a transmission that has been received. In some embodiments, an eNB or UE processing a transmission may determine or recognize the transmission's type and/or a condition associated with the transmission. For some embodiments, an eNB or UE processing a transmission may act in accordance with the transmission's type, and/or may act conditionally based upon the transmission's type. An eNB or UE processing a transmission may also recognize one or more values or fields of data carried by the transmission. Processing a transmission may comprise moving the transmission through one or more layers of a protocol stack (which may be implemented in, e.g., hardware and/or software-configured elements), such as by moving a transmission that has been received by an eNB or a UE through one or more layers of a protocol stack.

[0040] Various embodiments of eNBs and/or UEs discussed below may also generate one or more transmissions of various types. Some generating of a transmission may comprise receiving, conducting, and/or otherwise handling a transmission that is to be transmitted. In some embodiments, an eNB or UE generating a transmission may establish the transmission's type and/or a condition associated with the transmission. For some embodiments, an eNB or UE generating a transmission may act in accordance with the transmission's type, and/or may act conditionally based upon the transmission's type. An eNB or UE generating a transmission may also determine one or more values or fields of data carried by the transmission. Generating a transmission may comprise moving the transmission through one or more layers of a protocol stack (which may be implemented in, e.g., hardware and/or software-configured elements), such as by moving a transmission to be sent by an eNB or a UE through one or more layers of a protocol stack.

[0041] Fig. 1 illustrates a transmitter 102 and a receiver 130 communicating over a wireless channel 128, wherein the receiver 130 comprises a multi-path polar code decoder 134 comprising common decoding segments and/or common internal decoding nodes, in accordance with various embodiments. The transmitter 102 and/or the receiver 130 may be included in any appropriate devices capable of wireless communication in which data are encoded and/or decoded using polar codes. For example, the transmitter 102 and/or the receiver 130 may be included in one or more of: a eNB for communication with a UE, a UE for communication with a eNB, a UE for communication with another UE via Vehicle-to- Vehicle (V2V) transmission, a drone to communicate with another drone or with a drone controller, a television to communicate with a wireless sound system such as a headphone, and/or any other appropriate device.

[0042] In some embodiments, the transmitter 102 may comprise an encoder 104 that may receive input Ui^N, where the input Ui^N may comprise one or more data bits 112 and one or more frozen bits 116. In some embodiments, the relative positions of the data bits 112 and the frozen bits 116 in the input Ui^N may be based on a reliability ranking 108. In some embodiments, the input Ui^N may comprise N bits, such that 2ⁿ = N, where N may be the length of the codeword.

[0043] In some embodiments, a computing device 160 may generate the reliability ranking 108. For example, a ranking generation circuitry 162 may generate the reliability ranking 108.

[0044] In some embodiments, the encoder may arrange the data bits 112 and the frozen bits 116 within the input Ui^N, based on the reliability ranking 108, and generate coded bits Xi = UI^N.GN. The coded output UI^N.GN may be transmitted over a wireless channel 128, and received by a receiver 130 as Yi^N. In some embodiments, the receiver 130 may comprise the multi-path decoder 134 (also referred to as "decoder 134"), which may have common decoding segments and/or common internal decoding nodes, as will be discussed in further detail herein. The decoder 134 may decode the channel output Yi^N, e.g., based at least in part on the reliability ranking 108, to generate estimated data output 138. For example, the estimated data output 138 may be an estimate of the data bits 112.

[0045] Although not illustrated in Fig. 1, in some embodiments, the receiver 130 may comprise one or more antennas to receive data from the transmitter 102 over the channel 128. Although not illustrated in Fig. 1, in some embodiments, the receiver 130 may comprise one or more interfaces to transmit the data from the one or more antennas to the decoder 134.

[0046] In an example, the decoder 134 for binary linear codes (e.g., polar codes) may rl 0ΐ^Θη

be generated by a subset of rows of a matrix |_^ , where n is a positive integer. For simplicity, such codes are referred to herein as polar-like codes, or simply as polar codes. In an example, this class of codes may include Reed-Muller codes, and/or the like.

[0047] Fig. 2A illustrates a standard encoding/decoding circuit 200a for length-8 polar codes (e.g., for n = 3 and N = 8). As an encoder, the circuit 200a may receive as input data bits and frozen bits U₁, . . . , U₈ on the left (where the input bits are not labeled in the figure), wherein U₁, . . . , U₈ may correspond to Ui^N of Fig. 1. The circuit 200a may output coded bits on the right (where the output bits are not labeled in the figure). The

" 0" nodes 202 (e.g., only some of which are labelled as 202 in the figure) may perform binary XOR function, and the nodes 204 (e.g., with black dots, only some of which are labelled as 204 in the figure) may correspond to a "copy", or equivalently, "pass through" operation. The circuit of Fig. 2A may also be used for decoding after appropriate

modification (e.g., the XOR nodes at the encoder may correspond to a "check node" at the decoder, and the copy node at the encoder may correspond to a "variable node" at the decoder). The circuit of Fig. 2A is well known to those skilled in the art, and will not be discussed in further details herein.

[0048] Fig. 2B illustrates a circuit 200b comprising circuits 200b 1, 200b2, and 200b3, which are sections of the circuit 200a of Fig. 2A shown separately. Fig. 2C illustrates a circuit 200c, which may be similar to the circuit 200a of Fig. 1, but in reverse order.

[0049] In an example, the three circuits 200bl , 200b, and 200b3 of Fig. 2B may be connected in any order, without changing an input-output relationship of the overall circuit. For example, it may be verified that the circuit 200a of Fig. 2A is equivalent to (e.g., has the same input-output relationship) as the combination of the circuits 200bl , 200b, and 200b3 of Fig. 2B, and is also equivalent to the circuit 200c of Fig. 2C.

[0050] Referring to Fig. 2B, the circuit 200b has three sections 200b 1, 200b2, 200b3.

In an example, in general, for a polar encoder of length N = 2ⁿ, there may be n such sections, and connecting them in any of the n! possible orders may result in the same overall input-output relationship, where n\ is a factorial of n.

[0051] In an example, a belief propagation (BP) decoder may be used for polar codes.

In a BP decoder, initially, an appropriate graph representation may be chosen for a given code (out of the n\ possible representations). Common choices may be a direct order (e.g., illustrated in Fig. 2A), a reversed order (e.g., illustrated in Fig. C), or the like. The decoder architecture may mirror the chosen encoder, e.g., by substituting appropriate operations for the XOR nodes (e.g., nodes 202) and the copy nodes (e.g., nodes 204) in Figs. 2A-2C. In an example, in iterative decoding, the XOR nodes at the encoder may correspond to a "check node" at the decoder, and the copy node at the encoder may correspond to a "variable node" at the decoder. Messages may then be passed around over this decoding graph.

[0052] For purposes of discussion, it may be assumed that the encoder graph in Fig.

2A may also represent the decoder graph. BP decoding may start by initializing log- likelihood ratio (LLR) messages on each horizontal edge. For example, the rightmost edges of the circuit 200a may be initialized to the LLR values obtained from the channel output Yi^N, and the leftmost edges corresponding to frozen bits may be initialized to a very large LLR value (e.g., as the frozen bit values may be known a-priori by the decoder). All other LLR values corresponding to the data bits may be initialized to zero. After initialization, decoding may proceed by "processing sections in sequence" from the right to the left, then from the left to the right. This left-right-left iteration may then be repeated iteratively, e.g., several times. In an example, "processing a section" may involve updating messages in all of a 2x2 sub-section of the form illustrated in Fig. 3.

[0053] In an example, during a right-to-left traversal of the graph, the messages may be updated as:

[0054] ta = chk(c, var(b, d)) Equation 2.

[0055] tb = var(d, chk(a, c ) Equation 3.

[0056] a = ta Equation 4.

[0057] b = tb Equation 5.

[0058] In equations 2 and 3, var may represent the variable node operation and chk may represent the check node operation of a BP decoder to decode codewords that are encoded using polar codes. There may not be a dependency between the processing of 2x2 sub-sections within the same section, and therefore one or more 2x2 subsections (e.g., all the subsections) may be run in parallel. [0059] Similarly, during a left-to-right traversal of the graph, messages may be updated as:

[0060] tc = chk(a, var(b, d)) Equation 6.

[0061] td = var(b, chk(a, c)) Equation 7.

[0062] c = tc Equation 8.

[0063] d = td Equation 9.

[0064] In an example, an exception (e.g., the only exception) to this rule may be that at the leftmost section, the dangling edges may be reset to their initial values before traversing the section from left to right. Similar exception may also be valid for the rightmost section.

[0065] As illustrated in Figs. 2A-2C, multiple different representation of polar decoding graph may be possible. In an example, multiple different representations of the polar decoding graph may be used to improve the BP decoder's error performance. For example, a separate BP decoding path may be implemented for each representation, and the decoding paths may be allowed to share messages at the leftmost and rightmost sections. In some embodiments, since implementing a separate decoding path for each of the n! representations may be prohibitive, a number of parallel decoding paths may be limited to a relatively small number M that may be less than, or equal to n\ . For example, n cyclic shifts of the standard decoder in Fig. 2A may be considered. In general, the memory requirement of such a decoder may be M times a standard BP decoder's, and the throughput may be M times worse (e.g., using the same number of processing units).

[0066] Fig. 4A illustrates a circuit 400 that is a compact representation of the circuit

200a of Fig. 2A, according to some embodiments. The top section of Fig. 4A represents the circuit 200a, and the bottom section represents the equivalent compact representation circuit 400.

[0067] For example, a first segment 401 of the circuit 400 represents a compact version of a left section of the circuit 200a, which also corresponds to the circuit 200b 1 of Fig. 2B. A second segment 402 of the circuit 400 represents a compact version of a middle section of the circuit 200a, which also corresponds to the circuit 200b2 of Fig. 2B. Finally, a third segment 403 of the circuit 400 represents a compact version of a right section of the circuit 200a, which also corresponds to the circuit 200b3 of Fig. 2B. [0068] The circuit 400 has multiple decoding nodes - the leftmost and rightmost nodes are respectively labelled as 4501 and 450r, and the internal decoding nodes are generically labelled as 450i.

[0069] Fig. 4B illustrates a circuit 420 that is a compact representation of the circuit

200c of Fig. 2C, according to some embodiments. For example, as the circuit 200c is a symmetrically opposite or reverse of the circuit 200a of Fig. 2A, in Fig. 4B the segments are in the order 403, 402, and 401 from left to right (e.g., opposite of the ordering of the segments in Fig. 4A).

[0070] Figs. 4A-4B and other similar figures are referred to herein as a compact representation of a decoder graph or decoder circuit, e.g., for decoding polar codes.

[0071] In an example, each dot or node (e.g., decoding nodes) in the compact representation of Figs. 4A and 4B may correspond to a column of LLR messages between the segments. The leftmost and rightmost nodes (e.g., nodes 4501 and 450r) correspond to data and/or frozen LLRs, and channel LLRs, respectively. The edges may represent sections connecting columns of LLRs.

[0072] Figs. 4A-4B correspond to the scenario when N = 8 and n = 3. As discussed herein, there may be n!, or 6 possible permutations of various decoding segments (also referred to simply as "segments") of the decoder for n = 3. Figs. 5A-5B illustrate compact representations 500a and 500b, respectively, of parallel decoding paths of a decoder (e.g., for n = 3), according to some embodiments. For example, in Fig. 5A, three example cyclic shifts of a BP decoder are illustrated, in Fig. 5B all six (e.g., 3 !) possible permutations are represented.

[0073] The segments in Figs. 5A-5B and various other figures are generically represented using general numbers such as 1, 2, 3, and so on. Thus, for example, a segment "1" in Figs. 5A-5B may correspond to a segment in the left side of the circuit 200a of Fig. 2A, and may also correspond to the circuit 200b 1 of Fig. 2B. Also, for example, a segment "2" in Figs. 5A-5B may correspond to a segment in the middle of the circuit 200a of Fig. 2A, and may also correspond to the circuit 200b2 of Fig. 2B. Thus, each of the segments 1, 2, and 3 of Figs. 5A-5B are decoding segments which may respectively correspond to the circuits 200b 1, 200b2, and 200b3 of Fig. 2B.

[0074] In each of Figs. 5A-5B, the decoder may comprise multiple parallel decoding paths (also generically referred to simply as paths). Each path may comprise multiple segments and multiple decoding nodes. Generally, each path may have similar segments (e.g., segments 1 , 2, and 3), but the order of the segments appearing in the paths may be different.

[0075] For example, a first path in Fig. 5B comprises segments 1 , 2, and 3 in that order; a second path in Fig. 5B comprises segments 1 , 3, and 2 in that order; a third path in Fig. 5B comprises segments 2, 1 , and 3 in that order, and so on.

[0076] In an example, for each of the multiple paths of Fig. 5B, for example, the input column corresponds to the same first bits, and the output columns also correspond to the same second bits - hence, the end nodes of the parallel paths may be tied, as illustrated in Fig. 5B. Thus, for example, the multiple paths may share their LLR messages at the left and right extremes, as shown above.

[0077] Fig. 6A is a compact representation 600a of a decoder comprising multiple parallel decoding paths, and Fig. 6B represents an equivalent compact representation 600b of the compact representation 600a of Fig. 6A, wherein in the compact representation 600b of Fig. 6B, one or more internal decoding nodes and/or decoding segments are common among two or more decoding paths, according to some embodiments. For example, the compact representation 600a of Fig. 6A comprises two parallel paths 1 -2-3, and 1 -3-2, e.g., which may be similar to two of the parallel paths illustrated in Figs. 5A-5B. Furthermore, the two parallel paths in Fig. 6A comprises internal nodes 560a and 650b, respectively.

[0078] Also, in Fig. 6A, the two parallel paths share the input node and the output node (e.g., the leftmost and the rightmost nodes, respectively). Furthermore, the internal bits in the internal nodes 650a and 650b may also be similar for the two parallel paths, as the two parallel paths have the same segment 1 between the respective internal node and the leftmost input node. Thus, in some embodiments, the internal nodes 650a and 650b may be joined as a single internal common decoding node 650 (also generally referred to as "common node 605"), as illustrated in Fig. 6B. Thus, in Fig. 6B, the compact representation may comprise a common segment 1 and a common node 650 among the two decoding paths. The two decoding paths may therefore share the LLRs of the internal node 650, which may improve the memory requirement and/or the error performance of the decoder.

[0079] In some embodiments and merely as an example, the decoder 134 of Fig. 1 may be implemented by the decoder of Fig. 6B. For example, similar to Fig. 6B, the decoder 134 of Fig. 1 may comprise multiple decoding paths, and two or more decoding paths may have at least one common segment and/or at least one common internal node.

[0080] Fig. 7 represents a compact representation of a decoder 700 comprising multiple parallel paths, wherein one or more internal nodes are common among two or more parallel paths, according to some embodiments. For example, in general, let n (where 2ⁿ may be the length of the code word) be even, and consider all permutations of 1, n obtained by picking a subset of the odd numbers 1, 3, n-1, and swapping them by the even numbers to their right. There may be 2^(n/2) such permutations. In some embodiments, an n-section decoder consisting of at least some (or all) of these permutations may be implemented. By applying the idea discussed with respect to Fig. 6B, this decoder may be implemented using 2n sections and (n+1) LLR columns. For example, Fig. 7 illustrates such a decoder for n = 8.

[0081] Thus, the decoder 700 comprises 16 (e.g., 2n) sections or segments, and 9

(e.g., n+1) LLR columns. As illustrated, the decoder 700 has multiple common nodes (e.g., common node 750). A first path implemented by the decoder 700 may be 1-2-3-4-5-6-7-8, a second path implemented by the decoder 700 may be 1-2-3-4-5-6-8-7, a third path implemented by the decoder 700 may be 1-2-3-4-6-5-7-8, a fourth path implemented by the decoder 700 may be 2-1-3-4-5-6-7-8, and so on. Thus, there may be 2^(n/2), or 2⁴, e.g., 16 paths in the decoder, where the paths share one or more common internal nodes (e.g., node 750). Thus, in Fig. 7, it is seen that each of the 2^(n/2) = 16 permutations appear as a left-to- right path on this decoder graph, and the graph implements only 16 sections (e.g., instead of 16*8=128 sections). Joining the LLR columns after every second section may enable reducing complexity and sharing information between different permutations.

[0082] The principles discussed with respect to Figs. 6B and 7 (e.g., decoder with multiple paths having common segments and/or common internal nodes) may be extended even further. For this purpose, an altemative description of the decoding graphs may be used. Instead of indexing the segments of the graph by integers (e.g., 1, 2, 3. ... ), the nodes (e.g., the LLR columns) may be indexed by n-bit strings. For example, the leftmost LLR column may be indexed by all-zero string, and the rightmost column by all-one string. If two LLR columns are connected by a section i, then their index strings are identical except at the i^th position. For example, Fig. 8 illustrates an equivalent representation 800 of the compact representation 400 of Fig. 4A, according to some embodiments. The nodes of the representation 800 are indexed using n-bit strings, where n = 3, e.g., as discussed herein above.

[0083] Using the notation of n-bit strings for the nodes, each decoding permutation may correspond to a length-n path from the all-zero string to the all-one string, e.g., by adding a 1 at each step. For example, the n-bit strings may index vertices of an n- dimensional hypercube, and each decoding permutation may be a path from the all-zero vertex to the all-one vertex. The BP decoder on all paths may be implemented by, for example, implementing the n-dimensional hypercube. The memory requirement (e.g., normalized by that of a BP decoder) of this method may be determined by the number of nodes, which may be 2ⁿ. The amount of computation (also normalized) may be determined by the number of edges, which may be n * 2^n_1. Both of these requirements are significantly lower than the n! requirement of a naive implementation that implements separate paths without any common nodes or common segments.

[0084] An example of the n-dimensional hypercube for n = 3 is illustrated in Figs.

9A and 9B, according to some embodiments. For example, in the hypercube representation in Fig. 9A, the segments are represented using integers (e.g., 1, 2, 3, etc.); and in the hypercube representation in Fig. 9B, the nodes are represented using n-bit string (e.g., 000,

001, 010, ... , 111). BP decoding on such a graph may start by passing messages from the all- one node to weight (n— 1) nodes, then from weight (n— 1) nodes to weight-(n— 2) nodes, all the way down to the all-zero node. Then the graph may be traversed in the opposite direction, e.g., from the all-zero node to weight 1 nodes, etc., all the way up to the all-one node. This left-right-left traversal may be repeated several times.

[0085] Thus, for example, the decoder 134 may be implemented using a n- dimensional hypercube, e.g., the 3-dimensional hypercube of Figs. 9A-9B. In some embodiments, the decoder 134 may have all the paths or edges of such a hypercube; while in some other embodiments, the decoder 134 may have less than all the paths or edges of such a hypercube. Put differently, a decoder 134 for a 2ⁿ length codeword can have at most a number of paths corresponding to the corresponding n-dimensional hypercube. Thus, in some embodiments, arbitrary sets of parallel decoding paths may be implemented by the same method, e.g., by keeping the minimal subgraph of the hypercube that contains the desired set of paths. The processing order may be in general the same, going from the all-one vertex to the all-zero vertex and back, and then repeating the traversal multiple times.

[0086] Such a n-dimensional hypercube may have common segments and/or common internal nodes for two or more paths. For example, as illustrated in Figs. 9A-9B, a first example path may traverse nodes 000, 100, 101, and 111, which may have segments 1, 3, and

2. A second example path may traverse nodes 000, 100, 110, and 111, which may have segments 1, 2, and 3. Thus, the two paths may have a common internal node 100, and a common segment 1.

[0087] In some embodiments, a decoder with multiple paths may share common segments and/or common internal nodes. In an example, this may require much less than a proportional increase in hardware to implement several multiple BP decoders without shared segments and shared nodes (e.g., which may be referred to as "non-shared BP decoder"). For example, n! decoding graphs may be implemented by 2^n_1 sections, as opposed to n * (n!) sections in a BP decoder with multiple paths and no shared segments or internal nodes. In an example, the memory requirement may be only 2ⁿ/n times that of the non-shared BP decoder, e.g., as opposed to n! times. In some embodiments, the principles of this disclosure may apply to all possible selections of decoding graphs. As an example, a certain selection of n

2z parallel decoder graphs may be implemented by using only 2n sections (e.g., a 2x increase in the number of operations, and a 1.5x increase in memory requirement with respect to a non-shared BP decoder). In addition, all the parallel representations may share their LLR messages whenever possible (at the input node, output node, as well as intemal nodes), which may improve performance.

[0088] Fig. 10 illustrates a graph depicting example improvement in performance by using multipath decoder with common segments and/or common intemal nodes, according to some embodiments. The X axis represents erasure probability, and the Y axis represents block error rate (BLER). A polar code (128,256) (e.g., 128 data bits among total 256 input bits, and n = 8) and three different decoders for transmission over a binary erasure channel (BEC) is used to generate the graph. The line 1002 illustrates the BLER performance vs channel erasure probability under the standard BP decoding. The line 1004 is for a decoder that implements all 16 paths obtained by all possible swaps of the odd sections with their right-hand-side neighbor. The line 1006 illustrates the performance under the decoder that implements all 8! , e.g., 40320 paths by a decoder that implements only 1024 sections. As seen, the line 1006 may have better performance than the line 1002.

[0089] Referring again to Fig. 1, in some embodiments, the encoder 104 and the decoder 134 may have access to the reliability ranking 108. As discussed with respect to Fig. 1, the input Ui^N to the encoder 104 may comprise data bits 112 and frozen bits 116. For example, some of the bits of input vector Ui^N may comprise bits from data bits 112, and remaining of the bits of input vector Ui^N may comprise frozen bits 116. In some

embodiments, reliability ranking 108 may rank various positions of the input vector Ui^N, e.g., based on a reliability of the corresponding bits to be transmitted correctly over the channel and decoded by decoder 134.

[0090] Merely as a simple example of N = 8, the reliability ranking 108 may be [7, 5,

6, 3, 4, 2, 1, 0] (although such a ranking is merely an example). For such an example, position 7 (or bit number 7) of input vector Ui^N may have a highest probability of being correctly decoded by decoder 134, position 5 (or bit number 5) of input vector Ui^N may have a second highest probability of being correctly decoded by decoder 134, position 6 (or bit number 6) of input vector Ui^N may have a third highest probability of being correctly decoded by decoder 134, and so on.

[0091] In this example of the reliability ranking 108 being [7, 5, 6, 3, 4, 2, 1, 0], if coding rate is 1/8, then a single data bit 112 may be in position 7 of input vector Ui^N, and remaining bits of input vector Ui^N may be frozen bits 116. In another example, if coding rate is 2/8, then data bits 112 may comprise two bits in positions 7 and 5 of input vector Ui^N, and remaining bits of input vector Ui^N may be frozen bits 116. In another example, if coding rate is 4/8, then data bits 112 may comprise four bits in positions 7, 5, 6, and 3 of input vector Ui^N, and remaining bits of input vector Ui^N may be frozen bits 116.

[0092] Thus, in some embodiments, the encoder 104 may select appropriate positions for the data bits 112 in the input vector Ui^N, based on reliability ranking 108. Put differently, in some embodiments, data bits 112 and frozen bits 116, in combination, may form the input vector Ui^N received by encoder 104, where positions of the data bits 112 in the input vector Ui^N may be based on the reliability ranking 108. In some embodiments, the decoder 134 may also have access to the reliability ranking 108, based on which the decoder 134 may decode the output Yi^N from the channel 128, and generate the estimated data output 138.

[0093] As previously discussed herein, the reliability ranking 108 may be generated by the computing device 160. Computing device 160 may be a part of the transmitter 102 and/or the receiver 130, or may be separate from the transmitter 160 and/or the receiver 130. For example, the computing device 160 may generate the reliability ranking 108 in advance, and communicate the reliability ranking 108 to the transmitter 102 and/or the receiver 130 prior to communication between the transmitter 102 and/or the receiver 130.

[0094] In an example, given a codeword length and a code rate, polar code design may involve choosing a set of data bit positions and the complementary set of frozen bit positions. In some embodiments, the choice of data/frozen bit positions (e.g., the choice of the reliability ranking 108) depend on the representation chosen for the decoder. As discussed with respect to Figs. 1, 6B-9B, in some embodiments, a multipath decoder with common segments and/or common internal nodes may be used for decoding, e.g., in which polar codes may be decoded using many distinct graphical representations simultaneously and in effect using BP decoders for all representations in tandem. For ease of reference, such decoder will be referenced as multi-path BP decoder, examples of which may be the decoder 134 and/or any of the decoders discussed with respect to Figs. 6B-9B. In some embodiments, it may be useful to generate the reliability ranking 108 specifically for the multi-path BP decoder discussed herein.

[0095] For example, consider the decoder 70 of Fig. 7. There may be 16 left-to-right paths in this decoder, each of which may correspond to a different representation of the same polar encoding/decoding graph. For example, the path (1,2,3,4,5,6,7,8) may correspond to the standard decoding order. In a general case, each path may be denoted by a vector ρ , (n=8 in the example of Fig. 7), where pi ^ { Ι ,. , .,η} may correspond to the index of the i^th path.

[0096] In an example, various polar decoders (e.g., all polar decoders, or reasonable polar decoders), e.g., including successive cancellation, belief propagation, and list decoders, may belong to the class of message passing decoders. For such decoders, an ideal or near ideal polar code design for one graphical representation may be translated to an ideal or near ideal code design for another graphical representation, for example, as follows. Let p" denote the representation for which the code was designed, and let q" denote the

representation for which the code is to be translated to. Let H denote a permutation matrix that satisfies q" = H. p . Thus, the matrix H translates the representation p" to the representation q" . Also, the data/frozen bit indices l, . . . , 2ⁿ may be denoted by length-n binary vectors. Also, let A _≡ {0,l}ⁿ denote a set of data bit indices. It can be shown that the error probability of the polar code described by A, decoded over the graph p" , may be identical to that of the code described by the set {H. a a E A] when decoded over the graph q" . This suggests that for multi-path decoders, the code may be "symmetric" with respect to all paths (i.e., permutations) in the multi-path BP decoder, and all data indices may be good for at least one path.

[0097] This motivates the following example bit selection rule for a given multi-path

BP decoder: Suppose there exists an initial list L = [Z₁₍ . . . l_N] , where N = 2ⁿ, that is sorted with respect to the quality of bits for a given graphical representation p" . That is, l- is considered the most reliable bit index, l₂ the second most reliable, IN the least reliable bits, and so on, in the input vector Ui^N. Thus, L may be an initial reliability ranking that may be used to generate the reliability ranking 108 of Fig. 1.

[0098] Generation of the reliability ranking 108 (also referred to herein as a "final reliability ranking") from the initial reliability ranking L may be independent of how the initial reliability ranking L is generated. For example, the initial reliability ranking L may be generated using any appropriate technique to generate a reliability ranking for polar coding. Such an initial reliability ranking L may sometimes be referred to as a nested polar code construction rule.

[0099] The discussion above implies that under BP decoding over a path Hp", the most reliable bit index is H. ly. Put differently, if p" is a given decoding path and the reliability ranking L is generated for the decoding path p" (e.g. reliability ranking L is assumed to be ideal or near ideal for decoding path p" ), then H.L may be a reliability ranking for a decoding path H. p™.

[00100] Consider now a multi-path BP decoder characterized by a set of permutations

H- , . . . H_M. Thus, the multiple decoding paths of the multi-path decoder are given by H(p , i = 1, ... , M, where M may be the number of decoding paths in the multi-path BP decoder. In some embodiments, given a code rate of K/2ⁿ (e.g., there are total N = 2ⁿ bits in the input Ui^N, where K number of bits are data bits 112), a code can be obtained by adding all permutations of l- to the data index set, followed by all permutations of l₂, until there are K data bits. This may be formalized in the form of the following Algorithm 1 :

[00101] Operation 1 :

[00102] Start with an empty set A

[00103] Operation 2:

[00104] for i = 1, 2, 3, ... , 2ⁿ (e.g.,)

[00105] for j = 1, 2, ... , (e.g., M number of decoding paths)

[00106] add index Hj. I, to the set A;

[00107] if |A| > K, exit.

[00108] In algorithm 1, M may be the total number of decoding paths in the decoder

134, there may be total 2ⁿ bits in the input Ui^N, and K may be the number of data bits in the input Ui^N. Also, the set A at the end of the algorithm 1 may be the reliability ranking 108 of Fig. 1 (e.g., the set A may a final reliability ranking). \A \ represents the size of set A.

[00109] In an example, algorithm 1 starts with an empty set A. Also, an input to the algorithm is the initial reliability ranking L as discussed herein above. For example, the initial reliability ranking L is [l- , . . . l_N], and the initial reliability ranking L is assumed to be ideal or near ideal for an example decoding path p" . Also, assume that there are M possible decoding paths such that, for example, a first decoding path may be represented by Hi.L, a second decoding path may be represented by H2.L, a j^th decoding path may be represented by Hj.L, and so on. In a first iteration of operation 2 of algorithm 1, assume i = 1, and j = 1. Thus, the position Hi.h may be added to the set, and this number may be the most reliable position in the final version of the set A. Subsequently, H2. I1 may be added to the set, and this number may be the second most reliable position in the final version of the set A. This may be followed by additions of H3. I1, H4. I1, HM. II. During a second iteration (e.g., / = 2), Hi.h, H2.I2, Hu.h may be added to the set A.

[00110] This operation may be iteratively repeated until, for example, the set A has at least K number of reliability positions. For example, assume n = 8 (e.g., a code length of 256 and input Ui^N has 256 number of data and frozen bits) and a code rate of 128/256. Thus, there may be 128 data bits in the input Ui^N, and 128 frozen bits in the input Ui^N. So, the algorithm 1 may predict the most reliable 128 positions in the input Ui^N. The reliability of the remaining positions need not be ordered or ranked, as these positions may include frozen bits. Thus, the algorithm stops when |A| > K, e.g., the set A has at least 128 entries.

[00111] The algorithm 1 may have one or more variations. Merely as an example, only a subset (e.g., instead of all) of H_x, H_M may be included in the inner loop of the algorithm. In an example, such restrictions may lead to better performance, as has been verified empirically.

[00112] In some embodiments, the algorithm 1 may be applied to various or even all channel types, various or even all code lengths, and/or various or even all code rates.

Considerable performance gains may be achieved with this algorithm, e.g., by matching the code to the receiver's decoder.

[00113] Fig. 11 illustrates a graph depicting example improvement in performance by constructing the reliability ranking (e.g., based on algorithm 1) specifically for multipath decoder with common segments and/or common internal nodes, according to some embodiments. The X axis represents erasure probability, and the Y axis represents BLER. A polar code (128,256) (e.g., 128 data bits among total 256 input bits, and n = 8) for transmission over a binary erasure channel (BEC) is used to generate the graph.

[00114] The lines 1 104 and 1 110 show the performance of an ordinary polar code optimized for a single path, under a standard BP decoder (dashed line 1 104), and under the 16-path decoder of Fig. 7 (solid line 11 10). It can be seen that the multi-path decoder does not meaningfully improve performance here, since the code is optimized for a single path. The lines 1 102 and 1108 show the performance of the code optimized for all 16 paths as described with respect to algorithm 1 , also under standard BP (dotted line 1 102) and 16-path BP (solid line 1108). While the BP decoder performance is worse than the standard polar code, the multi-path decoder performance is noticeably better. The lines 1 106 and 11 12 are for a code that is optimized only for the paths (1,2,3,4,5,6,7,8) and (2,1 ,4,3,6,5,8,7), also under BP (dashed line 1 112) and the 16-path BP (solid line 1 106). It is seen that this code not only does well under multi-path decoding, but is significantly better even under standard BP decoding.

[00115] Fig. 12 illustrates an eNB and a UE, according to some embodiments. Fig. 12 includes block diagrams of an eNB 1210 and a UE 1230 which are operable to co-exist with each other and other elements of an LTE network. High-level, simplified architectures of eNB 1210 and UE 1230 are described so as not to obscure the embodiments. It should be noted that in some embodiments, eNB 1210 may be a stationary non-mobile device.

[00116] eNB 1210 is coupled to one or more antennas 1205, and UE 1230 is similarly coupled to one or more antennas 1225. However, in some embodiments, eNB 1210 may incorporate or comprise antennas 1205, and UE 1230 in various embodiments may incorporate or comprise antennas 1225.

[00117] In some embodiments, antennas 1205 and/or antennas 1225 may comprise one or more directional or omni-directional antennas, including monopole antennas, dipole antennas, loop antennas, patch antennas, microstrip antennas, coplanar wave antennas, or other types of antennas suitable for transmission of RF signals. In some MIMO (multiple- input and multiple output) embodiments, antennas 1205 are separated to take advantage of spatial diversity.

[00118] eNB 1210 and UE 1230 are operable to communicate with each other on a network, such as a wireless network. eNB 1210 and UE 1230 may be in communication with each other over a wireless communication channel 1250, which has both a downlink path from eNB 1210 to UE 1230 and an uplink path from UE 1230 to eNB 1210.

[00119] As illustrated in Fig. 12, in some embodiments, eNB 1210 may include a physical layer circuitry 1212, a MAC (media access control) circuitry 1214, a processor 1216, a memory 1218, and a hardware processing circuitry 1220. A person skilled in the art will appreciate that other components not shown may be used in addition to the components shown to form a complete eNB.

[00120] In some embodiments, physical layer circuitry 1212 includes a transceiver

1213 for providing signals to and from UE 1230. Transceiver 1213 provides signals to and from UEs or other devices using one or more antennas 1205. In some embodiments, MAC circuitry 1214 controls access to the wireless medium. Memory 1218 may be, or may include, a storage media/medium such as a magnetic storage media (e.g., magnetic tapes or magnetic disks), an optical storage media (e.g., optical discs), an electronic storage media (e.g., conventional hard disk drives, solid-state disk drives, or flash-memory-based storage media), or any tangible storage media or non-transitory storage media. Hardware processing circuitry 1220 may comprise logic devices or circuitry to perform various operations. In some embodiments, processor 1216 and memory 1218 are arranged to perform the operations of hardware processing circuitry 1220, such as operations described herein with reference to logic devices and circuitry within eNB 1210 and/or hardware processing circuitry 1220.

[00121] Accordingly, in some embodiments, eNB 1210 may be a device comprising an application processor, a memory, one or more antenna ports, and an interface for allowing the application processor to communicate with another device.

[00122] As is also illustrated in Fig. 12, in some embodiments, UE 1230 may include a physical layer circuitry 1232, a MAC circuitry 1234, a processor 1236, a memory 1238, a hardware processing circuitry 1240, a wireless interface 1242, and a display 1244. A person skilled in the art would appreciate that other components not shown may be used in addition to the components shown to form a complete UE.

[00123] In some embodiments, physical layer circuitry 1232 includes a transceiver

1233 for providing signals to and from eNB 1210 (as well as other eNBs). Transceiver 1233 provides signals to and from eNBs or other devices using one or more antennas 1225. In some embodiments, MAC circuitry 1234 controls access to the wireless medium. Memory 1238 may be, or may include, a storage media/medium such as a magnetic storage media (e.g., magnetic tapes or magnetic disks), an optical storage media (e.g., optical discs), an electronic storage media (e.g., conventional hard disk drives, solid-state disk drives, or flash- memory-based storage media), or any tangible storage media or non-transitory storage media. Wireless interface 1242 may be arranged to allow the processor to communicate with another device. Display 1244 may provide a visual and/or tactile display for a user to interact with UE 1230, such as a touch-screen display. Hardware processing circuitry 1240 may comprise logic devices or circuitry to perform various operations. In some embodiments, processor 1236 and memory 1238 may be arranged to perform the operations of hardware processing circuitry 1240, such as operations described herein with reference to logic devices and circuitry within UE 1230 and/or hardware processing circuitry 1240.

[00124] Accordingly, in some embodiments, UE 1230 may be a device comprising an application processor, a memory, one or more antennas, a wireless interface for allowing the application processor to communicate with another device, and a touch-screen display.

[00125] Elements of Fig. 12, and elements of other figures having the same names or reference numbers, can operate or function in the manner described herein with respect to any such figures (although the operation and function of such elements is not limited to such descriptions). For example, Fig. 12 also depicts embodiments of eNBs, hardware processing circuitry of eNBs, UEs, and/or hardware processing circuitry of UEs, and the embodiments described with respect to Fig. 12 can operate or function in the manner described herein with respect to any of the figures.

[00126] In addition, although eNB 1210 and UE 1230 are each described as having several separate functional elements, one or more of the functional elements may be combined and may be implemented by combinations of software-configured elements and/or other hardware elements. In some embodiments of this disclosure, the functional elements can refer to one or more processes operating on one or more processing elements. Examples of software and/or hardware configured elements include Digital Signal Processors (DSPs), one or more microprocessors, DSPs, Field-Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Radio-Frequency Integrated Circuits (RFICs), and so on.

[00127] Fig. 13 illustrates hardware processing circuitries for an eNB for operating as an encoder (e.g., the encoder 104 of Fig. 1) and/or operating as a multi-path decoder with common segments and/or common nodes (e.g., decoder 134 of Fig. 1), according to some embodiments. For example, the eNB may implement the encoder 134 to encode data prior to transmitting to one or more UEs, and/or may implement the decoder 134 while processing communication received from one or more UEs.

[00128] With reference to Fig. 12, an eNB may include various hardware processing circuitries discussed below, which may in turn comprise logic devices and/or circuitry operable to perform various operations. For example, in Fig. 12, eNB 1210 (or various elements or components therein, such as hardware processing circuitry 1220, or combinations of elements or components therein) may include part of, or all of, these hardware processing circuitries.

[00129] In some embodiments, one or more devices or circuitries within these hardware processing circuitries may be implemented by combinations of software-configured elements and/or other hardware elements. For example, processor 1216 (and/or one or more other processors which eNB 1210 may comprise), memory 1218, and/or other elements or components of eNB 1210 (which may include hardware processing circuitry 1220) may be arranged to perform the operations of these hardware processing circuitries, such as operations described herein with reference to devices and circuitry within these hardware processing circuitries. In some embodiments, processor 1216 (and/or one or more other processors which eNB 1210 may comprise) may be a baseband processor.

[00130] Returning to Fig. 13, an apparatus of eNB 1210 (or another eNB or base station), which may be operable to communicate with one or more UEs on a wireless network, may comprise hardware processing circuitry 1300. In some embodiments, hardware processing circuitry 1300 may comprise one or more antenna ports 1305 operable to provide various transmissions over a wireless communication channel (such as wireless

communication channel 1250). Antenna ports 1305 may be coupled to one or more antennas 1307 (which may be antennas 1205). In some embodiments, hardware processing circuitry 1300 may incorporate antennas 1307, while in other embodiments, hardware processing circuitry 1300 may merely be coupled to antennas 1307.

[00131] Antenna ports 1305 and antennas 1307 may be operable to provide signals from an eNB to a wireless communications channel and/or a UE, and may be operable to provide signals from a UE and/or a wireless communications channel to an eNB. For example, antenna ports 1305 and antennas 1307 may be operable to provide transmissions from eNB 1210 to wireless communication channel 1250 (and from there to UE 1230, or to another UE). Similarly, antennas 1307 and antenna ports 1305 may be operable to provide transmissions from a wireless communication channel 1250 (and beyond that, from UE 1230, or another UE) to eNB 1210.

[00132] Hardware processing circuitry 1300 may comprise various circuitries operable in accordance with the various embodiments discussed herein. With reference to Fig. 13, hardware processing circuitry 1300 may comprise a first circuitry 1310 and/or a second circuitry 1320. In some embodiments, the first circuitry 1310 may operate as an encoder, e.g., the encoder 104 of Fig. 1, to encode using polar coding to generate codewords based at least in part on the reliability ranking 108. In some embodiments, the second circuitry 1320 may operate as a decoder, e.g., the multipath decoder 134 of Fig. 1, to decode codewords received over a wireless channel, where the decoder may decode using multiple decoding paths having one or more common decoding segments and/or one or more common internal decoding nodes, as discussed herein.

[00133] In some embodiments, first circuitry 1310 and/or second circuitry 1320 may be implemented as separate circuitries. In other embodiments, first circuitry 1310 and/or second circuitry 1320 may be combined and implemented together in a circuitry without altering the essence of the embodiments. [00134] Fig. 14 illustrates hardware processing circuitries for a UE for operating as an encoder (e.g., the encoder 104 of Fig. 1) and/or operating as a multi-path decoder with common segments and/or common nodes (e.g., decoder 134 of Fig. 1), according to some embodiments. For example, the UE may implement the encoder 134 to encode data prior to transmitting to a eNB or to another UE (e.g., using V2V transmission), and/or may implement the decoder 134 while processing communication received from a eNB or from another UE. With reference to Fig. 12, a UE may include various hardware processing circuitries discussed below, which may in turn comprise logic devices and/or circuitry operable to perform various operations. For example, in Fig. 12, UE 1230 (or various elements or components therein, such as hardware processing circuitry 1240, or combinations of elements or components therein) may include part of, or all of, these hardware processing circuitries.

[00135] In some embodiments, one or more devices or circuitries within these hardware processing circuitries may be implemented by combinations of software-configured elements and/or other hardware elements. For example, processor 1236 (and/or one or more other processors which UE 1230 may comprise), memory 1238, and/or other elements or components of UE 1230 (which may include hardware processing circuitry 1240) may be arranged to perform the operations of these hardware processing circuitries, such as operations described herein with reference to devices and circuitry within these hardware processing circuitries. In some embodiments, processor 1236 (and/or one or more other processors which UE 1230 may comprise) may be a baseband processor.

[00136] Returning to Fig. 14, an apparatus of UE 1230 (or another UE or mobile handset), which may be operable to communicate with one or more eNBs on a wireless network, may comprise hardware processing circuitry 1400. In some embodiments, hardware processing circuitry 1400 may comprise one or more antenna ports 1405 operable to provide various transmissions over a wireless communication channel (such as wireless

communication channel 1250). Antenna ports 1405 may be coupled to one or more antennas 1407 (which may be antennas 1225). In some embodiments, hardware processing circuitry 1400 may incorporate antennas 1407, while in other embodiments, hardware processing circuitry 1400 may merely be coupled to antennas 1407.

[00137] Antenna ports 1405 and antennas 1407 may be operable to provide signals from a UE to a wireless communications channel and/or an eNB, and may be operable to provide signals from an eNB and/or a wireless communications channel to a UE. For example, antenna ports 1405 and antennas 1407 may be operable to provide transmissions from UE 1230 to wireless communication channel 1250 (and from there to eNB 1210, or to another eNB). Similarly, antennas 1407 and antenna ports 1405 may be operable to provide transmissions from a wireless communication channel 1250 (and beyond that, from eNB 1210, or another eNB) to UE 1230.

[00138] Hardware processing circuitry 1400 may comprise various circuitries operable in accordance with the various embodiments discussed herein. With reference to Fig. 14, hardware processing circuitry 1400 may comprise a first circuitry 1410 and/or a second circuitry 1420. In some embodiments, the first circuitry 1410 may operate as an encoder, e.g., the encoder 104 of Fig. 1, to encode using polar coding to generate codewords based at least in part on the reliability ranking 108. In some embodiments, the second circuitry 1420 may operate as a decoder, e.g., the multipath decoder 134 of Fig. 1, to decode codewords received over a wireless channel, where the decoder may decode using multiple decoding paths having one or more common decoding segments and/or one or more common internal decoding nodes, as discussed herein.

[00139] In some embodiments, first circuitry 1410 and/or second circuitry 1420 may be implemented as separate circuitries. In other embodiments, first circuitry 1410 and second circuitry 1420 may be combined and implemented together in a circuitry without altering the essence of the embodiments.

[00140] Referring now to Figs. 13 and 14, as previously discussed herein, the first circuitry 1310 and/or the first circuitry 1410 may operate as an encoder, e.g., the encoder 104 of Fig. 1, to encode using polar coding to generate codewords based at least in part on the reliability ranking 108. Also, the second circuitry 1320 and/or the second circuitry 1420 may operate as a decoder, e.g., the multipath decoder 134 of Fig. 1, to decode codewords received over a wireless channel, where the decoder may decode using multiple decoding paths having one or more common decoding segments and/or one or more common internal decoding nodes, as discussed herein.

[00141] For example, the encoder of any of the circuitry 1310 or 1410 may encode data using polar coding, e.g., based on the reliability ranking 108, and cause to transmit the encoded data over the channel 128.

[00142] For example, the decoder of any of the circuitry 1320 or 1420 may receive the encoded data over the channel 128 (e.g., via one or more antennas and an interface). In some embodiments, the decoder may decode the channel output. In some embodiments, the decoder may comprise a plurality of decoding paths, wherein a first decoding path and a second decoding path may comprise a common decoding segment. In some embodiments, the common decoding segment may comprise: one or more first nodes to perform

corresponding one or more check node operations; and one or more second nodes to perform corresponding one or more variable node operations. In some embodiments, the first decoding path and the second decoding path comprises a common internal decoding node. In some embodiments, the common internal decoding node is to join: the common decoding segment with a first segment of the first decoding path; and the common decoding segment with a second segment of the second decoding path. In some embodiments, the first decoding path and the second decoding path is to have common log-likelihood ratio (LLR) values at the common internal decoding node. In some embodiments, at least a part of the first decoding path is to operate in parallel with at least a part of the second decoding path. In some embodiments, each of the first decoding path and the second decoding path is to decode the channel output that is encoded using polar coding. In some embodiments, the channel output comprises 2n bit codewords; and individual ones of the plurality of decoding paths comprises corresponding individual edges of an n-dimensional hypercube. In some embodiments, the plurality of decoding paths may comprise two or more of factorial of n (n!) number of edges of the n-dimensional hypercube. In some embodiments, the decoder may be implemented using dedicated hardware circuitry and/or using a processor.

[00143] In some embodiments, the reliability ranking 108 may be generated by the computing device 160. In some embodiments, the computing device 160 may comprise one or more processors to: generate an initial reliability ranking, and generate a final reliability ranking based at least in part on the initial reliability ranking, the final reliability ranking associated with encoding codewords using polar code that is to be decoded with a multi-path decoder; and a memory to store one or both of: the initial reliability ranking or the final reliability ranking. In some embodiments, the initial reliability ranking is generated for a first decoding path; and the multi-path decoder comprises at least a second decoding path and a third decoding path that are different from the first decoding path. In some embodiments, a first factor is to translate the second decoding path to the first decoding path; a second factor is to translate the third decoding path to the first decoding path; and the one or more processors are to generate the final reliability ranking based at least in part on the initial reliability ranking, the first factor, and the second factor. In some embodiments, to generate the final reliability ranking, the one or more processors are to: access a first ranking and a second ranking of the initial reliability ranking; estimate a first modified ranking and a second modified ranking respectively from the first ranking and the second ranking, based at least in part on respectively the first factor and the second factor; and generate the final reliability ranking, based at least in part on the first modified ranking and the second modified ranking. In some embodiments, a transmitter is to encode data in accordance with polar coding, based at least in part on the final reliability ranking. In some embodiments, a receiver comprising the multi-path decoder is to decode data, based at least in part on the final reliability ranking. In some embodiments, a UE device may comprise an application processor, a memory, one or more antennas, a wireless interface for allowing the application processor to communicate with another device, and a touch-screen display, the UE device including: an encoder to: receive input data, and generate a code word using polar coding, based at least in part on the final reliability ranking. In some embodiments, an eNB device may comprise an application processor, a memory, one or more antennas, and a wireless interface for allowing the application processor to communicate with another device, the eNB device including: an encoder to: receive input data, and generate a code word using polar coding, based at least in part on the final reliability ranking. In some embodiments, a UE device may comprise an application processor, a memory, one or more antennas, a wireless interface for allowing the application processor to communicate with another device, and a touch-screen display, the UE device including: the multi-path decoder to decode data, based at least in part on the final reliability ranking. In some embodiments, an eNB device may comprise an application processor, a memory, one or more antennas, and a wireless interface for allowing the application processor to communicate with another device, the eNB device including: the multi-path decoder to decode data, based at least in part on the final reliability ranking.

[00144] Fig. 15 illustrates a method 1500 for a receiver (e.g., receiver 130 of Fig. 1) to decode polar encoded codewords using multi-path decoder, according to some embodiments. With reference to Fig. 12, the method 1500 may relate to the eNB 1210 acting as a receiver, or to the UE 1230 acting as a receiver. Although the actions in method 1500 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions may be performed in parallel. Some of the actions and/or operations listed in Fig. 15 are optional in accordance with certain embodiments. The numbering of the actions presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various actions must occur.

Additionally, operations from the various flows may be utilized in a variety of combinations.

[00145] Moreover, in some embodiments, machine readable storage media may have executable instructions that, when executed, cause eNB 1210 and/or hardware processing circuitry 1220 (or UE 1230 and/or hardware processing circuitry 1240) to perform an operation comprising the method of Fig. 15. Such machine readable storage media may include any of a variety of storage media, like magnetic storage media (e.g., magnetic tapes or magnetic disks), optical storage media (e.g., optical discs), electronic storage media (e.g., conventional hard disk drives, solid-state disk drives, or flash-memory -based storage media), or any other tangible storage media or non-transitory storage media.

[00146] In some embodiments, an apparatus may comprise means for performing various actions and/or operations of the method 1500 of Fig. 15.

[00147] Returning to Fig. 15, the method 1500 may be in accordance with the various embodiments discussed herein. The method 1500 may comprise, at 1504, accessing output data received over a wireless channel (e.g., channel 128). The method 1500 may comprise, at 1508, decoding the output data using a plurality of decoding paths, wherein a first decoding path and a second decoding path comprises a common internal decoding node. In some embodiments, the common internal decoding node is to join: a first segment and a second segment of the first decoding path; and a third segment and a fourth segment of the second decoding path. In some embodiments, the first segment of the first decoding path and the third segment of the second decoding path is implemented using a common segment that is included in both the first decoding path and the second decoding path. In some

embodiments, the first decoding path and the second decoding path is to have common log- likelihood ratio (LLR) values at the common internal decoding node. In some embodiments, the first decoding path and the second decoding path comprises a common decoding segment. In some embodiments, the common decoding segment comprises: one or more first nodes to perform corresponding one or more check node operations; and one or more second nodes to perform corresponding one or more variable node operations. In some embodiments, the method may further comprise operating at least a part of the first decoding path in parallel with at least a part of the second decoding path. In some embodiments, each of the first decoding path and the second decoding path is to decode the output data that is encoded using polar coding. In some embodiments, the output data comprises 2n bit codewords; and individual ones of the plurality of decoding paths comprises corresponding individual edges of an n-dimensional hypercube. In some embodiments, the plurality of decoding paths comprises two or more of factorial of n (n! ) number of edges of the n-dimensional hypercube. In some embodiments, the output data is received over the wireless channel from one of a User Equipment (UE) device or an Evolved Node B (eNB) device. In some embodiments,

[00148] Fig. 16 illustrates a method 1600 for a computing device (e.g., computing device 160) to generate a final reliability ranking (e.g., reliability ranking 108), according to some embodiments. With reference to Fig. 1, the method 1600 may relate to the computing device 160. Although the actions in method 1600 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions may be performed in parallel. Some of the actions and/or operations listed in Fig. 16 are optional in accordance with certain embodiments. The numbering of the actions presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various actions must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

[00149] Moreover, in some embodiments, machine readable storage media may have executable instructions that, when executed, cause the computing device 160 to perform an operation comprising the method of Fig. 16. Such machine readable storage media may include any of a variety of storage media, like magnetic storage media (e.g., magnetic tapes or magnetic disks), optical storage media (e.g., optical discs), electronic storage media (e.g., conventional hard disk drives, solid-state disk drives, or flash-memory -based storage media), or any other tangible storage media or non-transitory storage media.

[00150] In some embodiments, an apparatus may comprise means for performing various actions and/or operations of the method 1500 of Fig. 16.

[00151] Returning to Fig. 16, the method 1600 may be in accordance with the various embodiments discussed herein. The method 1600 may comprise, at 1604, generating an initial reliability ranking (e.g., initial reliability ranking discussed previously herein with respect to algorithm 1). The method 1600 may comprise, at 1608, generating a final reliability ranking based at least in part on the initial reliability ranking, the final reliability ranking associated with encoding codewords using polar code that is to be decoded with a multi-path decoder. In some embodiments, a memory of the computing device 160 may store one or both of: the initial reliability ranking or the final reliability ranking. In some embodiments, the initial reliability ranking is generated for a first decoding path; and the multi-path decoder comprises at least a second decoding path and a third decoding path that are different from the first decoding path. In some embodiments, a first factor is to translate the second decoding path to the first decoding path, and a second factor is to translate the third decoding path to the first decoding path, and wherein to generate the final reliability ranking, the method comprises: generating the final reliability ranking based at least in part on the initial reliability ranking, the first factor, and the second factor. In some embodiments, to generate the final reliability ranking, the method comprises: accessing a first ranking and a second ranking of the initial reliability ranking; estimating a first modified ranking and a second modified ranking respectively from the first ranking and the second ranking, based at least in part on respectively the first factor and the second factor; and generating the final reliability ranking, based at least in part on the first modified ranking and the second modified ranking. In some embodiments, a transmitter is to encode data in accordance with polar coding, based at least in part on the final reliability ranking. In some embodiments, a receiver comprising the multi-path decoder is to decode data, based at least in part on the final reliability ranking.

[00152] Fig. 17 illustrates an architecture of a system 1700 of a network, according to some embodiments. The system 1700 is shown to include a user equipment (UE) 1701 and a UE 1702. The UEs 1701 and 1702 are illustrated as smartphones (e.g., handheld touchscreen mobile computing devices connectable to one or more cellular networks), but may also comprise any mobile or non-mobile computing device, such as Personal Data Assistants (PDAs), pagers, laptop computers, desktop computers, wireless handsets, or any computing device including a wireless communications interface.

[00153] In some embodiments, any of the UEs 1701 and 1702 can comprise an Internet of Things (IoT) UE, which can comprise a network access layer designed for low-power IoT applications utilizing short-lived UE connections. An IoT UE can utilize technologies such as machine-to-machine (M2M) or machine-type communications (MTC) for exchanging data with an MTC server or device via a public land mobile network (PLMN), Proximity -Based Service (ProSe) or device-to-device (D2D) communication, sensor networks, or IoT networks. The M2M or MTC exchange of data may be a machine-initiated exchange of data. An IoT network describes interconnecting IoT UEs, which may include uniquely identifiable embedded computing devices (within the Internet infrastructure), with short-lived

connections. The IoT UEs may execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate the connections of the IoT network.

[00154] The UEs 1701 and 1702 may be configured to connect, e.g., communicatively couple, with a radio access network (RAN)— in this embodiment, an Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN) 1710. The UEs 1701 and 1702 utilize connections 1703 and 1704, respectively, each of which comprises a physical communications interface or layer (discussed in further detail below); in this example, the connections 1703 and 1704 are illustrated as an air interface to enable communicative coupling, and can be consistent with cellular communications protocols, such as a Global System for Mobile Communications (GSM) protocol, a code- division multiple access (CDMA) network protocol, a Push-to-Talk (PTT) protocol, a PTT over Cellular (POC) protocol, a Universal Mobile Telecommunications System (UMTS) protocol, a 3GPP Long Term Evolution (LTE) protocol, a fifth generation (5G) protocol, a New Radio (NR) protocol, and the like.

[00155] In this embodiment, the UEs 1701 and 1702 may further directly exchange communication data via a ProSe interface 1705. The ProSe interface 1705 may alternatively be referred to as a sidelink interface comprising one or more logical channels, including but not limited to a Physical Sidelink Control Channel (PSCCH), a Physical Sidelink Shared Channel (PSSCH), a Physical Sidelink Discovery Channel (PSDCH), and a Physical Sidelink Broadcast Channel (PSBCH).

[00156] The UE 1702 is shown to be configured to access an access point (AP) 1706 via connection 1707. The connection 1707 can comprise a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, wherein the AP 1706 would comprise a wireless fidelity (WiFi®) router. In this example, the AP 1706 is shown to be connected to the Internet without connecting to the core network of the wireless system (described in further detail below).

[00157] The E-UTRAN 1710 can include one or more access nodes that enable the connections 1703 and 1704. These access nodes (ANs) can be referred to as base stations (BSs), NodeBs, evolved NodeBs (eNBs), next Generation NodeBs (gNB), RAN nodes, and so forth, and can comprise ground stations (e.g., terrestrial access points) or satellite stations providing coverage within a geographic area (e.g., a cell). The E-UTRAN 1710 may include one or more RAN nodes for providing macrocells, e.g., macro RAN node 1711, and one or more RAN nodes for providing femtocells or picocells (e.g., cells having smaller coverage areas, smaller user capacity, or higher bandwidth compared to macrocells), e.g., low power (LP) RAN node 1712.

[00158] Any of the RAN nodes 1711 and 1712 can terminate the air interface protocol and can be the first point of contact for the UEs 1701 and 1702. In some embodiments, any of the RAN nodes 1711 and 1712 can fulfill various logical functions for the E-UTRAN 1710 including, but not limited to, radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

[00159] In accordance with some embodiments, the UEs 1701 and 1702 can be configured to communicate using Orthogonal Frequency-Division Multiplexing (OFDM) communication signals with each other or with any of the RAN nodes 1711 and 1712 over a multicarrier communication channel in accordance various communication techniques, such as, but not limited to, an Orthogonal Frequency-Division Multiple Access (OFDMA) communication technique (e.g., for downlink communications) or a Single Carrier Frequency Division Multiple Access (SC-FDMA) communication technique (e.g., for uplink and ProSe or sidelink communications), although the scope of the embodiments is not limited in this respect. The OFDM signals can comprise a plurality of orthogonal subcarriers.

[00160] In some embodiments, a downlink resource grid can be used for downlink transmissions from any of the RAN nodes 1711 and 1712 to the UEs 1701 and 1702, while uplink transmissions can utilize similar techniques. The grid can be a time-frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot. Such a time-frequency plane representation is a common practice for OFDM systems, which makes it intuitive for radio resource allocation. Each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to one slot in a radio frame. The smallest time-frequency unit in a resource grid is denoted as a resource element. Each resource grid comprises a number of resource blocks, which describe the mapping of certain physical channels to resource elements. Each resource block comprises a collection of resource elements; in the frequency domain, this may represent the smallest quantity of resources that currently can be allocated. There are several different physical downlink channels that are conveyed using such resource blocks.

[00161] The physical downlink shared channel (PDSCH) may carry user data and higher-layer signaling to the UEs 1701 and 1702. The physical downlink control channel (PDCCH) may carry information about the transport format and resource allocations related to the PDSCH channel, among other things. It may also inform the UEs 1701 and 1702 about the transport format, resource allocation, and H-ARQ (Hybrid Automatic Repeat Request) information related to the uplink shared channel. Typically, downlink scheduling (assigning control and shared channel resource blocks to the UE 102 within a cell) may be performed at any of the RAN nodes 1711 and 1712 based on channel quality information fed back from any of the UEs 1701 and 1702. The downlink resource assignment information may be sent on the PDCCH used for (e.g., assigned to) each of the UEs 1701 and 1702.

[00162] The PDCCH may use control channel elements (CCEs) to convey the control information. Before being mapped to resource elements, the PDCCH complex-valued symbols may first be organized into quadruplets, which may then be permuted using a sub- block interleaver for rate matching. Each PDCCH may be transmitted using one or more of these CCEs, where each CCE may correspond to nine sets of four physical resource elements known as resource element groups (REGs). Four Quadrature Phase Shift Keying (QPSK) symbols may be mapped to each REG. The PDCCH can be transmitted using one or more CCEs, depending on the size of the downlink control information (DCI) and the channel condition. There can be four or more different PDCCH formats defined in LTE with different numbers of CCEs (e.g., aggregation level, L=l, 2, 4, or 8).

[00163] Some embodiments may use concepts for resource allocation for control channel information that are an extension of the above-described concepts. For example, some embodiments may utilize an enhanced physical downlink control channel (EPDCCH) that uses PDSCH resources for control information transmission. The EPDCCH may be transmitted using one or more enhanced the control channel elements (ECCEs). Similar to above, each ECCE may correspond to nine sets of four physical resource elements known as an enhanced resource element groups (EREGs). An ECCE may have other numbers of EREGs in some situations.

[00164] The E-UTRAN 1710 is shown to be communicatively coupled to a core network— in this embodiment, an Evolved Packet Core (EPC) network 1720 via an S I interface 1713. In this embodiment the SI interface 1713 is split into two parts: the S l-U interface 1714, which carries traffic data between the RAN nodes 1711 and 1712 and the serving gateway (S-GW) 1722, and the SI -mobility management entity (MME) interface 1715, which is a signaling interface between the RAN nodes 1711 and 1712 and MMEs 1721.

[00165] In this embodiment, the EPC network 1720 comprises the MMEs 1721, the S-

GW 1722, the Packet Data Network (PDN) Gateway (P-GW) 1723, and a home subscriber server (HSS) 1724. The MMEs 1721 may be similar in function to the control plane of legacy Serving General Packet Radio Service (GPRS) Support Nodes (SGSN). The MMEs 1721 may manage mobility aspects in access such as gateway selection and tracking area list management. The HSS 1724 may comprise a database for network users, including subscription-related information to support the network entities' handling of communication sessions. The EPC network 1720 may comprise one or several HSSs 1724, depending on the number of mobile subscribers, on the capacity of the equipment, on the organization of the network, etc. For example, the HSS 1724 can provide support for routing/roaming, authentication, authorization, naming/addressing resolution, location dependencies, etc.

[00166] The S-GW 1722 may terminate the SI interface 1713 towards the E-UTRAN

1710, and routes data packets between the E-UTRAN 1710 and the EPC network 1720. In addition, the S-GW 1722 may be a local mobility anchor point for inter-RAN node handovers and also may provide an anchor for inter-3GPP mobility. Other responsibilities may include lawful intercept, charging, and some policy enforcement.

[00167] The P-GW 1723 may terminate an SGi interface toward a PDN. The P-GW

1723 may route data packets between the EPC network 1723 and external networks such as a network including the application server 1730 (alternatively referred to as application function (AF)) via an Internet Protocol (IP) interface 1725. Generally, the application server 1730 may be an element offering applications that use IP bearer resources with the core network (e.g., UMTS Packet Services (PS) domain, LTE PS data services, etc.). In this embodiment, the P-GW 1723 is shown to be communicatively coupled to an application server 1730 via an IP communications interface 1725. The application server 1730 can also be configured to support one or more communication services (e.g., Voice-over-Internet Protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) for the UEs 1701 and 1702 via the EPC network 1720.

[00168] The P-GW 1723 may further be a node for policy enforcement and charging data collection. Policy and Charging Enforcement Function (PCRF) 1726 is the policy and charging control element of the EPC network 1720. In a non-roaming scenario, there may be a single PCRF in the Home Public Land Mobile Network (HPLMN) associated with a UE's Internet Protocol Connectivity Access Network (IP-CAN) session. In a roaming scenario with local breakout of traffic, there may be two PCRFs associated with a UE's IP-CAN session: a Home PCRF (H-PCRF) within a HPLMN and a Visited PCRF (V-PCRF) within a Visited Public Land Mobile Network (VPLMN). The PCRF 1726 may be communicatively coupled to the application server 1730 via the P-GW 1723. The application server 1730 may signal the PCRF 1726 to indicate a new service flow and select the appropriate Quality of Service (QoS) and charging parameters. The PCRF 1726 may provision this rule into a Policy and Charging Enforcement Function (PCEF) (not shown) with the appropriate traffic flow template (TFT) and QoS class of identifier (QCI), which commences the QoS and charging as specified by the application server 1730.

[00169] Fig. 18 illustrates example components of a device 1800, according to some embodiments. In some embodiments, the device 1800 may include application circuitry 1802, baseband circuitry 1804, Radio Frequency (RF) circuitry 1806, front-end module (FEM) circuitry 1808, one or more antennas 1810, and power management circuitry (PMC) 1812 coupled together at least as shown. The components of the illustrated device 1800 may be included in a UE or a RAN node. In some embodiments, the device 1800 may include less elements (e.g., a RAN node may not utilize application circuitry 1802, and instead include a processor/controller to process IP data received from an EPC). In some embodiments, the device 1800 may include additional elements such as, for example, memory /storage, display, camera, sensor, or input/output (I/O) interface. In other embodiments, the components described below may be included in more than one device (e.g., said circuitries may be separately included in more than one device for Cloud-RAN (C-RAN) implementations).

[00170] The application circuitry 1802 may include one or more application processors. For example, the application circuitry 1802 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.). The processors may be coupled with or may include memory /storage and may be configured to execute instructions stored in the memory /storage to enable various applications or operating systems to run on the device 1800. In some embodiments, processors of application circuitry 1802 may process IP data packets received from an EPC.

[00171] The baseband circuitry 1804 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The baseband circuitry 1804 may include one or more baseband processors or control logic to process baseband signals received from a receive signal path of the RF circuitry 1806 and to generate baseband signals for a transmit signal path of the RF circuitry 1806. Baseband processing circuity 1804 may interface with the application circuitry 1802 for generation and processing of the baseband signals and for controlling operations of the RF circuitry 1806. For example, in some embodiments, the baseband circuitry 1804 may include a third generation (3G) baseband processor 1804A, a fourth generation (4G) baseband processor 1804B, a fifth generation (5G) baseband processor 1804C, or other baseband processor(s) 1804D for other existing generations, generations in development or to be developed in the future (e.g., second generation (2G), sixth generation (6G), etc.). The baseband circuitry 1804 (e.g., one or more of baseband processors 1804A-D) may handle various radio control functions that enable communication with one or more radio networks via the RF circuitry 1806. In other embodiments, some or all of the functionality of baseband processors 1804A-D may be included in modules stored in the memory 1804G and executed via a Central Processing Unit (CPU) 1804E. The radio control functions may include, but are not limited to, signal modulation/demodulation,

encoding/decoding, radio frequency shifting, etc. In some embodiments,

modulation/demodulation circuitry of the baseband circuitry 1804 may include Fast-Fourier Transform (FFT), precoding, or constellation mapping/demapping functionality. In some embodiments, encoding/decoding circuitry of the baseband circuitry 1804 may include convolution, tail-biting convolution, turbo, Viterbi, or Low Density Parity Check (LDPC) encoder/decoder functionality. Embodiments of modulation/demodulation and

encoder/decoder functionality are not limited to these examples and may include other suitable functionality in other embodiments.

[00172] In some embodiments, the baseband circuitry 1804 may include one or more audio digital signal processor(s) (DSP) 1804F. The audio DSP(s) 1804F may be include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments. Components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments. In some embodiments, some or all of the constituent components of the baseband circuitry 1804 and the application circuitry 1802 may be implemented together such as, for example, on a system on a chip (SOC).

[00173] In some embodiments, the baseband circuitry 1804 may provide for communication compatible with one or more radio technologies. For example, in some embodiments, the baseband circuitry 1804 may support communication with an evolved universal terrestrial radio access network (EUTRAN) or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), a wireless personal area network (WPAN). Embodiments in which the baseband circuitry 1804 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

[00174] RF circuitry 1806 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuitry 1806 may include switches, filters, amplifiers, etc. to facilitate the communication with the wireless network. RF circuitry 1806 may include a receive signal path which may include circuitry to down-convert RF signals received from the FEM circuitry 1808 and provide baseband signals to the baseband circuitry 1804. RF circuitry 1806 may also include a transmit signal path which may include circuitry to up-convert baseband signals provided by the baseband circuitry 1804 and provide RF output signals to the FEM circuitry 1808 for transmission.

[00175] In some embodiments, the receive signal path of the RF circuitry 1806 may include mixer circuitry 1806a, amplifier circuitry 1806b and filter circuitry 1806c. In some embodiments, the transmit signal path of the RF circuitry 1806 may include filter circuitry 1806c and mixer circuitry 1806a. RF circuitry 1806 may also include synthesizer circuitry 1806d for synthesizing a frequency for use by the mixer circuitry 1806a of the receive signal path and the transmit signal path. In some embodiments, the mixer circuitry 1806a of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 1808 based on the synthesized frequency provided by synthesizer circuitry 1806d. The amplifier circuitry 1806b may be configured to amplify the down-converted signals and the filter circuitry 1806c may be a low-pass filter (LPF) or band-pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals. Output baseband signals may be provided to the baseband circuitry 1804 for further processing. In some embodiments, the output baseband signals may be zero-frequency baseband signals, although this is not a requirement. In some embodiments, mixer circuitry 1806a of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.

[00176] In some embodiments, the mixer circuitry 1806a of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 1806d to generate RF output signals for the FEM circuitry 1808. The baseband signals may be provided by the baseband circuitry 1804 and may be filtered by filter circuitry 1806c.

[00177] In some embodiments, the mixer circuitry 1806a of the receive signal path and the mixer circuitry 1806a of the transmit signal path may include two or more mixers and may be arranged for quadrature downconversion and upconversion, respectively. In some embodiments, the mixer circuitry 1806a of the receive signal path and the mixer circuitry 1806a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuitry 1806a of the receive signal path and the mixer circuitry 1806a may be arranged for direct downconversion and direct upconversion, respectively. In some embodiments, the mixer circuitry 1806a of the receive signal path and the mixer circuitry 1806a of the transmit signal path may be configured for super-heterodyne operation.

[00178] In some embodiments, the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternate embodiments, the output baseband signals and the input baseband signals may be digital baseband signals. In these alternate embodiments, the RF circuitry 1806 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry and the baseband circuitry 1804 may include a digital baseband interface to communicate with the RF circuitry 1806. [00179] In some dual-mode embodiments, a separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.

[00180] In some embodiments, the synthesizer circuitry 1806d may be a fractional-N synthesizer or a fractional N/N+l synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable. For example, synthesizer circuitry 1806d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider.

[00181] The synthesizer circuitry 1806d may be configured to synthesize an output frequency for use by the mixer circuitry 1806a of the RF circuitry 1806 based on a frequency input and a divider control input. In some embodiments, the synthesizer circuitry 1806d may be a fractional N/N+l synthesizer.

[00182] In some embodiments, frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a requirement. Divider control input may be provided by either the baseband circuitry 1804 or the applications processor 1802 depending on the desired output frequency. In some embodiments, a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the applications processor 1802.

[00183] Synthesizer circuitry 1806d of the RF circuitry 1806 may include a divider, a delay-locked loop (DLL), a multiplexer and a phase accumulator. In some embodiments, the divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DP A). In some embodiments, the DMD may be configured to divide the input signal by either N or N+l (e.g., based on a carry out) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded, tunable, delay elements, a phase detector, a charge pump and a D-type flip-flop. In these embodiments, the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

[00184] In some embodiments, synthesizer circuitry 1806d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other. In some embodiments, the output frequency may be a LO frequency (fLO). In some embodiments, the RF circuitry 1806 may include an IQ/polar converter.

[00185] FEM circuitry 1808 may include a receive signal path which may include circuitry configured to operate on RF signals received from one or more antennas 1810, amplify the received signals and provide the amplified versions of the received signals to the RF circuitry 1806 for further processing. FEM circuitry 1808 may also include a transmit signal path which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 1806 for transmission by one or more of the one or more antennas 1810. In various embodiments, the amplification through the transmit or receive signal paths may be done solely in the RF circuitry 1806, solely in the FEM 1808, or in both the RF circuitry 1806 and the FEM 1808.

[00186] In some embodiments, the FEM circuitry 1808 may include a TX/RX switch to switch between transmit mode and receive mode operation. The FEM circuitry may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry may include an LNA to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 1806). The transmit signal path of the FEM circuitry 1808 may include a power amplifier (PA) to amplify input RF signals (e.g., provided by RF circuitry 1806), and one or more filters to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas 1810).

[00187] In some embodiments, the PMC 1812 may manage power provided to the baseband circuitry 1804. In particular, the PMC 1812 may control power-source selection, voltage scaling, battery charging, or DC-to-DC conversion. The PMC 1812 may often be included when the device 1800 is capable of being powered by a battery, for example, when the device is included in a UE. The PMC 1812 may increase the power conversion efficiency while providing desirable implementation size and heat dissipation characteristics.

[00188] While Fig. 18 shows the PMC 1812 coupled only with the baseband circuitry 1804. However, in other embodiments, the PMC 18 12 may be additionally or alternatively coupled with, and perform similar power management operations for, other components such as, but not limited to, application circuitry 1802, RF circuitry 1806, or FEM 1808.

[00189] In some embodiments, the PMC 1812 may control, or otherwise be part of, various power saving mechanisms of the device 1800. For example, if the device 1800 is in an RRC_Connected state, where it is still connected to the RAN node as it expects to receive traffic shortly, then it may enter a state known as Discontinuous Reception Mode (DRX) after a period of inactivity. During this state, the device 1800 may power down for brief intervals of time and thus save power.

[00190] If there is no data traffic activity for an extended period of time, then the device 1800 may transition off to an RRC Idle state, where it disconnects from the network and does not perform operations such as channel quality feedback, handover, etc. The device 1800 goes into a very low power state and it performs paging where again it periodically wakes up to listen to the network and then powers down again. The device 1800 may not receive data in this state, in order to receive data, it must transition back to RRC Connected state.

[00191] An additional power saving mode may allow a device to be unavailable to the network for periods longer than a paging interval (ranging from seconds to a few hours). During this time, the device is totally unreachable to the network and may power down completely. Any data sent during this time incurs a large delay and it is assumed the delay is acceptable.

[00192] Processors of the application circuitry 1802 and processors of the baseband circuitry 1804 may be used to execute elements of one or more instances of a protocol stack. For example, processors of the baseband circuitry 1804, alone or in combination, may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of the application circuitry 1804 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers). As referred to herein, Layer 3 may comprise a radio resource control (RRC) layer, described in further detail below. As referred to herein, Layer 2 may comprise a medium access control (MAC) layer, a radio link control (RLC) layer, and a packet data convergence protocol (PDCP) layer, described in further detail below. As referred to herein, Layer 1 may comprise a physical (PHY) layer of a UE/RAN node, described in further detail below.

[00193] Fig. 19 illustrates example interfaces of baseband circuitry, according to some embodiments. As discussed above, the baseband circuitry 1804 of FIG. 18 may comprise processors 1804A-1804E and a memory 1804G utilized by said processors. Each of the processors 1804A-1804E may include a memory interface, 1904A-1904E, respectively, to send/receive data to/from the memory 1804G.

[00194] The baseband circuitry 1804 may further include one or more interfaces to communicatively couple to other circuitries/devices, such as a memory interface 1912 (e.g., an interface to send/receive data to/from memory extemal to the baseband circuitry 1804), an application circuitry interface 1914 (e.g., an interface to send/receive data to/from the application circuitry 1802 of FIG. 18), an RF circuitry interface 1916 (e.g., an interface to send/receive data to/from RF circuitry 1806 of FIG. 18), a wireless hardware connectivity interface 1918 (e.g., an interface to send/receive data to/from Near Field Communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components), and a power management interface 1920 (e.g., an interface to send/receive power or control signals to/from the PMC 1812.

[00195] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[00196] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00197] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures e.g., Dynamic RAM (DRAM) may use the

embodiments discussed. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00198] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00199] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00200] Example 1. An apparatus comprising: an interface to receive a channel output; and a decoder to decode the channel output, the decoder comprising a plurality of decoding paths, wherein a first decoding path of the plurality of decoding paths and a second decoding path of the plurality of decoding paths comprise a common decoding segment.

[00201] Example 2. The apparatus of example 1 or any other example, wherein the common decoding segment comprises: one or more first nodes to perform one or more respectively corresponding check node operations of the decoder; and one or more second nodes to perform one or more respectively corresponding variable node operations of the decoder.

[00202] Example 3. The apparatus of example 1 or any other example, wherein the first decoding path and the second decoding path comprise a common internal decoding node.

[00203] Example 4. The apparatus of example 3 or any other example, wherein the common internal decoding node is to join: the common decoding segment with a first segment of the first decoding path; and the common decoding segment with a second segment of the second decoding path.

[00204] Example 5. The apparatus of example 3 or any other example, wherein the first decoding path and the second decoding path have common log-likelihood ratio (LLR) values at the common internal decoding node.

[00205] Example 6. The apparatus of any of examples 1 -5 or any other example, wherein at least a part of the first decoding path is to operate in parallel with at least a part of the second decoding path.

[00206] Example 7. The apparatus of any of examples 1 -5 or any other example, wherein each of the first decoding path and the second decoding path is to decode the channel output, and wherein the channel output is encoded using polar coding. [00207] Example 8. The apparatus of any of examples 1 -5 or any other example, wherein: the channel output carries codewords having 2n bits; and individual decoding paths of the plurality of decoding paths respectively correspond with individual edges of an n- dimensional hypercube.

[00208] Example 9. The apparatus of example 8 or any other example, wherein: the plurality of decoding paths comprise two or more of a factorial-of-n (n!) number of edges of the n-dimensional hypercube.

[00209] Example 10. The apparatus of any of examples 1-5 or any other example, further comprising: a processor including the decoder.

[00210] Example 11. A User Equipment (UE) device comprising an application processor, a memory, one or more antennas, a wireless interface for allowing the application processor to communicate with another device, and a touch-screen display, the UE device including the apparatus of any of examples 1 through 9 or any other example.

[00211] Example 12. An Evolved Node B (eNB) device comprising an application processor, a memory, one or more antennas, and a wireless interface for allowing the application processor to communicate with another device, the eNB device including the apparatus of any of examples 1 through 9 or any other example.

[00212] Example 13. Machine readable storage media having machine executable instructions that, when executed, cause one or more processors to perform an operation comprising: access output data received over a wireless channel; and decode the output data using a plurality of decoding paths, wherein a first decoding path of the plurality of decoding paths and a second decoding path of the plurality of decoding paths comprise a common internal decoding node.

[00213] Example 14. The machine readable storage media of example 13 or any other example, wherein the common internal decoding node is to join: a first segment and a second segment of the first decoding path; and a third segment and a fourth segment of the second decoding path.

[00214] Example 15. The machine readable storage media of example 14 or any other example, wherein the first segment of the first decoding path and the third segment of the second decoding path are implemented using a common segment that is included in both the first decoding path and the second decoding path.

[00215] Example 16. The machine readable storage media of example 13 or any other example, wherein the first decoding path and the second decoding path are to have common log-likelihood ratio (LLR) values at the common internal decoding node. [00216] Example 17. The machine readable storage media of example 13 or any other example, wherein the first decoding path and the second decoding path comprise a common decoding segment.

[00217] Example 18. The machine readable storage media of example 17 or any other example, wherein the common decoding segment comprises: one or more first nodes to perform one or more respectively corresponding check node operations of the decoder; and one or more second nodes to perform one or more respectively corresponding variable node operations of the decoder.

[00218] Example 19. The machine readable storage media of any of examples 13-18 or any other example, wherein the operation comprises: operate at least a part of the first decoding path in parallel with at least a part of the second decoding path.

[00219] Example 20. The machine readable storage media of any of examples 13-18 or any other example, wherein each of the first decoding path and the second decoding path is to decode the output data, and wherein the output data is encoded using polar coding.

[00220] Example 21. The machine readable storage media of any of examples 13-18 or any other example, wherein: the output data carries codewords having 2n bits; and individual decoding paths of the plurality of decoding paths respectively correspond with edges of an n-dimensional hypercube.

[00221] Example 22. The machine readable storage media of example 21 or any other example, wherein: the plurality of decoding paths comprise two or more of a factorial -of-n (n!) number of edges of the n-dimensional hypercube.

[00222] Example 23. The machine readable storage media of any of examples 13-18 or any other example, wherein: the output data is received over the wireless channel from one of a User Equipment (UE) device or an Evolved Node B (eNB) device.

[00223] Example 24. An apparatus comprising: one or more processors to: generate an initial reliability ranking, and generate a final reliability ranking based at least in part on the initial reliability ranking, the final reliability ranking to be used for encoding codewords using polar code that is to be decoded with a multi-path decoder; and a memory to store one or both of: the initial reliability ranking or the final reliability ranking.

[00224] Example 25. The apparatus of example 24 or any other example, wherein: the initial reliability ranking is generated for a first decoding path; and the multi-path decoder comprises at least a second decoding path and a third decoding path that are different from the first decoding path. [00225] Example 26. The apparatus of example 25 or any other example, wherein: a first factor is to translate the second decoding path to the first decoding path; a second factor is to translate the third decoding path to the first decoding path; and the one or more processors are to generate the final reliability ranking based at least in part on the initial reliability ranking, the first factor, and the second factor.

[00226] Example 27. The apparatus of example 26 or any other example, wherein to generate the final reliability ranking, the one or more processors are to: access a first ranking and a second ranking of the initial reliability ranking; estimate a first modified ranking and a second modified ranking respectively from the first ranking and the second ranking, based at least in part on the first factor and the second factor, respectively; and generate the final reliability ranking, based at least in part on the first modified ranking and the second modified ranking.

[00227] Example 28. The apparatus of any of examples 24-27 or any other example, wherein: a transmitter is to encode data in accordance with polar coding, based at least in part on the final reliability ranking.

[00228] Example 29. The apparatus of any of examples 24-27 or any other example, wherein: a receiver comprising the multi-path decoder is to decode data, based at least in part on the final reliability ranking.

[00229] Example 30. A User Equipment (UE) device comprising an application processor, a memory, one or more antennas, a wireless interface for allowing the application processor to communicate with another device, and a touch-screen display, the UE device including: an encoder to: receive input data, and generate a codeword using polar coding, based at least in part on the final reliability ranking of any of examples 24 through 29 or any other example.

[00230] Example 31. An Evolved Node B (eNB) device comprising an application processor, a memory, one or more antennas, and a wireless interface for allowing the application processor to communicate with another device, the eNB device including: an encoder to: receive input data, and generate a codeword using polar coding, based at least in part on the final reliability ranking of any of examples 24 through 29 or any other example.

[00231] Example 32. A User Equipment (UE) device comprising an application processor, a memory, one or more antennas, a wireless interface for allowing the application processor to communicate with another device, and a touch-screen display, the UE device including: the multi-path decoder of any of examples 24 through 29, based at least in part on the final reliability ranking. [00232] Example 33. An Evolved Node B (eNB) device comprising an application processor, a memory, one or more antennas, and a wireless interface for allowing the application processor to communicate with another device, the eNB device including: the multi-path decoder of any of examples 24 through 29, based at least in part on the final reliability ranking.

[00233] Example 34. Machine readable storage media having machine executable instructions that, when executed, cause one or more processors to perform an operation comprising: generate an initial reliability ranking; and generate a final reliability ranking based at least in part on the initial reliability ranking, the final reliability ranking to be used for encoding codewords using polar code that is to be decoded with a multi-path decoder.

[00234] Example 35. The machine readable storage media of example 34 or any other example, wherein: the initial reliability ranking is generated for a first decoding path; and the multi-path decoder comprises at least a second decoding path and a third decoding path that are different from the first decoding path.

[00235] Example 36. The machine readable storage media of example 35 or any other example, wherein a first factor is to translate the second decoding path to the first decoding path, and a second factor is to translate the third decoding path to the first decoding path, and wherein to generate the final reliability ranking, the operation comprises: generate the final reliability ranking based at least in part on the initial reliability ranking, the first factor, and the second factor.

[00236] Example 37. The machine readable storage media of example 36 or any other example, wherein to generate the final reliability ranking, the operation comprises: access a first ranking and a second ranking of the initial reliability ranking; estimate a first modified ranking and a second modified ranking respectively from the first ranking and the second ranking, based at least in part on the first factor and the second factor, respectively; and generate the final reliability ranking, based at least in part on the first modified ranking and the second modified ranking.

[00237] Example 38. The machine readable storage media of any of examples 34-37 or any other example, wherein: a transmitter is to encode data in accordance with polar coding, based at least in part on the final reliability ranking.

[00238] Example 39. The machine readable storage media of any of examples 34-37 or any other example, wherein: a receiver comprising the multi-path decoder is to decode data, based at least in part on the final reliability ranking. [00239] Example 40. A method comprising: accessing output data received over a wireless channel; and decoding the output data using a plurality of decoding paths, wherein a first decoding path of the plurality of decoding paths and a second decoding path of the plurality of decoding paths comprise a common internal decoding node.

[00240] Example 41. The method of example 40 or any other example, wherein the common internal decoding node is to join: a first segment and a second segment of the first decoding path; and a third segment and a fourth segment of the second decoding path.

[00241] Example 42. The method of example 41 or any other example, wherein the first segment of the first decoding path and the third segment of the second decoding path are implemented using a common segment that is included in both the first decoding path and the second decoding path.

[00242] Example 43. The method of example 40 or any other example, wherein the first decoding path and the second decoding path are to have common log-likelihood ratio (LLR) values at the common internal decoding node.

[00243] Example 44. The method of example 40 or any other example, wherein the first decoding path and the second decoding path comprise a common decoding segment.

[00244] Example 45. The method of example 44 or any other example, wherein the common decoding segment comprises: one or more first nodes to perform one or more respectively corresponding check node operations of the decoder; and one or more second nodes to perform one or more respectively corresponding variable node operations of the decoder.

[00245] Example 46. The method of any of examples 40-45 or any other example, further comprising: operating at least a part of the first decoding path in parallel with at least a part of the second decoding path, wherein each of the first decoding path and the second decoding path is to decode the output data, and wherein the output data is encoded using polar coding.

[00246] Example 47. The method of any of examples 40-45 or any other example, wherein: the output data carries codewords having 2n bits; and individual decoding paths of the plurality of decoding paths respectively correspond with edges of an n-dimensional hypercube; and wherein the plurality of decoding paths comprise two or more of a factorial- of-n (n!) number of edges of the n-dimensional hypercube.

[00247] Example 48. One or more non-transitory computer-readable storage media to store instructions that, when executed by a processor, cause the processor to execute a method of any of the examples 40-47 or any other example. [00248] Example 49. An apparatus comprising: means for performing the method of any of the examples 40-47 or any other example.

[00249] Example 50. An apparatus comprising: means for accessing output data received over a wireless channel; and means for decoding the output data using a plurality of decoding paths, wherein a first decoding path of the plurality of decoding paths and a second decoding path of the plurality of decoding paths comprise a common internal decoding node.

[00250] Example 51. The apparatus of example 50 or any other example, wherein the common internal decoding node is to join: a first segment and a second segment of the first decoding path; and a third segment and a fourth segment of the second decoding path.

[00251] Example 52. The apparatus of example 51 or any other example, wherein the first segment of the first decoding path and the third segment of the second decoding path are implemented using a common segment that is included in both the first decoding path and the second decoding path.

[00252] Example 53. The apparatus of example 50 or any other example, wherein the first decoding path and the second decoding path are to have common log-likelihood ratio (LLR) values at the common internal decoding node.

[00253] Example 54. The apparatus of example 50 or any other example, wherein the first decoding path and the second decoding path comprise a common decoding segment.

[00254] Example 55. The apparatus of example 54 or any other example, wherein the common decoding segment comprises: one or more first nodes to perform one or more respectively corresponding check node operations of the decoder; and one or more second nodes to perform one or more respectively corresponding variable node operations of the decoder.

[00255] Example 56. The apparatus of any of examples 50-55 or any other example, further comprising: means for operating at least a part of the first decoding path in parallel with at least a part of the second decoding path, wherein each of the first decoding path and the second decoding path is to decode the output data, and wherein the output data is encoded using polar coding.

[00256] Example 57. The apparatus of any of examples 50-55 or any other example, wherein: the output data carries codewords having 2n bits; individual decoding paths of the plurality of decoding paths respectively correspond with edges of an n-dimensional hypercube; and the plurality of decoding paths comprise two or more of a factorial-of-n (n!) number of edges of the n-dimensional hypercube. [00257] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

an interface to receive a channel output; and

a decoder to decode the channel output, the decoder comprising a plurality of decoding paths, wherein a first decoding path of the plurality of decoding paths and a second decoding path of the plurality of decoding paths comprise a common decoding segment.

2. The apparatus of claim 1, wherein the common decoding segment comprises:

one or more first nodes to perform one or more respectively corresponding check node operations of the decoder; and

one or more second nodes to perform one or more respectively corresponding variable node operations of the decoder.

3. The apparatus of claim 1, wherein the first decoding path and the second decoding path comprise a common internal decoding node.

4. The apparatus of claim 3, wherein the common internal decoding node is to join: the common decoding segment with a first segment of the first decoding path; and the common decoding segment with a second segment of the second decoding path.

5. The apparatus of claim 3, wherein the first decoding path and the second decoding path have common log-likelihood ratio (LLR) values at the common internal decoding node.

6. The apparatus of any of claims 1-5, wherein at least a part of the first decoding path is to operate in parallel with at least a part of the second decoding path.

7. The apparatus of any of claims 1-5, wherein each of the first decoding path and the second decoding path is to decode the channel output, and wherein the channel output is encoded using polar coding.

8. The apparatus of any of claims 1-5, wherein:

the channel output carries codewords having 2ⁿ bits; and individual decoding paths of the plurality of decoding paths respectively correspond with individual edges of an n-dimensional hypercube.

9. The apparatus of claim 8, wherein:

the plurality of decoding paths comprise two or more of a factorial-of-n (n! ) number of edges of the n-dimensional hypercube.

10. The apparatus of any of claims 1 -5, further comprising:

a processor including the decoder.

11. A User Equipment (UE) device comprising an application processor, a memory, one or more antennas, a wireless interface for allowing the application processor to communicate with another device, and a touch-screen display, the UE device including the apparatus of any of claims 1 through 9.

12. An Evolved Node B (eNB) device comprising an application processor, a memory, one or more antennas, and a wireless interface for allowing the application processor to communicate with another device, the eNB device including the apparatus of any of claims 1 through 9.

13. Machine readable storage media having machine executable instructions that, when executed, cause one or more processors to perform an operation comprising:

access output data received over a wireless channel; and

decode the output data using a plurality of decoding paths, wherein a first decoding path of the plurality of decoding paths and a second decoding path of the plurality of decoding paths comprise a common internal decoding node.

14. The machine readable storage media of claim 13, wherein the common internal decoding node is to join:

a first segment and a second segment of the first decoding path; and

a third segment and a fourth segment of the second decoding path.

15. The machine readable storage media of claim 14, wherein the first segment of the first decoding path and the third segment of the second decoding path are implemented using a common segment that is included in both the first decoding path and the second decoding path.

16. The machine readable storage media of claim 13, wherein the first decoding path and the second decoding path are to have common log-likelihood ratio (LLR) values at the common internal decoding node.

17. The machine readable storage media of claim 13, wherein the first decoding path and the second decoding path comprise a common decoding segment.

18. The machine readable storage media of claim 17, wherein the common decoding segment comprises:

19. The machine readable storage media of any of claims 13-18, wherein the operation comprises:

operate at least a part of the first decoding path in parallel with at least a part of the second decoding path.

20. The machine readable storage media of any of claims 13-18, wherein each of the first decoding path and the second decoding path is to decode the output data, and wherein the output data is encoded using polar coding.

21. The machine readable storage media of any of claims 13-18, wherein:

the output data carries codewords having 2ⁿ bits; and

individual decoding paths of the plurality of decoding paths respectively correspond with edges of an n-dimensional hypercube.

22. The machine readable storage media of claim 21, wherein:

the plurality of decoding paths comprise two or more of a factorial-of-n (n!) number of edges of the n-dimensional hypercube.

23. An apparatus comprising:

one or more processors to:

generate an initial reliability ranking, and

generate a final reliability ranking based at least in part on the initial reliability ranking, the final reliability ranking to be used for encoding codewords using polar code that is to be decoded with a multi-path decoder; and

a memory to store one or both of: the initial reliability ranking or the final reliability ranking.

24. The apparatus of claim 23, wherein:

the initial reliability ranking is generated for a first decoding path; and

the multi-path decoder comprises at least a second decoding path and a third decoding path that are different from the first decoding path.

25. The apparatus of claim 24, wherein:

a first factor is to translate the second decoding path to the first decoding path;

a second factor is to translate the third decoding path to the first decoding path; and the one or more processors are to generate the final reliability ranking based at least in part on the initial reliability ranking, the first factor, and the second factor.