WO2018111220A1

WO2018111220A1 - Sub-fin junction field effect diode for electrostatic discharge protection

Info

Publication number: WO2018111220A1
Application number: PCT/US2016/066178
Authority: WO
Inventors: Akm A. AHSAN
Original assignee: Intel Corporation
Priority date: 2016-12-12
Filing date: 2016-12-12
Publication date: 2018-06-21

Abstract

An electrostatic discharge (ESD) protection device and methods for manufacturing an ESD protection device are described. The ESD protection device includes a P-doped region that has a graded doping profile that includes a highly P-doped portion, a graded P-doped portion, and a lightly P-doped portion. The ESD protection device further includes an N-doped region that has a graded doping profile that includes a highly N-doped portion, a graded N-doped portion, and a lightly N-doped portion. The highly N-doped portion and the highly P-doped portion both interface with the gate electrode. The lightly P-doped portion interfaces with the lightly N-doped portion to provide a P-N junction that allows the P-doped region and the N-doped region form a diode.

Description

SUB-FIN JUNCTION FIELD EFFECT DIODE FOR ELECTROSTATIC DISCHARGE

PROTECTION

Technical Field

[0001] Electrostatic Discharge (ESD) is the sudden flow of electricity between two charged objects. The sudden flow of electricity can be caused by contact, an electrical short, and/or dielectric breakdown. Often ESD is caused by the buildup of static electricity on one of the objects. However, ESD can also be caused by electrostatic induction. ESD can damage electronic components and can result in degradation and/or failure of the electronic components. Accordingly, systems and methods are needed for protecting against ESD. The present disclosure relates to such systems and methods.

Brief Description of the Drawings

[0002] FIG. 1 is perspective drawing of a fin field effect transistor (FinFET) with an exemplary current ESD protection scheme that includes N+ diffusion/Pwell and P+diffusion/Nwell junctions.

[0003] FIG. 2 is circuit diagram illustrating the input/output (IO) circuit with the standard dual diode ESD protection scheme.

[0004] FIG. 3 is a perspective drawing of a fin field effect transistor (FinFET) that implements the present systems and methods.

[0005] FIG. 4 is circuit diagram illustrating the input/output (IO) circuit with the described ESD protection scheme.

[0006] FIG. 5 is a graph that compares the Current-Voltage characteristics of a conventional N+diff/Pwell ESD diode and the described sub-fin Nwell/Pwell ESD diode.

[0007] FIG. 6 is a perspective diagram illustrating another embodiment of a sub- fin Nwell/Pwell ESD diode. [0008] FIG. 7 illustrates a method for manufacturing a sub-fin Nwell/Pwell ESD diode.

[0009] FIG. 8 depicts a block diagram of a computer system that incorporates the present systems and methods.

Detailed Description

[0010] Electrostatic Discharges (ESD) is a major threat for the reliability of integrated circuits (ICs). New materials in IC fabrication and scaling challenges have increased the sensitivity of ICs to ESD events and degraded the dissipation capability of ESD charge. This poses increasing challenges for design of effective ESD protection schemes.

[001 1] ESD can be a discharge of positive charges, "positive ESD", or a discharge of negative charges, "negative ESD". Positive ESD finds the quickest path to the positive supply voltage (e.g., V_Cc, V_DD, V+, V_s+) while negative ESD finds the quickest path to ground or negative supply voltage (e.g., V_EE, V_SS, V-, V_S-). In either case, ESD is looking for the quickest path or most conductive path. So in general, an ESD protection scheme provides an alternative path for the ESD to pass through that is more conductive than other paths (e.g., through sensitive electronic

components) so that the sensitive electronic components are protected from the ESD. Often this alternate path is provided by a diode ("ESD diode"), which has the benefit of providing a conductive path in only one direction (e.g., the forward direction) while providing isolation in the other direction (e.g., in the reverse direction).

[0012] Current ESD protection schemes use very large (e.g., highly doped) diodes to provide this conductive path. These very large diodes are typically used as non-snapback devices for ESD protection in both planar and trigate technologies. It is appreciated that the level of doping of an ESD diode generally has a direct correlation with the conductivity of the ESD diode. The standard choice of ESD diodes are basically "N+ diffusion/Pwell" and "P+diffusion/Nwell" junctions because they offer high conductivity. An example ESD protection scheme using "N+ diffusion/Pwell" and "P+diffusion/Nwell" junctions is illustrated in FIGS. 1 and 2.

[0013] FIG. 1 is perspective drawing of a fin field effect transistor (FinFET) 100 with an exemplary current ESD protection scheme that includes N+ diffusion/Pwell 165 and P+diffusion/Nwell 145 junctions. A FinFET 100 includes a semiconductor fin 105 that is covered with a gate 1 10. In this case, ten fins 105 are illustrated (with tips identified as 140a-e and 160a-e, for example) and three gates 1 10 are illustrated. Since the FinFET 100 includes three gates 1 10, the FinFET 100 may be referred to as a trigate device. Although, the current ESD protection scheme is shown in connection with a trigate FinFET 100, it is appreciated that the current ESD protection scheme is usable with a variety of gate types and configurations.

[0014] Current ESD protection schemes use a fin 105 doping scheme that results in a plurality of N+ diffusion/Pwell 165 and P+diffusion/Nwell 145 junctions to provide ESD protection. N+ diffusion/Pwell junctions 165 include a highly N doped region N+ 160a-e at the tip of the fin 105, a P doped diffusion region 155 that constitutes most of the fin 105, and a lightly doped Pwell 150 that is below the P doped diffusion region 155 but that extends up at least partially into the fin 105. The junction of the highly N doped region N+ 160 with the P doped diffusion region 155 and Pwell 150 results in a highly doped diode 165, with each fin 105 resulting in a different junction diode. As illustrated, five N+ diff/Pwell junctions result in five N+ diff/Pwell junction diodes 165. The N+ diff/Pwell junction diodes 165 and P+ diff/Nwell junction diodes 145 may be disposed on a lightly P doped substrate (Psub) 125.

[0015] Similarly, P+ diffusion/Nwell junctions 145 include a highly P doped region N+ 140a-e at the tip of the fin 105, an N doped diffusion region 135 that constitutes most of the fin 105, and a lightly doped Nwell 130 that is below the N doped diffusion region 135 but that extends up at least partially into the fin 105. The junction of the highly P doped region P+ 140 with the N doped diffusion region 135 and Nwell 130 results in a highly doped diode 145, with each fin 105 resulting in a different diode. As illustrated, five P+ diff/Nwell junctions result in five P+ diff/Nwell junction diodes 145.

[0016] The highly P doped regions P+ 140a-e and the highly doped N regions N+ 160a-e each interface with the gate 1 10. Connections of the N+ diff/Pwell junction diodes 165 and P+ diff/Nwell junction diodes 145 with the supply or ground are not shown. However, these connections are illustrated in FIG. 2.

[0017] FIG. 2 is circuit diagram illustrating the input/output (IO) circuit 200 with the standard dual diode ESD protection scheme. The IO circuit 200 illustrates the functional circuit resulting from the N+ diff/Pwell junction diodes 165 and P+ diff/Nwell junction diodes 145 as illustrated in FIG. 1 .

[0018] An input gate 205 (e.g., FinFET 100) includes a gate terminal (e.g., gate 1 10), a source terminal and a drain terminal. In one example, the gate 1 10 is coupled to a controller 230 and the input resistance 210 associated with the gate 1 10 is 50 Ohms. In one example, the source terminal is coupled to a supply 215 and the drain terminal is coupled to a ground 220.

[0019] The P+ diff/Nwell junction diodes 145 identified as D2 145a and D4 145b are for positive ESD protection and couple the gate 1 10 to the supply 215, which is clamped high by clamp 225. The N+ diff/Pwell junction diodes 165 identified as D1 165a and D3 165b are for negative ESD protection and couple the gate 1 10 to ground 220. So positive ESD on the gate 1 10 will go through one or both of D2 145a and D4 145b to the supply 215 rather than going through, and potentially

damaging/or destroying, the input gate 205 to get to the supply 215. On the other hand, negative ESD on the gate 1 10 will go through one or both of D1 165a and D3 165b to ground 220 rather than going through, and potentially damaging/or destroying, the input gate 1 10 to get to ground 220. In this way the ESD diodes (e.g., D1 165a, D2 145a, D3 165b, and D4 145b) provide ESD protection to an input gate 205.

[0020] Diodes DJN (N+ diffusion/Psub junction) (e.g., D1 165a and D3 165b) and DJP (P+ diffusion/Nwell junction) (e.g., D2 145a and D4 145b) are typically used to protect internal devices from positive and negative ESD discharges experienced at the IO pad. These diodes are very large (i.e., highly doped) to provide a high conductive current path (that develops very low voltage across them while

discharging high ESD current, for example). However, big size (i.e., highly doped) diodes offer high capacitance & leakage which is not desirable.

[0021] As noted above, conduction of the ESD diodes 145, 165 is an important attribute for ESD diodes because the ESD diodes 145, 165 need to conduct ESD to where it wants to go so that it doesn't go through the sensitive electrical components (e.g., the input gate 210). Current ESD diodes 145, 165 using highly doped junctions (e.g., N+ diff/Pwell and P+ diff/Nwell junctions) to achieve the desired conduction levels. However, highly doped junctions result in high leakage currents. Leakage currents reduce power efficiency. However, as electrical components decrease in size, leakage current presents additional concerns, such as limiting processor performance. It is appreciated that leakage current through conventional ESD protection devices during normal operation mode is a big concern for sub 22 nanometer (nm) technology nodes. [0022] The present disclosure is directed to a non-planar sub-fin (Nwell/Pwell) junction device that offers very low "off-state" leakage current without sacrificing high conductance performance. This is desirable for effective ESD protection and relatively low speed 10 circuits which require low leakage performances.

[0023] The non-planar sub-fin (Nwell/Pwell) achieves the very low "off-state" leakage current in part due to the use of light doping at the N-P junction. Although lighter doping typically has the consequence of reduced conductivity, the introduction of sub-fin doping techniques (i.e., Boron-doped silicate glass (BSG) and

Phosphorus-doped silicate glass (PSG)) and other retro implants change Nwell/Pwell junction characteristics significantly so that Nwell/Pwell junction diodes may be effective ESD protection structures (in planar, non-planar, and trigate FinFET technologies, for example).

[0024] In some embodiments, the non-planar sub-fin (Nwell/Pwell) junction device includes an optional control gate feature. The control gate feature further allows optimization of conductance during ESD event (using field effect techniques, for example). As used herein, sub-fin refers to the N/P junction occurring

below/beneath the fin(s) 105.

[0025] FIG. 3 is a perspective drawing of a fin field effect transistor (FinFET) 300 that implements the present systems and methods. As is illustrated, the described ESD protection scheme includes a single sub-fin Nwell/Pwell junction diode 320. As noted previously, a FinFET 300 includes one or more semiconductor fins 105 that is/are covered with a gate 1 10. In this case, ten fins 105 are illustrated (with tips identified as 315a-e and 335a-e, for example) and three gates 1 10 are illustrated. Since the FinFET 300 includes three gates 1 10, the FinFET 300 may be referred to as a trigate device. Although, the described ESD protection scheme is shown in connection with a trigate FinFET 300, it is appreciated that the described ESD protection scheme is usable with a variety of gate types and configurations.

[0026] Whereas, the current ESD protection schemes uses a plurality of highly doped junctions within the fin 105 the described ESD protection scheme has a different doping scheme that uses a single lightly doped sub-fin junction between the Nwell 305 and the Pwell 325 to provide ESD protection. Both the N side of the junction and the P side of the junction include a varied doping profile, which are discussed in turn below. [0027] The N side of the junction or N region includes a highly N doped region N+ 315a-e, an N graded doping region 310, and a lightly doped Nwell 305. In some embodiments, as illustrated, the N region includes one or more fins 105 that includes the highly N doped region N+ 315a-e at the tip of the fin 105 which interfaces with the N graded doping region 310 that constituting most of the fin 105. The lightly doped Nwell 305 interfaces with the N graded doping region 310 and may extend at least partially up into the fin 105. The N graded doping region 310 may have a graded doping profile that has a higher doping profile in proximity to the highly N doped region N+ 315a-e and a lower doping profile in proximity to the Nwell 305. In one example, the N graded doping region 310 may have an N doping profile that includes a regular/medium N doped portion and a lightly N doped portion. This graded doping profile between the highly N doped region N+ 315a-e, the N graded doping region 310, and the Nwell 305 may provide good conductance into the Nwell 305 while minimizing the level of doping at the actual junction (e.g., sub-fin

Nwell/Pwell junction 320).

[0028] The P side of the junction or P region includes a highly P doped region P+ 335a-e, a P graded doping region 330, and a lightly doped Pwell 325. In some embodiments, as illustrated, the P region includes one or more fins 105 that includes the highly P doped region P+ 335a-e at the tip of the fin 105 which interfaces with the P graded doping region 330 that constituting most of the fin 105. The lightly doped Pwell 325 interfaces with the P graded doping region 330 and may extend at least partially up into the fin 105. The P graded doping region 330 may have a graded doping profile that has a higher doping profile in proximity to the highly P doped region P+ 335a-e and a lower doping profile in proximity to the Pwell 325. In one example, the P graded doping region 330 may have a P doping profile that includes a regular/medium P doped portion and a lightly P doped portion. This graded doping profile between the highly P doped region P+ 335a-e, the P graded doping region 330, and the Pwell 325 may provide good conductance into the Pwell 325 while minimizing the level of doping at the actual junction (e.g., Nwell/Pwell junction 320). Because the (sub-fin) junction is between the Nwell 305 and the Pwell 325 is between two lightly doped regions (e.g., the lightly doped Nwell 305 with the lightly doped Pwell 325), leakage current across the junction (e.g., Nwell/Pwell junction 320) is minimized. [0029] The highly N doped regions N+ 315a-e and the highly P doped regions P+ 335a-e each interface with the gate 1 10. In addition, the gate 1 10 may extend between the fins 105 (e.g., the gate may surround (separated by an insulating layer, for example) at least a portion of the fin 105). As illustrated, the gate 1 10 may extend into the substrate 120 beneath the gate 1 10. As such the portion of the gate 1 10 that extends into the substrate 120 is illustrated with a dotted line 1 10. At least a portion of the highly N doped regions N+ 315a-e and at least a portion of the highly P doped regions P+ 335a-e may extend into the gate 1 10. In some embodiments, at least a portion of the N graded doping region 310 and/or at least a portion of the P graded doping region 330 may also extend into the gate 1 10. The gate 1 10 interfaces with at least the highly N doped region N+ 315a-e and the highly P doped region P+ 335a-e. Thus, the ESD protection is protecting against ESD on the gate 1 10.

[0030] It is appreciated that the ESD diode 320 that is formed by the Nwell 305 / Pwell 325 junction protects against negative ESD. As such, the ESD diode 320 may replace the DJN (N+diff/Pwell junction diodes) illustrated in FIG. 2. In some embodiments, the Nwell 305 and the Pwell 325 may be disposed on a lightly P doped substrate (Psub) 125.

[0031] FIG. 4 is circuit diagram illustrating the input/output (IO) circuit 400 with the described ESD protection scheme. The IO circuit 400 illustrates the functional circuit resulting from the sub-fin Nwell/Pwell junction diodes 320. The sub-fin Nwell/Pwell junction diode 320 (e.g., diodes 320a, 320b) provides protection against negative ESD. Positive EDS protection is provided by D2 405a and D4 405b and are handled separately (using other ESD protection techniques, for example).

[0032] An input gate 205 (e.g., FinFET 100) includes a gate terminal (e.g., gate 1 10), a source terminal and a drain terminal. In one example, the gate 1 10 is coupled to a controller 230 and the input resistance 210 associated with the gate 1 10 is 50 Ohms. In one example, the source terminal is coupled to a supply 215 and the drain terminal is coupled to a ground 220.

[0033] D2 145a and D4 145b are for positive ESD protection and couple the gate 1 10 to the supply 215, which is clamped high by clamp 225. The described sub-fin Nwell/Pwell junction diode 320 identified as D1 320a and D3 320b are for negative ESD protection and couple the gate 1 10 to ground 220. So negative ESD on the gate 1 10 will go through one or both of D1 320a and D3 320b to ground 220 rather than going through, and potentially damaging/or destroying, the input gate 1 10 to get to ground 220. In this way the ESD diodes (e.g., D1 320a and D3 320b) provide ESD protection to an input gate 205.

[0034] With reference back to FIG. 2, the IO circuit 400 replaces the DJN (N+ diffusion/Psub junction) diodes (e.g., D1 165a and D3 165b) with a unique sub-fin (Nwel/Pwell) diode 320. Replacing the DJN (N+ diffusion/Psub junction) diodes (e.g., D1 165a and D3 165b) with a unique sub-fin (Nwel/Pwell) diode 320 offers low leakage benefit without sacrificing high conductance performance.

[0035] FIG. 5 is a graph that compares the Current-Voltage characteristics of a conventional N+diff/Pwell ESD diode 165 and the described sub-fin Nwell/Pwell ESD diode 320. The Current-Voltage characteristics of the conventional N+diff/Pwell ESD diode 165 are marked with gray squares while the Current-Voltage characteristics of the sub-fin Nwell/Pwell ESD diode 320 are marked with black diamonds. It is important to note that when reverse biased (e.g., at negative voltages less than -0.5 volts) the current leakage is reduced 405 from 1 .00E-08 to less than 1 .00E-10 at - 2.25 volts, which is a couple of order in magnitudes improvement of off-state leakage reduction. At the same time, when forward biased (e.g., at positive voltages, the characteristics associated with ESD protection) the sub-fin Nwell/Pwell ESD diode 320 closely matches the performance of the conventional N+diff/Pwell ESD diode 165. In other words, the sub-fin Nwell/Pwell ESD diode 320 shows no significant conductivity degradation.

[0036] Although not shown here, as described below, an optional control gate (gate electrode) may be added to the Nwell 305 and/or the Pwell 325 to increase the effective doping using field effect techniques. It is important to note, that these Current-Voltage characteristics are for 14nm node test chip data for both the conventional N+diff/Pwell ESD diode 165 and the sub-fin Nwell/Pwell ESD diode 320.

[0037] FIG. 6 is a perspective diagram illustrating another embodiment of a sub- fin Nwell/Pwell ESD diode 625. Although the embodiment illustrated in FIG. 6 is different from the embodiment illustrated in FIG. 3, it is appreciated that the sub-fin Nwell/Pwell ESD diode 625 may include many of the features and benefits discussed with respect to sub-fin Nwell/Pwell ESD diode 320 discussed previously.

[0038] As illustrated, the (sub-fin) extended Nwell 605 (which may be an example of an extended version of Nwell 305) and the (sub-fin) Pwell 610 (which may be an example of the Pwell 325) may be in the form of a fin 615 (e.g., fin 105). In one example, there may be a plurality of fins 615, each with an extended Nwell 605, Pwell 610, and Psub 125, as shown. The plurality of fins 615 may be disposed on a substrate 120 an may be separated by insulators 620.

[0039] As discussed previously, the N side of the Nwell/Pwell ESD diode 625 may include a graded doping profile with at least a highly N doped region N+ 640 and a lightly N doped extended Nwell 605. Similarly, the P side of the Nwell/Pwell ESD diode 625 may include a graded doping profile with at least a highly P doped region P+ 655 and a lightly P doped Pwell 610. Although not shown, in some cases, there may be respective N and P graded doping regions (as discussed with respect to FIG. 3, for example) to reduce capacitance associated with stark doping changes.

[0040] The extend Nwell 605 interfaces with the Pwell 610 to form a lightly doped N/P junction between an N region that includes the extended Nwell 605 and the highly N doped region N+ 640 and the P region that includes the Pwell 610 and the highly P doped region P+ 655. As discussed above, this Nwell/Pwell junction 625 may lower off-state leakage (as compared with conventional ESD diodes, for example) without degrading conductivity.

[0041] It is appreciated that the lightly doped Nwell/Pwell junction (e.g., 320, 625) lowers off-state leakage current through the use of lighter doping. Typically, lighter doping has the consequence of reduced conductivity. However, the introduction of sub-fin doping techniques (i.e., Boron-doped silicate glass (BSG) and Phosphorus- doped silicate glass (PSG)) and other retro implants change Nwell/Pwell junction characteristics significantly so that Nwell/Pwell junction diodes (e.g., 320, 625) are an effective ESD protection structures (in trigate FinFET technologies, for example). So the Nwell (e.g., 305, 605) and Pwell (e.g., 325, 610) doping and the graded profile doping as discussed herein may be doped using BSG and PSG doping techniques.

[0042] The conductivity of the extended Nwell 605 (also 305, for example) and/or Pwell 610 (also 325, for example) can be further improved by the addition of a gate electrode and/or control gate that uses field effect techniques to improve the conduction. As illustrated, an N side control gate 630 may be coupled to a cathode 635 which charges the N side control gate 630 with a negative charge. The control gate 630 may be insulated from the fins 615 but may extend down between the fins 615 (as partly shown by the dashed lines 630, for example) to at least partially surround at least a portion of the extended Nwell 605. The negative field produced by the control gate 630 may by way of field effect, cause additional negative charge to become available in the extended Nwell 605. This may increase the conductance associated with the extended Nwell 605 without increasing the current leakage during off-state operation. In some cases, the N side control gate 630 can be added to the structure without any area/process penalty. For example, although not shown, an N side control gate could be added in the area between the doped fins that is currently identified as substrate 120 (e.g., the shallow trench isolation (STI) area) in FIG. 3.

[0043] Similarly, a P side control gate 645 may be coupled to an anode 650 which charges the P side control gate 645 with a positive charge. The P side control gate 645 may be insulated from the fins 615 but may extend down between the fins 615 (similar to the dashed lines 630 as shown for the N side control gate 630, for example) to at least partially surround at least a portion of the Pwell 610. The positive field produced by the P side control gate 645 may by way of field effect, cause additional positive charge to become available in the Pwell 610. This may increase the conductance associated with the Pwell 610 without increasing the current leakage during off-state operation. In some cases, the P side control gate 645 can be added to the structure without any area/process penalty. For example, although not shown, a P side control gate could be added in the area between the doped fins that is currently identified as substrate 120 (e.g., the shallow trench isolation (STI) area) in FIG. 3.

[0044] In some cases, as shown, the P side control gate 645 may extend into the area of the extended Nwell 605 so as to reduce the depletion region between the Pwell 605 and the extended Nwell 605. It is noted that the combination of using lightly doped Nwell and Pwell and its associated reduced leakage current in connection with a control gate (e.g., N side control gate 630 and/or P side control gate 645) may be substantially more energy efficient than using highly doped materials that have higher leakage current during off-state operation. It is

appreciated, that the described Nwell/Pwell diode 325 has good conductance without the control gate as illustrated in FIG. 5. However, the control gate (e.g., N side control gate 630 and/or P side control gate 645) may be added to

enhance/selectively modulate conductivity. [0045] FIG. 7 illustrates a method 700 for manufacturing a sub-fin Nwell/Pwell ESD diode. At 705, a lightly P-doped semiconductor is disposed on a first area of a substrate. At 710, a lightly N-doped semiconductor is disposed on a second area of the substrate. At 715, a fin of graded P-doped semiconductor is disposed on a first portion of the lightly P-doped semiconductor to form a P-doped region that includes the lightly P-doped semiconductor and the fin of graded P-doped semiconductor. At 720, a fin of graded N-doped semiconductor is disposed on a first portion of the lightly N-doped semiconductor to form an N-doped region that includes the lightly N- doped semiconductor and the fin of graded N-doped semiconductor. The lightly P- doped semiconductor interfaces with the lightly N-doped semiconductor to provide a P-N junction that allows the P-doped region and the N-doped region to form a diode. At 725, a gate electrode is disposed over at least a tip of the fin of graded P-doped semiconductor and a tip of the fin of graded N-doped semiconductor.

[0046] FIG. 8 depicts a block diagram of a computer system 800 that incorporates the present systems and methods. The computer system 800 includes a bus 805 that interconnects major subsystems of the computer system 800, such as a central processor 810, a system memory 815 (typically RAM, but which may also include ROM, flash RAM, embedded DRAM (eDRAM), SRAM, spin-transfer torque memory (STT-MRAM), or the like), an input/output (I/O) controller 820, an external audio device, such as a speaker system 825 via an audio output interface 830, an external device, such as a display screen 835 via a display adapter 840, an input device 845 (e.g., keyboard, touchpad, touch screen, voice recognition module, etc.) (interfaced with an input controller 850), a sensor 855 via a serial interface 860, a fixed disk (or other storage medium, for example) 865 via a storage interface 870, and a network interface 875 (coupled directly to the bus 805).

[0047] The central processor 810 includes at least one FinFET 300. The FinFET 300 includes at least one sub-fin Nwell/Pwell junction ESD diode 320. Although, the ESD diode 320 is illustrated as being associated with a FinFET, it is appreciated that the ESD diode 320 may be associated with any of a variety of different gate topologies including both planar and non-planar transistors. Additionally or alternatively, the computer system 800 may include a separate processing unit that includes the ESD diode 320 (instead of or in addition to the ESD diode 320 in the central processor 810). [0048] The bus 805 allows data communication between the central processor 810 and the system memory 815, which may include read-only memory (ROM) or flash memory (neither shown), and random access memory (RAM) (not shown), as previously noted. The RAM is generally the main memory into which the operating system and application programs are loaded. The ROM or flash memory can contain, among other code, the Basic Input-Output system (BIOS), which controls basic hardware operation such as the interaction with peripheral components or devices. Applications resident with the computer system 800 are generally stored on and accessed via a non-transitory computer readable medium, such as a hard disk drive (e.g., the fixed disk 865) or another storage medium.

[0049] The storage interface 870, as with the other storage interfaces of the computer system 800, can connect to a standard computer readable medium for storage and/or retrieval of information, such as a fixed disk drive (e.g., the fixed disk 865). The fixed disk 865 may be a part of the computer system 800 or may be separate and accessed through other interface systems. The network interface 875 may provide a direct connection to a remote server via a direct network link to the Internet. The network interface 875 may provide such connection using wireless techniques, including digital cellular telephone connection, Cellular Digital Packet Data (CDPD) connection, digital satellite data connection, or the like.

[0050] Many other devices or subsystems (not shown) may be connected in a similar manner. Conversely, all of the devices shown in FIG. 8 need not be present to practice the present systems and methods. The devices and subsystems can be interconnected in different ways from that shown in FIG. 8. The operation of a computer system such as that shown in FIG. 8 is readily known in the art and is not discussed in detail in this application.

[0051] In various embodiments, the computer system 800 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a field programmable gate array (FPGA), a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computer system 800 may be any other electronic device that processes data.

[0052] Example Embodiments: [0053] Example 1 is an electrostatic discharge (ESD) protection device. The ESD protection device includes a P-doped region, the P-doped region having a graded doping profile that includes a highly P-doped portion at a tip of a P-doped fin, a graded P-doped portion, and a lightly P-doped portion beneath the P-doped fin, where at least the highly P-doped portion interfaces with a gate electrode. The ESD protect device also includes an N-doped region, the N-doped region having a graded doping profile that includes a highly N-doped portion at a tip of an N-doped fin, a graded N-doped portion, and a lightly N-doped portion beneath the N-doped fin, where at least the highly N-doped portion interfaces with the gate electrode, and where the lightly P-doped portion interfaces with the lightly N-doped portion to provide a P-N junction that allows the P-doped region and the N-doped region form a diode.

[0054] Example 2 is the ESD protection device of Example 1 or any of the other Examples, where the ESD protection device further includes a control gate to modulate a depletion region associated with the diode.

[0055] Example 3 is the ESD protection device of Example 2 or any of the other Examples, where the control gate is located between the P-doped fin and the N- doped fin and between the gate electrode and at least one of the lightly P-doped portion and the lightly N-doped portion.

[0056] Example 4 is the ESD protection device of any one of Examples 2 or 3 or any of the other Examples, where the control gate is selectively coupled to a cathode.

[0057] Example 5 is the ESD protection device of any one of Examples 2 or 3 or any of the other Examples, where the control gate is selectively coupled to an anode.

[0058] Example 6 is the ESD protection device of Example 1 or any of the other Examples, where the highly P-doped portion and the graded P-doped portion are in the P-doped fin that extends from the lightly P-doped portion to the gate electrode, and where the highly P-doped portion interfaces with the gate electrode at a tip of the P-doped fin and the graded P-doped portion attached

[0059] the highly P-doped portion with the lightly P-doped portion beneath the P- doped fin.

[0060] Example 7 is the ESD protection device of Example 6 or any of the other Examples, where the graded P-doped portion has a graded doping profile that includes a higher P-doping near the highly P-doped portion and a lower P-doped portion near the lightly P-doped portion.

[0061] Example 8 is the ESD protection device of Example 1 or any of the other Examples, where the highly N-doped portion and the graded N-doped portion are in the N-doped fin that extends from the lightly N-doped portion to the gate electrode, and where the highly N-doped portion interfaces with the gate electrode at a tip of the N-doped fin and the graded N-doped portion attaches the highly N-doped portion with the lightly N-doped portion beneath the N-doped fin.

[0062] Example 9 is the ESD protection device of Example 8 or any of the other Examples, where the graded N-doped portion has a graded doping profile that includes a higher N-doping near the highly N-doped portion and a lower N-doped portion near the lightly N-doped portion.

[0063] Example 10 is the ESD protection device of any of Examples 6-9 or any of the other Examples, where the ESD protection device includes multiple P-doped fins and multiple N-doped fins.

[0064] Example 1 1 is the ESD protection device of Example 10 or any of the other Examples, where the lightly P-doped portion and the lightly N-doped portion are disposed on a P-doped substrate.

[0065] Example 12 is the ESD protection device of Example 1 or any of the other Examples, where the P-doped fin, the N-doped fin, and the gate electrode form a fin field effect transistor (FinFET).

[0066] Example 13 is the ESD protection device of Example 1 or any of the other Examples, where at least a portion of the P-doped region is doped using Boron- doped silicate glass (BSG).

[0067] Example 14 is the ESD protection device of Example 13 or any of the other Examples, where the lightly P-doped portion is doped using BSG.

[0068] Example 15 is the ESD protection device of Example 1 or any of the other Examples, where at least a portion of the N-doped region is doped using

Phosphorus-doped silicate glass (PSG).

[0069] Example 16 is the ESD protection device of Example 15 or any of the other Examples, where the lightly N-doped portion is doped using PSG.

[0070] Example 17 is a method for manufacturing an electrostatic discharge (ESD) protection device. The method includes disposing a lightly P-doped semiconductor on a first area of a substrate, and disposing a lightly N-doped semiconductor on a second area of the substrate. The method also includes disposing a fin of graded P-doped semiconductor on a first portion of the lightly P- doped semiconductor to form a P-doped region that includes the lightly P-doped semiconductor and the fin of graded P-doped semiconductor, where a concentration of P-doping of the fin of graded P-doped semiconductor increases as a height of the fin of graded P-doped semiconductor increases. The method also includes disposing a fin of graded N-doped semiconductor on a first portion of the lightly N- doped semiconductor to form an N-doped region that includes the lightly N-doped semiconductor and the fin of graded N-doped semiconductor, where a concentration of N-doping of the fin of graded N-doped semiconductor increases as a height of the fin of graded N-doped semiconductor increases, where the lightly P-doped semiconductor interfaces with the lightly N-doped semiconductor to provide a P-N junction that allows the P-doped region and the N-doped region to form a diode. The method also includes disposing a gate electrode over at least a tip of the fin of graded P-doped semiconductor and at least a tip of the fin of graded N-doped semiconductor.

[0071] Example 18 is the method of Example 17 or any of the other Examples, where the method further includes disposing a control gate on a second portion of the of the lightly P-doped semiconductor, where the control gate is selectively attached to a cathode for selectively modulating a depletion layer of the diode.

[0072] Example 19 is the method of Example 17 or any of the other Examples, where the method further includes disposing a control gate on a second portion of the of the lightly N-doped semiconductor, where the control gate is selectively attached to an anode for selectively modulating a depletion layer of the diode.

[0073] Example 20 is the method of any of Examples 17-19 or any of the other Examples, where the tip of the fin of graded P-doped semiconductor is highly P- doped while a base of the fin of graded P-doped semiconductor is lightly P-doped.

[0074] Example 21 is the method of any of Examples 17-19 or any of the other Examples, where the method further includes disposing a highly P-doped

semiconductor on the fin of graded P-doped semiconductor to form the tip of the fin of graded P -doped semiconductor.

[0075] Example 22 is the method of any of Examples 17-19 or any of the other Examples, where the tip of the fin of graded N-doped semiconductor is highly N- doped while a base of the fin of graded N-doped semiconductor is lightly N-doped. [0076] Example 23 is the method of any of Examples 17-19 or any of the other Examples, where the method further includes disposing a highly N-doped

semiconductor on the fin of graded N-doped semiconductor to form the tip of the fin of graded N-doped semiconductor.

[0077] Example 24 is the method of any of Examples 17-19 or any of the other Examples, where the lightly P-doped semiconductor is doped using Boron-doped silicate glass (BSG).

[0078] Example 25 is the method of any of Examples 17-19 or any of the other Examples, where the lightly N-doped semiconductor is doped using Phosphorus- doped silicate glass (PSG).

[0079] Example 26 is a computing device. The computing device includes a fin field effect transistor (FinFET), where the FinFET includes a P-doped region, the P- doped region having a graded doping profile that includes a highly P-doped portion at a tip of a P-doped fin, a graded P-doped portion, and a lightly P-doped portion beneath the P-doped fin, where at least the highly P-doped portion interfaces with a gate electrode. The computing device includes an N-doped region, the N-doped region having a graded doping profile that includes a highly N-doped portion at a tip of an N-doped fin, a graded N-doped portion, and a lightly N-doped portion beneath the N-doped fin, where at least the highly N-doped portion interfaces with the gate electrode, and where the lightly P-doped portion interfaces with the lightly N-doped portion to provide a P-N junction that allows the P-doped region and the N-doped region form a diode. The gate electrode may be disposed on at least a portion of the P-doped fin and the N-doped fin to form the FinFET.

[0080] Example 27 is the computing device of Example 26 or any of the other Examples, where the FinFET further includes a control gate to modulate a depletion region associated with the diode.

[0081] Example 28 is the computing device of Example 27 or any of the other Examples, where the control gate is located between the gate electrode and at least one of the lightly P-doped portion and the lightly N-doped portion.

[0082] It will be obvious to those having skill in the art that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. The scope of the present invention should, therefore, be determined only by the following claims.

Claims

1 . An electrostatic discharge (ESD) protection device, comprising:

a P-doped region, the P-doped region having a graded doping profile that includes a highly P-doped portion at a tip of a P-doped fin, a graded P- doped portion, and a lightly P-doped portion beneath the P-doped fin, wherein at least the highly P-doped portion interfaces with a gate electrode; and

an N-doped region, the N-doped region having a graded doping profile that includes a highly N-doped portion at a tip of an N-doped fin, a graded N-doped portion, and a lightly N-doped portion beneath the N-doped fin, wherein at least the highly N-doped portion interfaces with the gate electrode, and wherein the lightly P-doped portion interfaces with the lightly N-doped portion to provide a P-N junction that allows the P- doped region and the N-doped region form a diode.

2. The ESD protection device of claim 1 , further comprising:

a control gate to modulate a depletion region associated with the diode.

3. The ESD protection device of claim 2, wherein the control gate is located between the P-doped fin and the N-doped fin and between the gate electrode and at least one of the lightly P-doped portion and the lightly N-doped portion.

4. The ESD protection device of any one of claims 2 or 3, wherein the control gate is selectively coupled to a cathode.

5. The ESD protection device of any one of claims 2 or 3, wherein the control gate is selectively coupled to an anode.

6. The ESD protection device of claim 1 , wherein the highly P-doped portion and the graded P-doped portion are in the P-doped fin that extends from the lightly P-doped portion to the gate electrode, and wherein the highly P-doped portion interfaces with the gate electrode at a tip of the P-doped fin and the graded P-doped portion couples the highly P-doped portion with the lightly P-doped portion beneath the P-doped fin.

7. The ESD protection device of claim 6, wherein the graded P-doped portion has a graded doping profile that includes a higher P-doping near the highly P-doped portion and a lower P-doped portion near the lightly P-doped portion.

8. The ESD protection device of claim 1 , wherein the highly N-doped portion and the graded N-doped portion are in the N-doped fin that extends from the lightly N-doped portion to the gate electrode, and wherein the highly N-doped portion interfaces with the gate electrode at a tip of the N-doped fin and the graded N-doped portion couples the highly N-doped portion with the lightly N-doped portion beneath the N-doped fin.

9. The ESD protection device of claim 8, wherein the graded N-doped portion has a graded doping profile that includes a higher N-doping near the highly N-doped portion and a lower N-doped portion near the lightly N-doped portion.

10. The ESD protection device of any of claims 6-9, wherein the ESD protection device includes a plurality of P-doped fins and a plurality of N-doped fins.

1 1 . The ESD protection device of claim 10, wherein the lightly P-doped portion and the lightly N-doped portion are disposed on a P-doped substrate.

12. The ESD protection device of claim 1 , wherein the P-doped fin, the N- doped fin, and the gate electrode are form a fin field effect transistor (FinFET).

13. A method for manufacturing an electrostatic discharge (ESD) protection device, comprising:

disposing a lightly P-doped semiconductor on a first area of a substrate;

disposing a lightly N-doped semiconductor on a second area of the substrate; disposing a fin of graded P-doped semiconductor on a first portion of the

lightly P-doped semiconductor to form a P-doped region that includes the lightly P-doped semiconductor and the fin of graded P-doped semiconductor, wherein a concentration of P-doping of the fin of graded P-doped semiconductor increases as a height of the fin of graded P-doped semiconductor increases;

disposing a fin of graded N-doped semiconductor on a first portion of the

lightly N-doped semiconductor to form an N-doped region that includes the lightly N-doped semiconductor and the fin of graded N-doped semiconductor, wherein a concentration of N-doping of the fin of graded N-doped semiconductor increases as a height of the fin of graded N-doped semiconductor increases, wherein the lightly P-doped semiconductor interfaces with the lightly N-doped semiconductor to provide a P-N junction that allows the P-doped region and the N-doped region to form a diode; and disposing a gate electrode over at least a tip of the fin of graded P-doped semiconductor and at least a tip of the fin of graded N-doped semiconductor.

14. The method of claim 13, further comprising:

disposing a control gate on a second portion of the of the lightly P-doped semiconductor, wherein the control gate is selectively coupled to a cathode for selectively modulating a depletion layer of the diode.

15. The method of claim 13, further comprising:

disposing a control gate on a second portion of the of the lightly N-doped semiconductor, wherein the control gate is selectively coupled to an anode for selectively modulating a depletion layer of the diode.

16. The method of any of claims 13-15, wherein the tip of the fin of graded P-doped semiconductor is highly P-doped while a base of the fin of graded P-doped semiconductor is lightly P-doped.

17. The method of any of claims 13-15, further comprising:

disposing a highly P-doped semiconductor on the fin of graded P-doped semiconductor to form the tip of the fin of graded P -doped semiconductor.

18. The method of any of claims 13-15, wherein the tip of the fin of graded N-doped semiconductor is highly N-doped while a base of the fin of graded N-doped semiconductor is lightly N-doped.

19. The method of any of claims 13-15, further comprising:

disposing a highly N-doped semiconductor on the fin of graded N-doped semiconductor to form the tip of the fin of graded N-doped semiconductor.

20. The method of any of claims 13-15, wherein the lightly P-doped semiconductor is doped using Boron-doped silicate glass (BSG).

21 . The method of any of claims 13-15, wherein the lightly N-doped semiconductor is doped using Phosphorus-doped silicate glass (PSG).

22. A computing device, comprising:

a fin field effect transistor (FinFET), wherein the FinFET comprises:

a P-doped region, the P-doped region having a graded doping profile that includes a highly P-doped portion at a tip of a P-doped fin, a graded P- doped portion, and a lightly P-doped portion beneath the P-doped fin, wherein at least the highly P-doped portion interfaces with a gate electrode; and an N-doped region, the N-doped region having a graded doping profile that includes a highly N-doped portion at a tip of an N-doped fin, a graded N- doped portion, and a lightly N-doped portion beneath the N-doped fin, wherein at least the highly N-doped portion interfaces with the gate electrode, and wherein the lightly P-doped portion interfaces with the lightly N-doped portion to provide a P-N junction that allows the P-doped region and the N-doped region form a diode.

23. The computing device of claim 22, wherein the FinFET further comprises a control gate to modulate a depletion region associated with the diode.

24. The computing device of claim 23, wherein the control gate is located between the gate electrode and at least one of the lightly P-doped portion and the lightly N-doped portion.