WO2018109782A1

WO2018109782A1 - Network analyzer for measuring s-parameters of rf device

Info

Publication number: WO2018109782A1
Application number: PCT/IN2017/050575
Authority: WO
Inventors: Girish Kumar; Debapratim GHOSH
Original assignee: Indian Institute Of Technology Bombay
Priority date: 2016-12-13
Filing date: 2017-12-07
Publication date: 2018-06-21

Abstract

Embodiments herein provide a network analyzer to measure S-parameter magnitudes of a DUT at UHF, L, and S band respectively. The proposed network analyzer includes a signal generator for generating a microwave signal. The proposed network analyzer includes a harmonic suppressor for suppressing harmonics of the generated microwave signal to obtain a filtered microwave signal. The proposed network analyzer includes a signal separator for isolating the filtered microwave signal incident on the DUT from a reflected signal, reflected by the DUT, for obtaining transmission coefficient and reflection coefficient of the DUT. The proposed network analyzer includes a computing unit for measuring the S-parameters of the DUT based on the determined transmission coefficient and reflection coefficient.

Description

NETWORK ANALYZER FOR MEASURING S -PARAMETERS OF

RF DEVICE FIELD OF INVENTION

[0001] The present method relates to network analyzer and more particularly to a broadband system (network analyzer) to measure Scattering (S)-parameter magnitudes of RF devices at Ultra High Frequency (UHF) band, L band and S band. The present application is based on, and claims priority from an Indian Application Number 201621042495 filed on 13^th December, 2016 the disclosure of which is hereby incorporated by reference herein.

BACKGROUND OF INVENTION

[0002] A network analyzer consists of an RF source whose output is passed through a power divider, in which part of the power is used as a reference. The rest of the power is incident on an arbitrary load or a Device under Test (DUT), and the reflected wave is usually isolated through a directional coupler. The incident power, reflected power, and transmitted power, are captured by different receivers or power detectors and are used for computing the S -parameters of the DUT. A scalar network analyzer (also referred as network analyzer) has power magnitude detectors to measure the magnitude of the S -parameters of the DUT. Measuring the S- parameters of a circuit or a system provides an indication of its performance over a wide range of frequencies.

[0003] In the existing system architecture, low isolation signal separators are used. This results in considerable error in measuring the incident and reflected waves at the load, which reduces the dynamic range. An appreciable dynamic range allows the network analyzer to distinguish matched and mismatched loads which in turn allows simplification in designing the calibration method. In order to achieve high isolation, the existing systems utilize certain techniques such as lumped-element compensation, epsilon negative structures and multi-layering, or the like. However, these techniques are inherently narrowband and hence multiple couplers are required for measuring the S-parameters in a wide bandwidth. In order to measure S-parameters over a broad bandwidth, the existing system architectures use multiple signal separator blocks controlled by switches depending on the required frequency band.

[0004] The existing system architectures utilize waveguide components for efficient power handling, low losses, or the like. However, waveguide components increase the cost, size, complexity and weight of the overall system, i.e., the network analyzer, considerably.

[0005] Thus, there is a need for a design and realization of the signal separator which allows measurement of S-parameters over a large bandwidth, provide appreciable dynamic range and isolation between the transmitted and reflected signals.

[0006] The above information is presented as background only to help the reader for understanding the present invention. Applicants have made no determination and make no assertion as to whether any of the above might be applicable as Prior Art with regard to the present application.

OBJECT OF INVENTION

[0007] The principal object of the embodiments herein is to provide a broadband system (network analyzer) to measure S -parameter magnitudes of various devices at UHF, L, and S band respectively.

[0008] Another object of the embodiments herein is to provide a single signal separator which achieves high isolation and dynamic range, and is independent of subsequent isolation error correction.

[0009] Another object of the embodiments herein is to provide the design and use of the single signal separator which is capable of providing high isolation consistently over a broad bandwidth. [0010] Another object of the embodiments herein is to provide a network analyzer design which allows reduction in cost, size and weight.

[0011] Another object of the embodiments herein is to provide protection to a test signal source of the network analyzer against load mismatch.

[0012] Another object of the embodiments herein is to provide a network analyzer which facilitates powering, programming control and data acquisition over Universal Serial Bus (USB) interface.

SUMMARY

[0013] Accordingly embodiments herein provide a broadband system (network analyzer) to measure S-parameter magnitudes of RF devices at UHF, L, and S band respectively, i.e., in the range of (500MHz to 2.5 GHz). The RF device for which the S-parameters are measured is a Device under Test (DUT). The proposed system includes a signal generator for generating a microwave signal. The proposed system includes a harmonic suppressor for suppressing harmonics of the generated microwave signal to obtain a filtered microwave signal. The proposed system includes a signal separator for isolating the filtered microwave signal incident on a DUT from a reflected signal, reflected by the DUT, for obtaining transmission coefficient and reflection coefficient of the DUT. The proposed system includes a computing unit for calculating the S- parameters of the DUT based on the determined transmission coefficient and reflection coefficient.

[0014] In an embodiment, the microwave signal is generated through a Phase Locked Loop (PLL), with an integrated Voltage Control Oscillator (VCO). The harmonic suppressor is a multi-notch bandstop filter, in which the notches are located at the harmonics of the generated microwave signal. This allows suppression of the higher order harmonics of the generated microwave signal and a filtered microwave signal is obtained. The filtered microwave signal is fed to an impedance matching network consisting of a series inductance realized using microstrip technique. The matched filtered microwave signal is fed to the signal separator.

[0015] In an embodiment, the signal separator includes a differential amplifier which generates two versions of the filtered microwave signal, having same magnitude but opposite phase with respect to each other. The signal separator includes two two-section power dividers, viz., a first two-section power divider and a second two-section power divider. The two-section power dividers perform impedance matching between the differential amplifier and a two-section power combiner. The two- section power combiner, included in the signal separator, combines the filtered microwave signal and the filtered microwave signal with opposite phase, in which the filtered microwave signal with opposite phase is coupled with the reflected signal from the DUT.

[0016] One of the versions of the filtered microwave signal, i.e. the first version, reaches the two- section power combiner through the first two- section power divider and the other version of the filtered microwave signal, i.e. the second version with an opposite phase with respect to the first version, reaches the two-section power combiner through the second two-section power divider. However, the second version of the filtered microwave signal is coupled with the reflected signal from the DUT if the first two-section power divider and the second two-section power divider are not terminated with matched loads.

[0017] In an embodiment, the first two-section power divider is terminated at predefined load impedance and the second two-section power divider is terminated at with an impedance of the DUT. The two-section power combiner consists of two ports and signals from the first two-section power divider and the second two- section power divider are incident at the two ports. The two-section power combiner provides an equal phase delay to the signals incident at both ports.

[0018] If the first two-section power divider and the second two- section power divider are terminated with matched loads, then output power of the two-section power combiner, i.e., the reflected power, will be very low since the incident signals are equal in magnitude and opposite in phase. On the other hand if the first two-section power divider and the second two-section power divider are not terminated with matched loads, then the second version of the filtered microwave signal is coupled with the reflected signal from the DUT at the second two-section power divider. Since the two-section power combiner provides an equal phase delay to the signals incident at both ports, the reflected power can be easily identified and isolated.

[0019] In an embodiment, the proposed system includes a two-way power divider for splitting the power of the filtered microwave signal into two parts, in which one part is fed to a reference power detector and the other part is fed to an impedance matching network before the signal separator. The reference power is used to determine the power incident at the DUT. The part of the filtered microwave signal fed to the impedance matching network is fed to the signal separator. The proposed system includes a transmitted power detector for determining the power transmitted to the DUT. The proposed system includes a reflected power detector for determining the power reflected by the DUT.

[0020] In an embodiment, the computing unit is configured to control the generated microwave signal. The computing unit is further configured to determine the power level of the reference power detector, the transmitted power detector, and the reflected power detector. The computing unit is further configured to measure the S -parameters of the DUT based on the determined power level at the transmitted power detector and the reflected power detector. The computing unit is further configured to cause to display the measured S-parameters. The computing unit receives instructions for controlling the PLL, measuring S-parameters of the DUT, and displaying the measured S-parameters through a Universal Serial Bus (USB) interface.

[0021] Accordingly embodiments herein provide a network analyzer to measure S -parameter magnitudes of RF devices at UHF, L, and S band respectively. The proposed network analyzer includes a signal generator for generating a microwave signal. The proposed network analyzer includes a harmonic suppressor for suppressing harmonics of the generated microwave signal to obtain a filtered microwave signal. The proposed network analyzer includes a signal separator for isolating the filtered microwave signal incident on a Device under Test (DUT) from a reflected signal, reflected by the DUT, for obtaining transmission coefficient and reflection coefficient of the DUT. The proposed network analyzer includes a computing unit for measuring the S-parameters of the DUT based on the determined transmission coefficient and reflection coefficient.

[0022] These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications. BRIEF DESCRIPTION OF FIGURES

[0023] This method is illustrated in the accompanying drawings, throughout which like reference letters indicate corresponding parts in the various figures. The embodiments herein will be better understood from the following description with reference to the drawings, in which:

[0024] FIG. 1 is a block diagram of proposed system (scalar network analyzer), according to the embodiments as disclosed herein;

[0025] FIG. 2 illustrates circuit of a microcontroller, a Phase Locked Loop (PLL) with an integrated Voltage Controlled Oscillator (VCO), incorporating a loop filter and attenuator, and programming modes of the microcontroller, according to the embodiments as disclosed herein;

[0026] FIG. 3a illustrates configuration of harmonic suppressor filter, according to the embodiments as disclosed herein;

[0027] FIG. 3b illustrates frequency response of the harmonic suppression filter, according to the embodiments as disclosed herein;

[0028] FIG. 4 illustrates configuration of signal separator of the proposed scalar network analyzer, according to the embodiments as disclosed herein;

[0029] FIG. 5a illustrates circuit of a reference power detector, a transmitted power detector, and a reflected power detector, in the proposed network analyzer, according to the embodiments as disclosed herein;

[0030] FIG. 5b illustrates the magnitude of the coefficients of one of the power detectors, according to the embodiments as disclosed herein;

[0031] FIG. 6a illustrates un-calibrated reflection coefficient of standard open, short and matched loads respectively, according to the embodiments as disclosed herein; and

[0032] FIG. 6b illustrates un-calibrated reflection coefficients and transmission coefficients of a bandstop filter used as a Device under Test (DUT), obtained using the proposed network analyzer, according to the embodiments as disclosed herein.

DETAILED DESCRIPTION OF INVENTION

[0033] The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well- known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. Also, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The term "or" as used herein, refers to a nonexclusive or, unless otherwise indicated. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein can be practiced and to further enable those skilled in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.

[0034] Accordingly embodiments herein provide a broadband system (network analyzer) to measure S -parameter magnitudes of RF devices at UHF, L, and S band respectively, i.e., in the range of (500MHz to 2.5 GHz). In an embodiment, the RF device is a DUT. The proposed system incorporates elements viz., a signal generator, a harmonic suppressor, a high isolation signal separator and power detection circuits, which include a reference power detector, transmitted power detector and a reflected power detector. In an embodiment, the elements are implemented in microstrip technique in order to realize a low cost, low power, broad bandwidth, and high dynamic range scalar network analyzer. The proposed network analyzer utilizes a partially unilateral active test set as a signal separator, which consistently provides a high isolation. In an example, the signal separator provides a load dynamic range of 28 to 35 dB over the frequency range of 500MHz to 3 GHz. The signal separator in the proposed network analyzer is designed as a single element using planar microstrip technique. The planar microstrip design allows maintaining the size of the signal separator and also the network analyzer compact, which is suitable for low cost realization. The signal separator is designed using active elements which provide acceptable reverse isolation. In an example, the reverse isolation is higher than 30 dB. The active elements in the signal separator provide protection to the signal generator against load mismatch.

[0035] One of the factors that govern the performance of the network analyzer is the design of the signal separator or the test set. In order to measure the S-parameters in a wide bandwidth, multiple couplers are used in which each coupler is designed at a different center frequency. The couplers form a coupler bank which includes electronically controlled microwave switches at the input and output. The position of the microwave switches is changed for selecting a particular coupler depending on the frequency at the source. In an example, four couplers are required in a coupler bank in order to obtain S -parameter measurements in the frequency range of 800MHz to 2.5GHz, in which each coupler is a three branch coupler providing a bandwidth of 30%. Another factor which governs the performance of the network analyzer is the isolation between the transmitted and reflected signals sent and received the DUT. The signal separator determines the degree by which the incident waves to the DUT and reflected waves from the DUT are separated and measured.

[0036] The proposed network analyzer can be used for measuring the S-parameters of active/passive devices and circuits such as filters, amplifiers, couplers, power dividers/combiners, antennas, attenuators, switches, or the like. The proposed network analyzer can be used in a wide variety of RF/microwave applications.

[0037] Unlike conventional systems, the proposed broadband system (network analyzer) is economical and incurs about 1-5% of the cost incurred by the existing network analyzers. The existing network analyzer architectures use low isolation signal separators which results in considerable error in measuring the incident and reflected waves at the load. This also reduces the dynamic range. These errors are removed later using error correction.

[0038] Unlike conventional network analyzers, the proposed network analyzer uses a single signal separator which achieves high isolation and dynamic range, which makes it independent of subsequent isolation error correction.

[0039] In order to measure S -parameters over a wide bandwidth

(around 100 kHz to 5 GHz), the existing network analyzer architectures use multiple signal separator blocks, which are controlled by switches, depending on the required frequency band. Unlike conventional network analyzers, the proposed network analyzer includes a single signal separator capable of providing a high isolation, between the incident and reflected signals, consistently over a wide bandwidth (500MHz to 3 GHz). The proposed network analyzer provides the design and use of a single broadband, partially unilateral active signal separator which provides high isolation (for example: greater than 38 dB) over a wide bandwidth, i.e., 500MHz to 3 GHz. The proposed network analyzer allows measurement of S-parameters in frequency range of 800MHz to 2.5 GHz, which covers the commercial cellular and wireless frequency bands and is suitable for testing of devices/circuits for these applications.

[0040] The existing network analyzers use waveguide components for efficient power handling, minimizing losses, or the like, at the cost of increased size. However, increase in size of the network analyzer increases the cost, size and weight of the network analyzer considerably. Unlike conventional network analyzers, the constituent hardware blocks of the proposed network analyzer are fully designed in planar microstrip, which reduces the cost, size and weight of the proposed network analyzer. The realization of the proposed network analyzer using planar microstrip technique on low cost standard substrate makes the proposed network analyzer to be suitable for low cost utilization and mass production.

[0041] The un-calibrated dynamic range of the load, for example: is in the range of 24 to 37 dB, indicates that the reduction of size of the proposed network analyzer and realization of the proposed network analyzer in microstrip does not affect its performance.

[0042] Unlike existing network analyzers, the entire hardware configuration of the proposed network analyzer is realized on a low cost glass epoxy substrate which facilitates control of the proposed network analyzer, and power and display functionalities, through USB. The usage of low cost substrate and de-centralization of the display functionality to a separate host computer allows designing the proposed network analyzer at a low cost which is portable through the USB plug and play interface. The proposed network analyzer is powered by the USB power supply of 5V DC supply and consumes a power of around 1W, which is lower in comparison with the existing network analyzers. The proposed network analyzer is suitable for low power applications.

[0043] Referring now to the drawings, and more particularly to FIGS. 1 through 6b, there are shown preferred embodiments.

[0044] FIG. 1 is a block diagram of the proposed system 100 (network analyzer), according to the embodiments as disclosed herein. The proposed network analyzer consists of a (low power) signal generator, (microwave source) which generates a microwave signal which is incident on a DUT. The microwave signal is generated through a Phase Locked Loop (PLL) with an integrated Voltage Control Oscillator (VCO). The output signal from the microwave source, i.e., generated microwave signal, is passed through a harmonic suppressor, which suppresses higher order harmonics in the generated microwave signal and a filtered microwave signal is obtained. Thereafter, the filtered microwave signal is fed to a two- way power divider which divides the power of the filtered signal into two parts, in which one part of the filtered signal is fed to a reference power detector, in order to have a reference of the measured power of the filtered microwave signal; and the other part is fed to a signal separator.

[0045] The signal separator includes a differential amplifier which generates two versions of the filtered microwave signal having same magnitude but opposite phase with respect to each other. The signal separator includes two two-section power dividers. The two-section power dividers perform impedance matching between the differential amplifier and a two-section power combiner. The two-section power combiner, included in the signal separator, combines the filtered microwave signal and the filtered microwave signal with opposite phase, coupled with a reflected signal from the DUT.

[0046] One of the versions of the filtered microwave signal (first version) reaches the two-section power combiner through the top two- section power divider (first two- section power divider) and the other version (second version) of the filtered microwave signal, with the opposite phase, reaches the two-section power combiner through the bottom two- section power divider (second two-section power divider). However, the second version of the filtered microwave signal is coupled with the reflected signal from the DUT if the top two- section power divider and the bottom two- section power divider are not terminated with matched loads.

[0047] As depicted in FIG. 1, the top two-section power divider is terminated at particular impedance and is also connected to an auxiliary detector. In an example, the top two-section power divider is terminated at an impedance of 50Ω. The bottom two- section power divider is connected to the DUT. The two-section power combiner consists of two ports and receives signals from both two-section power dividers. The two-section power combiner provides an equal phase delay to the signals incident at both ports.

[0048] If the impedance at which both two-section power dividers are terminated is matched, then reflected power from the DUT will be at a minimum. This is due to the fact that the received signals at the two ports of the two-section power combiner are equal in magnitude and opposite in phase and equal phase delay is provided at both ports of the two- section power combiner. If the impedance at which both two-section power dividers are terminated is not matched, then the filtered microwave signal in the bottom two-section power divider is coupled with the reflected signal from the DUT. Since the two-section power combiner provides an equal phase delay to the signals incident at both ports, the reflected power can be easily identified and isolated.

[0049] The power transmitted to the DUT is determined through a transmitted power detector and the power reflected by the DUT is determined through a reflected power detector. The reference power detector, the transmitted power detector, and the reflected power detector are connected to respective decoupling circuits in order to counter noise or spurious phase shift introduced. The DUT is connected to one of the ports of the signal separator (bottom two-section power divider) and a transmitted power detector. The reflected power detector is connected to another port of the signal separator (two- section power combiner).

[0050] The proposed system 100 includes a computing unit to determine S -parameters of the DUT based on the reflection coefficient and transmission coefficient, which are obtained by measuring the transmitted power and reflected power from the transmitted and reflected power detectors respectively. In an embodiment, the computing unit is a microcontroller (MCU). The microcontroller in the proposed system 100 communicates through the USB in order to control the output of the microwave source, i.e., the generated microwave signal. The MCU can be utilized for determining and reading the power of the reference power detector, transmitted power detector, and the reflected power detector. The incident power, transmitted power, and reflected power determined from the respective power detectors are used for computing the S-parameters of the DUT. The MCU sends the S-parameter values to a host PC after every sweep cycle, and a user interface program may be used to display the measured S-parameters.

[0051] In an embodiment, the MCU collects the transmitted power, reflected power, and reference power and sends the respective power level to the host PC. The host PC computes the transmission coefficient and reflection coefficient. Thereafter the S-parameters are computed by the host PC, based on the transmission coefficient and reflection coefficient.

[0052] Multiple connecting points Ά J' are depicted in the

FIG. 1, which are used to explain the interconnection of the different subsystems in the forthcoming figure descriptions.

[0053] FIG. 2 illustrates circuit of the microcontroller, a PLL with an integrated VCO, incorporating a loop filter and attenuator, and programming modes of the microcontroller, according to the embodiments as disclosed herein.

[0054] The reference microwave source, in an example, can be considered to be an ideal sine wave generator which generates a microwave signal with a precisely controlled frequency. A chip-based PLL with integrated VCO is used for generating the reference frequency for the proposed network analyzer. The PLL is controlled by the PIC18F4550 microcontroller. As the PIC18F4550 has an on-chip Serial Peripheral Interface (SPI) port, a USB controller and a 10-bit Analog to Digital Converter (ADC) channel, the PIC18F4550 is found to be suitable for PLL control, PC interface and reading the measured power levels.

[0055] The PIC18F4550 is interfaced with the LTC6946 PLL through four SPI lines viz., Serial Clock (SCK), Serial Data-Out (SDO), Serial Data-in (SDI), and Chip Select (CS), which are connected to the LTC6946. The LTC6946 uses a 10MHz clock as a reference frequency input (fi ) which is multiplied in order to obtain the desired test frequency (fotrr) for the proposed network analyzer. The test frequency (fotrr) is obtained by means of programmed values of a reference CR-divider, an output stage Co-divider and a CN-counter/divider in the PLL feedback loop using the relation:

The CN is a 16-bit value which decides the multiplication factor for the reference frequency, and the C_R and the Co primarily govern the frequency resolution (step size) of the microwave signal source for the proposed network analyzer.

[0056] The phase detector of the LTC6946 provides a charge-pump current at the output, corresponding to phase error between the reference input and the feedback signal. This current pulse stream is converted into a tuning voltage signal using a low-pass I -V loop filter. The PIC18F4550 MCU is programmed with an on-chip bootloader which communicates with a host PC through USB. The PIC18F4550 MCU is operated in two modes, viz. a bootloader mode, in which PIC18F4550 MCU communicates with the PC (for programming), and an application mode, in which PIC18F4550 MCU runs the application program in its Electrically Erasable Programmable Read Only Memory (EEPROM) in order to control the PLL. The control of the operating mode is achieved by reading the status of the RESET pin as well as the status of the RB4 port pin. Switches are provided for the purpose of reading the status of the RESET pin and the RB4 port pin. [0057] FIG. 2 also depicts the state diagram for controlling the operating mode of the PIC18F4550 MCU, the circuit of the power supply, and the PLL blocks in the proposed network analyzer. All the entities in the proposed network analyzer, apart from the harmonic suppressor, are realized on a glass-epoxy FR4 substrate (ε_Γ = 4.4, tan5 = 0.02).

[0058] FIG. 3a illustrates configuration of the harmonic suppression filter, according to the embodiments as disclosed herein.

[0059] FIG. 3b illustrates frequency response of the harmonic suppression filter, according to the embodiments as disclosed herein.

[0060] In order to suppress the higher order harmonics present in the generated microwave signal, a multi-notch microstrip bandstop filter is designed. In an example, the multi-notch microstrip bandstop filter suppresses the harmonics such that the amplitude of the harmonics is less than -30 dB. A lumped element filter is not preferred since the roll-off is not quite as sharp as desired. The multi-notch microstrip bandstop filter is having a stop-band in the range of 3 to 7.5 GHz, thereby suppressing the second and third harmonics (S -parameters are measured in the frequency band of 500MHz-3GHz). The integrity of the generated microwave signal can be lost due to the spurious reference feed-through. Since a PLL input reference frequency of 10MHz couples through to the detector, a high -pass filter capacitor of 4.7 pF is placed at the input of the filter. The high-pass filter capacitor is the only component of the proposed system 100 (network analyzer) that is realized on an Arlon substrate (ε_Γ = 2.55, h = 1.6 mm, tan5 = 0.02) in order to obtain an appreciable suppression of the harmonics of the generated microwave signal.

[0061] FIG. 4 illustrates configuration of the signal separator of the proposed scalar network analyzer, according to the embodiments as disclosed herein. [0062] The proposed signal separator isolates the incident and reflected waves from the DUT in order to allow measuring the power of the incident and reflected waves. The incident and reflected waves are utilized for calculating the transmission coefficient and reflection coefficient of the DUT. The proposed signal separator consists of a number of stages. The first stage is a compact, broadband two-way two-section power divider which splits the filtered microwave signal into two parts and channels one part to a reference power detector for a reference measurement, which indicates the incident power at point C. The section of the proposed signal separator which isolates the reflected wave from the DUT, from the signal incident to the DUT; is based on a two-section power divider-two-section power combiner configuration, in which the first stage consists of a broadband out of phase divider, which splits the filtered microwave signal into two parts of equal magnitude and opposite phase. The two parts of the filtered microwave signal are thereafter cancelled by an in-phase combiner (two- section power combiner), the output of which is connected to the reflected power detector. The complete picture of the proposed signal separator is depicted in FIG. 4. The out of phase divider is designed using a differential amplifier with a unity gain frequency of 6GHz. The differential amplifier is having capacitive input impedance, which is compensated by adding a series inductance (impedance matching network) at the input. The series inductance is realized using a thin microstrip line whose impedance Z and electrical length Θ are related by the relation Z = 2 fL/sin0. The input Voltage Standing Wave Ratio (VSWR) is below 2 in the frequency range of 500MHz to 3GHz. Lossy resistive matching is performed at both input and output of the differential amplifier to match the impedances to 50Ω.

[0063] As the differential amplifier provides two signals at the output which are out of phase of each other, the two- section power combiner needs to provide equal phase delay to each of these signals and thereafter perform phase cancellation of the two out of phase signals at the input of the reflected power detector. Hence a multi- section broadband power divider/combiner is used in the proposed system 100.

[0064] A compact two-section power combiner is used, in which each section is having a length of λ/8. Therefore, total effective length of the two-section power combiner arm is λ/4. Two isolation resistors, Rl and R2, are included in the two-section power combiner at the intermediate and terminating stages respectively, in order to provide to provide adequate isolation (at least 15 to 20 dB) between the two input ports of the two- section power combiner (points B and D). In an embodiment, the resistors are designed to be Ri = 68Ω and R₂ = 200Ω. This provides a superior performance in terms of bandwidth. The length of the arm of the two- section power combiner is designed to be λ/8 for a frequency of lGHz. This ensures that the input VSWR is below 2 in the frequency range of 0.5GHz to 3.9GHz, and output VSWR is below 2 in the frequency range of 0.6GHz to 4GHz. The reference (incident) power is measured using the reference power detector through the two-way power divider.

[0065] At point F, the reflected power from the load is measured. The load is known as DUT, and is connected to port D, and an auxiliary detector is used for measuring the reference (incident) power. The auxiliary detector is placed at point G. The input impedance looking into the terminals of the top and bottom two-section power dividers, located at the output terminals of the differential amplifier, is dependent on the output impedance of the differential amplifier as well as the input impedance of the in-phase two-section power combiner. Thus, a pair of two-section power combiner, which is used as impedance matching network is placed between the differential amplifier and the in-phase two- section power combiner, is placed as an intermediate matching network. As point G the top two-way power divider is having a 50Ω termination (or auxiliary detector input impedance), any ηοη-50Ω load on point D would disturb the symmetry of the circuit. In the configuration (depicted in FIG. 4), if at point D a load is matched at 50Ω, then there is phase cancellation and minimum power reaches at point F. When a mismatched load is connected to point D, the unequal amplitudes of the signals at the two input ports of the two- section power combiner causes an improper phase cancellation, thereby causing more power to flow to point F. This increases the dynamic range of the proposed network analyzer.

[0066] FIG. 5a illustrates the circuit of the reference power detector, the transmitted power detector, and the reflected power detector, in the proposed network analyzer, according to the embodiments as disclosed herein.

[0067] In an embodiment, a broadband logarithmic peak detector MAX2015 is used in the proposed network analyzer. The logarithmic peak detector provides a DC voltage as output, which is proportional to the input RF peak power. Identical designs are used for measuring the incident, reflected and transmitted power respectively. A separate test is performed in one of the MAX2015s, in which a complete frequency response is obtained for various input power levels, ranging from OdBm to -60dBm.

[0068] The relation between the detector output voltage V_out and the input power level P becomes nonlinear for P > -5dBm and for P < -55dBm. Since the proposed network analyzer is able to estimate the reference/transmitted/reflected power level at the input using only the respective power detector, V_out and P at different frequencies are related using the following third order equation:

in which ai for 0 <= i <= 3 is non-zero. Real numbers are used to fit the reference/transmitted/reflected power detector response into a curve. This fitting is performed in order to cover the frequency range of 800MHz to 2.5GHz. The frequency response is measured for the frequency range of 800MHz to 2.5GHz.

[0069] FIG. 5b illustrates the magnitude of the coefficients of one of the power detectors, according to the embodiments as disclosed herein. FIG. 5b depicts the variation of ai for one of the power detectors over the frequency range of 800MHz to 2.5GHz, indicating its frequency response.

[0070] FIG. 6a illustrates un-calibrated reflection coefficient of standard open, short and matched loads respectively, according to the embodiments as disclosed herein.

[0071] For various DUTs, the output power from the three power detectors, i.e., the reference power detector, the transmitted power detector, and the reflected power detector, in the frequency range of 800MHz to 2.5GHz are computed. Thereafter, the un-calibrated reflection and transmission coefficients respectively are calculated.

[0072] In an embodiment, FIG. 6a depicts the un-calibrated reflection coefficients of open, short and matched loads of Keysight85033E kit (standard calibration kit consisting of coaxial-SMA open, short and matched terminations) measured using the proposed network analyzer. The mismatch between open load and short load is less than 1.2dB, and the dynamic range of the load varies from 24dB to 36dB for the entire frequency range of 800MHz to 2.5GHz.

[0073] FIG. 6b illustrates un-calibrated reflection coefficients and transmission coefficients of the bandstop filter used as the DUT, obtained using the proposed network analyzer, according to the embodiments as disclosed herein.

[0074] As depicted in FIG. 6b, the notches of the two-notch bandstop filter used as the DUT are located at a frequency of 915MHz and 1.95GHz. The measured S-parameters of the DUT, post obtaining reflection coefficient and transmission coefficient, are compared against those measured by a fully calibrated E5071 VNA. The proposed network analyzer, even without any calibration, can measure both reflection coefficient (Sn) and transmission coefficient (S₂₁) of the bandstop filter quite close to the expected values for the frequency range of 800MHz to 3GHz, with a dynamic range of at least 30dB.

[0075] The elements shown in the FIGS. 1 and 6b include blocks which can be at least one of a hardware device, or a combination of hardware device and software module.

[0076] The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the embodiments as described herein.

Claims

STATEMENT OF CLAIMS We claim:

1. A system for measuring Scattering (S) -parameters of a Device under Test (DUT), the system comprising:

a signal generator for generating a microwave signal;

a harmonic suppressor for suppressing harmonics of the generated microwave signal to obtain a filtered microwave signal;

a signal separator for isolating the filtered microwave signal incident on the DUT and a reflected signal reflected by the DUT to determine a transmission coefficient and a reflection coefficient of the DUT; and

a computing unit for measuring the S -parameters of the DUT based on the determined transmission coefficient and reflection coefficient.

2. The system of claim 1, wherein the signal separator comprises of: a differential amplifier for generating a first version and a second version of the filtered microwave signal, wherein magnitude of the first version and the second version is same and phase of the first version and the second version is opposite;

a first two- section power divider and a second two- section power divider for impedance matching between the differential amplifier and a two- section power combiner;

wherein the two-section power combiner for combining the first version and second version of the filtered microwave signal, wherein the first version and second version are combined at two ports of the two- section power combiner, wherein the second version is coupled with the reflected signal from the DUT.

3. The system of claim 2, wherein the first two-section power divider is terminated at predefined load impedance and the second two-section power divider is terminated at an impedance of the DUT.

4. The system of claim 2, wherein the two- section power combiner provides an equal phase delay to incident signals at the two ports.

5. The system of claim 1, wherein the system further comprises:

a two-way power divider for splitting the power of the filtered microwave signal into two parts, wherein one part is fed to a reference power detector and the other part is fed to an impedance matching network;

a transmitted power detector for determining the power transmitted to the DUT; and

a reflected power detector for determining the power reflected by the DUT.

6. The system of claim 1, wherein the computing unit is configured to: control the generated microwave signal;

determine the power level of the reference power detector, the transmitted power detector, and the reflected power detector;

measure S -parameters of the DUT based on the determined power level at the transmitted power detector and the reflected power detector; and

cause to display the measured S-parameters.

7. The system of claim 6, wherein the computing unit is configured to receive instructions for at least one of controlling the PLL, measuring S-parameters of the DUT, and displaying the measured S-parameters through a Universal Serial Bus (USB) interface.

8. A network analyzer comprising:

a signal generator for generating a microwave signal; a harmonic suppressor for suppressing harmonics of the generated microwave signal to obtain a filtered microwave signal;

a signal separator for isolating the filtered microwave signal incident on a Device under Test (DUT) and a reflected signal reflected by the DUT to determine a transmission coefficient and a reflection coefficient of the DUT; and

9. The network analyzer of claim 8, wherein the signal separator comprises of:

a differential amplifier for generating a first version and a second version of the filtered microwave signal, wherein magnitude of the first version and the second version is same and phase of the first version and the second version is opposite;

a first two-section power divider and a second two-section power divider for impedance matching between the differential amplifier and a two- section power combiner;

10. The network analyzer of claim 9, wherein the first two-section power divider is terminated at predefined load impedance and the second two-section power divider is terminated at an impedance of the DUT.

11. The network analyzer of claim 9, wherein the two-section power combiner provides an equal phase delay to incident signals at the two ports.

12. The network analyzer of claim 8, wherein the network analyzer further comprises:

a reflected power detector for determining the power reflected by the DUT.

13. The network analyzer of claim 8, wherein the computing unit is configured to:

control the generated microwave signal;

measure S-parameters of the DUT based on the determined power level at the transmitted power detector and the reflected power detector; and

cause to display the measured S-parameters.

14. The network analyzer of claim 13, wherein the computing unit is configured to receive instructions for at least one of controlling the PLL, measuring S-parameters of the DUT, and displaying the measured S-parameters through a Universal Serial Bus (USB) interface.