WO2018104566A1

WO2018104566A1 - Digital electronic circuit for calculating sines and cosines of multiples of an angle

Info

Publication number: WO2018104566A1
Application number: PCT/ES2017/000123
Authority: WO
Inventors: David GUERRERO MARTOS; Julián VIEJO CORTÉS; Paulino RUIZ DE CLAVIJO VÁZQUEZ; Jorge JUAN CHICO; Manuel Jesús BELLIDO DÍAZ; Alejandro MILLÁN CALDERÓN; Enrique OSTUA ARANGÜENA; José Ignacio VILLAR DE OSSORNO; Juan QUIRÓS CARMONA; Alejandro Munoz Rivera
Original assignee: Universidad De Sevilla
Priority date: 2016-10-10
Filing date: 2017-10-05
Publication date: 2018-06-14
Also published as: ES2663168B2; ES2663168A1

Abstract

An electronic circuit for calculating the sines and cosines of multiples of an angle makes it possible to implement efficiently the calculation of the twiddle factors of the Fourier transform.

Description

Title

Digital electronic circuit for the calculation of sines and cosines of multiples of an angle

Object of the invention The present invention aims at a digital electronic circuit that calculates the twiddle coefficients of the Fourier transform using a subcircuit that calculates the sines and cosines of integer multiples of a particular angle comprising semiconductor memories whose total number of inputs It is of the order of the logarithm of the length of the transform. This implies considerable savings in area (components) and memory consumption in applications where the data stream is long.

It has its application in the area of electronic technology, specifically, in digital signal processing.

State of the art

Among the main objectives of the designers of digital electronic circuits are the reduction of the area occupied by them as well as the reduction of their energy consumption and the increase in their speed. The reduction of area allows reducing the production costs of the chips and generally leads to a reduction in consumption. The latter is especially important in portable equipment powered by batteries in order to increase their autonomy. Many of these teams integrate circuits that calculate sines and / or cosines of multiples of an angle. A notable example is the circuits that implement the fast Fourier transform. They require a series of complex coefficients (called twiddle or pivot) whose values are obtained from the corresponding sine / cosine pairs of certain multiples of the same angle. Since the calculation of trigonometric functions is costly in time, in hardware implementations of the transform where the speed is critical, these values are precalculated in direct access memories (usually of the ROM type). These memories can have a large number of positions as many coefficients are required as samples have the series. This is a serious penalty in area and hardware consumption of calculation of long sequence transforms, the memory size being very large compared to the rest of the components (1).

Therefore, several ways of reducing the number of positions required have been proposed:

- D. Cohen showed that a number of positions equal to half the number of samples (2) was sufficient.

- Y. Ma, L. Wanhammar, Y. Chang and K K Parhi reduced the number of positions to a quarter by storing only the angle coefficients in a quarter circumference interval. The rest is obtained easily and quickly by means of simple trigonometric relationships that only need to permute and change the sign of the components of the stored values (3) and (4).

- M. Hasan and T. Arsian reduced the number of positions to just over an eighth of the number of samples by storing only the coefficients in a range of one eighth of circumference. Again, the remaining coefficients can be quickly calculated from them by applying trigonometric relationships {5).

- T. Sansaloni, A. Pérez-Pascual, V. Torres and J Valls reduced the number of positions to exactly one eighth of the number of samples using specific hardware to detect and treat the coefficients whose reai / imaginary part has a magnitude equal to

This allows to avoid the problems derived from implementing a semiconductor memory whose size is not a power of 2 (6)

However, all these improvements require a memory of a number of positions that Imealmerite grows with the number of samples. This is inconvenient in applications where the data sequence is long such as PLC (7) or DVB-T2 (8) (with lengths of the order of

respectively) or very long as is the case of applications based on photon counting (9) or the use of radio telescopes (10) (with lengths of the order respectively).

References

(1) O. Gustafsson, "Analysis of Twiddle Factor Memory Complexity of Radix-2 Pipelined FFTs", Conference Record of the Forty-Third Asilomar Conference on Signáis, Systems and Computers, 2009. pages 217-220

(2) "Simplified control of FFT hardware", IEEE Trans. Acoust Speech Signal Process, pages 577-579, 1976

(3) "Efficient FFT implementation using digit-serial arithmetic", IEEE Workshop on Signal Processing Systems, pages 645-653, 1999 (4) "Hardware efficient control o rnemory addressing for high performance FFT processors", IEEE Trans. Signel Process, pages 917-921, 2000

(5) "Scherm for reducing size of coefficient rnemory in FFT processor", Electronics Letters, pages 907-911, February 14, 2002

(6) "Scheme for Reducmg the Storage Requirements of FFT Twtddle Factors on FPGAs", Journal of VLSI Signal Processing, pages 183-187, 2006

(7) IEEE 1901, "IEEE Standard for Broadband over Power Une Networks: Medium Access Control and Physical Layer Specifications", IEEE Communications Society, 2010.

(8) "Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system (DVB-T2)" Ref. REN / JTC DVB-308, ETSI EN 302 755 v1 3. 1, 2012

(9) Siantón, R H., "PhotonCounting - One More Time", The Society for Astronomical Scimces, 31st Annual Symposium on Telescope Science, May 22-24, 2Ό12, Big Bear Lake, CA. Society for Astronomical Sciences, 2012, pp. 177-184.

(10) Nakahara, H., Nakanishi, H., Sasao, T, "On a Wideband Fast Fourier Trasform for a Radio Telescope", ACM SIGARCH Computer Architecture News, Vol. 40, No. 5, pp. 46-51, December 2012.

Description of the figures

Figure 1 .- A subcircuit is calculated that calculates the sines and cosines of the multiples of

in the interval

that is, the powers of the complex

The subcircuit is structured in two phases and comprises four small memories

denominated Each K index memory maintains

the coefficients (sine / cosine pairs) of the multiple angles of

It has only two address lines (q = 2) and the other three memories (r = 3) have one more line. In total, these ROMs only add up to 28 memory locations. Let d be the subcircuit input (11 bits), this calculates the complex

where n is the number coded in d The bits of d are distributed between the address lines of the memories so that each of them provides the sine / cosine pair of a sub-angle

being

Ε \ complex

It is obtained by multiplying the outputs of the memories using two levels of complex multipliers (2) so that the total delay of the subcircuit is two complex multipliers.

Figure 2 - A circuit is calculated that calculates the Twiddle coefficients of the Fourier transform for length samples

following the scheme of T. Sansaloni Jan! example case The index of the coefficient to calculate is encoded in the input

The circuit comprises a subcircuit as illustrated in Figure 2 (3). A multfplexor (4a) and an adder (5) are used so that the subcircuit that returns the sines and cosines receives as input

when

or its complement to two when

A logic gate (6a) checks if the bit

it is worth 1 and the rest of the less significant bits of 8 are worth 0, in which case the magnitude returned for the sine and cosine is thanks to a pair of muitiplexers (4b). In

the last stage another logic gate (6b) calculates the logical operation EXOR of

If the value of the EXOR logic operation is 0 a pair of muitiplexers (4c) will make the magnitude of the imaginary part and the real part equal to that of the sine and the cosine calculated by the subciretiite (3) respectively. In the coniferous case, the imaginary and real magnitudes will be those of the cosine and sine respectively. The sign of the real and the imaginary part are easily calculated with simple logic gates (6e) based on

Description of the invention

The invention relates to a digital electronic circuit that calculates the twiddle coefficients of the Fourier transform. Twiddle coefficients are the sine / cosine pairs of the multiple angles of

where L is the length of the sequence on which the transform is applied That is, the twiddle coefficients are the powers of the complex

To carry it out, a subcircuit has been devised that calculates the complex

that is, the sine and cosine of nΦ being Φ a constant angle and n a coded number in base 2 that is supplied as input. It should be noted that the subcircuit can be used for trigonometric calculation in general and not: only for the calculation of twiddle coefficients. The subcircuit consists of the following components:

• semiconductor memories (usually ROM type)

■ multiplier complexes

• lines that interconnect them in the form of a tree

Let b be the subcircuit input and E the number of bits of h, N = 2 ^E different angles can be encoded. The subcircuit is structured in a number F of phases being F not greater than the logarithm in base 2 of E. In total the subcircuit comprises d = 2 ^F direct access memories that we will call

Let q be the ratio of dividing E by d and let r be the rest, from among the memories r will have q + 1 address lines. The rest will only have address lines. Let lines (M _k ) be the number of address lines of each memory k, you have

Each memory position p of the memory M _m will contain the sine and cosine of the angle

In other words, said memory position will contain the multiplex defined by

Be

the sub-circuit entry encoding the number n, to obtain the sine and cosine of ηΦ, that is, the complex

h is divided into d length chains

Notice that

where n _k denotes the number represented by the sübcadenaS _k . Therefore we have to be each angle α _k defined by

So the desired value can be calculated using the product

The address lines of each memory M _m are connected to the subentry S _m so that its output provides the complex

The value is calculated by the

multipliers from the outputs of the memories. The multipliers are arranged in parallel so that each phase introduces a delay equal to that of a complex multiplier. In the case of taking for F the value of the whole part by default of

At most, E memories of no more than two address lines would be available, so that the number of total memory locations will be bounded above by

This dimension grows logarithmically with the number of angles N.

The presented subcircuit can be used to directly calculate the twiddie coefficients of a transform of length l. taking

The number of bits of input E would be the integer part in excess of log ₂ (L) so that

If the number of the default integer part of F is taken as the number of phases F

no more than F memories of no more than two address lines would be had, so that the number of total memory locations will be bounded above by Although this alone saves a lot of resources.

with respect to the state of the art, if L is power of 2 an even more optimized circuit can be used. The optimized circuit is composed of the following elements:

· A subcircuit as described in the previous section

• Five mu! Tiplexers 2: 1

• An adder

• A set of logical doors

This circuit uses a scheme similar to that presented by T. Sansaloni so that the cases in which the multiple of Φ corresponds to the angles

They are detected with a simple logic gate and are treated separately. The gate is limited to checking whether the bit is worth 1 and the other less significant bits of β are worth

0, in which case the magnitude returned for the sine (imaginary part) and the cosine (real part) is

Bleachers to a pair of multiplexers. Unlike the T. Sansaloni scheme, this circuit does not use a ROM to obtain the sines and cosines of the multiples of

in the interval A subcircuit is used instead

as described above to calculate the sine / cosine pairs of the multiples of

in the interval this makes it possible to greatly reduce memory

necessary to implement the system In addition, since the breasts and cosines of all angles are positive in the interval

complex multipliers can be implemented using unsigned magnitude multipliers. Be the length of the transform

the input of the optimized circuit that encodes the index of the twiddle coefficient to calculate, when

the input to the subcircuit that returns the sines and cosines becomes the same as the substring

Otherwise, the complement to two of said substring is equal. For this a muitiplexer and an adder are used. A logic gate checks if the bit

it is worth 1 and the rest of the least significant bits of B are worth 0, in which case the magnitude returned for the sine and the cosine is

thanks to a pair of multiplexers connected to the saiida of the subcircuit. In the last stage a can calculate the logical operation EXOR of If 0 a pair of multiplexers will make the magnitude of the imaginary part

and of the real part equal to the sine and the cosine calculated by the subsireuito respectively. Otherwise the imaginary and real magnitudes will be those of the cosine and the sine respectively. The sign of the real part and the imaginary part is calculated with simple logic gates based on

Embodiment of the invention

As an example, FPGA (Field Programmable Gate Array) has been made a circuit that calculates the Twiddle coefficients of the Fourier transform for sequences of length

This requires knowing the sines and cosines of the integer multiples of the angle

In the scheme presented by T. Sansaloni the coefficients corresponding to the angles in the interval would be stored in a ROM

(one eighth of a circle, that is,

The ROM would have 11 address lines (E = 11) and 2048 memory locations. Instead of this ROM, the subcircuit of Figure 1 has been used, which calculates the breasts (imaginary part) and cosines (real part) of the multiples of

in the interval

using only a total of 28 memory locations. Said subcircuit is used in the circuit of Figure 2 for the calculation of the twiddle coefficients.

Claims

1. Subcircuit that calculates the complex, that is, the sine and cosine of ηΦ being constante a constant angle and n a coded number in base 2 that is supplied as input characterized in that the subcircuit consists of the following components:

• semiconductor memories {usually ROM type)

• complex multipliers

• lines that interconnect them in the form of a tree

Let b be the input of the subcircuit and E the number of bits of b, they can be encoded at different angles. The subcircuit is structured in a number F of phases being F not greater than the logarithm in base 2 of E. In total the subcircuit comprises

shortcut memories that we will call

Μ _{d - 1} . Let q be the quotient of dividing B by d and let r be the rest, among the d memories r will have q + 1 address lines. The rest will only have address lines. Let lines (M _k ) be the number of address lines of each memory k, you have

In other words, said memory location will contain the complex defined by

Let the subcircuit input encoding the number n,

to obtain the sine and cosine of nΦ, that is, the complex

b is divided into dsubcaderissS of lengths

Notice that

where m denotes the number represented by substring S _k . Therefore we have to

each angle α _{k being} defined by

The searched value is calculated by the product

The address lines of each memory M _m are connected to the subentry

Your exit provides the complex

The value

It is calculated by the multipliers from the outputs of the memerias. The multipliers are arranged in parallel to optimize the speed.

2. A circuit for the calculation of the twiddle coefficients of a Fourler transform of length L using a subcircuit as described in the preceding claim to calculate the sine / cosine pairs of the multiples of in the interval Let be the length of the transformed and be

the entry that encodes the Index of! twiddle coefficient a

calculate, characterized in that when

the input to the subcircuit that returns the breasts and cosines becomes the same as your chain

Otherwise, the complement to two of said substring is equal. For this, a multipiexor and an adder are used. A logic gate checks if the bit

it is worth 1 and the rest of the least significant bits of B are worth 0, in which case the magnitude returned for the sine and cosine is

thanks to a pair of multipiexores connected to the output of the sub-circuit. In the last stage a door calculates the logical operation EXOR of If a pair of 0 is worth

multiplexers will make the magnitude of the imaginary part and the real part equal to that of the sine and the cosine calculated by the subcircuit respectively. Otherwise the imaginary and real magnitudes will be those of the cosine and the sine respectively. The sign of the imaginary part is calculated with an inverter whose input is connected to

while that of the real part is calculated with an EXOR logic gate whose inputs are connected to