WO2018103866A1

WO2018103866A1 - Digital-to-analog converter with conversion cells converting ternary signal pairs

Info

Publication number: WO2018103866A1
Application number: PCT/EP2016/080515
Authority: WO
Inventors: Patrick Vandenameele; Sofia VATTI; Johannes SAMSOM; Koen Cornelissens; Paul STYNEN; Enrico ROVERATO; Marko Kosunen; Jussi Ryynänen
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2016-12-09
Filing date: 2016-12-09
Publication date: 2018-06-14
Also published as: CN110050411B; CN110050411A

Abstract

The disclosure relates to a digital-to-analog converter, DAC (100) for converting a digital input signal (x[n], 110) to an analog output signal (y), the DAC (100) comprising: an encoder (102), configured to generate a pair of ternary signals (c1[n], c2[n], 103, 104) based on the digital input signal (110); and a pair of single bit DACs (105, 106) coupled to the encoder (102) and configured to convert the pair of ternary signals (103, 104) to a pair of analog output states (y1[n], y2[n], 107, 108), wherein each ternary signal (103, 104) of the pair of ternary signals (103, 104) comprises a high, a zero and a low state producing a corresponding output state (107, 108) at the single bit DAC (105, 106) coupled with the respective ternary signal (103, 104).

Description

Digital-to-Analog Converter with conversion cells converting ternary signal pairs

TECHNICAL FIELD

The present disclosure relates to a Digital-to-Analog Converter (DAC), in particular a Radio Frequency DAC, with a plurality of conversion cells converting ternary signal pairs. The disclosure further relates to a digital transmitter, in particular an all-digital RF transmitter including such a DAC. The disclosure particularly relates to a method to perform Dynamic Element Matching (DEM) in digital transmitters for improved power efficiency.

BACKGROUND Multi-bit RF-DACs (Radio Frequency Digital to Analog Converters) having a design according to Figs. 1 or 2 use multiple conversion cells 105, 106 to convert digital signals 110 to analog RF 120 in digital transmitters. The mismatch in these conversion cells 105, 106, arising due to imperfections inherent to all fabrication processes, results in a nonlinear mismatch error being introduced in the output. DEM (Dynamic Element

Matching) is a technique used to attenuate the effects of this nonlinearity inherent to multi- bit RF-DACs. The basic idea behind DEM is to scramble the order of the conversion cells in a RF-DAC on a sample-by-sample basis, in order to convert the nonlinearity caused by static mismatches into pseudorandom noise. Optionally, the power density of this noise can be also spectrally shaped, a process known as mismatch error shaping.

A quite apparent problem with the use of common DEM encoders is the excessive power usage in the RF-DAC stage even when the output is zero. The zeros here are generated using addition of high and low outputs of conversion cells. As a result excessive power is used, even to generate zeros.

In the prior art the DEM has been used in what are called fully differential RF-DACs, the RF-DACs made up of single bit conversion cells with only 2 output states: high (or +1 ) and low (or -1 ). A simple three level RF-DAC 100 along with the DEM encoder 102 is shown in Figure 1 . The equations governing the indicated signals are:

It is quite clear from Figure 1 and the above mentioned equations that in order to produce zero output (y[n] = 0), both the 1-b DACs 105, 106 have to be used, with one set to high output and the other to low output and their simple sum providing zero. This is the biggest disadvantage of this art: the use of both high and low values to generate zero output. This results in an excessive power consumption even to generate zeros.

The example of Figure 1 is a very simplified case, used here for the sake of explaining the basic concept. The simple structure of figure 1 will cause the DEM encoder's 102 complexity and the number of 1-b DACs 105, 106 to increase exponentially with increase in the RF-DAC resolution.

A workaround to this problem is the use of segmented DEM RF-DACs, e.g. as described by K. L. Chan et al., "Segmented dynamic element matching for high-resolution digital-to- analog conversion," IEEE TCAS-I, Dec. 2008, and shown in Fig. 2. Segmented DEM RF- DACs have 1 -b DACs in groups with unary/binary weights assigned to each group. They also have a modified structure for DEM encoders. A fully segmented DEM for a 14 bit high resolution DAC, however, has severe range restrictions on DEM encoded input to DAC, which results in higher power dissipation at a given SNR (Signal to Noise Ratio). Therefore, a trade off or balance has to be maintained between the unary and binary weighted parts of the DEM RF-DAC.

In this disclosure, the terms "conversion cells" and "1 -bit DAC" are always used as synonyms. Therefore, a conversion cell is just a circuit that converts a digital signal into analog form, with two (fully differential) or three (pseudo differential) possible output values. The DEM encoder is a digital circuit, which encodes the global digital input signal into the individual digital signals for each conversion cell. Therefore, there is only one DEM encoder for the whole system, which is external to the conversion cells.

Referring to Figures 1 and 2, Fig. 1 depicts a DAC with a DEM encoder and two conversion cells. Fig. 2 depicts a DAC with a DEM encoder and 28 conversion cells. Fig. 2 also shows the internal structure of the DEM encoder. Therefore, Fig. 1 is just a simplified version of Fig. 2, used to explain the basic concept.

SUMMARY

It is the object of the invention to provide design techniques for low complexity digital-to- analog converters (DAC), in particular DEM RF-DACs, providing high linearity at reduced power consumption.

This object is achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

A basic idea of the invention is to solve the excessive power usage problem described above by modifying the DEM encoder in such a way that it allows for the individual conversion cells to be set to zero. In this disclosure the problem of excessive power consumption to generate zeros is directly addressed. The solution is to use 1 -b DACs that have the ability to produce zeros, called pseudo differential RF-DACs. Referring again to Figure 1 , it is quite clear that if the 1-b DACs 105, 106 have three output states: high (or +1 ), zero and low (or -1 ) the results will be quite power efficient. Here zeros will be generated directly without the excessive power needed to generate both high and low outputs. In order to realize this change, the disclosure presents an adaptation of the DEM encoder in such a way that it can work with pseudo differential RF-DACs, where 1-b DAC cells can produce zeros.

In order to describe the invention in detail, the following terms, abbreviations and notations will be used:

RF: Radio Frequency

DAC: Digital-to-Analog Converter

DEM: Dynamic Element Matching

MSB: Most Significant Bit

LSB: Least Significant Bit

LTE: Long Term Evolution (specification)

E-UTRA: evolved UMTS Terrestrial Radio Access, air interface for LTE

PAPR: Peak-to-Average Power Ratio

WCDMA Wideband Code Division Multiple Access

According to a first aspect, the invention relates to a digital-to-analog converter (DAC) for converting a digital input signal to an analog output signal, the DAC comprising: an encoder, configured to generate a pair of ternary signals based on the digital input signal; and a pair of single bit DACs coupled to the encoder and configured to convert the pair of ternary signals to a pair of analog output states, wherein each ternary signal of the pair of ternary signals comprises a high, a zero and a low state producing a corresponding output state at the single bit DAC coupled with the respective ternary signal.

Such a DAC can be implemented as a low complexity DAC, e.g. as a DEM RF-DAC, providing high linearity at reduced power consumption. The excessive power usage problem is solved by modifying the DEM encoder in such a way that it allows for the individual conversion cells to be set to zero, i.e. by using the above described ternary signal which includes the three states: high, zero and low. This allows producing an output signal by applying the zero state. In a first possible implementation form of the DAC according to the first aspect, the DAC comprises an adder configured to add the analog output states of the pair of analog output states to generate an analog output contributing to the analog output signal. The adder can be used to add contributions from different conversion cells allowing the implementation of multiple dynamic element matching which improves resolution and linearity.

In a second possible implementation form of the DAC according to the first

implementation form of the first aspect, the adder is configured to produce an analog output of zero when both ternary signals of the pair of ternary signals have a zero state.

Allowing the individual conversion cells to be set to zero reduces the power consumption of the DAC. It is quite clear that if the 1-b DACs have three output states: high (or +1 ), zero and low (or -1 ) the results will be quite power efficient. Here zeros will be generated directly without the excessive power needed to generate both high and low outputs.

In a third possible implementation form of the DAC according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the DAC is configured to set both single bit DACs of the pair of single bit DACs to zero to produce a zero output.

Producing a zero output by setting both single bit DACs to zero is more power efficient than producing a zero output by setting one single bit DAC to a positive power state (high) and the other one to a negative power state (low).

In a fourth possible implementation form of the DAC according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, The DAC is configured to produce a pair of analog output states having five output levels.

This provides the advantage of having a higher flexibility for producing the output signal.

In a fifth possible implementation form of the DAC according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the DAC is configured to produce a pair of analog output states (y1 [n], y2[n]) for a pair of ternary ignals (c1 [n], c2[n]) according to the following equations:

where Δ denotes an analog output step.

This provides the advantage of a higher resolution for producing the output signal when five output states can be used.

In a sixth possible implementation form of the DAC according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the encoder comprises a plurality of encoder cells which are cascaded forming a segmented tree structured dynamic element matching (DEM) encoder.

Such a DEM encoder structure reduces the complexity since it avoids an exponential increase with DAC resolution.

In a seventh possible implementation form of the DAC according to the sixth

implementation form of the first aspect, each encoder cell of the plurality of encoder cells forms one of a non-segmenting switching block and a segmenting switching block of the segmented tree structured DEM encoder.

This provides the advantage that the DAC using non-segmenting switching blocks and segmenting switching blocks can efficiently shape the mismatch errors, thereby increasing accuracy. In an eighth possible implementation form of the DAC according to the seventh implementation form of the first aspect, at least a portion of the non-segmenting switching blocks and the segmenting switching blocks is configured to switch their input signal into two components based on a switching sequence.

By switching the input signals into two components based on an appropriate switching sequences, the outputs of the conversion cells can be designed to have similar properties as the digital input signal. This results in a high precision digital-to-analog conversion. In a ninth possible implementation form of the DAC according to the eighth

implementation form of the first aspect, a first component of a segmenting switching block corresponds to the switching sequence, and a second component of the segmenting switching block corresponds to a weighted combination of the input signal and the inverse switching sequence.

This provides the advantage that a recursive scheme can be implemented for shaping the mismatch error and thus increasing the precision.

In a tenth possible implementation form of the DAC according to the eighth or the ninth implementation form of the first aspect, a first component of a non-segmenting switching block corresponds to a weighted combination of the input signal and the switching sequence, and a second component of the non-segmenting switching block corresponds to a weighted combination of the input signal and the inverse switching sequence. This provides the advantage that these non-segmenting and segmenting switching blocks produce the encoded digital samples in such a way that the conversion cells can be set to three states (high, zero and low) as described above.

In an eleventh possible implementation form of the DAC according to any of the eighth to the tenth implementation forms of the first aspect, each of the non-segmenting switching blocks and the segmenting switching blocks comprises a switching sequence generator configured to generate the switching sequence.

This provides the advantage that the switching sequence generator can flexibly generate different switching sequences according to specific constraints. In a twelfth possible implementation form of the DAC according to the eleventh implementation form of the first aspect, the switching sequence generator is configured to generate the switching sequence as a pseudo random sequence for shaping mismatch errors of the DAC.

This provides the advantage that a switching sequence generated as a pseudo random sequence can efficiently shape the mismatch errors of the DAC, and thus reduce noise and interference and improve accuracy.

In a thirteenth possible implementation form of the DAC according to any of the seventh to the twelfth implementation forms of the first aspect, each non-segmenting switching block is configured to process the following switching sequence equation:

and each segmenting switching block is configured to process the following switching sequence equation:

where denotes a switching sequence of a non-segmenting block, denotes

an input sequence of a non-segmenting block, denotes a switching sequence of a

segmenting block and denotes an input sequence of a segmenting block.

These modified equations produce the encoded digital samples in such a way that the conversion cells inside the RF-DAC can be set to three states (high, zero and low).

Moreover, only those 1-b DACs are turned on (set to high (or +1 ) or low (or -1 )) that contribute directly to the output generation. All the other 1-b DACs are turned off (set to zero) and hence this pseudo differential DEM RF-DAC doesn't use up excessive power.

According to a second aspect, the invention relates to a digital transmitter, comprising: a delta-sigma modulator, configured to modulate a radio signal based on a delta modulation to provide a digital input signal; and a DAC according to the first aspect as such or according to any of the implementation forms of the first aspect, configured to convert the digital input signal to an analog output signal. Such a digital transmitter utilizes a DAC that can be implemented as a low complexity

DAC, e.g. as a DEM RF-DAC, providing high linearity at reduced power consumption. The DEM encoder of the DAC is modified in such a way that it allows for the individual conversion cells to be set to zero, i.e. by using the above described ternary signal which includes the three states: high, zero and low. This allows producing an output signal by applying the zero state, i.e., using nearly zero power.

BRIEF DESCRIPTION OF THE DRAWINGS Further embodiments of the invention will be described with respect to the following figures, in which:

Fig. 1 shows a block diagram illustrating a basic structure of a digital-to-analog converter (DAC) 100 according to an implementation form;

Fig. 2 shows a block diagram illustrating a digital-to-analog converter (DAC) 200 with cascaded structure according to an implementation form;

Figs. 3a and 3b show block diagrams illustrating segmenting 300a and non-segmenting 300b switching blocks for a fully differential DEM RF-DAC;

Figs. 4a and 4b show block diagrams illustrating exemplary segmenting 400a and non- segmenting 400b switching blocks for a DAC 100, 200 according to the disclosure; Fig. 5 shows a block diagram illustrating the digital part of a digital transmitter 500 according to an implementation form;

Fig. 6 shows output spectra of a DAC according to the disclosure with 20 MHz bandwidth of LTE signals; and Fig. 7 shows output spectra of a DAC according to the disclosure with 15 MHz bandwidth of LTE signals.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

Fig. 1 shows a block diagram illustrating a basic structure of a digital-to-analog converter (DAC) 100 according to an implementation form. The DAC 100 can convert a digital input signal x[n], 1 10 to an analog output signal y. The DAC 100 includes an encoder 102 and a pair of single bit DACs 105, 106. The encoder 102 is configured to generate a pair of ternary signals c1 [n], c2[n], 103, 104 based on the digital input signal 1 10. The pair of single bit DACs 105, 106, which is coupled to the encoder 102, is configured to convert the pair of ternary signals 103, 104 to a pair of analog output states y1 [n], y2[n], 107, 108. Each ternary signal 103, 104 of the pair of ternary signals 103, 104 includes a high, a zero and a low state producing a

corresponding output state 107, 108 at the single bit DAC 105, 106 coupled with the respective ternary signal 103, 104. The DAC 100 may further include an adder 109 to add the analog output states 107, 108 of the pair of analog output states 107, 108 to generate an analog output y[n], 120 contributing to the analog output signal. The adder 109 may produce an analog output 120 of zero when both ternary signals 103, 104 of the pair of ternary signals 103, 104 have a zero state.

The DAC 100 may be configured to set both single bit DACs 105, 106 of the pair of singl bit DACs 105, 106 to zero to produce a zero output. The DAC 100 may be configured to produce a pair of analog output states 107, 108 having five output levels, e.g. as described below with respect to Fig. 4.

The DAC 100 may be configured to produce a pair of analog output states 107, 108 for a pair of ternary signals 103, 104 according to the following equations as described below with respect to Fi . 4:

where Δ denotes an analog output step.

The encoder 102 may include a plurality of encoder cells which may be cascaded forming a segmented tree structured dynamic element matching (DEM) encoder 210 as described below with respect to Fig. 2. Each encoder cell 102, 213, 214, 215, 216, 217, 218, 219 of the plurality of encoder cells may form a non-segmenting switching block 400b or a segmenting switching block 400a of the segmented tree structured DEM encoder 210 as further described below with respect to Figures 4a and 4b. At least a portion of the non-segmenting switching blocks 400b and the segmenting switching blocks 400a may be configured to switch their input signal 31 1 , 301 into two components 318, 319, 306, 307 based on a switching sequence 313, 403 as further described below with respect to Figures 3 and 4. A first component 306 of a segmenting switching block 400a may correspond to the switching sequence 403, and a second component 307 of the segmenting switching block 400a may correspond to a weighted 305 combination 304 of the input signal 301 and the inverse switching sequence 403 as described below with respect to Figures 3 and 4. A first component 318 of a non- segmenting switching block 400b may correspond to a weighted 316 combination 314 of the input signal 31 1 and the switching sequence 313, and a second component 319 of the non-segmenting switching block 400b may correspond to a weighted 317 combination 315 of the input signal 31 1 and the inverse switching sequence 313 as described below with respect to Figures 3 and 4. Each of the non-segmenting switching blocks 400b and the segmenting switching blocks 400a may include a switching sequence generator configured to generate the switching sequence 313, 403 as described below with respect to Figures 3 and 4. The switching sequence generator may be configured to generate the switching sequence 313, 403 as a pseudo random sequence for shaping mismatch errors of the DAC 100, 200 as described below with respect to Figures 3 and 4.

Each non-segmenting switching block 400b may be configured to process the following switching sequence (313) equation:

and each segmenting switching block 400a may be configured to process the following switching sequence (403) equation:

where denotes a switching sequence 313 of a non-segmenting block 400b,

denotes an input sequence 31 1 of a non-segmenting block 400b, denotes a

switching sequence 403 of a segmenting block 400a and denotes an input

sequence 301 of a segmenting block 400a as further described below with respect to Figures 3 and 4. Fig. 2 shows a block diagram illustrating a digital-to-analog converter (DAC) 200 with cascaded structure according to an implementation form.

Figure 2 shows a 10-bit DEM RF-DAC implementation 200 with trade-off between segmenting and non-segmenting parts. The 4 MSBs are unary weighted and 6 LSBs are binary weighted. The DEM encoder 210 includes 6 segmenting blocks 215, 214, 213 from Ss,i to Sio,i and 21 non segmenting blocks 216, 217, 218, 219 represented as Sk,_r with k = 1 , ...,4 and r = 1 , ...14. This structure of DEM encoder 210 is also referred to as tree encoder.

The tree encoder of Fig. 2 includes of a cascade of segmenting 215, 214, 213 and non- segmenting 216, 217, 218, 219 switching blocks. The function of a non-segmenting switching block 216, 217, 218, 219 (see also Fig. 3b) is to split its input signal into two components, according to:

where is a switching sequence generated within the block, which satisfies:

Likewise, the outputs of a segmenting switching block (see Fig. 3a) are given by:

where the switching sequence s constrained by:

The basic working principle of the tree structure encoder can be described as follows. Let be the encoder input, which is a linear mapping of the modulator output to the set of nonnegative integers belonging to the encoder's maximum linear range. By applying recursively the above described equations of the non-segmenting switching blocks and the segmenting switching blocks, it can be demonstrated that if the spectral densities of all switching sequences show a notch at the RX-band similar to that of the input signal x[n]

201 of the tree structure encoder 210, then the 1 -bit outputs

share the same property.

Figs. 3a and 3b show block diagrams illustrating segmenting 300a and non-segmenting 300b switching blocks for a fully differential DEM RF-DAC having the structure as described above with respect to Fig. 2.

In a segmenting switching block 300a an input signal 301 is switched (or split) into two components 306, 307 based on a switching sequence 303. The switching sequence 303 corresponds to the first component 306. The switching sequence 303 is subtracted from the input signal 301 by using an inverse adder 304 and weighted by 0.5 by using an amplifier 305 to produce the second component 307.

In a non-segmenting switching block 300b an input signal 31 1 is switched (or split) into two components 318, 319 based on a switching sequence 313. The switching sequence 313 is added to the input signal 31 1 , by using an adder 314, and weighted by a factor 0.5, by using a first amplifier 316 to produce the first component 318. The switching sequence 313 is subtracted from the input signal 31 1 by using an inverse adder 315 and weighted by a factor 0.5 by using a second amplifier 317 to produce the second component 319.

In the prior art, e.g. as described by E. Roverato et al., "RX-band noise reduction in all- digital transmitters with configurable spectral shaping of quantization and mismatch errors," IEEE TCAS-I, Nov. 2014, the tree DEM encoder, split into binary and unary weighted parts, is used only in a fully differential DEM RF-DAC.

In this disclosure, an adaptation of the tree DEM encoder structure is presented in such a way that it can also be used for the pseudo differential RF-DACs. This adaptation of tree DEM encoder requires changing the internal structure of the switching blocks.

Figures 3a and 3b show the internal structures of segmenting 300a and non-segmenting 300b switching blocks for a fully differential DEM RF-DAC. The switching sequence Sk,_r[n] is a pseudo random sequence which shapes the mismatch errors. This switching sequence can be generated in several possible ways, however it must obey a set of constraints. The equations describing such constraints are different for pseudo and fully differential DEM RF-DACs.

The switching sequence equations for a fully differential DEM RF-DAC

1 ) For the segmenting switching blocks:

2) For the non-segmenting switching blocks:

The internal structures of segmenting and non-segmenting switching blocks 300a, 300b adapted for a pseudo-differential DEM RF-DAC according to the disclosure are described below with respect to Figures 4a and 4b.

Figs. 4a and 4b show block diagrams illustrating exemplary segmenting 400a and non- segmenting 400b switching blocks for a DAC 100, 200 according to the disclosure.

The switching sequence equations for a pseudo-differential DEM RF-DAC according to this disclosure are:

1 ) for the segmenting switching blocks:

2) for the non-segmenting switching blocks

The internal structures of segmenting and non-segmenting switching blocks 400a, 400b adapted for the pseudo-differential DEM RF-DAC according to this disclosure are shown in Figures 4a and 4b.

These modified equations produce the encoded digital samples in such a way that the conversion cells inside the RF-DAC can be set to three states (high, zero and low). Moreover, only those 1-b DACs are turned on (set to high (or +1 ) or low (or -1 )) that contribute directly to the output generation. All the other 1-b DACs are turned off (set to zero) and hence this pseudo differential DEM RF-DAC doesn't use up excessive power.

Referring back to Fig. 1 , the pseudo differential DEM RF-DAC implementation will now result in following equations governing the indicated signals:

It is quite clear now that if the pseudo differential DEM RF-DAC implementation is used there are 5 output levels instead of the 3 output levels previously available. These 2 extra output levels are +Δ/2 and -Δ/2 and can be produced by any one of the 1-b DACs set to high (or +1 ) and low (or -1 ) respectively with the other 1-b DAC set to zero. It also becomes quite clear that to produce zero both the 1-b DACs have to be just set to zero, not using any excessive power.

Fig. 5 shows a block diagram illustrating the digital part of a digital transmitter 500 according to an implementation form.

The digital transmitter 500 includes a delta-sigma modulator 502 to modulate a radio signal 501 based on a delta modulation to provide a digital input signal 503, for example as a 10 bit signal as shown in Fig. 5. The digital transmitter 500 further includes a DAC 504, 507, e.g. a DAC 100, 200 as described above with respect to Figures 1 and 2, to convert the digital input signal 503 to an analog output signal 508. This DAC may include a DEM encoder 504 for encoding the digital input signal 503 as described above with respect to Figures 1 and 2 to generate MSBs (most significant bits), e.g. according to the MSB segment 222 depicted in Fig. 2 and LSBs (least significant bits), e.g. according to the LSB segment 221 depicted in Fig. 2. This DAC may further include an RF-DAC 507 for digital-analog converting the MSBs 505 and the LSBs 506 to generate the analog output signal RFout 508.

Fig. 6 shows output spectra of a DAC according to the disclosure with 20 MHz bandwidth of LTE signals. Fig. 7 shows output spectra of a DAC according to the disclosure with 15 MHz bandwidth of LTE signals. As a verification of the presented pseudo differential DEM RF-DAC performance, system level simulations were carried out. The basic simulation setup is shown in figure 6. The system is an all-digital RF transmitter for 4G applications, where DEM is used to attenuate the nonlinearity caused by analog mismatches between the conversion cells in the multi- bit RF-DAC.

In the simulations, LTE signals of bandwidths 20 (Fig. 6) and 15 MHz (Fig. 7) are converted to E-UTRA bands 1 and 3 respectively. The spectra of signals at the output of the pseudo differential RF-DAC are shown in the Figure 6. The RX-band noise values for Fig. 6 are: RX-band noise of ideal RF-DAC (graph 601 ) = -182.3277 dBc/Hz; RX-band noise of real RF-DAC, without DEM (graph 602) = -151 .8763 dBc/Hz; RX-band noise of real RF-DAC, with DEM (graph 603) = -157.7007 dBc/Hz.

Similarly the RX-band noise values for Fig. 7 are: RX-band noise of ideal RF-DAC (graph 701 ) = -184.7596 dBc/Hz; RX-band noise of real RF-DAC, without DEM (graph 702) = - 148.8152 dBc/Hz; RX-band noise of real RF-DAC, with DEM (graph 703) = -163.2539 dBc/Hz.

Comparing these results with the results described E. Roverato et al., "RX-band noise reduction in all-digital transmitters with configurable spectral shaping of quantization and mismatch errors," IEEE TCAS-I, Nov. 2014, it is clear that the presented pseudo differential DEM RF-DAC provides the above described advantages, i.e. a low complexity DEM RF-DACs providing high linearity at reduced power consumption. The lower power consumption can be explained in practice by the fact that a fully differential DEM RF-DAC always consumes the peak power (since many cells have to be kept turned on, so that the peak amplitude of the signal can be accommodated), whereas a pseudo differential one consumes just the actual needed power (the rms value). So a DAC according to this disclosure is advantageous especially for signals with high PAPR (Peak-to-Average Power Ratio), like LTE or WCDMA signals in modern

communication systems. For a full-scale input signal, the power consumption saved should be exactly equal to the PAPR. For example, in the simulations of figures 6 and 7, the PAPR of the full-scale LTE signals is 8.5 dB, meaning that the power consumed in the pseudo differential case is 8.5 dB less than the power consumed in the fully differential case (or equivalently, the saving is 86%). For an input signal with amplitude smaller than full-scale, the power consumption saving is even higher.

Further generalized implementations can be applied to the above described pseudo differential DEM RF-DAC: The same technique can be applied to baseband DACs. DEM is not required on the entire RF-DAC. Since the contribution of the LSB mismatches on the total RF-DAC error is minor, DEM can be disabled on some LSBs. The RF-DAC is not always fed with full-scale signals, but sometimes the input signal is scaled down to allow for backoff operation. Part of the DEM encoder may be disabled during backoff, in order to save power. Besides pseudo and fully differential, other modes of operation are possible, where all three conversion cell states -1 , 0, +1 are allowed simultaneously. This allows more randomization for DEM (thus making it more effective), while representing a compromise between the power consumption of pseudo and fully differential modes. The present disclosure also supports a method for converting a digital input signal x[n], 1 10 to an analog output signal, by a digital-to-analog converter, DAC 100. The method includes: generating, by an encoder 102, a pair of ternary signals c1 [n], c2[n], 103, 104 based on the digital input signal 1 10. The method further includes: converting, by a pair of single bit DACs 105, 106 coupled to the encoder 102, the pair of ternary signals 103, 104 to a pair of analog output states y1 [n], y2[n], 107, 108, wherein each ternary signal 103, 104 of the pair of ternary signals 103, 104 comprises a high, a zero and a low state producing a corresponding output state 107, 108 at the single bit DAC 105, 106 coupled with the respective ternary signal 103, 104. The method allows performing the further functionality of the DAC 100, 200 as described above.

The present disclosure also supports a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the performing and computing steps described herein, in particular the steps of the method described above. Such a computer program product may include a readable non-transitory storage medium storing program code thereon for use by a computer. The program code may perform the method described above.

While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms "coupled" and "connected", along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other. Although specific aspects have been illustrated and described herein, it will be

appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the invention beyond those described herein. While the present invention has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the present invention. It is therefore to be understood that within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described herein.

Claims

CLAIMS:

1. A digital-to-analog converter, DAC (100) for converting a digital input signal (x[n], 1 10) to an analog output signal (y), the DAC (100) comprising: an encoder (102), configured to generate a pair of ternary signals (c1 [n], c2[n],

103, 104) based on the digital input signal (1 10); and a pair of single bit DACs (105, 106) coupled to the encoder (102) and configured to convert the pair of ternary signals (103, 104) to a pair of analog output states (y1 [n], y2[n], 107, 108), wherein each ternary signal (103, 104) of the pair of ternary signals (103, 104) comprises a high, a zero and a low state producing a corresponding output state (107, 108) at the single bit DAC (105, 106) coupled with the respective ternary signal (103, 104).

2. The DAC (100) of claim 1 , comprising: an adder (109) configured to add the analog output states (107, 108) of the pair of analog output states (107, 108) to generate an analog output (y[n], 120) contributing to the analog output signal (y, 202).

3. The DAC (100) of claim 2, wherein the adder (109) is configured to produce an analog output (120) of zero when both ternary signals (103, 104) of the pair of ternary signals (103, 104) have a zero state.

4. The DAC (100) of one of the preceding claims, configured to set both single bit DACs (105, 106) of the pair of single bit DACs (105, 106) to zero to produce a zero output.

5. The DAC (100) of one of the preceding claims, configured to produce a pair of analog output states (107, 108) having five output levels.

6. The DAC (100) of one of the preceding claims, configured to produce a pair of analog output states (107, 108) for a pair of ternary signals (103, 104) according to the following equations:

where Δ denotes an analog output step.

7. The DAC (100, 200) of one of the preceding claims, wherein the encoder comprises a plurality of encoder cells (102, 213, 214, 215, 216, 217, 218, 219)which are cascaded forming a segmented tree structured dynamic element matching (DEM) encoder (210).

8. The DAC (100, 200) of claim 7, wherein each encoder cell (102, 213, 214, 215, 216, 217, 218, 219) of the plurality of encoder cells forms one of a non-segmenting switching block (400b) and a segmenting switching block (400a) of the segmented tree structured DEM encoder (210).

9. The DAC (100, 200) of claim 8, wherein at least a portion of the non-segmenting switching blocks (400b) and the segmenting switching blocks (400a) is configured to switch their input signal (31 1 , 301 ) into two components (318, 319, 306, 307) based on a switching sequence (313, 403).

10. The DAC (100, 200) of claim 9, wherein a first component (306) of a segmenting switching block (400a) corresponds to the switching sequence (403), and wherein a second component (307) of the segmenting switching block (400a) corresponds to a weighted (305) combination (304) of the input signal (301 ) and the inverse switching sequence (403).

1 1. The DAC (100, 200) of claim 9 or 10, wherein a first component (318) of a non-segmenting switching block (400b) corresponds to a weighted (316) combination (314) of the input signal (31 1 ) and the switching sequence (313), and wherein a second component (319) of the non-segmenting switching block (400b) corresponds to a weighted (317) combination (315) of the input signal (31 1 ) and the inverse switching sequence (313).

12. The DAC (100, 200) of one of claims 9 to 1 1 , wherein each of the non-segmenting switching blocks (400b) and the segmenting switching blocks (400a) comprises a switching sequence generator configured to generate the switching sequence (313, 403).

13. The DAC (100, 200) of claim 12, wherein the switching sequence generator is configured to generate the switching sequence (313, 403) as a pseudo random sequence for shaping mismatch errors of the DAC (100, 200).

14. The DAC (100, 200) of one of claims 8 to 13, wherein each non-segmenting switching block (400b) is configured to process the following switching sequence (313) equation:

wherein each segmenting switching block (400a) is configured to process the following switching sequence (403) equation:

where denotes a switching sequence (313) of a non-segmenting block

(400b),

denotes an input sequence (31 1 ) of a non-segmenting block (400b),

denotes a switching sequence (403) of a segmenting block (400a) and denotes an

input sequence (301 ) of a segmenting block (400a).

15. A digital transmitter (500), comprising:

A delta-sigma modulator (502), configured to modulate a radio signal (501 ) based on a delta modulation to provide a digital input signal (503); and a DAC (504, 507) according to one of the preceding claims, configured to convert the digital input signal (503) to an analog output signal (508).