WO2018100642A1 - Display panel, thin-film transistor, and method of manufacturing thin-film transistor - Google Patents

Display panel, thin-film transistor, and method of manufacturing thin-film transistor Download PDF

Info

Publication number
WO2018100642A1
WO2018100642A1 PCT/JP2016/085415 JP2016085415W WO2018100642A1 WO 2018100642 A1 WO2018100642 A1 WO 2018100642A1 JP 2016085415 W JP2016085415 W JP 2016085415W WO 2018100642 A1 WO2018100642 A1 WO 2018100642A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode film
film transistor
thin film
drain electrode
semiconductor layer
Prior art date
Application number
PCT/JP2016/085415
Other languages
French (fr)
Japanese (ja)
Inventor
英俊 中川
Original Assignee
堺ディスプレイプロダクト株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 堺ディスプレイプロダクト株式会社 filed Critical 堺ディスプレイプロダクト株式会社
Priority to PCT/JP2016/085415 priority Critical patent/WO2018100642A1/en
Publication of WO2018100642A1 publication Critical patent/WO2018100642A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements

Definitions

  • the present invention relates to a display panel, a thin film transistor, and a method for manufacturing the thin film transistor.
  • liquid crystal display which is a representative flat panel display, is widely used not only in the field of medium-sized panels or small panels but also in the field of large panels for TVs and the like.
  • an active matrix type liquid crystal display device is widely used.
  • a display panel of an active matrix liquid crystal display device includes a plurality of source bus lines (video signal lines), a plurality of gate bus lines, a pixel formation portion, and the like.
  • the pixel formation portion is provided at a location where a plurality of source bus lines and a plurality of gate bus lines intersect, and is arranged in a matrix.
  • Each pixel forming unit includes a pixel thin film transistor and a pixel capacitor for holding a pixel voltage value.
  • the gate terminal of the pixel thin film transistor is connected to a gate bus line that passes through a location where the gate bus line and the source bus line intersect. Further, the source terminal of the pixel thin film transistor is connected to a source bus line passing through the portion.
  • the active matrix liquid crystal display device includes a gate driver for driving a gate bus line, a source driver for driving a source bus line, and the like.
  • the gate driver (driving circuit) has a configuration in which a plurality of shift registers are connected so that the plurality of gate bus lines are sequentially selected for a predetermined period.
  • the gate driver sequentially outputs a drive signal from each stage shift register to each gate bus line based on a plurality of clock signals (see Patent Document 1).
  • the present invention has been made in view of such circumstances, and an object of the present invention is to provide a display panel capable of preventing performance deterioration due to mixing of minute foreign matter, a thin film transistor constituting the display panel, and a method of manufacturing the thin film transistor. To do.
  • a display panel is a display panel including a thin film transistor that supplies a driving voltage for turning on / off a pixel thin film transistor corresponding to each of a plurality of pixels arranged in a matrix on a substrate.
  • the thin film transistor includes a gate electrode film formed on the surface of the substrate, a semiconductor layer formed on the gate electrode film, a long source electrode film formed on the semiconductor layer, A plurality of elongated drain electrode films formed on the semiconductor layer, and a width of at least one of the plurality of drain electrode films is larger than a width of the source electrode film.
  • a thin film transistor is a thin film transistor that supplies a driving voltage for turning on / off a thin film transistor for a pixel corresponding to each of a plurality of pixels arranged in a matrix on a substrate.
  • a width of at least one of the plurality of drain electrode films is larger than a width of the source electrode film.
  • a method of manufacturing a thin film transistor according to an embodiment of the present invention is a method of manufacturing a thin film transistor that supplies a driving voltage for turning on / off a pixel thin film transistor corresponding to each of a plurality of pixels arranged in a matrix on a substrate.
  • a gate electrode film is formed on the surface of the substrate; a semiconductor layer is formed on the gate electrode film; a long source electrode film is formed on the semiconductor layer; and
  • a plurality of long drain electrode films including at least one long drain electrode film having a width larger than the width of the source electrode film is formed.
  • FIG. 5 is a schematic cross-sectional view of a main part viewed from the line VV in FIG.
  • FIG. 5 is a schematic cross-sectional view of a main part viewed from the line VV in FIG.
  • FIG. 5 is a principal part plane schematic diagram which shows an example of the structure of the thin-film transistor as a comparative example. It is explanatory drawing which shows an example of the manufacturing method of the thin-film transistor of this Embodiment.
  • FIG. 1 is a schematic diagram illustrating an example of a main configuration of a display panel 100 according to the present embodiment.
  • the display panel 100 includes a pixel unit 50 in which a plurality of pixels are arranged in a matrix, a gate circuit unit 60 and a source terminal unit 70 arranged around the pixel unit 50, and the like.
  • the source terminal unit 70 includes a plurality of terminals to which signal lines from a source circuit (not shown) outside the display panel 100 are connected.
  • the pixel portion 50 and the gate circuit portion 60 are formed on a thin film transistor (TFT) substrate (also referred to as a TFT substrate).
  • TFT thin film transistor
  • a liquid crystal display panel will be described as an example of the display panel 100, but the display panel 100 is not limited to the liquid crystal display panel.
  • the pixel unit 50 is provided with a pixel thin film transistor (also referred to as TFT) corresponding to each pixel.
  • the pixel thin film transistor of the pixel unit 50 is a transistor for supplying a current that changes the luminance of each pixel. Note that changing the luminance of each pixel is synonymous with changing the transmittance of each pixel.
  • the gate circuit unit 60 includes a thin film transistor that supplies a driving voltage (gate voltage) for turning on and off the pixel thin film transistor of the pixel unit 50.
  • a driving thin film transistor that supplies a driving voltage (gate voltage) for turning on / off the pixel thin film transistor is simply referred to as a thin film transistor in order to distinguish from the pixel thin film transistor.
  • the thin film transistor has a function of controlling switching (on / off control) of the pixel thin film transistor of the pixel portion 50 and selecting which pixel luminance is changed.
  • a source circuit (not shown) connected to the source terminal unit 70 supplies a signal voltage to the pixel thin film transistor of the pixel unit 50, and changes the light transmittance of each pixel in accordance with the supplied signal voltage.
  • the pixel thin film transistor of the pixel unit 50 corresponds to each pixel and operates as a switching element for writing the voltage of the data line to the pixel electrode.
  • the thin film transistor of the gate circuit unit 60 operates as a switching element that supplies a gate voltage for turning on and off the pixel thin film transistor of the pixel unit 50.
  • FIG. 2 is a schematic diagram showing an example of a circuit pattern of the GOA circuit.
  • a region surrounded as a TFT constitutes all or part of one thin film transistor in the GOA circuit.
  • Reference numeral 40 schematically illustrates a voltage supply unit that supplies a voltage to the gate of each thin film transistor.
  • the voltage supply unit 40 can be disposed at an appropriate location of the gate circuit unit 60.
  • the gate circuit unit 60 has a configuration in which a plurality of shift registers are connected.
  • FIG. 3 is a circuit diagram showing an example of a basic configuration of the shift register.
  • the shift register includes, for example, three thin film transistors M1 to M3 and one capacitor cap. More specifically, in the shift register, a predetermined clock signal CKA is input to the source, a Gout output thin film transistor M1 that outputs a drive signal from the drain to the output node (Gout / Qn), and a predetermined set signal ( For example, a first input thin film transistor M2 having a drain connected to the gate of the thin film transistor M1 and a gate connected to the source is input.
  • a source is connected to an output control node (also referred to as netA) in which the drain of the thin film transistor M2 for one input and the gate of the thin film transistor M1 for Gout output are connected, a predetermined potential is applied to the drain, and a predetermined reset signal (for example, the shift register on the downstream side of the shift register The output of the static, and a like second input TFT M3 indicated at R2) is input.
  • a capacitor cap is connected between the gate and drain of the Gout output thin film transistor M1.
  • the thin film transistor of this embodiment is a Gout output thin film transistor M1 shown in FIG.
  • FIG. 4 is a schematic plan view of an essential part showing an example of the structure of the thin film transistor of this embodiment.
  • a thin film transistor TFT: Thin Film Transistor, also referred to as a TFT substrate
  • TFT Thin Film Transistor
  • a gate insulating film (not shown) (for example, SiO 2 film) is formed so as to cover it.
  • An amorphous semiconductor layer 11 as a semiconductor layer is formed on the surface of the gate insulating film and above the gate electrode film 10.
  • the semiconductor layer is not limited to an amorphous semiconductor layer (amorphous semiconductor), and may be, for example, an oxide semiconductor layer.
  • a plurality of long source electrode films 13 and a plurality of long drain electrode films 14 are formed on the amorphous semiconductor layer 11.
  • the width w1 of the drain electrode film 14 (the length in the direction perpendicular to the longitudinal direction of the drain electrode film 14) is the width w2 of the source electrode film 13 (the length in the direction perpendicular to the longitudinal direction of the source electrode film 13). Greater than (w1> w2).
  • a plurality of source electrode films 13 are arranged in parallel along a direction orthogonal to the longitudinal direction of the source electrode film 13, and each of the plurality of drain electrode films 14 is arranged.
  • each source electrode film 13 is connected by a common electrode 131.
  • the end portions of the drain electrode films 14 are connected by a common electrode 141.
  • the number of electrode films arranged in parallel depends on the performance of an actual thin film transistor. The number is not limited to three, and may be 20, 50, 100, for example.
  • the drain electrode film having a width larger than the width of the source electrode film 13 may be at least one drain electrode film when a plurality of drain electrode films are arranged in parallel. Alternatively, some of the drain electrode films may be a plurality of drain electrode films.
  • the width of a part of the drain electrode films among the plurality of drain electrode films is made larger than the width of the source electrode film 13
  • the width of the drain electrode film other than the part of the drain electrode film is, for example, the source electrode film 13
  • the width is substantially the same.
  • FIG. 5 is a schematic cross-sectional view of the relevant part viewed from the line VV in FIG.
  • a gate electrode film 10 is formed on the surface of a glass substrate 1, and a gate insulating film 3 (for example, a SiO 2 film) covers the gate electrode film 10. Is formed.
  • An amorphous semiconductor layer 11 is formed on the surface of the gate insulating film 3 and above the gate electrode film 10.
  • a source electrode film 13 and a drain electrode film 14 are formed at required locations on the amorphous semiconductor layer 11.
  • the width of the drain electrode film 14 is larger than the width of the source electrode film 13.
  • a passivation film 4 is formed so as to cover the source electrode film 13 and the drain electrode film 14, and an organic film 5 is formed on the surface of the passivation film 4 to flatten the surface.
  • FIG. 6 is a schematic plan view of an essential part showing an example of the structure of a thin film transistor as a comparative example. The difference from FIG. 4 is that the width of the source electrode film 13 and the width of the drain electrode film 24 are approximately the same in the comparative example of FIG.
  • a minute foreign substance for example, symbol P in FIG. 6 schematically represents the drain electrode film 24.
  • symbol P in FIG. 6 schematically represents the drain electrode film 24.
  • the width of the drain electrode film 24 is 4.5 ⁇ m and the size of the minute foreign matter is 4.5 ⁇ m, the minute foreign matter occupies one drain electrode film)
  • the drain electrode film 24 becomes a foreign matter disconnection (indicated by hatching in FIG. 6). Further, when the output current value of the thin film transistor is relatively large, even if a foreign matter breakage occurs, the current change is not so large, and the foreign matter breakage may not be detected at the inspection stage.
  • a minute foreign substance (indicated by P in FIG. 4) is present in the drain electrode film 14. Even if it is mixed, the probability of occurrence of disconnection of foreign matter can be reduced, performance deterioration of the thin film transistor can be prevented, or failure of the thin film transistor can be prevented.
  • the drain electrode film 14 has a width (for example, 10 ⁇ m to 20 ⁇ m) that is larger than the width of the source electrode film 13 (for example, 4.5 ⁇ m). Even if a minute foreign substance (for example, a dimension of about 4.5 ⁇ m) enters the electrode film 14, the possibility of disconnection of the drain electrode film 14 can be reduced, and the drain electrode film 14 other than the drain electrode film 14 can be formed. An increase in flowing current can be suppressed, performance deterioration of the thin film transistor can be prevented, or failure of the thin film transistor can be prevented.
  • a minute foreign substance for example, a dimension of about 4.5 ⁇ m
  • a capacitor electrode film 15 is formed on the upper side of the gate electrode film 10.
  • An insulating film 12 (for example, a SiO 2 film) is formed between the gate electrode film 10 and the capacitor electrode film 15. Note that an insulating film and a semiconductor film may be formed instead of the insulating film 12.
  • the capacitor electrode film 15 has a required dimension w3 along the width direction of the drain electrode film 14.
  • the capacitive electrode film 15 includes a first connection point 151 connected to the drain electrode film 14 (more precisely, the common electrode 141) and a second connection point connected to the output terminal (not shown) of the thin film transistor. 152. Note that the first connection point 151 and the second connection point 152 are not literal points but have required areas.
  • the capacitor electrode film 15 has a required dimension w3 in a direction parallel to the width direction of the drain electrode film 14, and a dimension in a direction parallel to the longitudinal direction of the drain electrode film 14 is the length of the drain electrode film 14. It can be made into a rectangular shape which is the same size as the size.
  • the capacitor electrode film 15 forms a capacitor (specifically, a capacitor cap between the gate and the drain of the thin film transistor shown in FIG. 3) between the capacitor electrode film 15 and the gate electrode film 10 through the insulating film 12.
  • the capacitor cap is a bootstrap capacitor.
  • the capacitor between the drain electrode film 14 and the gate electrode film 10 through the amorphous semiconductor layer 11 becomes large. Even if the required dimension of the electrode film 15 is reduced (for example, the dimension w3 of the capacitive electrode film 15 in FIG. 4 is smaller than the dimension w23 of the capacitive electrode film 25 in FIG. 6), the gate-drain gap of the thin film transistor is reduced. The amount of change in the capacitance of the capacitor can be reduced, and the amount of change in the size of the entire element can also be reduced. In other words, even if the width of the drain electrode film 14 is increased, the required dimension of the capacitor electrode film 15 can be reduced, and the amount of change in the size of the entire element can be reduced.
  • FIG. 7 is an explanatory view showing an example of a method for manufacturing the thin film transistor of the present embodiment.
  • a copper (Cu) film is formed on a substrate (glass substrate) in a room temperature environment using a sputtering method, and the copper (Cu) film is patterned using a photolithography method and an etching method.
  • the gate electrode film 10 having a required width is formed (S11).
  • the material used for the gate electrode film 10 is not limited to copper, and for example, elemental elements such as aluminum, titanium, tungsten, gold, platinum, molybdenum, or nickel, or alloys thereof may be used.
  • a gate insulating film is formed on the substrate so as to cover the gate electrode film 10 using a plasma CVD method (S12).
  • a semiconductor layer (for example, an amorphous semiconductor layer) 11 is formed on the gate insulating film using a sputtering method in a room temperature environment or a high temperature environment that does not crystallize (S13).
  • the required pattern can be appropriately determined according to the arrangement or structure of the source electrode film 13 and the drain electrode film 14.
  • the width of the predetermined drain electrode film 14 is made larger than the width of the source electrode film 13 on the etched semiconductor layer 11, and the source electrode film 13 and The drain electrode film 14 is formed (S16).
  • the capacitor electrode film 15 can be formed simultaneously with the source electrode film 13 and the drain electrode film 14.
  • the drain electrode film width of the gate waveform output element (TFT) in the GOA circuit is made larger (thicker) than the opposing source electrode film width.
  • TFT gate waveform output element
  • the display panel according to the present embodiment is a display panel including a thin film transistor that supplies a driving voltage for turning on / off a pixel thin film transistor corresponding to each of a plurality of pixels arranged in a matrix on a substrate,
  • the thin film transistor includes a gate electrode film formed on a surface of the substrate, a semiconductor layer formed above the gate electrode film, a long source electrode film formed on the semiconductor layer, and the semiconductor layer A plurality of elongated drain electrode films formed thereon, and a width of at least one of the plurality of drain electrode films is larger than a width of the source electrode film.
  • the thin film transistor according to the present embodiment is a thin film transistor that supplies a driving voltage for turning on / off a thin film transistor for a pixel corresponding to each of a plurality of pixels arranged in a matrix on the substrate.
  • a width of at least one of the plurality of drain electrode films is larger than a width of the source electrode film.
  • the method for manufacturing a thin film transistor according to the present embodiment is a method for manufacturing a thin film transistor that supplies a driving voltage for turning on / off a pixel thin film transistor corresponding to each of a plurality of pixels arranged in a matrix on a substrate.
  • a gate electrode film is formed on the surface of the substrate, a semiconductor layer is formed on the gate electrode film, a long source electrode film is formed on the semiconductor layer, and the source is formed on the semiconductor layer.
  • a plurality of long drain electrode films including at least one long drain electrode film having a width larger than the width of the electrode film is formed.
  • the thin film transistor includes a gate electrode film formed on a surface of a substrate, a semiconductor layer formed above the gate electrode film, a long source electrode film and a plurality of long drain electrode films formed on the semiconductor layer.
  • the semiconductor layer is formed above the gate electrode film on which the gate insulating film is formed.
  • the width of at least one drain electrode film among the plurality of drain electrode films is larger than the width of the source electrode film.
  • the drain electrode film may be broken.
  • the current of the remaining drain electrode film increases, and characteristics such as threshold voltage at the time of switching shift, and there is a possibility that the performance of the thin film transistor is deteriorated due to stress or the thin film transistor is consequently defective.
  • the width of the drain electrode film By making the width of the drain electrode film larger than the width of the source electrode film, it is possible to reduce the probability of occurrence of foreign matter disconnection even if a minute foreign matter is mixed in the drain electrode film, preventing the performance deterioration of the thin film transistor, or Defects of the thin film transistor can be prevented.
  • the thin film transistor includes a plurality of the source electrode films arranged in parallel along a direction orthogonal to the longitudinal direction of the source electrode film, and each of the plurality of drain electrode films. Between the adjacent source electrode films in parallel with the source electrode film.
  • a plurality of source electrode films are arranged in parallel along a direction orthogonal to the longitudinal direction of the source electrode film, and each of the plurality of drain electrode films is parallel to the source electrode film between adjacent source electrode films. It is arranged in. That is, in the thin film transistor, a plurality of long source electrode films and drain electrode films are alternately arranged in parallel in a region corresponding to the gate electrode film.
  • the width of the drain electrode film is approximately the same as the width of the source electrode film, if a small foreign matter enters the drain electrode film and the drain electrode film is disconnected, no current flows through the drain electrode film. Therefore, the current flowing through the drain electrode film other than the drain electrode film increases. Due to an increase in current, characteristics such as a threshold voltage at the time of switching shift, and there is a possibility that the performance of the thin film transistor is deteriorated due to stress, or the thin film transistor is consequently defective.
  • the width of the drain electrode film By making the width of the drain electrode film larger than the width of the source electrode film, the possibility of disconnection of the drain electrode film can be reduced even if a minute foreign matter enters the drain electrode film. An increase in the current flowing through the drain electrode film can be suppressed, performance deterioration of the thin film transistor can be prevented, or failure of the thin film transistor can be prevented.
  • the display panel according to the present embodiment includes a capacitor electrode film formed on the gate electrode film, the capacitor electrode film including a first connection point connected to the drain electrode film, and the thin film. And a second connection point connected to the output terminal of the transistor.
  • the display panel includes a capacitor electrode film formed on the upper side of the gate electrode film.
  • the capacitor electrode film has a first connection point connected to the drain electrode film and a second connection point connected to the output end of the thin film transistor.
  • the capacitance electrode film has a required dimension in a direction parallel to the width direction of the drain electrode film, and a dimension in a direction parallel to the longitudinal direction of the drain electrode film is approximately the same as the length dimension of the drain electrode film. It can be made into the rectangular shape which is the dimension of these.
  • the capacitor electrode film forms, for example, a capacitor (specifically, a capacitor between the gate and the drain of the thin film transistor) between the insulating film or the gate electrode film via the insulating film and the semiconductor layer.
  • the capacitor is a bootstrap capacitor.
  • the capacitor between the drain electrode film and the gate electrode film through the semiconductor layer increases, so the required dimension of the capacitor electrode film is reduced.
  • the capacitor between the gate and the drain of the thin film transistor can be kept unchanged, and there is no need to change the size of the entire device. In other words, even if the width of the drain electrode film is increased, the required dimension of the capacitor electrode film can be reduced, and the size of the entire element does not change.

Abstract

Provided are a display panel, a thin-film transistor, and a method of manufacturing the thin-film transistor, with which it is possible to prevent performance degradation due to inclusion of minute foreign matter. A display panel comprising a thin-film transistor that supplies a drive voltage for turning on or off a thin-film transistor for pixels that corresponds to each of a plurality of pixels arranged in a matrix on a substrate, wherein the thin-film transistor comprises a gate electrode film (10) formed on the surface of the substrate, a semiconductor layer (11) formed on the top side of the gate electrode film, a long source electrode film (13) formed on the semiconductor layer, and a plurality of long drain electrode films (14) formed on the semiconductor layer. The width of at least one of the drain electrode films is larger than the width of the source electrode film.

Description

表示パネル、薄膜トランジスタ及び薄膜トランジスタの製造方法Display panel, thin film transistor, and method of manufacturing thin film transistor
　本発明は、表示パネル、薄膜トランジスタ及び薄膜トランジスタの製造方法に関する。 The present invention relates to a display panel, a thin film transistor, and a method for manufacturing the thin film transistor.
　近年、フラットパネルディスプレイの代表である液晶ディスプレイ（ＬＣＤ）は、中型パネルまたは小型パネルの分野だけでなくＴＶ用等の大型パネルの分野でも広く用いられている。このような液晶ディスプレイでは、アクティブマトリクス型の液晶表示装置が広く使用されている。 In recent years, a liquid crystal display (LCD), which is a representative flat panel display, is widely used not only in the field of medium-sized panels or small panels but also in the field of large panels for TVs and the like. In such a liquid crystal display, an active matrix type liquid crystal display device is widely used.
　アクティブマトリクス型の液晶表示装置の表示パネルは、複数のソースバスライン（映像信号線）、複数のゲートバスライン及び画素形成部などを備える。画素形成部は、複数のソースバスラインと複数のゲートバスラインとが交差する箇所に設けられ、マトリクス状に配置されている。各画素形成部は、画素用薄膜トランジスタ及び画素電圧値を保持するための画素容量などを備える。画素用薄膜トランジスタのゲート端子は、ゲートバスラインとソースバスラインが交差する箇所を通過するゲートバスラインに接続されている。また、画素用薄膜トランジスタのソース端子は、当該箇所を通過するソースバスラインに接続されている。また、アクティブマトリクス型の液晶表示装置は、ゲートバスラインを駆動するためのゲートドライバ及びソースバスラインを駆動するためのソースドライバなど備える。 A display panel of an active matrix liquid crystal display device includes a plurality of source bus lines (video signal lines), a plurality of gate bus lines, a pixel formation portion, and the like. The pixel formation portion is provided at a location where a plurality of source bus lines and a plurality of gate bus lines intersect, and is arranged in a matrix. Each pixel forming unit includes a pixel thin film transistor and a pixel capacitor for holding a pixel voltage value. The gate terminal of the pixel thin film transistor is connected to a gate bus line that passes through a location where the gate bus line and the source bus line intersect. Further, the source terminal of the pixel thin film transistor is connected to a source bus line passing through the portion. The active matrix liquid crystal display device includes a gate driver for driving a gate bus line, a source driver for driving a source bus line, and the like.
　一つのソースバスラインは、複数行分の画素電圧値を示す映像信号を同時に伝達することができない。このため、マトリクス状に配置された画素形成部内の画素容量への映像信号の書き込み（充電）は１行ずつ順次に行う必要がある。そこで、複数のゲートバスラインが所定期間ずつ順次に選択されるように、ゲートドライバ（駆動回路）は、シフトレジスタが複数段接続された構成をなす。ゲートドライバは、複数のクロック信号に基づいて、各段のシフトレジスタから各ゲートバスラインへ駆動信号を順次出力する（特許文献１参照）。 One source bus line cannot simultaneously transmit video signals indicating pixel voltage values for a plurality of rows. For this reason, it is necessary to sequentially write (charge) video signals to the pixel capacitors in the pixel formation portions arranged in a matrix, row by row. Therefore, the gate driver (driving circuit) has a configuration in which a plurality of shift registers are connected so that the plurality of gate bus lines are sequentially selected for a predetermined period. The gate driver sequentially outputs a drive signal from each stage shift register to each gate bus line based on a plurality of clock signals (see Patent Document 1).
特許第５１３２８１８号公報Japanese Patent No. 5132818
　シフトレジスタを構成する複数の薄膜トランジスタのうち、ゲートバスラインへ駆動信号を出力する出力用（駆動用）の薄膜トランジスタのドレイン電極膜を形成する際に、微小な異物が混入した場合、ドレイン電極膜の異物断線が生じる可能性がある。異物断線が生じると、残りのドレイン電極膜の電流が増加し、スイッチング時の閾値電圧などの特性がシフトし、ストレスによる出力用の薄膜トランジスタの性能劣化、あるいは結果的に出力用の薄膜トランジスタの不良となる場合がある。 When forming a drain electrode film of an output (drive) thin film transistor that outputs a drive signal to a gate bus line among a plurality of thin film transistors constituting a shift register, Foreign matter disconnection may occur. When foreign matter disconnection occurs, the current of the remaining drain electrode film increases, and characteristics such as threshold voltage at the time of switching shift, and the performance of the output thin film transistor is deteriorated due to stress, or as a result, the output thin film transistor is defective. There is a case.
　本発明は斯かる事情に鑑みてなされたものであり、微小な異物混入による性能劣化を防止することができる表示パネル、該表示パネルを構成する薄膜トランジスタ及び薄膜トランジスタの製造方法を提供することを目的とする。 The present invention has been made in view of such circumstances, and an object of the present invention is to provide a display panel capable of preventing performance deterioration due to mixing of minute foreign matter, a thin film transistor constituting the display panel, and a method of manufacturing the thin film transistor. To do.
　本発明の実施の形態に係る表示パネルは、基板上にマトリクス状に配置された複数の画素それぞれに対応する画素用薄膜トランジスタをオン／オフさせるための駆動電圧を供給する薄膜トランジスタを備える表示パネルであって、前記薄膜トランジスタは、前記基板の表面に形成されたゲート電極膜と、該ゲート電極膜の上側に形成された半導体層と、該半導体層上に形成された長尺のソース電極膜と、前記半導体層上に複数形成された長尺のドレイン電極膜とを備え、前記複数のドレイン電極膜のうちの少なくとも一つのドレイン電極膜の幅は、前記ソース電極膜の幅より大きい。 A display panel according to an embodiment of the present invention is a display panel including a thin film transistor that supplies a driving voltage for turning on / off a pixel thin film transistor corresponding to each of a plurality of pixels arranged in a matrix on a substrate. The thin film transistor includes a gate electrode film formed on the surface of the substrate, a semiconductor layer formed on the gate electrode film, a long source electrode film formed on the semiconductor layer, A plurality of elongated drain electrode films formed on the semiconductor layer, and a width of at least one of the plurality of drain electrode films is larger than a width of the source electrode film.
　本発明の実施の形態に係る薄膜トランンジスタは、基板上にマトリクス状に配置された複数の画素それぞれに対応する画素用薄膜トランジスタをオン／オフさせるための駆動電圧を供給する薄膜トランジスタであって、前記基板の表面に形成されたゲート電極膜と、該ゲート電極膜の上側に形成された半導体層と、該半導体層上に形成された長尺のソース電極膜と、前記半導体層上に複数形成された長尺のドレイン電極膜とを備え、前記複数のドレイン電極膜のうちの少なくとも一つのドレイン電極膜の幅は、前記ソース電極膜の幅より大きい。 A thin film transistor according to an embodiment of the present invention is a thin film transistor that supplies a driving voltage for turning on / off a thin film transistor for a pixel corresponding to each of a plurality of pixels arranged in a matrix on a substrate. A gate electrode film formed on the surface of the substrate, a semiconductor layer formed above the gate electrode film, a long source electrode film formed on the semiconductor layer, and a plurality of films formed on the semiconductor layer. And a width of at least one of the plurality of drain electrode films is larger than a width of the source electrode film.
　本発明の実施の形態に係る薄膜トランンジスタの製造方法は、基板上にマトリクス状に配置された複数の画素それぞれに対応する画素用薄膜トランジスタをオン／オフさせるための駆動電圧を供給する薄膜トランジスタの製造方法であって、前記基板の表面にゲート電極膜を形成し、該ゲート電極膜の上側に半導体層を形成し、前記半導体層上に長尺のソース電極膜を形成し、前記半導体層上に前記ソース電極膜の幅より大きい幅を有する長尺のドレイン電極膜を少なくとも一つ含む複数の長尺のドレイン電極膜を形成する。 A method of manufacturing a thin film transistor according to an embodiment of the present invention is a method of manufacturing a thin film transistor that supplies a driving voltage for turning on / off a pixel thin film transistor corresponding to each of a plurality of pixels arranged in a matrix on a substrate. A gate electrode film is formed on the surface of the substrate; a semiconductor layer is formed on the gate electrode film; a long source electrode film is formed on the semiconductor layer; and A plurality of long drain electrode films including at least one long drain electrode film having a width larger than the width of the source electrode film is formed.
　本発明によれば、微小な異物混入による性能劣化を防止することができる。 According to the present invention, it is possible to prevent performance deterioration due to minute foreign matter mixing.
本実施の形態の表示パネルの要部構成の一例を示す模式図である。It is a schematic diagram which shows an example of the principal part structure of the display panel of this Embodiment. ＧＯＡ回路の回路パターンの一例を示す模式図である。It is a schematic diagram which shows an example of the circuit pattern of a GOA circuit. シフトレジスタの基本の構成の一例を示す回路図である。It is a circuit diagram which shows an example of the basic composition of a shift register. 本実施の形態の薄膜トランジスタの構造の一例を示す要部平面模式図である。It is a principal part plane schematic diagram which shows an example of the structure of the thin-film transistor of this Embodiment. 図４のＶ－Ｖ線から見た要部断面模式図である。FIG. 5 is a schematic cross-sectional view of a main part viewed from the line VV in FIG. 比較例としての薄膜トランジスタの構造の一例を示す要部平面模式図である。It is a principal part plane schematic diagram which shows an example of the structure of the thin-film transistor as a comparative example. 本実施の形態の薄膜トランジスタの製造方法の一例を示す説明図である。It is explanatory drawing which shows an example of the manufacturing method of the thin-film transistor of this Embodiment.
　以下、本発明をその実施の形態を示す図面に基づいて説明する。図１は本実施の形態の表示パネル１００の要部構成の一例を示す模式図である。表示パネル１００は、複数の画素がマトリクス状に配置された画素部５０、画素部５０の周辺に配置されたゲート回路部６０及びソース端子部７０などを備える。ソース端子部７０は、表示パネル１００の外部のソース回路（不図示）からの信号線が接続される複数の端子で構成される。画素部５０及びゲート回路部６０は、薄膜トランジスタ（ＴＦＴ：Thin Film Transistor）基板（ＴＦＴ基板とも称する）上に形成されている。本実施の形態では、表示パネル１００の例として液晶表示パネルについて説明するが、表示パネル１００は、液晶表示パネルに限定されるものではない。 Hereinafter, the present invention will be described with reference to the drawings showing embodiments thereof. FIG. 1 is a schematic diagram illustrating an example of a main configuration of a display panel 100 according to the present embodiment. The display panel 100 includes a pixel unit 50 in which a plurality of pixels are arranged in a matrix, a gate circuit unit 60 and a source terminal unit 70 arranged around the pixel unit 50, and the like. The source terminal unit 70 includes a plurality of terminals to which signal lines from a source circuit (not shown) outside the display panel 100 are connected. The pixel portion 50 and the gate circuit portion 60 are formed on a thin film transistor (TFT) substrate (also referred to as a TFT substrate). In this embodiment, a liquid crystal display panel will be described as an example of the display panel 100, but the display panel 100 is not limited to the liquid crystal display panel.
　画素部５０は、各画素に対応する画素用薄膜トランジスタ（ＴＦＴとも称する）が設けられている。画素部５０の画素用薄膜トランジスタは、各画素の輝度を変化させる電流を流すためのトランジスタである。なお、各画素の輝度を変化させるとは、各画素の透過率を変化させることと同義である。 The pixel unit 50 is provided with a pixel thin film transistor (also referred to as TFT) corresponding to each pixel. The pixel thin film transistor of the pixel unit 50 is a transistor for supplying a current that changes the luminance of each pixel. Note that changing the luminance of each pixel is synonymous with changing the transmittance of each pixel.
　ゲート回路部６０は、画素部５０の画素用薄膜トランジスタをオン／オフさせるための駆動電圧（ゲート電圧）を供給する薄膜トランジスタを有する。なお、本明細書では、画素用薄膜トランジスタと区別するため、便宜上、画素用薄膜トランジスタをオン／オフさせるための駆動電圧（ゲート電圧）を供給する駆動用の薄膜トランジスタを単に薄膜トランジスタと称する。薄膜トランジスタは、画素部５０の画素用薄膜トランジスタのスイッチング（オン・オフ制御）を制御し、いずれの画素の輝度を変化させるかを選択する機能を有する。また、ソース端子部７０に接続される不図示のソース回路は、画素部５０の画素用薄膜トランジスタに信号電圧を供給し、供給する信号電圧に応じて各画素の光の透過率を変化させる。 The gate circuit unit 60 includes a thin film transistor that supplies a driving voltage (gate voltage) for turning on and off the pixel thin film transistor of the pixel unit 50. Note that in this specification, for the sake of convenience, a driving thin film transistor that supplies a driving voltage (gate voltage) for turning on / off the pixel thin film transistor is simply referred to as a thin film transistor in order to distinguish from the pixel thin film transistor. The thin film transistor has a function of controlling switching (on / off control) of the pixel thin film transistor of the pixel portion 50 and selecting which pixel luminance is changed. A source circuit (not shown) connected to the source terminal unit 70 supplies a signal voltage to the pixel thin film transistor of the pixel unit 50, and changes the light transmittance of each pixel in accordance with the supplied signal voltage.
　すなわち、画素部５０の画素用薄膜トランジスタは、各画素に対応し、データラインの電圧を画素電極に書き込むためのスイッチング素子として作動する。また、ゲート回路部６０の薄膜トランジスタは、画素部５０の画素用薄膜トランジスタをオン、オフさせるためのゲート電圧を供給するスイッチング素子として作動する。 That is, the pixel thin film transistor of the pixel unit 50 corresponds to each pixel and operates as a switching element for writing the voltage of the data line to the pixel electrode. The thin film transistor of the gate circuit unit 60 operates as a switching element that supplies a gate voltage for turning on and off the pixel thin film transistor of the pixel unit 50.
　次に、ゲート回路部６０の一例としてＧＯＡ（Gate Driver On Array）回路について説明する。図２はＧＯＡ回路の回路パターンの一例を示す模式図である。図２において、ＴＦＴとして囲まれた領域が、ＧＯＡ回路の内の１個の薄膜トランジスタの全部又は一部を構成する。また、符号４０は、各薄膜トランジスタのゲートに電圧を供給する電圧供給部を模式的に図示している。電圧供給部４０は、ゲート回路部６０の適当な箇所に配置することができる。 Next, a GOA (Gate Driver On Array) circuit will be described as an example of the gate circuit unit 60. FIG. 2 is a schematic diagram showing an example of a circuit pattern of the GOA circuit. In FIG. 2, a region surrounded as a TFT constitutes all or part of one thin film transistor in the GOA circuit. Reference numeral 40 schematically illustrates a voltage supply unit that supplies a voltage to the gate of each thin film transistor. The voltage supply unit 40 can be disposed at an appropriate location of the gate circuit unit 60.
　ゲート回路部６０は、複数のシフトレジスタが接続された構成を有する。図３はシフトレジスタの基本の構成の一例を示す回路図である。図３に示すように、シフトレジスタは、例えば、３個の薄膜トランジスタＭ１～Ｍ３、１個のキャパシタｃａｐを備える。より具体的には、シフトレジスタは、ソースに所定のクロック信号ＣＫＡが入力され、ドレインから出力ノード（Ｇｏｕｔ／Ｑｎ）へ駆動信号を出力するＧｏｕｔ出力用の薄膜トランジスタＭ１、ソースに所定のセット信号（例えば、当該シフトレジスタよりも前段側のシフトレジスタの出力など、符号Ｓ１で示す）が入力され、ドレインが薄膜トランジスタＭ１のゲートに接続され、ゲートがソースに接続された第一入力用薄膜トランジスタＭ２、第一入力用薄膜トランジスタＭ２のドレインとＧｏｕｔ出力用の薄膜トランジスタＭ１のゲートとが接続された出力制御ノード（ｎｅｔＡとも称する）にソースが接続され、ドレインに所定電位が印加され、ゲートに所定のリセット信号（例えば、当該シフトレジスタよりも後段側のシフトレジスタの出力、符号Ｒ２で示す）が入力される第二入力用薄膜トランジスタＭ３などを備える。また、Ｇｏｕｔ出力用の薄膜トランジスタＭ１のゲート・ドレイン間にはキャパシタｃａｐが接続されている。本実施の形態の薄膜トランジスタは、図３に示すＧｏｕｔ出力用の薄膜トランジスタＭ１である。 The gate circuit unit 60 has a configuration in which a plurality of shift registers are connected. FIG. 3 is a circuit diagram showing an example of a basic configuration of the shift register. As shown in FIG. 3, the shift register includes, for example, three thin film transistors M1 to M3 and one capacitor cap. More specifically, in the shift register, a predetermined clock signal CKA is input to the source, a Gout output thin film transistor M1 that outputs a drive signal from the drain to the output node (Gout / Qn), and a predetermined set signal ( For example, a first input thin film transistor M2 having a drain connected to the gate of the thin film transistor M1 and a gate connected to the source is input. A source is connected to an output control node (also referred to as netA) in which the drain of the thin film transistor M2 for one input and the gate of the thin film transistor M1 for Gout output are connected, a predetermined potential is applied to the drain, and a predetermined reset signal ( For example, the shift register on the downstream side of the shift register The output of the static, and a like second input TFT M3 indicated at R2) is input. A capacitor cap is connected between the gate and drain of the Gout output thin film transistor M1. The thin film transistor of this embodiment is a Gout output thin film transistor M1 shown in FIG.
　次に、本実施の形態の薄膜トランジスタの詳細について説明する。 Next, details of the thin film transistor of this embodiment will be described.
　図４は本実施の形態の薄膜トランジスタの構造の一例を示す要部平面模式図である。図４に示すように、薄膜トランジスタ（ＴＦＴ：Thin Film Transistor、ＴＦＴ基板とも称する）は、不図示のガラス基板（基板とも称する）の表面にゲート電極膜１０を形成してあり、ゲート電極膜１０を覆って不図示のゲート絶縁膜（例えば、ＳｉＯ2 膜など）を形成してある。ゲート絶縁膜の表面であってゲート電極膜１０の上側には、半導体層としての非晶質半導体層１１を形成してある。なお、半導体層は非晶質半導体層（アモルファス半導体）に限定されず、例えば、酸化物半導体層であってもよい。 FIG. 4 is a schematic plan view of an essential part showing an example of the structure of the thin film transistor of this embodiment. As shown in FIG. 4, a thin film transistor (TFT: Thin Film Transistor, also referred to as a TFT substrate) has a gate electrode film 10 formed on the surface of a glass substrate (also referred to as a substrate) (not shown). A gate insulating film (not shown) (for example, SiO 2 film) is formed so as to cover it. An amorphous semiconductor layer 11 as a semiconductor layer is formed on the surface of the gate insulating film and above the gate electrode film 10. Note that the semiconductor layer is not limited to an amorphous semiconductor layer (amorphous semiconductor), and may be, for example, an oxide semiconductor layer.
　非晶質半導体層１１上には、複数の長尺のソース電極膜１３及び複数の長尺のドレイン電極膜１４を形成してある。そして、ドレイン電極膜１４の幅ｗ１（ドレイン電極膜１４の長手方向に直交する方向の長さ）は、ソース電極膜１３の幅ｗ２（ソース電極膜１３の長手方向に直交する方向の長さ）より大きい（ｗ１＞ｗ２）。 A plurality of long source electrode films 13 and a plurality of long drain electrode films 14 are formed on the amorphous semiconductor layer 11. The width w1 of the drain electrode film 14 (the length in the direction perpendicular to the longitudinal direction of the drain electrode film 14) is the width w2 of the source electrode film 13 (the length in the direction perpendicular to the longitudinal direction of the source electrode film 13). Greater than (w1> w2).
　より具体的には、本実施の形態の薄膜トランジスタは、ソース電極膜１３をソース電極膜１３の長手方向と直交する方向に沿って複数並列して配置してあり、複数のドレイン電極膜１４のそれぞれを隣り合うソース電極膜１３の間にソース電極膜１３と平行に配置してある。すなわち、薄膜トランジスタは、ゲート電極膜１０に対応する領域内において、長尺のソース電極膜１３及びドレイン電極膜１４が交互に複数並列して配置してある。 More specifically, in the thin film transistor of this embodiment, a plurality of source electrode films 13 are arranged in parallel along a direction orthogonal to the longitudinal direction of the source electrode film 13, and each of the plurality of drain electrode films 14 is arranged. Are arranged in parallel with the source electrode film 13 between the adjacent source electrode films 13. That is, in the thin film transistor, a plurality of long source electrode films 13 and drain electrode films 14 are alternately arranged in parallel in a region corresponding to the gate electrode film 10.
　各ソース電極膜１３の端部は共通電極１３１により接続されている。また、各ドレイン電極膜１４の端部は共通電極１４１により接続されている。なお、図４の例では、ソース電極膜１３を３個、ドレイン電極膜１４を３個だけ図示しているが、実際の薄膜トランジスタの性能等に応じて、並列して配置する電極膜の数は３個に限定されず、例えば、２０個、５０個、１００個などとすることができる。また、ソース電極膜１３の幅よりも幅を大きくするドレイン電極膜は、ドレイン電極膜が複数並列に配置されている場合、少なくとも一つのドレイン電極膜であればよく、また、すべてのドレイン電極膜でもよく、すべてのドレイン電極膜のうちの一部の複数のドレイン電極膜であってもよい。複数のドレイン電極膜のうちの一部のドレイン電極膜の幅をソース電極膜１３の幅よりも大きくする場合、該一部のドレイン電極膜以外のドレイン電極膜の幅は、例えばソース電極膜１３の幅と略同じである。 The end of each source electrode film 13 is connected by a common electrode 131. The end portions of the drain electrode films 14 are connected by a common electrode 141. In the example of FIG. 4, only three source electrode films 13 and three drain electrode films 14 are illustrated, but the number of electrode films arranged in parallel depends on the performance of an actual thin film transistor. The number is not limited to three, and may be 20, 50, 100, for example. The drain electrode film having a width larger than the width of the source electrode film 13 may be at least one drain electrode film when a plurality of drain electrode films are arranged in parallel. Alternatively, some of the drain electrode films may be a plurality of drain electrode films. When the width of a part of the drain electrode films among the plurality of drain electrode films is made larger than the width of the source electrode film 13, the width of the drain electrode film other than the part of the drain electrode film is, for example, the source electrode film 13 The width is substantially the same.
　図５は図４のＶ－Ｖ線から見た要部断面模式図である。図５に示すように、本実施の形態の薄膜トランジスタは、ガラス基板１の表面にゲート電極膜１０を形成してあり、ゲート電極膜１０を覆ってゲート絶縁膜３（例えば、ＳｉＯ2 膜など）を形成してある。 FIG. 5 is a schematic cross-sectional view of the relevant part viewed from the line VV in FIG. As shown in FIG. 5, in the thin film transistor of the present embodiment, a gate electrode film 10 is formed on the surface of a glass substrate 1, and a gate insulating film 3 (for example, a SiO 2 film) covers the gate electrode film 10. Is formed.
　ゲート絶縁膜３の表面であってゲート電極膜１０の上側には、非晶質半導体層１１を形成してある。 An amorphous semiconductor layer 11 is formed on the surface of the gate insulating film 3 and above the gate electrode film 10.
　非晶質半導体層１１上の所要の箇所にはソース電極膜１３及びドレイン電極膜１４を形成してある。ドレイン電極膜１４の幅はソース電極膜１３の幅よりも大きい。ソース電極膜１３及びドレイン電極膜１４を覆うようにして、パッシベーション膜４を形成してあり、パッシベーション膜４の表面には有機膜５を形成して表面を平坦化している。 A source electrode film 13 and a drain electrode film 14 are formed at required locations on the amorphous semiconductor layer 11. The width of the drain electrode film 14 is larger than the width of the source electrode film 13. A passivation film 4 is formed so as to cover the source electrode film 13 and the drain electrode film 14, and an organic film 5 is formed on the surface of the passivation film 4 to flatten the surface.
　図６は比較例としての薄膜トランジスタの構造の一例を示す要部平面模式図である。図４との相違点は、図６の比較例では、ソース電極膜１３の幅とドレイン電極膜２４の幅とは同程度である。 FIG. 6 is a schematic plan view of an essential part showing an example of the structure of a thin film transistor as a comparative example. The difference from FIG. 4 is that the width of the source electrode film 13 and the width of the drain electrode film 24 are approximately the same in the comparative example of FIG.
　図６に示すように、仮に、ドレイン電極膜２４の幅をソース電極膜１３の幅と同程度にした場合に、ドレイン電極膜２４に微小な異物（例えば、図６において符号Ｐで模式的に示すように、ドレイン電極膜２４の幅が４．５μｍであって、微小な異物の寸法が４．５μｍのように、微小な異物が１本のドレイン電極膜を占めるような場合）が混入すると、当該ドレイン電極膜２４は、異物断線となる（図６において斜線で示す）。また、薄膜トランジスタの出力電流値が比較大きい場合には、異物断線が発生した場合でも、電流変化が余り大きくなく、検査段階で異物断線を検出することができないこともある。異物断線が生じると、残りのドレイン電極膜の電流が増加し、長期駆動の結果、スイッチング時の閾値電圧などの特性がシフトし、ストレスによる薄膜トランジスタの性能劣化、あるいは結果的に薄膜トランジスタの不良となる可能性がある。 As shown in FIG. 6, if the drain electrode film 24 has the same width as that of the source electrode film 13, a minute foreign substance (for example, symbol P in FIG. 6 schematically represents the drain electrode film 24). As shown, when the width of the drain electrode film 24 is 4.5 μm and the size of the minute foreign matter is 4.5 μm, the minute foreign matter occupies one drain electrode film) The drain electrode film 24 becomes a foreign matter disconnection (indicated by hatching in FIG. 6). Further, when the output current value of the thin film transistor is relatively large, even if a foreign matter breakage occurs, the current change is not so large, and the foreign matter breakage may not be detected at the inspection stage. When foreign matter disconnection occurs, the current of the remaining drain electrode film increases, and as a result of long-term driving, characteristics such as threshold voltage at the time of switching shift, resulting in performance deterioration of the thin film transistor due to stress, or eventually failure of the thin film transistor. there is a possibility.
　本実施の形態では、図４に示すように、ドレイン電極膜１４の幅をソース電極膜１３の幅より大きくすることにより、ドレイン電極膜１４に微小な異物（図４において符号Ｐで示す）が混入しても、異物断線の発生確率を低下させることができ、薄膜トランジスタの性能劣化を防止し、あるいは薄膜トランジスタの不良を防止することができる。 In the present embodiment, as shown in FIG. 4, by making the width of the drain electrode film 14 larger than the width of the source electrode film 13, a minute foreign substance (indicated by P in FIG. 4) is present in the drain electrode film 14. Even if it is mixed, the probability of occurrence of disconnection of foreign matter can be reduced, performance deterioration of the thin film transistor can be prevented, or failure of the thin film transistor can be prevented.
　すなわち、本実施の形態では、図４に示すように、ドレイン電極膜１４の幅（例えば、１０μｍ～２０μｍなど）をソース電極膜１３の幅（例えば、４．５μｍ）より大きくすることにより、ドレイン電極膜１４に微小な異物（例えば、寸法が４．５μｍ程度）が混入してもドレイン電極膜１４の断線の可能性を小さくすることができ、当該ドレイン電極膜１４以外のドレイン電極膜１４に流れる電流の増加を抑制することができ、薄膜トランジスタの性能劣化を防止し、あるいは薄膜トランジスタの不良を防止することができる。 That is, in the present embodiment, as shown in FIG. 4, the drain electrode film 14 has a width (for example, 10 μm to 20 μm) that is larger than the width of the source electrode film 13 (for example, 4.5 μm). Even if a minute foreign substance (for example, a dimension of about 4.5 μm) enters the electrode film 14, the possibility of disconnection of the drain electrode film 14 can be reduced, and the drain electrode film 14 other than the drain electrode film 14 can be formed. An increase in flowing current can be suppressed, performance deterioration of the thin film transistor can be prevented, or failure of the thin film transistor can be prevented.
　また、本実施の形態の表示パネル１００では、図４に示すように、ゲート電極膜１０の上側に容量用電極膜１５を形成してある。ゲート電極膜１０と容量用電極膜１５との間には、絶縁膜１２（例えば、ＳｉＯ2 膜など）を形成してある。なお、絶縁膜１２に代えて、絶縁膜及び半導体膜を形成してもよい。 Further, in the display panel 100 of the present embodiment, as shown in FIG. 4, a capacitor electrode film 15 is formed on the upper side of the gate electrode film 10. An insulating film 12 (for example, a SiO 2 film) is formed between the gate electrode film 10 and the capacitor electrode film 15. Note that an insulating film and a semiconductor film may be formed instead of the insulating film 12.
　容量用電極膜１５は、ドレイン電極膜１４の幅方向に沿って所要の寸法ｗ３を有する。また、容量用電極膜１５は、ドレイン電極膜１４（正確には共通電極１４１）と接続される第１接続点１５１と、薄膜トランンジスタの出力端（不図示）と接続される第２接続点１５２とを有する。なお、第１接続点１５１、第２接続点１５２は、文字通りの点ではなく、所要の領域を有する。 The capacitor electrode film 15 has a required dimension w3 along the width direction of the drain electrode film 14. The capacitive electrode film 15 includes a first connection point 151 connected to the drain electrode film 14 (more precisely, the common electrode 141) and a second connection point connected to the output terminal (not shown) of the thin film transistor. 152. Note that the first connection point 151 and the second connection point 152 are not literal points but have required areas.
　容量用電極膜１５は、例えば、ドレイン電極膜１４の幅方向と平行な向きの寸法が所要の寸法ｗ３であり、ドレイン電極膜１４の長手方向と平行な向きの寸法がドレイン電極膜１４の長さ寸法と同程度の寸法である、矩形状とすることができる。容量用電極膜１５は、絶縁膜１２を介してゲート電極膜１０との間でキャパシタ（具体的には、図３に示す、薄膜トランジスタのゲート・ドレイン間のキャパシタｃａｐ）を構成する。当該キャパシタｃａｐは、ブートストラップのためのキャパシタである。 For example, the capacitor electrode film 15 has a required dimension w3 in a direction parallel to the width direction of the drain electrode film 14, and a dimension in a direction parallel to the longitudinal direction of the drain electrode film 14 is the length of the drain electrode film 14. It can be made into a rectangular shape which is the same size as the size. The capacitor electrode film 15 forms a capacitor (specifically, a capacitor cap between the gate and the drain of the thin film transistor shown in FIG. 3) between the capacitor electrode film 15 and the gate electrode film 10 through the insulating film 12. The capacitor cap is a bootstrap capacitor.
　ドレイン電極膜１４の幅ｗ１をソース電極膜１３の幅ｗ２より大きくした場合、非晶質半導体層１１を介したドレイン電極膜１４とゲート電極膜１０との間のキャパシタが大きくなるので、容量用電極膜１５の所要の寸法を小さくしても（例えば、図４の容量用電極膜１５の寸法ｗ３は、図６の容量用電極膜２５の寸法ｗ２３より小さい）、薄膜トランジスタのゲート・ドレイン間のキャパシタの容量の変化量を少なくすることができ、素子全体のサイズの変更量も少なくすることができる。別言すれば、ドレイン電極膜１４の幅を大きくしても、容量用電極膜１５の所要の寸法を小さくすることができ、素子全体のサイズの変更量を少なくすることができる。 When the width w1 of the drain electrode film 14 is larger than the width w2 of the source electrode film 13, the capacitor between the drain electrode film 14 and the gate electrode film 10 through the amorphous semiconductor layer 11 becomes large. Even if the required dimension of the electrode film 15 is reduced (for example, the dimension w3 of the capacitive electrode film 15 in FIG. 4 is smaller than the dimension w23 of the capacitive electrode film 25 in FIG. 6), the gate-drain gap of the thin film transistor is reduced. The amount of change in the capacitance of the capacitor can be reduced, and the amount of change in the size of the entire element can also be reduced. In other words, even if the width of the drain electrode film 14 is increased, the required dimension of the capacitor electrode film 15 can be reduced, and the amount of change in the size of the entire element can be reduced.
　図７は本実施の形態の薄膜トランジスタの製造方法の一例を示す説明図である。図７に示すように、スパッタリング法を用いて室温環境下で、基板（ガラス基板）上に銅（Cu）膜を形成し、フォトリソグラフィ法及びエッチング法を用いて銅（Cu）膜をパターニングして所要の幅のゲート電極膜１０を形成する（Ｓ１１）。なお、ゲート電極膜１０に用いられる材料は、銅に限定されるものではなく、例えば、アルミニウム、チタン、タングステン、金、白金、モリブデン、もしくはニッケル等の元素単体又は合金を用いてよい。 FIG. 7 is an explanatory view showing an example of a method for manufacturing the thin film transistor of the present embodiment. As shown in FIG. 7, a copper (Cu) film is formed on a substrate (glass substrate) in a room temperature environment using a sputtering method, and the copper (Cu) film is patterned using a photolithography method and an etching method. Then, the gate electrode film 10 having a required width is formed (S11). Note that the material used for the gate electrode film 10 is not limited to copper, and for example, elemental elements such as aluminum, titanium, tungsten, gold, platinum, molybdenum, or nickel, or alloys thereof may be used.
　次に、ゲート電極膜１０を覆うようにして基板上に、プラズマＣＶＤ法を用いてゲート絶縁膜を形成する（Ｓ１２）。 Next, a gate insulating film is formed on the substrate so as to cover the gate electrode film 10 using a plasma CVD method (S12).
　次に、スパッタリング法を用いて室温環境下、又は結晶化しない程度の高温環境下で、ゲート絶縁膜上に半導体層（例えば、非晶質半導体層）１１を形成する（Ｓ１３）。 Next, a semiconductor layer (for example, an amorphous semiconductor layer) 11 is formed on the gate insulating film using a sputtering method in a room temperature environment or a high temperature environment that does not crystallize (S13).
　次に、露光処理、現像処理を行い（Ｓ１４）、半導体層１１に所要のパターンを形成する。所要のパターンは、ソース電極膜１３、ドレイン電極膜１４などの配置又は構造に応じて適宜定めることができる。 Next, exposure processing and development processing are performed (S14), and a required pattern is formed in the semiconductor layer 11. The required pattern can be appropriately determined according to the arrangement or structure of the source electrode film 13 and the drain electrode film 14.
　次に、半導体層１１の所要の箇所をエッチングし（Ｓ１５）、エッチング後の半導体層１１上に、所定のドレイン電極膜１４の幅をソース電極膜１３の幅より大きくしてソース電極膜１３及びドレイン電極膜１４を形成する（Ｓ１６）。なお、容量用電極膜１５は、ソース電極膜１３及びドレイン電極膜１４と同時に形成することができる。 Next, a required portion of the semiconductor layer 11 is etched (S15), and the width of the predetermined drain electrode film 14 is made larger than the width of the source electrode film 13 on the etched semiconductor layer 11, and the source electrode film 13 and The drain electrode film 14 is formed (S16). The capacitor electrode film 15 can be formed simultaneously with the source electrode film 13 and the drain electrode film 14.
　上述のように、本実施の形態によれば、ＧＯＡ回路の内、ゲート波形出力用素子（ＴＦＴ）のドレイン電極膜幅を相対するソース電極膜幅より大きく（太く）する。これにより、微小な異物による断線確率を低下させることができる。また、ドレイン電極膜の幅を大きくしても、ドレイン電極膜の部分は、ブートストラップ用の容量部を兼ねているため、ブートストラップ用の容量電極膜を、ドレイン電極膜の幅を大きくした分に相当する分だけ小さくすることができ、結果として素子全体のサイズを大きくする必要がなく、素子全体のサイズの変更量を少なくすることができる。 As described above, according to the present embodiment, the drain electrode film width of the gate waveform output element (TFT) in the GOA circuit is made larger (thicker) than the opposing source electrode film width. Thereby, the disconnection probability by a minute foreign material can be reduced. Even if the width of the drain electrode film is increased, the portion of the drain electrode film also serves as a bootstrap capacitor. Therefore, the capacity electrode film for bootstrap is made larger than the width of the drain electrode film. As a result, it is not necessary to increase the size of the entire device, and the amount of change in the size of the entire device can be reduced.
　本実施の形態に係る表示パネルは、基板上にマトリクス状に配置された複数の画素それぞれに対応する画素用薄膜トランジスタをオン／オフさせるための駆動電圧を供給する薄膜トランジスタを備える表示パネルであって、前記薄膜トランジスタは、前記基板の表面に形成されたゲート電極膜と、該ゲート電極膜の上側に形成された半導体層と、該半導体層上に形成された長尺のソース電極膜と、前記半導体層上に複数形成された長尺のドレイン電極膜とを備え、前記複数のドレイン電極膜のうちの少なくとも一つのドレイン電極膜の幅は、前記ソース電極膜の幅より大きい。 The display panel according to the present embodiment is a display panel including a thin film transistor that supplies a driving voltage for turning on / off a pixel thin film transistor corresponding to each of a plurality of pixels arranged in a matrix on a substrate, The thin film transistor includes a gate electrode film formed on a surface of the substrate, a semiconductor layer formed above the gate electrode film, a long source electrode film formed on the semiconductor layer, and the semiconductor layer A plurality of elongated drain electrode films formed thereon, and a width of at least one of the plurality of drain electrode films is larger than a width of the source electrode film.
　本実施の形態に係る薄膜トランンジスタは、基板上にマトリクス状に配置された複数の画素それぞれに対応する画素用薄膜トランジスタをオン／オフさせるための駆動電圧を供給する薄膜トランジスタであって、前記基板の表面に形成されたゲート電極膜と、該ゲート電極膜の上側に形成された半導体層と、該半導体層上に形成された長尺のソース電極膜と、前記半導体層上に複数形成された長尺のドレイン電極膜とを備え、前記複数のドレイン電極膜のうちの少なくとも一つのドレイン電極膜の幅は、前記ソース電極膜の幅より大きい。 The thin film transistor according to the present embodiment is a thin film transistor that supplies a driving voltage for turning on / off a thin film transistor for a pixel corresponding to each of a plurality of pixels arranged in a matrix on the substrate. A gate electrode film formed on the surface; a semiconductor layer formed above the gate electrode film; a long source electrode film formed on the semiconductor layer; and a plurality of lengths formed on the semiconductor layer. And a width of at least one of the plurality of drain electrode films is larger than a width of the source electrode film.
　本実施の形態に係る薄膜トランンジスタの製造方法は、基板上にマトリクス状に配置された複数の画素それぞれに対応する画素用薄膜トランジスタをオン／オフさせるための駆動電圧を供給する薄膜トランジスタの製造方法であって、前記基板の表面にゲート電極膜を形成し、該ゲート電極膜の上側に半導体層を形成し、前記半導体層上に長尺のソース電極膜を形成し、前記半導体層上に前記ソース電極膜の幅より大きい幅を有する長尺のドレイン電極膜を少なくとも一つ含む複数の長尺のドレイン電極膜を形成する。 The method for manufacturing a thin film transistor according to the present embodiment is a method for manufacturing a thin film transistor that supplies a driving voltage for turning on / off a pixel thin film transistor corresponding to each of a plurality of pixels arranged in a matrix on a substrate. A gate electrode film is formed on the surface of the substrate, a semiconductor layer is formed on the gate electrode film, a long source electrode film is formed on the semiconductor layer, and the source is formed on the semiconductor layer. A plurality of long drain electrode films including at least one long drain electrode film having a width larger than the width of the electrode film is formed.
　薄膜トランジスタは、基板の表面に形成されたゲート電極膜と、ゲート電極膜の上側に形成された半導体層と、半導体層上に形成された長尺のソース電極膜及び複数の長尺のドレイン電極膜とを備える。なお、より具体的には、半導体層は、ゲート絶縁膜が形成されたゲート電極膜の上側に形成される。そして、複数のドレイン電極膜のうちの少なくとも一つのドレイン電極膜の幅は、ソース電極膜の幅より大きい。 The thin film transistor includes a gate electrode film formed on a surface of a substrate, a semiconductor layer formed above the gate electrode film, a long source electrode film and a plurality of long drain electrode films formed on the semiconductor layer. With. More specifically, the semiconductor layer is formed above the gate electrode film on which the gate insulating film is formed. The width of at least one drain electrode film among the plurality of drain electrode films is larger than the width of the source electrode film.
　仮に、ドレイン電極膜の幅をソース電極膜の幅と同程度にした場合に、ドレイン電極膜に微小な異物が混入した場合、ドレイン電極膜の異物断線が生じる可能性がある。異物断線が生じると、残りのドレイン電極膜の電流が増加し、スイッチング時の閾値電圧などの特性がシフトし、ストレスによる薄膜トランジスタの性能劣化、あるいは結果的に薄膜トランジスタの不良となる可能性がある。 If the width of the drain electrode film is approximately the same as the width of the source electrode film, and if a minute foreign matter is mixed in the drain electrode film, the drain electrode film may be broken. When the disconnection of the foreign matter occurs, the current of the remaining drain electrode film increases, and characteristics such as threshold voltage at the time of switching shift, and there is a possibility that the performance of the thin film transistor is deteriorated due to stress or the thin film transistor is consequently defective.
　ドレイン電極膜の幅をソース電極膜の幅より大きくすることにより、ドレイン電極膜に微小な異物が混入しても異物断線の発生確率を低下させることができ、薄膜トランジスタの性能劣化を防止し、あるいは薄膜トランジスタの不良を防止することができる。 By making the width of the drain electrode film larger than the width of the source electrode film, it is possible to reduce the probability of occurrence of foreign matter disconnection even if a minute foreign matter is mixed in the drain electrode film, preventing the performance deterioration of the thin film transistor, or Defects of the thin film transistor can be prevented.
　本実施の形態に係る表示パネルにおいて、前記薄膜トランジスタは、前記ソース電極膜を該ソース電極膜の長手方向と直交する方向に沿って複数並列して配置してあり、前記複数のドレイン電極膜のそれぞれを隣り合う前記ソース電極膜の間に該ソース電極膜と平行に配置してある。 In the display panel according to the present embodiment, the thin film transistor includes a plurality of the source electrode films arranged in parallel along a direction orthogonal to the longitudinal direction of the source electrode film, and each of the plurality of drain electrode films. Between the adjacent source electrode films in parallel with the source electrode film.
　薄膜トランジスタは、ソース電極膜をソース電極膜の長手方向と直交する方向に沿って複数並列して配置してあり、複数のドレイン電極膜のそれぞれを隣り合うソース電極膜の間にソース電極膜と平行に配置してある。すなわち、薄膜トランジスタは、ゲート電極膜に対応する領域内において、長尺のソース電極膜及びドレイン電極膜が交互に複数並列して配置してある。 In the thin film transistor, a plurality of source electrode films are arranged in parallel along a direction orthogonal to the longitudinal direction of the source electrode film, and each of the plurality of drain electrode films is parallel to the source electrode film between adjacent source electrode films. It is arranged in. That is, in the thin film transistor, a plurality of long source electrode films and drain electrode films are alternately arranged in parallel in a region corresponding to the gate electrode film.
　仮に、ドレイン電極膜の幅をソース電極膜の幅と同程度にした場合に、ドレイン電極膜に微小な異物が混入して当該ドレイン電極膜が断線すると、当該ドレイン電極膜には電流が流れないため、当該ドレイン電極膜以外のドレイン電極膜に流れる電流が増加する。電流の増加により、スイッチング時の閾値電圧などの特性がシフトし、ストレスによる薄膜トランジスタの性能劣化、あるいは結果的に薄膜トランジスタの不良となる可能性がある。 If the width of the drain electrode film is approximately the same as the width of the source electrode film, if a small foreign matter enters the drain electrode film and the drain electrode film is disconnected, no current flows through the drain electrode film. Therefore, the current flowing through the drain electrode film other than the drain electrode film increases. Due to an increase in current, characteristics such as a threshold voltage at the time of switching shift, and there is a possibility that the performance of the thin film transistor is deteriorated due to stress, or the thin film transistor is consequently defective.
　ドレイン電極膜の幅をソース電極膜の幅より大きくすることにより、ドレイン電極膜に微小な異物が混入してもドレイン電極膜の断線の可能性を小さくすることができ、当該ドレイン電極膜以外のドレイン電極膜に流れる電流の増加を抑制することができ、薄膜トランジスタの性能劣化を防止し、あるいは薄膜トランジスタの不良を防止することができる。 By making the width of the drain electrode film larger than the width of the source electrode film, the possibility of disconnection of the drain electrode film can be reduced even if a minute foreign matter enters the drain electrode film. An increase in the current flowing through the drain electrode film can be suppressed, performance deterioration of the thin film transistor can be prevented, or failure of the thin film transistor can be prevented.
　本実施の形態に係る表示パネルは、前記ゲート電極膜の上側に形成された容量用電極膜を備え、前記容量用電極膜は、前記ドレイン電極膜と接続される第１接続点と、前記薄膜トランンジスタの出力端と接続される第２接続点とを有する。 The display panel according to the present embodiment includes a capacitor electrode film formed on the gate electrode film, the capacitor electrode film including a first connection point connected to the drain electrode film, and the thin film. And a second connection point connected to the output terminal of the transistor.
　表示パネルは、ゲート電極膜の上側に形成された容量用電極膜を備える。そして、容量用電極膜は、ドレイン電極膜と接続される第１接続点と、薄膜トランンジスタの出力端と接続される第２接続点とを有する。 The display panel includes a capacitor electrode film formed on the upper side of the gate electrode film. The capacitor electrode film has a first connection point connected to the drain electrode film and a second connection point connected to the output end of the thin film transistor.
　容量用電極膜は、例えば、ドレイン電極膜の幅方向と平行な向きの寸法が所要の寸法であり、ドレイン電極膜の長手方向と平行な向きの寸法がドレイン電極膜の長さ寸法と同程度の寸法である、矩形状とすることができる。容量用電極膜は、例えば、絶縁膜、あるいは絶縁膜及び半導体層を介してゲート電極膜との間でキャパシタ（具体的には、薄膜トランジスタのゲート・ドレイン間のキャパシタ）を構成する。当該キャパシタは、ブートストラップのためのキャパシタである。 For example, the capacitance electrode film has a required dimension in a direction parallel to the width direction of the drain electrode film, and a dimension in a direction parallel to the longitudinal direction of the drain electrode film is approximately the same as the length dimension of the drain electrode film. It can be made into the rectangular shape which is the dimension of these. The capacitor electrode film forms, for example, a capacitor (specifically, a capacitor between the gate and the drain of the thin film transistor) between the insulating film or the gate electrode film via the insulating film and the semiconductor layer. The capacitor is a bootstrap capacitor.
　ドレイン電極膜の幅をソース電極膜の幅より大きくした場合、半導体層を介したドレイン電極膜とゲート電極膜との間のキャパシタが大きくなるので、容量用電極膜の所要の寸法を小さくしても、薄膜トランジスタのゲート・ドレイン間のキャパシタは変わらないようすることができ、素子全体のサイズを変更する必要がない。別言すれば、ドレイン電極膜の幅を大きくしても、容量用電極膜の所要の寸法を小さくすることができ、素子全体のサイズは変わらない。 When the width of the drain electrode film is made larger than the width of the source electrode film, the capacitor between the drain electrode film and the gate electrode film through the semiconductor layer increases, so the required dimension of the capacitor electrode film is reduced. However, the capacitor between the gate and the drain of the thin film transistor can be kept unchanged, and there is no need to change the size of the entire device. In other words, even if the width of the drain electrode film is increased, the required dimension of the capacitor electrode film can be reduced, and the size of the entire element does not change.
　１０　ゲート電極膜
　１１　非晶質半導体層
　１２　絶縁膜
　１３　ソース電極膜
　１４　ドレイン電極膜
　１５　容量用電極膜
　６０　ゲート回路部
　１００　表示パネル DESCRIPTION OF SYMBOLS 10 Gate electrode film 11 Amorphous semiconductor layer 12 Insulating film 13 Source electrode film 14 Drain electrode film 15 Capacitor electrode film 60 Gate circuit part 100 Display panel

Claims (5)

  1. 　基板上にマトリクス状に配置された複数の画素それぞれに対応する画素用薄膜トランジスタをオン／オフさせるための駆動電圧を供給する薄膜トランジスタを備える表示パネルであって、
    　前記薄膜トランジスタは、
    　前記基板の表面に形成されたゲート電極膜と、
    　該ゲート電極膜の上側に形成された半導体層と、
    　該半導体層上に形成された長尺のソース電極膜と、
    　前記半導体層上に複数形成された長尺のドレイン電極膜と
    　を備え、
    　前記複数のドレイン電極膜のうちの少なくとも一つのドレイン電極膜の幅は、前記ソース電極膜の幅より大きい表示パネル。     A display panel including a thin film transistor that supplies a driving voltage for turning on / off a thin film transistor for a pixel corresponding to each of a plurality of pixels arranged in a matrix on a substrate,
    The thin film transistor
    A gate electrode film formed on the surface of the substrate;
    A semiconductor layer formed above the gate electrode film;
    A long source electrode film formed on the semiconductor layer;
    A plurality of elongated drain electrode films formed on the semiconductor layer,
    The display panel has a width of at least one drain electrode film of the plurality of drain electrode films larger than a width of the source electrode film.
  2. 　前記薄膜トランジスタは、
    　前記ソース電極膜を該ソース電極膜の長手方向と直交する方向に沿って複数並列して配置してあり、
    　前記複数のドレイン電極膜のそれぞれを隣り合う前記ソース電極膜の間に該ソース電極膜と平行に配置してある請求項１に記載の表示パネル。     The thin film transistor
    A plurality of the source electrode films are arranged in parallel along a direction perpendicular to the longitudinal direction of the source electrode film,
    The display panel according to claim 1, wherein each of the plurality of drain electrode films is arranged in parallel with the source electrode film between the adjacent source electrode films.
  3. 　前記ゲート電極膜の上側に形成された容量用電極膜を備え、
    　前記容量用電極膜は、
    　前記ドレイン電極膜と接続される第１接続点と、
    　前記薄膜トランンジスタの出力端と接続される第２接続点と
    　を有する請求項１又は請求項２に記載の表示パネル。     A capacitor electrode film formed on the gate electrode film;
    The capacitor electrode film comprises:
    A first connection point connected to the drain electrode film;
    The display panel according to claim 1, further comprising: a second connection point connected to an output end of the thin film transistor.
  4. 　基板上にマトリクス状に配置された複数の画素それぞれに対応する画素用薄膜トランジスタをオン／オフさせるための駆動電圧を供給する薄膜トランジスタであって、
    　前記基板の表面に形成されたゲート電極膜と、
    　該ゲート電極膜の上側に形成された半導体層と、
    　該半導体層上に形成された長尺のソース電極膜と、
    　前記半導体層上に複数形成された長尺のドレイン電極膜と
    　を備え、
    　前記複数のドレイン電極膜のうちの少なくとも一つのドレイン電極膜の幅は、前記ソース電極膜の幅より大きい薄膜トランジスタ。     A thin film transistor that supplies a driving voltage for turning on / off a thin film transistor for a pixel corresponding to each of a plurality of pixels arranged in a matrix on a substrate,
    A gate electrode film formed on the surface of the substrate;
    A semiconductor layer formed above the gate electrode film;
    A long source electrode film formed on the semiconductor layer;
    A plurality of elongated drain electrode films formed on the semiconductor layer,
    A thin film transistor in which a width of at least one of the plurality of drain electrode films is larger than a width of the source electrode film.
  5. 　基板上にマトリクス状に配置された複数の画素それぞれに対応する画素用薄膜トランジスタをオン／オフさせるための駆動電圧を供給する薄膜トランジスタの製造方法であって、
    　前記基板の表面にゲート電極膜を形成し、
    　該ゲート電極膜の上側に半導体層を形成し、
    　前記半導体層上に長尺のソース電極膜を形成し、
    　前記半導体層上に前記ソース電極膜の幅より大きい幅を有する長尺のドレイン電極膜を少なくとも一つ含む複数の長尺のドレイン電極膜を形成する薄膜トランジスタの製造方法。     A method of manufacturing a thin film transistor for supplying a driving voltage for turning on / off a thin film transistor for a pixel corresponding to each of a plurality of pixels arranged in a matrix on a substrate,
    Forming a gate electrode film on the surface of the substrate;
    Forming a semiconductor layer on the gate electrode film;
    Forming a long source electrode film on the semiconductor layer;
    A method of manufacturing a thin film transistor, wherein a plurality of long drain electrode films including at least one long drain electrode film having a width larger than the width of the source electrode film is formed on the semiconductor layer.
PCT/JP2016/085415 2016-11-29 2016-11-29 Display panel, thin-film transistor, and method of manufacturing thin-film transistor WO2018100642A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2016/085415 WO2018100642A1 (en) 2016-11-29 2016-11-29 Display panel, thin-film transistor, and method of manufacturing thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2016/085415 WO2018100642A1 (en) 2016-11-29 2016-11-29 Display panel, thin-film transistor, and method of manufacturing thin-film transistor

Publications (1)

Publication Number Publication Date
WO2018100642A1 true WO2018100642A1 (en) 2018-06-07

Family

ID=62242393

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2016/085415 WO2018100642A1 (en) 2016-11-29 2016-11-29 Display panel, thin-film transistor, and method of manufacturing thin-film transistor

Country Status (1)

Country Link
WO (1) WO2018100642A1 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009150864A1 (en) * 2008-06-12 2009-12-17 シャープ株式会社 Tft, shift register, scanning signal line drive circuit, and display
JP2010272664A (en) * 2009-05-21 2010-12-02 Sony Corp A-sitft and shift register having this a-sitft
JP2010277652A (en) * 2009-05-29 2010-12-09 Mitsubishi Electric Corp Shift register circuit, method for designing shift register circuit, and semiconductor device
WO2011135873A1 (en) * 2010-04-28 2011-11-03 シャープ株式会社 Shift register and display device
JP2014026258A (en) * 2012-07-24 2014-02-06 Samsung Display Co Ltd Display device
JP2016526247A (en) * 2013-04-24 2016-09-01 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． Shift register unit and display device
JP2016167093A (en) * 2012-04-20 2016-09-15 シャープ株式会社 Display device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009150864A1 (en) * 2008-06-12 2009-12-17 シャープ株式会社 Tft, shift register, scanning signal line drive circuit, and display
JP2010272664A (en) * 2009-05-21 2010-12-02 Sony Corp A-sitft and shift register having this a-sitft
JP2010277652A (en) * 2009-05-29 2010-12-09 Mitsubishi Electric Corp Shift register circuit, method for designing shift register circuit, and semiconductor device
WO2011135873A1 (en) * 2010-04-28 2011-11-03 シャープ株式会社 Shift register and display device
JP2016167093A (en) * 2012-04-20 2016-09-15 シャープ株式会社 Display device
JP2014026258A (en) * 2012-07-24 2014-02-06 Samsung Display Co Ltd Display device
JP2016526247A (en) * 2013-04-24 2016-09-01 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． Shift register unit and display device

Similar Documents

Publication Publication Date Title
JP5630937B2 (en) Gate driver
CN106935214B (en) Display device
US5744820A (en) Liquid crystal display device with a disconnected wiring pattern attached by independent metal wiring
US10254612B2 (en) Display panel and method of fabricating the same
US7804097B2 (en) Liquid crystal display device
US5606340A (en) Thin film transistor protection circuit
KR101359923B1 (en) Display device and method of drive for the same
JP6196015B2 (en) TFT substrate and manufacturing method thereof
US8780309B2 (en) Mother panel of liquid crystal display and method of manufacturing liquid crystal display using the same
CN110658658B (en) Image display device
JP2007316104A (en) Display device
KR20060134730A (en) Array substrate and display device having the same
JP4532180B2 (en) LCD panel
WO2020015493A1 (en) Electrostatic protection circuit, array substrate and display device
WO2015122393A1 (en) Active matrix substrate
US10698273B2 (en) Image display device
US20180149911A1 (en) Drive circuit of display device
US7550764B2 (en) Liquid crystal display device and method of fabricating the same
KR101696393B1 (en) Display panel
KR20150087647A (en) Gate driving circuit and display device having the same
KR102365774B1 (en) Thin film trannsistor array panel and manufacturing method thereof
US20060158598A1 (en) Liquid crystal display
US20150338692A1 (en) Display device
WO2018100642A1 (en) Display panel, thin-film transistor, and method of manufacturing thin-film transistor
JP2009015049A (en) Liquid crystal display

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16923051

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16923051

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP