WO2018089055A1 - Remplacement de composant de bande de base par un composant logiciel - Google Patents

Remplacement de composant de bande de base par un composant logiciel Download PDF

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Publication number
WO2018089055A1
WO2018089055A1 PCT/US2017/039909 US2017039909W WO2018089055A1 WO 2018089055 A1 WO2018089055 A1 WO 2018089055A1 US 2017039909 W US2017039909 W US 2017039909W WO 2018089055 A1 WO2018089055 A1 WO 2018089055A1
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WIPO (PCT)
Prior art keywords
component
target
data
radio
interface
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PCT/US2017/039909
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English (en)
Inventor
Markus Dominik Mueck
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Intel IP Corporation
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Publication of WO2018089055A1 publication Critical patent/WO2018089055A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end

Definitions

  • This application relates to radio access technology (RAT) and, in particular, to apparatus for substituting a software component for a baseband or higher level component of the radio equipment (RAT).
  • RAT radio access technology
  • RAT radio equipment
  • RTS Radio Virtual Machine
  • ETSI technical specification (TS) 103 146-4 introduces the RVM programming environment which allows providers to build software components based on a hierarchical combination of so-called Radio Virtual Machines (RVM), which can be combined horizontally to implement components in the physical layer of the open systems interconnection (OSI) model, for example, the cyclic redundancy code (CRC) generation, channel encoding, interleaving, constellation mapping and modulation functions in the physical layer of a mobile device.
  • RVM Radio Virtual Machines
  • CRC cyclic redundancy code
  • the frequency spectrum used for voice and data transmission may vary from locality to locality. Furthermore, in some jurisdictions, spectrum may be lightly used and, thus, available for sharing among different types of devices. Using the RVM model, a manufacturer may provide multiple sets of radio components so that a single hardware device may be reprogrammed conform to the spectrum limitations of multiple jurisdictions.
  • FIG.1 is a block diagram of an example RVM.
  • FIG. 2A is a block diagram showing baseband components of a spell RAT.
  • FIGs. 2B, 2C, 2D, 2E, and 2F are a block diagrams of RATs in which one or more of the baseband components or higher level components have been replaced by a standard functional block (SFB) or user defined functional block (UDFB).
  • SFB standard functional block
  • UDFB user defined functional block
  • FIGs.3A and 3B are flowchart diagrams describing the generation and use of a black-box SFB implementing an interface to a component of RVM.
  • FIGs. 4A, 4B, 4C and 4D are block diagrams of example RATs configured to allow third-party developers to implement replacements for components of the RAT.
  • FIG.5 is a block diagram showing example hardware components used in a unidirectional black box SFB.
  • FIG.6 is a block diagram showing example hardware components used in a bidirectional black box SFB.
  • FIG. 7 is a block diagram showing a replacement RVM that uses the same hardware as the component it replaces.
  • FIG. 8 is a block diagram showing possible configurations of hardware elements to implement a replacement RVM.
  • ETSI technical specification concerns software-defined modules that implement an entire RAT. It would be beneficial if an equipment manufacturer could provide a device having multiple hardware elements and selectively allows third-party developers to substitute software components for one or more of these hardware elements.
  • a selected element of an initial (hardwired) implementation can be replaced by an RVM software module component.
  • any location dependent command may be validated by a“black-box” component which is typically integrated on the communication chipset (or interacts with the communication chipset as an external component).
  • This black box component determines the location of the device and compares any reconfiguration/re- parameterization command with an internal lookup-table that contains locally applicable requirements (such as allowed carrier frequencies, allowed bandwidths, allowed maximum output power levels, etc.). Only when the device operates according to the applicable rules after reconfiguration/re-parameterization, will the reconfiguration/re-parameterization commands be finally executed. Otherwise, the reconfiguration/re-parameterization commands are rejected or the closest allowable parameter set is chosen.
  • the determination of the location can be performed in various ways, including i) using NGSS (e.g., GPS, etc.) and/or ii) decoding (beacon) signals of surrounding communication systems (such as WiFi, LTE, etc.) in order to extract location/country Identifiers.
  • NGSS e.g., GPS, etc.
  • decoding beacon signals of surrounding communication systems (such as WiFi, LTE, etc.) in order to extract location/country Identifiers.
  • This identifier provides information on the country where the device is currently positioned and the requirements/rules of this country will thus be enforced.
  • the device may either take a) any available signal (such as WiFi, LTE, etc.) or b) only signals from trusted sources (e.g., LTE of a known carrier) or c) use a group of available signals and compares the country identifiers; if all signals indicate the same country, this country identifier is assumed to be reliable and will be applied.
  • the device uses the country identifier which is carried by the largest number of signals (e.g., one signal indicates “FRANCE” and 10 others signals indicate“JAPAN”, then we assume that “JAPAN” is the correct identifier).
  • a large number of signals need to indicate the same country identifier before it is considered to be reliable and trustworthy.
  • the system may require that a certain percentage of signals need to indicate the some country identifier (e.g., 60% of all signals of, e.g., at least 10 signals or more must indicate the same country identifier, otherwise it is rejected; alternatively, two or more different systems (such as LTE Base Stations and WiFi Access Points) may be required to carry the same country identifier).
  • the system may either reject the reconfiguration/re-parameterization command or may require that some basic parameter requirements must be met which are allowed in all regions (i.e., carrier frequencies allowed in all regions, bandwidth allowed in all regions, maximum output power allowed in all regions, etc.).
  • Hardwired implementations may include circuitry (such as accelerator circuits, etc.), Digital Signal Processor(s) (DSPs), Application Processor(s) (APs), Field Programmable Gate Array(s) (FPGA(s)), etc.
  • the hardwired implementations may include software or firmware that allows for some level of reconfigurability. When the change is substantial or involves adding features, however, such a hardwired component may be replaced by fully software reconfigurable resources and the corresponding code as described in the example embodiments.
  • FIG. 1 is a block diagram of an example radio virtual machine (RVM) 100 that allows for user-defined functional blocks (UDFBs).
  • the RVM 100 includes a program memory 102 that holds code for basic operations, a program memory 104 that holds configcodes and a control unit 106.
  • the control unit controls multiple abstract processing elements (APEs) 110–110M, multiple data objects (DOs) 108A–108N and an abstract switch fabric 112.
  • the basic operations stored in the memory 102 include both standard functional blocks (SFBs) and UDFBs.
  • the SFBs and UDFBs are in the form of object code for the APEs 110A–110M.
  • the configcodes in the program memory 104 may be in the form of source code, for example C, C++, etc. configcodes stored in the program memory 104 may be converted to object code SFBs or UDFBs for the APEs 110A – 110M by a compiler configured to run on one of the APEs or on the control unit 106.
  • the components of the example RVM 100 are meant to convey the operational flow of the RVM.
  • the actual implementation may be different from what is shown in FIG.1.
  • the processing elements of the RVM (APEs 110A-110M) and the control unit 106 may include one or more single-core or multi-core processors, digital signal processors (DSPs), microcontrollers, field- programmable gate arrays (FPGAs), programmable logic arrays (PLAs), or other programmable processing elements.
  • the memory elements of the RVM may include a single memory that is shared by the processing elements, multiple shared memory elements (DOs 108A-108N) and/or multiple dedicated memory elements coupled, respectively, to the multiple processing elements.
  • the switch fabric may be a system of busses coupling the memories to the processors and/or a multiple- input multiple output switch fabric, such as a cross-point switch.
  • the control unit 106 stores data provided by one of the APEs 110A–110M or from the external ports 114 into one or more of the data objects 108A–108N.
  • the abstract switch fabric 112 is controlled by control unit 106 to couple one or more of the data objects 108A–108N to one or more of the APEs 110A–110M.
  • the control unit 106 also receives status information from the DOs 108A–108N and from the APEs 110A–110M.
  • the status information from the DOs 108A–108N includes information on the amount of data in each DO.
  • the status information from the APEs 110A–110M includes information on the status of the operations performed by each of the APEs.
  • the control unit 106 provides status information to the RAT.
  • FIG. 2A shows a RAT 200 that includes five baseband components: a cyclic redundancy code (CRC) generator 202, a channel encoder 204, an interleaver 206, a constellation mapper 208 and a modulator 210.
  • the RAT 200 may be, for example, part of user equipment (UE), part of and access point (AP), part of an evolved node B (eNB), part of a next generation Node B (gNB), including a microcell or picocell, or part of another radio device.
  • UE user equipment
  • AP access point
  • eNB evolved node B
  • gNB next generation Node B
  • FIG.2B shows an example RAT 200 in which the channel encoder 204 has been replaced by an RVM based component 220 (e.g. an SFB implemented on one or more processing elements of an RVM).
  • the RVM component 220 may change a Turbo Code encoding component of the RAT 200 to target component including a modern Multi-Edge low density parity check (LDPC) encoding.
  • LDPC Multi-Edge low density parity check
  • the RVM described by the above-referenced ETSI technical specification does not describe how the interfacing to the inputs/outputs of the original possibly hardwired component can be“rerouted” to a RVM Software based component. The embodiments described below show how this interface can be implemented and made available to the developer of software components.
  • Embodiments described below disclose how a user programmable interface can be introduced which“reroutes” the inputs/outputs of the original component to an RVM based software solution replacement of that component.
  • Current RVM proposals do not foresee the replacement of specific (baseband) component by software based versions. Rather, an entire Radio Access Technology (RAT) is provided in a software version.
  • RAT Radio Access Technology
  • Embodiments of the present disclosure allow manufacturers to gradually open a given platform to software developers–possibly third party software developers– and enable the developers to replace only those components which are authorized to be changed by the manufacturers.
  • the manufacturer identifies the inputs/outputs of the target radio component that will be available for replacement through a software component and provides a“black-box” SFB 222, shown in FIG. 2C, that provides the developers with access those inputs and outputs.
  • the manufacturer defines specific inputs and outputs for the target radio component 204 to be used by the (third party) software developer as shown by the respective circles 203 and 205 in FIG.2C.
  • the manufacturer then generates a black-box SFB 222 that provides developers with access to the inputs of the original (e.g. hardwired) component 204 and also to accept outputs replacing the outputs of the original component 204.
  • the black-box SFB 222 may have no functionality beyond providing data describing one or more interfaces (e.g. application program interfaces (APIs)) for the target radio component 204 to the developers.
  • the black-box SFB 222 may have limited functionality, such as buffering, synchronization or similar interfacing features. This functionality may be implemented either in hardware or software.
  • the example black-box serves to connect the inputs/outputs of additional software components in place of the original inputs/outputs of the target radio component 204 of the RAT.
  • the corresponding black-box SFB 222 may be provided to the software development ecosystem in the form of native object code of the APE of the RVM.
  • the black-box SFB 222 can either be made available to a front-end compiler (e.g., offline compilation in a remote site– e.g., different from compilation on the device including the RAT 200) or a back-end compiler (e.g., online compilation on the device).
  • a third party software developer may replace the original component 204 by accessing the inputs/outputs of the black-box SFB 222 which are made available for specific usage.
  • This (third party) component may then be made available as a User Defined Functional Block (UDFB) to a Radio App Store.
  • UDFB User Defined Functional Block
  • FIG. 2C shows how the new functionality, for example, the New RVM Channel Coding 224 can fully replace the original component 204.
  • the RAT may switch between the original component 204 and the new (e.g. software) component 224 when needed.
  • the example RAT 200 can remove power from the original component 204 using the switch 226.
  • the new component 224 can be replaced by a newer version whenever required, the new component 224 can be activated for a pre-define duration, for example from now until the end of the year, etc., or for a fraction of the time for example, for any week-day from 9 am to noon, etc. Alternatively or in addition, the new component 224 can be activated upon occurrence of an external trigger or an internal trigger such as a sensing a new location by the RAT, sensing a particular type of interference for which the new component would perform better, etc.
  • a specific authorization may be provided to allow access to the black-box SFB 222.
  • the hardware manufacturer may include a request for a password or encryption key in the black-box SFB 222 before allowing the developer access to the input and output data.
  • this authorization is valid only for a limited period and must be re-confirmed for any extension. If a malfunctioning of the new component 224 is detected (either through an external trigger or by the target platform itself e.g. through suitable (loop-back) tests, sensing, etc.), the RAT 200 may fall back to a safe state, e.g. the original component 204 may be reactivated and the new component 224 may be deactivated.
  • the activation of the new component 224 may also depend on environmental triggers, such as the presence of interferers, incumbent users, etc.
  • the power supply for the component 204 can be disabled, for example using the switch 226.
  • the switch 226 may be a transmission gate that is controlled by control circuitry in the RAT 200 or in the new component 224 to decouple the original component from a source of operational power (e.g. VCC). This will save power for the target device that includes the RAT 200.
  • a source of operational power e.g. VCC
  • various black box SFBs each for a respective component of the RAT 200 can be made available to software developers, including third- party software developers, over time, e.g., the manufacturer has full control over which components will be available for replacement when and by whom. It is thus possible for a manufacturer to carefully open up the RAT platform 200 step by step and component by component.
  • a black-box SFB 226 may be used to replace more than one component of the RAT 200.
  • the black-box SFB 226 includes data describing an interface (e.g. an API) for the inputs to component 204 and for the outputs of component 206.
  • the manufacturer determines the inputs to component 204 and the outputs from component 206 as shown by the circles 203 and 207, respectively.
  • the target module including the black box SFB 226 and the new component 228 replaces both the channel encoding and interleaving components 204 and 206.
  • the black-box SFB is a unidirectional module, providing inputs for the new component 224 at an output port and receiving outputs from the new component 224 at an input port.
  • a new component 232 may be bidirectional.
  • the RAT shown in FIG. 2E includes a demodulator 252, a constellation demapper 254, a deinterleaver 256, a channel decoder 258 and a CRC checker 260.
  • the new component 232 replaces both the channel encoder 204 and the channel decoder 258.
  • the black- box SFB 230 provides access to the inputs and outputs of both components 204 and 258.
  • the examples described above concern components in the physical layer of the RAT 200. It is contemplated, however, that an RVM may also replace components at higher layers of the OSI model. For example, device security is often implemented at OSI levels 2 and 3.
  • a new component 236 may replace the security mechanism employed on the RAT 200.
  • the manufacturer may provide data describing the input and output interfaces for the security module 272 implemented in the level 2/level 3 processing block 270 of the RAT 200 as the black-box SFB 234.
  • the new component 236, may then replace the security module in the block 270.
  • the replaced components may be at higher layers of the OSI model, for example, the application layer.
  • the manufacturer may open a target component, for example, a function of the operating system of the device including the RAT to be replaced by a UDFB running on the RVM computing platform.
  • FIG.3A is a flowchart diagram showing how a manufacturer may produce a black-box SFB.
  • the manufacturer identifies input and output signals for the target radio component or components to be replaced.
  • the manufacturer may identify constraints on the input and output values and timing restrictions.
  • the manufacturer uses the information from blocks 302 and 304 at block 306 to generate the data describing the input and output interfaces (e.g. APIs) for the block to be replaced.
  • the manufacturer converts the data describing the input and output interfaces into one or more SFBs.
  • the SFBs as well as descriptions of the SFBs and any constraints and timing requirements are provided in the radio app library (not shown in FIG.3A).
  • FIG. 3B is a flowchart diagram showing how a developer, including a third-party developer, may use the black-box SFB to generate a replacement for the target component.
  • the developer accesses the descriptions of the black-box interfaces as well as any constraints and timing restrictions from the library. Based on these descriptions, constraints and restrictions, the developer generates program code for the replacement for the target component at block 354. The generated code may be compiled to generate an SFB in the native object code of a processor in the RVM platform of the RAT 200.
  • the developer links the replacement for the target component to the interfaces described in the black box SFB from the library to generate the target component.
  • the developer may incorporate the black-box SFBs into the UDFB that implements the replacement for the target component.
  • the developer tests the replacement component in the RAT 200 at block 358.
  • the combination of the black-box SFB and the UDFB forms a target module that is configured to replace the target component of the device including the RAT 400.
  • FIG. 4A is a block diagram of a RAT 400 that includes an RVM computing platform 412 and that is linked to an APPS store 430 and optionally is configured to receive radio APPS source code from a database 420.
  • the RVM platform 412 may also include a third-party developer interface 432 configured to provide the developer with access to the interfaces described in the black box SFB via ports 434 as well as timing signals 436.
  • the RVM platform 412 is coupled to the application circuitry 402 as well as to the baseband circuitry 404.
  • UDFBs configured to run on the RVM computing platform may substitute for target software components configured to run using the application circuitry 402. These may include target components in the transport, session, presentation and application layers of the OSI model.
  • Embodiments of the RAT 400 described herein may be implemented in a system using any suitably configured hardware and/or software.
  • the RAT 400 may be incorporated into, or otherwise be a part of user equipment (UE), including: a Global System for Mobile Communications (GSM) radio communication technology, a General Packet Radio Service (GPRS) radio communication technology, an Enhanced Data Rates for GSM Evolution (EDGE) radio communication technology, and/or a Third Generation Partnership Project (3GPP) radio communication technology, for example Universal Mobile Telecommunications System (UMTS), Freedom of Multimedia Access (FOMA), 3GPP Long Term Evolution (LTE), 3GPP Long Term Evolution Advanced (LTE Advanced), Code division multiple access 2000 (CDMA2000), Cellular Digital Packet Data (CDPD), Mobitex, Third Generation (3G), Circuit Switched Data (CSD), High-Speed Circuit-Switched Data (HSCSD), Universal Mobile Telecommunications System (Third Generation) (UMTS (3G)), Wideband Code Division Multiple Access (Universal Mobile Mobile Communications (GSM
  • Applicable spectrum bands include IMT (International Mobile Telecommunications) spectrum (including 450– 470 MHz, 790– 960 MHz, 1710 – 2025 MHz, 2110– 2200 MHz, 2300– 2400 MHz, 2500– 2690 MHz, 698-790 MHz, 610– 790 MHz, 3400– 3600 MHz, etc.).
  • IMT-advanced spectrum IMT-2020 spectrum (expected to include 3600-3800 MHz, 3.5 GHz bands, 700 MHz bands, bands within the 24.25-86 GHz range, etc.), spectrum made available under FCC’s "Spectrum Frontier" 5G initiative (including 27.5– 28.35 GHz, 29.1– 29.25 GHz, 31– 31.3 GHz, 37– 38.6 GHz, 38.6– 40 GHz, 42– 42.5 GHz, 57– 64 GHz, 64 – 71 GHz, 71– 76 GHz, 81– 86 GHz and 92– 94 GHz, etc.), the ITS (Intelligent Transport Systems) band of 5.9 GHz (typically 5.85-5.925 GHz) and 63-64 GHz, bands currently allocated to WiGig such as WiGig Band 1 (57.24-59.40 GHz), WiGig Band 2 (59.40-61.56 GHz) and WiGig Band 3
  • WiGig Band 1 57.24-59.40 GHz
  • the scheme can be used on a secondary basis on bands such as the TV White Space bands (typically below 790 MHz) where in particular the 400 MHz and 700 MHz bands are promising candidates.
  • TV White Space bands typically below 790 MHz
  • PMSE Program Making and Special Events
  • medical, health, surgery, automotive, low-latency, drones, and other applications are also possible.
  • Example embodiments may be implemented with a hierarchical prioritization of usage for different types of users (e.g., low/medium/high priority, etc.), based on a prioritized access to the spectrum. For example, users with highest priority may be assigned to tier-1, followed by tier-2, then tier-3, etc. for lower priority users.
  • Example embodiments can also be applied to different Single Carrier or OFDM flavors (CP-OFDM, SC-FDMA, SC-OFDM, filter bank-based multicarrier (FBMC), OFDMA, etc.) and in particular 3GPP NR (New Radio) by allocating the OFDM carrier data bit vectors to the corresponding symbol resources.
  • CP-OFDM Single Carrier or OFDM flavors
  • SC-FDMA SC-FDMA
  • SC-OFDM filter bank-based multicarrier
  • OFDMA filter bank-based multicarrier
  • 3GPP NR New Radio
  • the application circuitry 402 may include one or more application processors.
  • the application circuitry 402 may include circuitry such as, but not limited to, one or more single-core or multi-core processors (not separately shown).
  • the processor(s) may include any combination of general- purpose processors and dedicated processors (e.g., graphics processors, application processors, DSPs, etc.).
  • the processors may be coupled with and/or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications and/or operating systems to run on the system.
  • the baseband circuitry 404 may include circuitry such as, but not limited to, one or more single-core or multi-core processors.
  • the baseband circuitry 404 may include one or more baseband processors and/or control logic to process baseband signals received from a receive signal path of the RF circuitry 406 and to generate baseband signals for a transmit signal path of the RF circuitry 406.
  • Baseband processing circuity 404 may interface with the application circuitry 402 for generation and processing of the baseband signals and for controlling operations of the RF circuitry 406.
  • the baseband circuitry 404 includes one or more of baseband processors 404A-404D that may handle various radio control functions which enable communication with one or more radio networks via the RF circuitry 406.
  • the radio control functions may include, but are not limited to, signal modulation/demodulation, constellation mapping/demapping, interleaving/deinterleaving, channel encoding/decoding, CRC generation/checking radio frequency shifting, etc.
  • modulation/demodulation circuitry of the baseband circuitry 404 may include a Fast-Fourier Transform (FFT) and/or inverse FFT (IFFT).
  • FFT Fast-Fourier Transform
  • IFFT inverse FFT
  • encoding/decoding circuitry of the baseband circuitry 404 may include convolution, tail-biting convolution, turbo, Viterbi, and/or Low Density Parity Check (LDPC) encoder/decoder functionality.
  • LDPC Low Density Parity Check
  • the baseband circuitry 404 may include elements of a protocol stack such as, for example, elements of an evolved universal terrestrial radio access network (EUTRAN) protocol including, for example, physical (PHY), media access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), and/or radio resource control (RRC) elements.
  • EUTRAN evolved universal terrestrial radio access network
  • a central processing unit (CPU) 404E of the baseband circuitry 404 may be configured to run elements of the protocol stack for signaling of the PHY, MAC, RLC, PDCP and/or RRC layers.
  • the baseband circuitry may include one or more audio digital signal processor(s) (DSP) 404F.
  • DSP audio digital signal processor
  • the audio DSP(s) 404F may be include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments.
  • the baseband circuitry 404 may further include memory/storage 404G.
  • the memory/storage 404G may be used to load and store data and/or instructions for operations performed by the processors of the baseband circuitry 404.
  • Memory/storage for one embodiment may include any combination of suitable volatile memory and/or non-volatile memory.
  • the memory/storage 404G may include any combination of various levels of memory/storage including, but not limited to, read-only memory (ROM) having embedded software instructions (e.g., firmware), random access memory (e.g., dynamic random access memory (DRAM)), cache, buffers, etc.
  • the memory/storage 404G may be shared among the various processors or dedicated to particular processors.
  • Components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments.
  • some or all of the constituent components of the baseband circuitry 404 and the application circuitry 402 and the RVM computing platform 412 may be implemented together such as, for example, on a system on a chip (SOC).
  • the components of the baseband circuitry 404 are coupled to each other via a bus 405. Traffic on the bus 405 is controlled by an arbitration module 404H.
  • the bus 405 shown in FIG. 4A is a control bus through which the CPU 404E controls the baseband processors 404A, 404B, 404C and 404D and the audio DSP 404G.
  • the data processed by baseband processors 404A, 404B, 404C, and 404D is passed sequentially between the baseband processors via respective buses 407A, 407B and 407C.
  • Data provided by the application circuitry 402 and by each of the baseband processors 404A, 404B, 404C, and 404D is provided to the RVM computing platform 412 by separate buses coupled to the inputs and outputs of the baseband processors. Although it is not shown, it is contemplated that inputs and outputs of the audio DSP 404G may also be provided to the RVM computing platform 412.
  • the RVM computing platform 412 may be coupled to receive SFBs and UDFBs from an APPS store 430.
  • Source code for the radio APPS is stored in a library 420.
  • the source code in the library 420 is also coupled to the RVM computing platform 412 to provide source code for the SFBs and UDFBs to a radio library 412C and a backend compiler 412D.
  • source code for the SFBs and UDFBs is compiled into programs in the native object code of a processing element (e.g. an APE) of the RVM computing platform 412 by the backend compiler 412D.
  • the object code programs provided by the backend compiler 412D may be stored in the radio library 412C for use by one of the processors 412A–412K to implement a substitute component for one or more of the existing components of the RAT.
  • the database 420 containing source code for the radio APPs may also be provided to a front-end compiler 422 which compiles the source code APPs either from the database 420 or the radio library 424 these apps are compiled in the native object code of at least one processing element of the RVM computing platform 412. These compiled APPs may then be tested on a shadow radio platform 426 before me being combined with other APPs to form a radio APPs package 428 which is then made available to the RAT 400 via the APPs store 430.
  • the baseband circuitry 404 may provide for communication compatible with one or more radio technologies.
  • the baseband circuitry 404 may support communication with an evolved universal terrestrial radio access network (EUTRAN) and/or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), a wireless personal area network (WPAN).
  • EUTRAN evolved universal terrestrial radio access network
  • WMAN wireless metropolitan area networks
  • WLAN wireless local area network
  • WPAN wireless personal area network
  • multi-mode baseband circuitry Embodiments in which the baseband circuitry 404 is configured to support radio communications of more than one wireless protocol.
  • RF circuitry 406 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium.
  • the RF circuitry 406 may include switches, filters, amplifiers, etc. to facilitate the communication with the wireless network.
  • RF circuitry 406 may include one or more transmit /receive signal paths which may include circuitry to up-convert or down-convert RF signals provided to or received from the FEM circuitry 408 and receive baseband signals from or provide baseband signals to the baseband circuitry 404.
  • the RF circuitry 406 may include a one or more receive signal paths and transmit signal paths.
  • the example receive signal path of the RF circuitry 406 may include mixer circuitry 406A, amplifier circuitry 406B and filter circuitry 406C.
  • the transmit signal path of the RF circuitry 406 may include filter circuitry 406C and mixer circuitry 406A.
  • RF circuitry 406 may also include synthesizer circuitry 406D for synthesizing a frequency for use by the mixer circuitry 406A of the receive signal path and the transmit signal path.
  • the mixer circuitry 406A of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 408 based on the synthesized frequency provided by synthesizer circuitry 406D.
  • the amplifier circuitry 406B may be configured to amplify the down-converted signals and the filter circuitry 406C may be a low-pass filter (LPF) or band-pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals.
  • Output baseband signals may be provided to the baseband circuitry 404 for further processing.
  • the output baseband signals may be, without limitation, low intermediate frequency (LIF), very low intermediate frequency (VLIF) or zero-frequency baseband signals.
  • mixer circuitry 406A of the receive signal path may comprise, without limitation, active or passive mixers.
  • the mixer circuitry 406A of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 406D to generate RF output signals for the FEM circuitry 408.
  • the baseband signals may be provided by the baseband circuitry 404 and may be filtered by filter circuitry 406C.
  • the filter circuitry 406C may include a BPF or a high-pass filter (HPF), although the scope of the embodiments is not limited in this respect.
  • the mixer circuitry 406A of the receive signal path and the mixer circuitry 406A of the transmit signal path may include two or more mixers and may be arranged for quadrature downconversion and/or upconversion respectively.
  • the mixer circuitry 406A of the receive signal path and the mixer circuitry 406A of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection).
  • the mixer circuitry 406A of the receive signal path and the mixer circuitry 406A may be arranged for direct downconversion and/or direct upconversion, respectively.
  • the mixer circuitry 406A of the receive signal path and the mixer circuitry 406A of the transmit signal path may be configured for super-heterodyne operation.
  • the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect.
  • the output baseband signals and the input baseband signals may be digital baseband signals.
  • the RF circuitry 406 may include analog- to-digital converter (ADC) circuitry (not shown) and digital-to-analog converter (DAC) circuitry (not shown) and the baseband circuitry 404 may include a digital baseband interface to communicate with the RF circuitry 406.
  • ADC analog- to-digital converter
  • DAC digital-to-analog converter
  • separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.
  • the synthesizer circuitry 406D may be a fractional-N synthesizer or a fractional N/N+1 synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable.
  • synthesizer circuitry 406D may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider.
  • the synthesizer circuitry 406D may be configured to synthesize an output frequency for use by the mixer circuitry 406A of the RF circuitry 406 based on a frequency input and a divider control input. In some embodiments, the synthesizer circuitry 406D may be a fractional N/N+1 synthesizer.
  • Synthesizer circuitry 406D of the RF circuitry 406 may include a divider, a delay-locked loop (DLL), a multiplexer and a phase accumulator.
  • the divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DPA).
  • the DMD may be configured to divide the input signal by either N or N+1 (e.g., based on a carry out) to provide a fractional division ratio.
  • the DLL may include a set of cascaded, tunable, delay elements, a phase detector, a charge pump and a D-type flip-flop.
  • the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line.
  • Nd is the number of delay elements in the delay line.
  • frequency input to the synthesizer 406D may be provided by a voltage controlled oscillator (VCO) (not shown), although that is not a requirement.
  • VCO voltage controlled oscillator
  • Divider control input for the synthesizer 406D may be provided by either the baseband circuitry 404 or the applications processor 402 depending on the desired output frequency.
  • a divider control input e.g., N
  • N may be determined from a look-up table based on a channel indicated by the applications processor 402.
  • synthesizer circuitry 406D may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other.
  • the output frequency may be a local oscillator (LO) frequency (fLO).
  • the RF circuitry 406 may include a converter that converts between in-phase–quadrature (IQ) and polar signal formats.
  • FEM circuitry 408 may include a receive signal path that includes circuitry configured to operate on RF signals received from one or more antennas 410, amplify the received signals and provide the amplified versions of the received signals to the RF circuitry 406 for further processing.
  • FEM circuitry 408 may also include a transmit signal path which includes circuitry configured to amplify signals provided by the RF circuitry 406 for transmission by one or more of the one or more antennas 410.
  • the FEM circuitry 408 may include a TX/RX switch to switch between transmit mode and receive mode operation.
  • the FEM circuitry may include a receive signal path and a transmit signal path.
  • the receive signal path of the FEM circuitry may include a low-noise amplifier (LNA) to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 406).
  • the transmit signal path of the FEM circuitry 408 may include a power amplifier (PA) to amplify input RF signals (e.g., provided by RF circuitry 406), and one or more filters to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas 410).
  • PA power amplifier
  • the RAT 400 may be implemented in a device that includes additional elements such as, for example, memory/storage, display, camera, sensor, and/or input/output (I/O) interface.
  • the RAT 400 described herein may be part of a portable wireless communication device, such as a personal digital assistant (PDA), a laptop or portable computer with wireless communication capability, a web tablet, a wireless telephone, a gaming system, a smartphone, a smart watch, wireless headset, a pager, an instant messaging device, a digital camera, an access point, a television, a medical device (e.g., a heart rate monitor, a blood pressure monitor, etc.), or other device that may receive and/or transmit information wirelessly.
  • PDA personal digital assistant
  • a laptop or portable computer with wireless communication capability such as a personal digital assistant (PDA), a laptop or portable computer with wireless communication capability, a web tablet, a wireless telephone, a gaming system, a smartphone, a smart watch, wireless headset, a pager, an instant messaging device
  • the RAT 400 may include one or more user interfaces designed to enable user interaction with the system and/or peripheral component interfaces designed to enable peripheral component interaction with the system.
  • the RAT 400 may include one or more of a keyboard, a keypad, a touchpad, a display, a sensor, a non-volatile memory port, a universal serial bus (USB) port, an audio jack, a power supply interface, one or more antennas, a graphics processor, an application processor, a speaker, a microphone, and other I/O components.
  • the display may be a liquid crystal device (LCD), electroluminescent (EL) or light emitting diode (LED) screen that may include a touch screen input device.
  • the sensor may include a gyro sensor, an accelerometer, a proximity sensor, an ambient light sensor, and a positioning unit. The positioning unit may communicate with components of a positioning network, e.g., a global positioning system (GPS) satellite.
  • GPS global positioning system
  • the antennas 410 may comprise one or more directional or omnidirectional antennas, including, for example, dipole antennas, monopole antennas, patch antennas, loop antennas, microstrip antennas, fractal antennas or other types of antennas suitable for transmission of RF signals.
  • the antennas 410 may be effectively separated and/or polarized to take advantage of spatial diversity and the different channel characteristics among the different transmission points of the base station to implement multi-layer communication.
  • the antennas 410 may be configured in a beam-forming array to direct a transmitted beam toward a particular UE to implement spatial multiplexing and/or spatial diversity and/or to determine the angle of arrival (AoA) of a signal received from a UE.
  • AoA angle of arrival
  • the RAT 400 is illustrated as having several separate functional elements, one or more of the functional elements may be combined and may be implemented as a RVM by combinations of software-configured elements, such as processing elements including digital signal processors (DSPs), and/or other hardware elements.
  • DSPs digital signal processors
  • some elements may comprise one or more microprocessors, DSPs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), application specific integrated circuits (ASICs), radio- frequency integrated circuits (RFICs) and combinations of various hardware and logic circuitry for performing at least the functions described herein.
  • the functional elements may refer to one or more processes operating on one or more processing elements.
  • Embodiments may be implemented in one or a combination of hardware, firmware and software. Embodiments may also be implemented as instructions stored on a computer-readable storage device, which may be read and executed by at least one processor to perform the operations described herein.
  • a computer-readable storage device may include any non-transitory mechanism for storing information in a form readable by a machine (e.g., a computer).
  • a computer-readable storage device may include read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash-memory devices, and other storage devices and media, including optical storage media.
  • Some embodiments may include one or more processors and may be configured with instructions stored on a computer-readable storage device.
  • FIG. 4B includes a block diagram showing an alternative representation of a RAT 450 in accordance with some embodiments.
  • the RAT 450 may be implemented in a UE, eNB, gNB, Wi-Fi transceiver, Bluetooth transceiver, ZigBee transceiver or other wireless device.
  • the physical layer circuitry 452 may perform various encoding and decoding functions that may include formation of baseband signals for transmission and decoding of received signals.
  • the RAT 450 may also include media access control (MAC) layer circuitry 454 for controlling access to the wireless medium.
  • the RAT 450 may further include processing circuitry 458, such as one or more single- core or multi-core processors, and memory 460 arranged to perform the operations described herein.
  • the physical layer circuitry 452, MAC circuitry 454, transceiver circuitry 456, processing circuitry 458, memory 460 and interface circuitry 462 may be the same as the RAT 400, described above, and may handle various radio control functions that enable communication with one or more radio networks compatible with one or more radio technologies.
  • the radio control functions may include signal modulation, encoding, decoding, radio frequency shifting, etc.
  • the RAT 450 also includes an RVM platform 464 which may operate as described above to allow a manufacturer to provide one or more black-box SFBs to developers enabling the developers to generate replacement modules for components of the RAT as allowed by the manufacturer.
  • communication may be enabled with one or more of a WMAN, a WLAN, and a WPAN.
  • the RAT 450 can be configured to operate in accordance with 3GPP standards or other protocols or standards, including ZigBee, WiMAX, Wi-Fi, WiGig, GSM, EDGE, GERAN, UMTS, UTRAN, or other 3G, 3G, 4G, 5G, etc. technologies either already developed or to be developed.
  • the RAT 450 may include transceiver circuitry 456 to enable communication with other external devices wirelessly and interfaces 462 to enable wired communication (including optical fiber communication) with other eternal devices.
  • the transceiver circuitry 462 may perform various transmission and reception functions such as conversion of signals between a baseband range and a Radio Frequency (RF) range.
  • RF Radio Frequency
  • the RAT 450 is illustrated as having several separate functional elements, one or more of the functional elements may be combined and may be implemented by combinations of software-configured elements, such as processing elements including DSPs, and/or other hardware elements.
  • some elements may comprise one or more microprocessors, DSPs, FPGAs, PLDs, ASICs, RFICs and combinations of various hardware and logic circuitry for performing at least the functions described herein.
  • the functional elements may refer to one or more processes operating on one or more processing elements.
  • Embodiments may be implemented in one or a combination of hardware, firmware and software. Embodiments may also be implemented as instructions stored on a computer- readable storage device, which may be read and executed by at least one processor to perform the operations described herein.
  • FIG. 4A shows an example or VM computing platform 412 that includes multiple processors 412A–412K.
  • These processors may include, for example, a combination of the DOs and APEs as shown in FIG.1.
  • the processors 412A–412K may include one or more single-core or multi-core processors, digital signal processors (DSPs), microcontrollers, field- programmable gate arrays (FPGAs), programmable logic arrays (PLAs) or other programmable processing elements. All of the multiple processing elements 412A–412K include memory elements e.g. DOs (not shown) which may be separate for each processing element or may be shared by multiple processing elements.
  • DOs not shown
  • the input and output data for the baseband processors 404A, 404B, 404C and 404D are provided by connections to the input data to the baseband circuitry 404 from the application circuitry 402, connections to the buses 407A, 407B and 407C and by a connection to the output of baseband processor 404D.
  • the CPU 404E implements the RVM replacement component by disabling one of the baseband processors 404A, 404B, 404C and/or 404D while enabling the RVM replacement component (e.g. a UDFB running on a processing element) in the RVM computing platform 412 to receive input data provided to the disabled component and provide output data in place of the output data of the disabled component.
  • the disabled component may have its input and output ports forced into a high impedance state.
  • the CPU 404E may also perform the functions of the control unit 106, shown in FIG.1.
  • the input and output data of the disabled component may be accessed by a developer using the interface 432.
  • This interface may implement at least a portion of the black-box RVM, providing the developer with input and output interfaces of the disabled component as well as timing signals 436 for the disabled component.
  • Third party developer can use this data to generate programming for the replacement RVM either on one of the processors 412A–412K or on a processor external to the RVM computing platform 412.
  • the generated programming may then be combined with or linked to programming for the black-box RVM to generate the replacement RVM which is added to the radio library 412C or applied directly to one or more of the processors 412A–412K.
  • FIG.4C shows an alternative method for interfacing the input and output data sets of the baseband processors 404A, 404B, 404C and 404D with the RVM computing platform 412.
  • the bus 405 connecting the baseband processors with the CPU 404E transfers both control data from the CPU 404E and the input and output data sets of the baseband processors 404A, 404B, 404C and 404D.
  • All other elements of the RAT 400 shown in FIG.4C are the same as the corresponding elements described above with reference to FIG. 4A and, thus, are not described in detail herein.
  • contention on the bus 405 is controlled by the arbitration unit 404H.
  • the CPU 404E may disable one of the baseband processors or may change the addresses assigned the packets containing data for the disabled processor to be addresses of the processors 412A–412K in the RVM computing platform 412.
  • the third-party developer interface 432 may be used by the developer to access one or more of the processors 412A–412K to directly program the accessed processor(s) to implement the replacement RVM.
  • the readdressed packets may be routed through the developer interface 432 to a processing element (not shown) external to the RVM computing platform for use by the third-party developer.
  • FIG. 4D shows another embodiment of the RAT 404.
  • the input and output data of each of the baseband processors 404A, 404B, 404C and 404D are routed through the RVM computing platform 412. All other elements of the RAT 400 shown in FIG.4D are the same as the corresponding elements described above with reference to FIGs.4A and 4C, and, thus, are not described in detail herein.
  • the embodiment shows the input and output data of all of the baseband processors being routed through the platform 412, it is contemplated that a manufacturer may implement the RAT 400 and route the input and output data for fewer than all of the baseband processors through the RVM computing platform 412. All other elements of the RAT 400 shown in FIG.4C are the same as the corresponding elements described above with reference to FIG.4A and, thus, are not described in detail herein.
  • FIGs.5 and 6 show example implementations of a black-box RVM interfacing the input and output data of one of baseband processors 404B to one of the RVM processors, in this embodiment, processor 412A.
  • the example black- box RVM 500 shown in FIG.5 includes control logic 502, a demultiplexer 504, buffers 506 and 508 and a multiplexer 510.
  • these elements may be implemented using a field programmable gate array (FPGA) or a programmable logic array (PLA).
  • FPGA field programmable gate array
  • PLA programmable logic array
  • the programming for the UDFB defining the black-box RVM is programming for the FPGA or PLA.
  • Output data from the baseband processor 404A is routed to the demultiplexer 504 which is controlled by control logic 502 to route the data either to the input port of baseband processor 404B or to the buffer 506.
  • the control logic 502 may be controlled by the RVM processor 512A or by the CPU 404E of the baseband circuitry 404 (not shown in FIG.5).
  • the multiplexer 510 is controlled by the control logic 502 to route the output data of baseband processor 404B or the output data of buffer 508 to the input port of baseband processor 404C.
  • the control logic 502 also controls the buffers 506 and 508 to latch data from the demultiplexer 504 and from the RV and processor 412A to synchronize the data provided by the baseband processor 404A and the data provided to the baseband processor 404C.
  • FIG. 5 also shows a switch 226 configured to selectively decouple the baseband processor 404B from the source of operating potential VCC.
  • the switch 226 may be controlled by the control logic 502, the CPU 404E, and/or the RVM processor 412A.
  • the black-box RVM 500 thus, provides the input data to the baseband processor 404B at the output port of buffer 506 and accepts output data corresponding to the output data of baseband processor 404B at the input port of buffer 508. This data is routed around baseband processor 404B, replacing it in the RAT by the processing performed by the RVM processor 412A.
  • FIG.6 shows an example implementation of an alternative black- box RVM 600 that accommodates bidirectional data flow through the baseband processor 604.
  • data flow from left to right in FIG. 6 represents data being processed for transmission by the RAT and data flow from right to left represents received data being processed by the RAT.
  • the demultiplexer 504 and multiplexer 510 of FIG.5 are replaced by multiplexer/demultiplexers 524 and 530 respectively.
  • the multiplexer/demultiplexer 524 is controlled by the control logic 522 to route either output data provided by baseband processors 602 in transmit mode and/or output data provided by baseband processor 604 in receive mode to the input buffer 526 of the RVM processor 412A.
  • the multiplexer/demultiplexer 524 may also be controlled to route output data of the baseband processor 602 to the input of baseband processor 604 in the transmit mode and/or to route output data of baseband processors 604 two the input port of baseband processor 602 in receive mode.
  • the multiplexer/demultiplexer 530 may be configured to route the output data of the RVM processor 412A, provided via the buffer 528 to the input port of baseband processor 606 in transmit mode and to the input port of baseband processor 604 in receive mode.
  • the multiplexer demultiplexer 530 may couple the output port of processor 604 to the input port of processor 606 in transmit mode and couple the output processor of processor 606 two the input port of processor 604 in transmit mode.
  • FIG. 7 shows an embodiment in which the UDFB for the replacement component is implemented using the same hardware that implements the component of the RAT being replaced.
  • the third-party developer may be provided with a description of the input and output data for the component being replaced as well as timing constraints.
  • the developer may then generate object code for the baseband processing element 702 that is configured to execute the element being replaced.
  • the RVM processor may then cause the generated object code to be stored into a memory 704 coupled to the baseband processing element 702.
  • the code for the current component is stored in memory locations 706 while the code for the new component is stored in different memory locations 708.
  • the CPU 404E or the RVM processor may be configured to provide the third-party developer with access to the memory 704 via a connection to the bus 405, shown in FIG.4C.
  • FIG. 8 shows another embodiment in which the UDFB for the replacement component is implemented using another baseband processor 404L of the RAT rather than using a processing component of the RVM computing platform.
  • the CPU 404E may change the packet address for packets transferred via the bus 405 and directed to baseband processor 404B so that they are instead directed to baseband processor 404L.
  • the code for the new component is executed in a processor of the RAT rather than being processed by the RVM processing platform.
  • Example 1 may include apparatus for use with radio access technology (RAT), the apparatus comprising: a plurality of components including multiple radio components coupled in a configuration to implement the RAT; a target component of the plurality of components including a first interface coupling the target component to a first other component and a second interface coupling the target component to a second other component; a computing platform including a data processing element coupled to the target component; an interface module including program code configured to be executed by the data processing element to provide at least one black box interface describing and implementing the first and second interfaces, wherein the program code includes compiled program instructions in the native object code of the data processing element; and a controller coupled to the computing platform and the multiple radio components, the controller being configured to substitute data provided via the at least one black box interface for respective data provided via the first and second interfaces to the first and second other radio components, respectively.
  • RAT radio access technology
  • Example 2 may include the apparatus of example 1 and/or some other example herein, further comprising a compiler configured to compile a source-code version of the interface module to generate the compiled code program instructions of the interface module.
  • Example 3 may include the apparatus of example 1 and/or some other example herein, wherein the at least one black box interface includes a first API describing and implementing a first standard functional block (SFB), the first SFB configured to implement the first interface and a second API describing and implementing a second SFB configured to implement the second interface.
  • FFB standard functional block
  • Example 4 may include the apparatus of example 1 and/or some other example herein, wherein the interface module includes buffering functionality configured to temporarily hold data provided by the first other component or to temporarily hold data to be provided to the second other component.
  • the interface module includes buffering functionality configured to temporarily hold data provided by the first other component or to temporarily hold data to be provided to the second other component.
  • Example 5 may include the apparatus of example 1 and/or some other example herein, wherein the processing element of the interface module includes logic gates configured by the program code to provide the buffering functionality.
  • Example 6 may include the apparatus of example 5, wherein the logic gates are components of a field programmable gate array (FPGA) or a programmable logic array (PLA) that is configured to be programmed by the program instructions.
  • FPGA field programmable gate array
  • PLA programmable logic array
  • Example 7 may include the apparatus of example 1 and/or some other example herein, wherein the interface module includes synchronizing functionality configured to synchronize data transfer between the interface module and at least one of the first and second other components.
  • Example 8 may include the apparatus of example 1 and/or some other example herein, wherein: the target component includes first and second subcomponents, the first subcomponent being coupled to the second subcomponent; and the first subcomponent includes the first interface and the second subcomponent includes the second interface.
  • Example 9 may include the apparatus of example 1 and/or some other example herein, wherein the computing platform includes a radio virtual machine (RVM) computing platform.
  • RVM radio virtual machine
  • Example 10 may include the apparatus of example 1 and/or some other example herein, wherein the RAT is part of a user equipment (UE) mobile device, the multiple radio components include physical layer components of the UE mobile device and the target component includes at least one of the physical layer components.
  • UE user equipment
  • Example 11 may include the apparatus of example 10, wherein the target component includes at least one of a cyclic redundancy code (CRC) generator, a channel encoder, an interleaver, a constellation mapper or a modulator.
  • CRC cyclic redundancy code
  • Example 12 may include the apparatus of example 10, wherein the target component includes at least one of a demodulator, a constellation demapper, a deinterleaver, a channel decoder and a cyclic redundancy code (CRC) checker.
  • the target component includes at least one of a demodulator, a constellation demapper, a deinterleaver, a channel decoder and a cyclic redundancy code (CRC) checker.
  • CRC cyclic redundancy code
  • Example 13 may include the apparatus of example 1 and/or some other example herein, wherein the target component includes at least one component in the data-link, network, transport, session, presentation, or application layers of the UE.
  • Example 14 may include the apparatus of example 13, wherein the at least one component includes a security module in the data link and network layers of the UE.
  • Example 15 may include the apparatus of example 1 and/or some other example herein, wherein: the interface module is combined with or linked to a target module; and the target module and the interface module are configured to implement functionality to replace the target component.
  • Example 16 may include the apparatus of example 15, wherein the target module and the interface module form a radio virtual machine (RVM).
  • RVM radio virtual machine
  • Example 17 may include the apparatus of example 1 and/or some other example herein, wherein one of the controller, the target module or the computing platform is configured to decouple the target radio component from a source of operational power after substituting the RVM for the first and second interfaces to the first and second other radio components.
  • Example 18 may include a nontransitory computer-readable medium including program instructions implementing an interface module, the program instructions are configured to cause a processor to: provide, via a black box interface, first data describing input data for a target radio component of multiple radio components constituting radio access technology (RAT) coupled to the processor; receive input data for the target radio component from the RAT; provide the input data at an output port of the interface module; provide via the black box interface, second data describing output data of the target radio component; receive output data corresponding to output data of the target radio component at an input port of the interface module; and provide the output data to the RAT as the output data of the target radio component.
  • RAT radio access technology
  • Example 19 may include the nontransitory computer readable medium of example 18 or some other example herein, including further program instructions that are configured to cause the processor to compile a source-code version of the interface module to generate compiled code program instructions of the interface module.
  • Example 20 may include the nontransitory computer readable medium of example 18 or some other example herein, wherein the first and second data are configured as standard functional block (SFB) of a radio virtual machine (RVM) to implement the interface module.
  • SFB standard functional block
  • RVM radio virtual machine
  • Example 21 may include the nontransitory computer readable medium of example 18 or some other example herein, wherein the program instructions are configured to further cause the processor to: temporarily hold the input data for the target radio component before providing the input data at the output port of the interface module; and to temporarily hold the output data corresponding to the output data of the target radio component before providing the output data to the RAT as the output data of the target radio component.
  • Example 22 may include the nontransitory computer readable medium of example 18 or some other example herein, wherein the black box interface is configured to provide synchronization functionality for the input and output data of the target radio component.
  • Example 23 may include the nontransitory computer readable medium of example 18 or some other example herein, wherein the target component includes first and second subcomponents, the first subcomponent being coupled to the second subcomponent, and the program instructions are configured to cause the processor to: receive the input data for first subcomponent as the input data of the target radio component; and receive the output data corresponding to output data of the second subcomponent as the output data corresponding to the output data of the target radio component.
  • Example 24 may include the nontransitory computer readable medium of example 18 or some other example herein, wherein the program instructions are configured to: provide the input data to an input port of a target module; and receive output data from the target module as the output data corresponding to the output data of the target radio component.
  • Example 25 may include the nontransitory computer readable medium of example 18 or some other example herein, wherein the program instructions are further configured to cause the processor to decouple the target radio component from a source of operational power.
  • Example 26 may include an apparatus including means for providing, via a black box interface, first data describing input data for a target radio component of multiple radio components constituting radio access technology (RAT) coupled to the processor; means for receiving input data for the target radio component from the RAT; means for providing the input data at an output port of the interface module; means for providing, via the black box interface, second data describing output data of the target radio component; means for receiving output data corresponding to output data of the target radio component at an input port of the interface module; and means for providing the output data to the RAT as the output data of the target radio component.
  • RAT radio access technology
  • Example 27 may include the apparatus of example 26 or some other example herein, including means for compiling a source-code version of the interface module to generate compiled code program instructions of the interface module.
  • Example 28 the apparatus of example 26 or some other example herein, further including means for temporarily holding the input data for the target radio component before providing the input data at the output port of the interface module; and for temporarily holding the output data corresponding to the output data of the target radio component before providing the output data to the RAT as the output data of the target radio component.
  • Example 29 may include the apparatus of example 26 or some other example herein, further including means for synchronizing the input and output data of the target radio component.
  • Example 30 may include the apparatus of example 26 or some other example herein, wherein the target component includes first and second subcomponents, the first subcomponent being coupled to the second subcomponent, and the apparatus include means for receiving the input data for first subcomponent as the input data of the target radio component; and means for receiving the output data corresponding to output data of the second subcomponent as the output data corresponding to the output data of the target radio component.
  • Example 31 may include the apparatus of example 26 or some other example herein, further including means for providing the input data to an input port of a target module; and means for receiving output data from the target module as the output data corresponding to the output data of the target radio component.
  • Example 32 may include the apparatus of example 26 or some other example herein, further including means for decoupling the target radio component from a source of operational power.

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Abstract

Un dispositif comprend une pluralité de composants comprenant de multiples composants configurés en tant que technologie d'accès radio (RAT). Un composant cible de la pluralité de composants possède des première et seconde interfaces couplant le composant cible à des premier et second autres composants respectifs de la pluralité de composants. Le dispositif comprend une plateforme informatique ayant un élément de traitement de données couplé au composant cible. Un module d'interface comprend un code de programme compilé configuré pour être exécuté par l'élément de traitement de données pour amener l'élément de traitement à fournir au moins une interface de boîte noire décrivant et mettant en œuvre les première et seconde interfaces. Un dispositif de commande est couplé à la plateforme de calcul et aux multiples composants radio et est configuré pour remplacer des données fournies en fonction de la ou des interfaces de boîte noire avec des données respectives fournies aux premier et second composants radio par l'intermédiaire des première et seconde interfaces, respectivement.
PCT/US2017/039909 2016-11-14 2017-06-29 Remplacement de composant de bande de base par un composant logiciel WO2018089055A1 (fr)

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