WO2018076684A1 - 一种资源分配方法和高速缓冲存储器 - Google Patents

一种资源分配方法和高速缓冲存储器 Download PDF

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WO2018076684A1
WO2018076684A1 PCT/CN2017/086027 CN2017086027W WO2018076684A1 WO 2018076684 A1 WO2018076684 A1 WO 2018076684A1 CN 2017086027 W CN2017086027 W CN 2017086027W WO 2018076684 A1 WO2018076684 A1 WO 2018076684A1
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cache
processor
capacity
register
statistical
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French (fr)
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薛长花
孙志文
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

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  • the present invention relates to the field of multiprocessors, and in particular, to a resource allocation method and a cache cache.
  • the area cost is a crucial factor, and while reducing the area cost, how to ensure the performance of the processor has become a key issue that has been urgently solved.
  • multi-core shared cache is the most basic way to improve processor access performance.
  • each processor core handles different tasks, and each core processes tasks at different times. In this way, the usage requirements of each check Cache resource are different.
  • the use of the Cache capacity by the processor is statically allocated, and the processor pair is not considered.
  • the demand for Cache dynamic access changes. In this case, the NIC access performance of the Cache access request is not improved, and the Cache resource used by the Cache with a small Cache is wasted, which is not conducive to the area cost and access performance of the multi-core system. balance.
  • embodiments of the present invention are expected to provide a resource allocation method and cache storage.
  • the performance of multiple processors is guaranteed while reducing the cost of the area, improving the user experience.
  • an embodiment of the present invention provides a resource allocation method, where the method is applied to a Cache shared by a multi-processor, where the Cache includes: a Cache controller and a Cache register; and the Cache register includes: each processing Corresponding statistical register and a lock register corresponding to each of the processors; the method includes: each statistical register is configured to count the Cache capacity accessed by the processor corresponding to each statistical register within a preset time, and obtain a Cache access capacity of each processor, sending the Cache access capacity of each processor to the Cache controller; the Cache controller determines the each according to the Cache access capacity of each processor The Cache of the processors allocates capacity; the Cache controller writes the Cache Allocation Capacity of each of the processors into a lock register corresponding to each of the processors.
  • the Cache controller determines, according to the Cache access capacity of each processor, the Cache allocation capacity of each processor, including: the Cache controller is configured according to each processor.
  • the size of the Cache access capacity determines the Cache allocation capacity of each processor according to a positive correlation.
  • the Cache controller determines, according to the size of the Cache access capacity of each processor, the Cache allocation capacity of each processor according to a positive correlation, including: the Cache controller according to the The size of the Cache access capacity of each processor is determined, and the Cache allocation capacity of each processor is determined according to a proportional relationship.
  • the Cache register further includes: a counting register; correspondingly, each of the statistical registers counts a Cache capacity accessed by the processor corresponding to each of the statistical registers within a preset time, and obtains a
  • the Cache access capacity of each processor includes: the Cache controller controls the statistics register to start counting the Cache capacity accessed by the processor corresponding to each of the statistics registers, and starts counting the count registers; The Cache The controller controls the statistics register to end the statistics of the Cache capacity accessed by the processor corresponding to each of the statistical registers, and obtains the Cache access capacity of each processor.
  • the bit width of each of the statistical registers is positively correlated with the amount of software code running in the processor corresponding to each of the statistical registers.
  • the embodiment of the present invention provides a Cache, where the Cache includes: a Cache controller and a Cache register; the Cache register includes: a statistical register corresponding to each processor and a lock corresponding to each processor a register; wherein each of the statistics registers is configured to count the Cache capacity accessed by the processor corresponding to each of the statistical registers within a preset time, obtain a Cache access capacity of each processor, and send each of the Caches Cache access capacity of the processor to the Cache controller; the Cache controller is configured to determine, according to the Cache access capacity of each processor, a Cache allocation capacity of each processor; The Cache allocation capacity of each processor is written into the lock register corresponding to each processor.
  • the Cache controller is configured to determine a Cache allocation capacity of each processor according to a positive correlation according to a size of a Cache access capacity of each processor.
  • the Cache controller is further configured to determine, according to a size of the Cache access capacity of each processor, a Cache allocation capacity of each processor according to a proportional relationship.
  • the Cache register further includes: a count register; and correspondingly, the Cache controller is configured to control the statistics register to start counting statistics accessed by the processor corresponding to each of the statistic registers Cache capacity, and the counting of the counting register is started; when it is determined that the counting of the counting register is ended, controlling each of the statistical registers to end counting the Cache capacity accessed by the processor corresponding to each of the statistical registers, to obtain the Processing Cache access capacity.
  • the bit width of each of the statistical registers is positively correlated with the amount of software code running in the processor corresponding to each of the statistical registers.
  • the resource allocation method and the Cache provided by the embodiments of the present invention are applied to a Cache shared by multiple processors, where the Cache includes: a Cache controller and a Cache register; the Cache register includes: a statistical register corresponding to each processor and Each processor corresponds to a lock register; first, each statistical register counts the Cache capacity accessed by the processor corresponding to each statistical register within a preset time, thereby obtaining the Cache access capacity of each processor, and The Cache access capacity of each processor is sent to the Cache controller; then, the Cache controller determines the Cache allocation capacity of each processor according to the Cache access capacity of each processor; finally, the Cache controller will each processor The Cache allocation capacity is written into the lock register corresponding to each processor, so that the Cache resources allocated for each processor are re-allocated according to the actual needs of each processor, and the dynamic management multi-core shared Cache resource can be achieved.
  • the purpose of the implementation is to achieve the multi-processor access performance while reducing the area cost. High user experience.
  • FIG. 1 is a schematic flowchart of a resource allocation method according to an embodiment of the present invention.
  • FIG. 2 is an optional structural diagram of a multiprocessor and a shared Cache according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a Cache according to an embodiment of the present invention.
  • Embodiments of the present invention provide a resource allocation method, which is applied to multi-processor sharing.
  • each processor corresponds to an ID (ID), which is used to identify the processor; and, before using the Cache, the Cache capacity has been fixedly configured for each processor, here
  • ID ID
  • the Cache can be a group connection structure.
  • the Cache capacity can include multiple channels. Each path includes a fixed number of rows. For example, when the Cache capacity includes 4 processors, the Cache capacity can be 4 channels for each processor. Can include 10 lines;
  • the Cache includes: a Cache controller and a Cache register; the Cache register includes: a statistic register corresponding to each processor and a lock register corresponding to each processor;
  • FIG. 1 is a schematic flowchart of a resource allocation method according to an embodiment of the present invention. As shown in FIG. 1, the method includes:
  • each statistical register counts the Cache capacity accessed by the processor corresponding to each statistical register within a preset time, obtains a Cache access capacity of each processor, and sends a Cache access capacity of each processor to the Cache controller;
  • the Cache capacity has been fixedly configured for each processor before using the Cache. Therefore, at the beginning of each processor, the Cache capacity that has been fixedly configured for each processor is used first; each processor The Cache capacity of the fixed configuration may be evenly distributed, or may be allocated according to the frequency of use of the processor.
  • Each of the above statistical registers is a configurable multi-bit width register, wherein the bit width of each statistical register is positively correlated with the amount of software code running in the processor corresponding to each statistical register, that is, the statistical register
  • the bit width can be determined according to the actual application of each processor, avoiding the occurrence of statistical failure caused by the inappropriate register width.
  • the preset time may be preset in the Cache controller by using a code, for example, 1000 cycles, where the cycle is related to the frequency of the processor; the Cache access capacity of each of the processors may be in units of rows. For example, 20 lines, 5 lines, etc.
  • S101 may include :
  • the Cache controller controls each statistical register to start counting the Cache capacity accessed by the processor corresponding to each statistical register, and starts counting register counting; the Cache controller controls each statistical register to end each statistic when determining the counting of the counting register ends.
  • the Cache capacity accessed by the processor corresponding to the statistics register obtains the Cache access capacity of each processor.
  • the Cache controller when the Cache controller determines that one or more processors are running a program code for a time greater than a preset time threshold, the Cache controller triggers each of the statistics registers and the above-mentioned counting registers to generate a trigger signal, respectively triggering each
  • the statistical register and the counting register start to work, that is, each statistical register starts counting the Cache capacity accessed by the processor corresponding to each statistical register, and the counting register starts counting, wherein the trigger signal may be an enable signal, a rising edge trigger signal, or The falling edge trigger signal is not specifically limited in the embodiment of the present invention.
  • the above-mentioned counting register is a configurable multi-bit width register
  • the bit width of the counting register is related to the preset time, that is, when the preset time is long, the bit width of the counting register is large, when the above-mentioned pre- When the set time is short, the bit width of the count register is small, that is, the bit width of the count register can be artificially determined according to the preset time.
  • the value of the count register is configured to be 5000 in decimal, and the count register is in each The cycle of the processor is reduced by 1.
  • the Cache controller controls the statistics of each statistical register to obtain the Cache access capacity of each processor.
  • the Cache access capacity of each processor can be sent to the Cache controller, so that the Cache controller knows that each processor is within a preset time.
  • the Cache controller determines, according to the Cache access capacity of each processor, a Cache allocation capacity of each processor.
  • the Cache controller receives the Cache access capacity of each processor. After knowing the actual Cache access capacity of each processor within a preset time, the Cache capacity can be re-allocated for each processor according to actual conditions;
  • S102 may include: the Cache controller determines a Cache allocation capacity of each processor according to a positive correlation according to a size of a Cache access capacity of each processor.
  • the locality principle of Cache access includes spatial locality and temporal locality, where spatial locality: the address accessed by the processor in the future is likely to be near the currently accessed address; time locality: if an address is processed Access, then it is likely to be accessed again in the near future; then, according to the locality principle of Cache access, it is known that the current frequent access to the Cache is likely to be accessed frequently, so according to the size of the Cache access capacity of each processor, The Cache allocation capacity of each processor is determined according to a positive correlation.
  • the Cache controller sorts according to the size of the Cache access capacity of each processor, and determines the Cache access capacity of the processor.
  • the Cache allocation capacity is large. For a processor with a small Cache access capacity, the determined Cache allocation capacity is small;
  • the Cache controller is configured according to the Cache access capacity of each processor.
  • the Cache allocation capacity of each processor is determined according to the positive correlation, and the Cache controller determines the Cache allocation capacity of each processor according to a proportional relationship according to the size of the Cache access capacity of each processor.
  • the access capacity of the Caches of the two processors is 20 rows and 5 rows, respectively, and the total size of the Cache capacity is 4 channels, then, according to the proportional relationship for each processing
  • the Cache allocation capacity of the two processors determined is 3 channels and 1 channel;
  • the Cache controller writes the Cache allocation capacity of each processor into a lock register corresponding to each processor.
  • the Cache controller After determining the Cache allocation capacity of each processor, the Cache controller drives to configure a lock register corresponding to each processor, for example, when it is determined that the Cache allocation capacity of the two processors is 3 channels and 1 channel, then The corresponding lock registers are respectively written to the binary 10 and 00, thereby completing the purpose of dynamically adjusting the Cache capacity of each processor.
  • FIG. 2 is an optional structural diagram of a multiprocessor and a shared Cache according to an embodiment of the present invention; as shown in FIG. 2, including: n+1 processors and a Cache20;
  • the Cache 20 includes a Cache Controller 201, a Cache Cache 202, and a Cache Register 203;
  • a counting register In the Cache register 203, a counting register, n+1 locking registers corresponding to n+1 processors, and n+1 statistical registers one-to-one corresponding to n+1 processors are included;
  • the above resource allocation methods include:
  • Step A When the Cache controller 201 determines that one or more processors are running a program code for a time greater than a preset time threshold, respectively triggering n+1 statistical registers and the counting register to generate an enable signal as valid signals;
  • Step B Each statistical register starts to count the Cache capacity accessed by the processor corresponding to each statistical register, and the counting register starts counting;
  • Step C The cache controller 201 controls each statistical register to end the statistics of the Cache capacity accessed by the processor corresponding to each statistical register, and obtains the Cache access capacity of the corresponding processor.
  • Step D The Cache controller 201 determines the Cache allocation capacity of the corresponding processor according to the proportional relationship of the Cache access capacity of the corresponding processor.
  • Step E The Cache Controller 201 writes the Cache Allocation Capacity of the corresponding processor into the corresponding lock register.
  • the Cache access capacity of the statistical register can be allocated to the processor with a large capacity at a time, so that the performance of the processor that frequently accesses the Cache can be directly improved, and the smaller path size can be allocated to the frequent first.
  • Accessing the Cache processor in the following processor access, the Cache access capacity of each processor is also counted according to the above embodiment, and if the frequently accessed processor is accessed frequently in the subsequent time period, the continuation continues.
  • the Cache capacity of the path size is allocated to the processor, but if the locality of the program is not so good, the amount of access to the Cache cache is reduced after the currently accessed processor, which in turn reduces the Cache capacity for frequent access processing. In this way, you can flexibly and dynamically adjust the Cache capacity of each processor step by step to ensure the performance of multiple processors.
  • the Cache requirement of each processor is dynamically counted, and the Cache capacity of the processor is dynamically adjusted according to the change of requirements in different time periods, thereby avoiding the increase of the on-chip memory size in order to improve performance, and dynamically improving while saving costs.
  • Processor access performance is dynamically counted, and the Cache capacity of the processor is dynamically adjusted according to the change of requirements in different time periods, thereby avoiding the increase of the on-chip memory size in order to improve performance, and dynamically improving while saving costs.
  • the resource allocation method provided by the embodiment of the present invention is applied to a Cache shared by multiple processors, where the Cache includes: a Cache controller and a Cache register; the Cache register includes: a statistical register corresponding to each processor and each The lock register corresponding to the processor; first, each statistical register counts the Cache capacity accessed by the processor corresponding to each statistical register within a preset time, thereby obtaining the Cache access capacity of each processor, and each The Cache access capacity of the processor is sent to the Cache controller; then, the Cache controller is based on The Cache access capacity of each processor determines the Cache allocation capacity of each processor; finally, the Cache controller writes the Cache allocation capacity of each processor into the lock register corresponding to each processor, so that for each The Cache resources allocated by the processors are re-allocated according to the actual needs of each processor, which can achieve the purpose of dynamically managing multi-core shared Cache resources, thereby realizing the access performance of multiple processors while reducing the area cost. , to improve the user experience.
  • FIG. 3 is a schematic structural diagram of a Cache according to an embodiment of the present invention.
  • the Cache includes: a Cache Controller 31 and a Cache Register 32; and a Cache Register 32.
  • the method includes: a statistical register 321 corresponding to each processor and a lock register 322 corresponding to each processor; wherein
  • Each statistic register 321 is configured to count the Cache capacity accessed by the processor corresponding to each statistic register 321 within a preset time, obtain a Cache access capacity of each processor, and send a Cache access capacity of each processor to the Cache.
  • the controller 31 is configured to determine, according to the Cache access capacity of each processor, a Cache allocation capacity of each processor; and write a Cache allocation capacity of each processor to a lock corresponding to each processor. In register 322.
  • Each of the statistical registers 321 is a configurable multi-bit width register, and the bit width of each statistical register 321 is positively correlated with the amount of software code running in the processor corresponding to each statistical register 321 .
  • the Cache controller 31 receives the Cache access capacity of each processor. After knowing the actual Cache access capacity of each processor within a preset time, the Cache capacity can be re-allocated for each processor according to the actual situation. In an optional embodiment, the Cache controller 31 is configured to determine the Cache allocation capacity of each processor according to a positive correlation according to the size of the Cache access capacity of each processor.
  • the Cache controller 31 is configured to determine the Cache allocation capacity of each processor according to a proportional relationship according to the size of the Cache access capacity of each processor.
  • the preset time may also be set by hardware.
  • the Cache control The controller 31 is configured to control each of the statistics registers 321 to start counting the Cache capacity accessed by the processor corresponding to each of the statistical registers 321 and to start the counting of the counting registers; when determining the end of the counting of the counting registers, control each statistical register 321 to end the statistics.
  • the Cache capacity accessed by the processor corresponding to each statistical register 321 obtains the Cache access capacity of each processor.
  • the resource allocation method provided by the embodiment of the present invention is applied to a Cache shared by multiple processors, where the Cache includes: a Cache controller and a Cache register; the Cache register includes: a statistical register corresponding to each processor and each The lock register corresponding to the processor; first, each statistical register counts the Cache capacity accessed by the processor corresponding to each statistical register within a preset time, thereby obtaining the Cache access capacity of each processor, and each The Cache access capacity of the processor is sent to the Cache controller; then, the Cache controller determines the Cache allocation capacity of each processor according to the Cache access capacity of each processor; finally, the Cache controller will cache each processor.
  • the allocated capacity is written into the lock register corresponding to each processor, so that the Cache resources allocated for each processor are re-allocated according to the actual needs of each processor, and the purpose of dynamically managing the multi-core shared Cache resources can be achieved. , thereby achieving the reduction of the area cost while ensuring the access performance of the multi-processor, and improving User experience degrees.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated.
  • the components displayed as the unit may be, or may not be, physical units; they may be located in one place or on multiple network units; some or all of the units may be selected according to actual needs to implement the solution of the embodiment. purpose.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and when executed, the program includes The foregoing steps of the method embodiment; and the foregoing storage medium includes: a removable storage device, a read only memory (ROM), a magnetic disk, or an optical disk, and the like, which can store program codes.
  • ROM read only memory
  • the above-described integrated unit of the present invention may be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a standalone product.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a mobile storage device, a ROM, a magnetic disk, or an optical disk.

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Abstract

本发明公开了一种资源分配方法，该方法应用于多处理器共享的Cache中，其中，Cache包括：Cache控制器和Cache寄存器；Cache寄存器包括：每个处理器对应的统计寄存器和每个处理器对应的锁定寄存器；该方法包括：每个统计寄存器统计每个统计寄存器对应的处理器在预设时间内所访问的Cache容量，得到每个处理器的Cache访问容量，发送每个处理器的Cache访问容量至Cache控制器；Cache控制器根据每个处理器的Cache访问容量，确定出每个处理器的Cache分配容量；Cache控制器将每个处理器的Cache分配容量写入每个处理器对应的锁定寄存器中。本发明实施例还同时公开了一种Cache。

Description

一种资源分配方法和高速缓冲存储器
相关申请的交叉引用
本申请基于申请号为201610931953.9、申请日为2016年10月31日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及多处理器领域，尤其涉及一种资源分配方法和高速缓冲存储器Cache。
背景技术
目前，在芯片系统中，面积成本是一个至关重要的因素，而在降低面积成本的同时，如何保证处理器的性能也成为了人们一直在亟待解决的关键问题。
在现代多核系统中，多核共享高速缓冲存储器是最基本的提升处理器访问性能的方法，但是，在多核系统架构中，每一个处理器核处理的任务不同，每个核处理任务的时间不同，这样，就导致每个核对Cache资源的使用需求不同；而在当前的多核架构中，Cache的锁定(lockdown)模式下，处理器对Cache容量的使用都是静态分配好的，没有考虑处理器对Cache动态访问的需求变化，这种情况下，Cache访问需求比较大的核访问性能得不到提升，Cache需求比较小的核使用的Cache资源出现浪费，不利于多核系统中面积成本和访问性能的平衡。
发明内容
有鉴于此，本发明实施例期望提供一种资源分配方法和高速缓冲存储 器，在多核系统中，在降低面积成本的同时保证多个处理器的性能，提高用户体验。
为达到上述目的，本发明实施例的技术方案是这样实现的：
第一方面，本发明实施例提供一种资源分配方法，该方法应用于多处理器共享的Cache中，其中，所述Cache包括：Cache控制器和Cache寄存器；所述Cache寄存器包括：每个处理器对应的统计寄存器和所述每个处理器对应的锁定寄存器；所述方法包括：每个统计寄存器统计所述每个统计寄存器对应的处理器在预设时间内所访问的Cache容量，得到所述每个处理器的Cache访问容量，发送所述每个处理器的Cache访问容量至所述Cache控制器；所述Cache控制器根据所述每个处理器的Cache访问容量，确定出所述每个处理器的Cache分配容量；所述Cache控制器将所述每个处理器的Cache分配容量写入所述每个处理器对应的锁定寄存器中。
在一实施例中，所述Cache控制器根据所述每个处理器的Cache访问容量，确定出所述每个处理器的Cache分配容量，包括：所述Cache控制器根据所述每个处理器的Cache访问容量的大小，按照正相关关系确定出所述每个处理器的Cache分配容量。
在一实施例中，所述Cache控制器根据所述每个处理器的Cache访问容量的大小，按照正相关确定出所述每个处理器的Cache分配容量，包括：所述Cache控制器根据所述每个处理器的Cache访问容量的大小，按照正比例关系确定出所述每个处理器的Cache分配容量。
在一实施例中，所述Cache寄存器还包括：一个计数寄存器；相应地，所述每个统计寄存器统计所述每个统计寄存器对应的处理器在预设时间内所访问的Cache容量，得到所述每个处理器的Cache访问容量，包括：所述Cache控制器控制所述每个统计寄存器开始统计所述每个统计寄存器对应的处理器所访问的Cache容量，且启动所述计数寄存器计数；所述Cache 控制器在确定所述计数寄存器计数结束时，控制所述每个统计寄存器结束统计所述每个统计寄存器对应的处理器所访问的Cache容量，得到所述每个处理器的Cache访问容量。
在一实施例中，所述每个统计寄存器的位宽与所述每个统计寄存器对应的处理器中运行的软件代码量成正相关。
第二方面，本发明实施例提供了一种Cache，所述Cache包括：Cache控制器和Cache寄存器；所述Cache寄存器包括：每个处理器对应的统计寄存器和所述每个处理器对应的锁定寄存器；其中，每个统计寄存器，配置为统计所述每个统计寄存器对应的处理器在预设时间内所访问的Cache容量，得到所述每个处理器的Cache访问容量，发送所述每个处理器的Cache访问容量至所述Cache控制器；所述Cache控制器，配置为根据所述每个处理器的Cache访问容量，确定出所述每个处理器的Cache分配容量；将所述每个处理器的Cache分配容量写入所述每个处理器对应的锁定寄存器中。
在一实施例中，所述Cache控制器，配置为根据所述每个处理器的Cache访问容量的大小，按照正相关关系确定出所述每个处理器的Cache分配容量。
在一实施例中，所述Cache控制器，还配置为根据所述每个处理器的Cache访问容量的大小，按照正比例关系确定出所述每个处理器的Cache分配容量。
在一实施例中，所述Cache寄存器还包括：一个计数寄存器；相应地，所述Cache控制器，配置为控制所述每个统计寄存器开始统计所述每个统计寄存器对应的处理器所访问的Cache容量，且启动所述计数寄存器计数；在确定所述计数寄存器计数结束时，控制所述每个统计寄存器结束统计所述每个统计寄存器对应的处理器所访问的Cache容量，得到所述每个处理 器的Cache访问容量。
在一实施例中，所述每个统计寄存器的位宽与所述每个统计寄存器对应的处理器中运行的软件代码量成正相关。
本发明实施例所提供的资源分配方法和Cache，该方法应用于多处理器共享的Cache中，其中，Cache包括：Cache控制器和Cache寄存器；Cache寄存器包括：每个处理器对应的统计寄存器和每个处理器对应的锁定寄存器；首先，每个统计寄存器统计出每个统计寄存器对应的处理器在预设时间内所访问的Cache容量，从而得到了每个处理器的Cache访问容量，并将每个处理器的Cache访问容量发送至Cache控制器；然后，Cache控制器根据每个处理器的Cache访问容量，确定出每个处理器的Cache分配容量；最后，Cache控制器将每个处理器的Cache分配容量写入每个处理器对应的锁定寄存器中，这样，为每个处理器分配的Cache资源是按照每个处理器的实际需求来重新进行分配的，能够达到动态管理多核共享Cache资源的目的，从而实现了在降低面积成本的同时保证了多处理器的访问性能，提高了用户体验度。
附图说明
图1为本发明实施例中资源分配方法的流程示意图；
图2为本发明实施例中多处理器和共享的Cache的一种可选的结构示意图；
图3为本发明实施例中Cache的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
本发明实施例提供一种资源分配方法，该方法应用于多处理器共享的 Cache中，其中，每个处理器都对应由一个身份识别码(ID，Identification)，该ID用于识别处理器；并且，在使用Cache之前已经为每个处理器固定配置好了Cache容量，这里，Cache可以为组相连结构，Cache容量可以包括多路，每一路包括固定数目的行，例如，当Cache容量包括4个处理器时，为每个处理器配置Cache容量可以为4路，每一路可以包括10行；
其中，上述Cache包括：Cache控制器和Cache寄存器；上述Cache寄存器包括：每个处理器对应的统计寄存器和每个处理器对应的锁定寄存器；
图1为本发明实施例中资源分配方法的流程示意图，如图1所示，该方法包括：
S101：每个统计寄存器统计每个统计寄存器对应的处理器在预设时间内所访问的Cache容量，得到每个处理器的Cache访问容量，发送每个处理器的Cache访问容量至Cache控制器；
这里，在使用Cache之前已经为每个处理器固定配置好了Cache容量，所以，在每个处理器刚开始运行时，先使用已经为每个处理器固定配置好的Cache容量；每个处理器固定配置好的Cache容量可以是平均分配的，也可以是按照处理器的使用频率来分配的，这里，本发明实施例不做具体限定。
上述每个统计寄存器都是可配的多比特位宽的寄存器，其中，每个统计寄存器的位宽与每个统计寄存器对应的处理器中运行的软件代码量成正相关，也就是说，统计寄存器的位宽可以根据对应的每个处理器的在实际中的应用来确定，避免统计寄存器位宽不合适所导致的统计失败的发生。
另外，上述预设时间可以在Cache控制器中通过代码的方式预先进行设置，例如，1000个周期，该周期与处理器的频率相关；上述每个处理器的Cache访问容量可以是以行为单位的，例如，20行，5行等。
上述预设时间还可以通过硬件的方式进行设置，在一种可选的实施例中，通过在Cache寄存器中增加一个计数寄存器来实现，当Cache寄存器还包括一个计数寄存器；相应地，S101可以包括：
Cache控制器控制每个统计寄存器开始统计每个统计寄存器对应的处理器所访问的Cache容量，且启动计数寄存器计数；Cache控制器在确定计数寄存器计数结束时，控制每个统计寄存器结束统计每个统计寄存器对应的处理器所访问的Cache容量，得到每个处理器的Cache访问容量。
其中，当Cache控制器在确定出一个或多个处理器在运行一段程序代码的时间大于预设时间阈值时，Cache控制器触发每个统计寄存器和上述计数寄存器分别生成触发信号，分别触发每个统计寄存器和计数寄存器开始工作，即每个统计寄存器开始统计每个统计寄存器对应的处理器所访问的Cache容量，计数寄存器开始计数，其中，上述触发信号可以为使能信号、上升沿触发信号或者下降沿触发信号，这里，本发明实施例不做具体限定。
这里，上述计数寄存器是可配的多比特位宽的寄存器，该计数寄存器的位宽与上述预设时间相关，即当上述预设时间较长时，计数寄存器的位宽较大，当上述预设时间较短时，计数寄存器的位宽较小，也就是说，计数寄存器的位宽可以根据预设时间人为的确定，例如，计数寄存器的值配置为十进制的5000时，计数寄存器在每一个处理器的周期减少1，当计数寄存器的值由5000减小到0时，Cache控制器控制每个统计寄存器结束统计，得到每个处理器的Cache访问容量。
那么，每个统计寄存器统计出每个处理器的Cache访问容量之后，便可以将每个处理器的Cache访问容量发送至Cache控制器，使得Cache控制器得知每个处理器在预设时间内的每个处理器实际所访问的Cache容量。
S102：Cache控制器根据每个处理器的Cache访问容量，确定出每个处理器的Cache分配容量；
通过S101，Cache控制器接收到每个处理器的Cache访问容量，在了解每个处理器在预设时间内实际的Cache访问容量之后，可以根据实际情况来重新为每个处理器分配Cache容量；
在一种可选的实施例中，S102可以包括：Cache控制器根据每个处理器的Cache访问容量的大小，按照正相关关系确定出每个处理器的Cache分配容量。
需要说明的是，Cache访问的局部性原理包括空间局部性和时间局部性，其中，空间局部性：将来处理器访问的地址很可能在当前访问的地址附近；时间局部性：如果一个地址被处理器访问，那么近期内很可能会被再次访问；那么，根据Cache访问的局部性原理可知，当前对Cache频繁访问很可能后面还会频繁访问，所以根据每个处理器的Cache访问容量的大小，按照正相关关系确定出每个处理器的Cache分配容量。
在一实施例中，Cache控制器在得到每个处理器的Cache访问容量之后，根据每个处理器的Cache访问容量的大小进行排序，对于Cache访问容量较大的处理器来说，确定出的Cache分配容量较大，对于Cache访问容量较小的处理器来说，确定出的Cache分配容量较小；
当多处理器运行的过程中，有些处理器访问的Cache容量较大，有些处理器访问的Cache容量较小，并且，访问的Cache容量较大的处理器与访问的Cache容量较小的处理器之间的访问容量差值较大时，为了为每个处理器确定出更加合理的Cache分配容量，在一种可选的实施例中，Cache控制器根据每个处理器的Cache访问容量的大小，按照正相关确定出每个处理器的Cache分配容量，包括：Cache控制器根据每个处理器的Cache访问容量的大小，按照正比例关系确定出每个处理器的Cache分配容量。
其中，当确定出每个处理器的Cache分配容量的大小，按照每个处理器的Cache访问容量与每个处理器的Cache分配容量的正比例关系，为每 个处理器确定出Cache分配容量。
举例来说，当存在两个处理器时，统计出两个处理器的Cache的访问容量分别为20行和5行，并且Cache容量的总大小为4路，那么，按照正比例关系为每个处理器分配的Cache分配容量为20/(20+5)×4＝3.2，按照四舍五入原则，所确定出的两个处理器的Cache分配容量为3路和1路；
这样，便得到了为每个处理器所分配的Cache分配容量。
S103：Cache控制器将每个处理器的Cache分配容量写入每个处理器对应的锁定寄存器中。
在确定出每个处理器的Cache分配容量之后，Cache控制器驱动配置每个处理器对应的锁定寄存器，例如，当确定出的两个处理器的Cache分配容量为3路和1路时，那么，分别驱动对应的锁定寄存器写入二进制的10和00，从而完成了动态的调整每个处理器的Cache容量的目的。
下面举实例来对上述资源分配方法进行说明。
图2为本发明实施例中多处理器和共享的Cache的一种可选的结构示意图；如图2所示，包括：n+1个处理器和一个Cache20；
其中，Cache20中包括一个Cache控制器201、一个Cache缓存(Cache memory)202和一个Cache寄存器203；
在Cache寄存器203中，包括一个计数寄存器、与n+1个处理器一一对应的n+1个锁定寄存器和与n+1个处理器一一对应的n+1个统计寄存器；
上述资源分配方法包括：
步骤A：在Cache控制器201确定出一个或多个处理器在运行一段程序代码的时间大于预设时间阈值时，分别触发n+1个统计寄存器和计数寄存器生成使能信号为有效信号；
步骤B：每个统计寄存器开始统计每个统计寄存器对应的处理器所访问的Cache容量，计数寄存器开始计数；
步骤C：Cache控制器201在确定计数寄存器计数结束时，控制每个统计寄存器结束统计每个统计寄存器对应的处理器所访问的Cache容量，得到对应处理器的Cache访问容量；
步骤D：Cache控制器201根据对应处理器的Cache访问容量的大小，按照正比例关系确定出对应处理器的Cache分配容量；
步骤E：Cache控制器201将对应处理器的Cache分配容量写入对应的锁定寄存器中。
通过上述实例，可以一次给统计寄存器统计的Cache访问容量大的处理器多分配路大小的容量，这样比较直接的提升频繁访问Cache的处理器的性能，还可以先分配比较小的路大小给频繁访问Cache的处理器，在接下来的处理器访问中，同样按照上述实施例统计出每个处理器的访问的Cache访问容量，如果后续的时间段内访问频繁的处理器还是访问频繁，就继续给这个处理器分配路大小的Cache容量，但是如果因为程序局部性不太好，导致当前访问频繁的处理器后面对Cache缓存的访问量下降，则反过来减小Cache容量给访问频繁的处理器，这样，可以灵活地一步步动态调整每个处理器对应的Cache容量，从而保证多处理器的性能。
本发明实施例动态统计每个处理器对Cache的需求，在不同的时间段，根据需求的变化，动态调整处理器的Cache容量，避免为了提高性能增加片上memory大小，在节省成本的同时动态提升处理器的访问性能。
本发明实施例所提供的资源分配方法，该方法应用于多处理器共享的Cache中，其中，Cache包括：Cache控制器和Cache寄存器；Cache寄存器包括：每个处理器对应的统计寄存器和每个处理器对应的锁定寄存器；首先，每个统计寄存器统计出每个统计寄存器对应的处理器在预设时间内所访问的Cache容量，从而得到了每个处理器的Cache访问容量，并将每个处理器的Cache访问容量发送至Cache控制器；然后，Cache控制器根据 每个处理器的Cache访问容量，确定出每个处理器的Cache分配容量；最后，Cache控制器将每个处理器的Cache分配容量写入每个处理器对应的锁定寄存器中，这样，为每个处理器分配的Cache资源是按照每个处理器的实际需求来重新进行分配的，能够达到动态管理多核共享Cache资源的目的，从而实现了在降低面积成本的同时保证了多处理器的访问性能，提高了用户体验度。
基于同一发明构思，本发明实施例还提供一种Cache，图3为本发明实施例中Cache的结构示意图，如图3所示，该Cache包括：Cache控制器31和Cache寄存器32；Cache寄存器32包括：每个处理器对应的统计寄存器321和每个处理器对应的锁定寄存器322；其中，
每个统计寄存器321，配置为统计每个统计寄存器321对应的处理器在预设时间内所访问的Cache容量，得到每个处理器的Cache访问容量，发送每个处理器的Cache访问容量至Cache控制器31；Cache控制器31，配置为根据每个处理器的Cache访问容量，确定出每个处理器的Cache分配容量；将每个处理器的Cache分配容量写入每个处理器对应的锁定寄存器322中。
其中，上述每个统计寄存器321都是可配的多比特位宽的寄存器，每个统计寄存器321的位宽与每个统计寄存器321对应的处理器中运行的软件代码量成正相关。
Cache控制器31接收到每个处理器的Cache访问容量，在了解每个处理器在预设时间内实际的Cache访问容量之后，可以根据实际情况来重新为每个处理器分配Cache容量，在一种可选的实施例中，Cache控制器31，配置为根据每个处理器的Cache访问容量的大小，按照正相关关系确定出每个处理器的Cache分配容量。
当多处理器运行的过程中，有些处理器访问的Cache容量较大，有些 处理器访问的Cache容量较小，并且，访问的Cache容量较大的处理器与访问的Cache容量较小的处理器之间的访问容量差值较大时，为了为每个处理器确定出更加合理的Cache分配容量，在一种可选的实施例中，Cache控制器31，配置为根据每个处理器的Cache访问容量的大小，按照正比例关系确定出每个处理器的Cache分配容量。
上述预设时间还可以通过硬件的方式进行设置，在一种可选的实施例中，通过在Cache寄存器中增加一个计数寄存器来实现，当Cache寄存器32还包括一个计数寄存器；相应地，Cache控制器31，配置为控制每个统计寄存器321开始统计每个统计寄存器321对应的处理器所访问的Cache容量，且启动计数寄存器计数；在确定计数寄存器计数结束时，控制每个统计寄存器321结束统计每个统计寄存器321对应的处理器所访问的Cache容量，得到每个处理器的Cache访问容量。
本发明实施例所提供的资源分配方法，该方法应用于多处理器共享的Cache中，其中，Cache包括：Cache控制器和Cache寄存器；Cache寄存器包括：每个处理器对应的统计寄存器和每个处理器对应的锁定寄存器；首先，每个统计寄存器统计出每个统计寄存器对应的处理器在预设时间内所访问的Cache容量，从而得到了每个处理器的Cache访问容量，并将每个处理器的Cache访问容量发送至Cache控制器；然后，Cache控制器根据每个处理器的Cache访问容量，确定出每个处理器的Cache分配容量；最后，Cache控制器将每个处理器的Cache分配容量写入每个处理器对应的锁定寄存器中，这样，为每个处理器分配的Cache资源是按照每个处理器的实际需求来重新进行分配的，能够达到动态管理多核共享Cache资源的目的，从而实现了在降低面积成本的同时保证了多处理器的访问性能，提高了用户体验度。
这里需要指出的是：以上Cache实施例项的描述，与上述方法描述是 类似的，具有同方法实施例相同的有益效果，因此不做赘述。对于本发明Cache实施例中未披露的技术细节，本领域的技术人员请参照本发明方法实施例的描述而理解，为节约篇幅，这里不再赘述。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本发明的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。上述本发明实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的， 作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：移动存储设备、只读存储器(Read Only Memory，ROM)、磁碟或者光盘等各种可以存储程序代码的介质。
或者，本发明上述集成的单元如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：移动存储设备、ROM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种资源分配方法，该方法应用于多处理器共享的高速缓冲存储器Cache中，其中，所述Cache包括：Cache控制器和Cache寄存器；所述Cache寄存器包括：每个处理器对应的统计寄存器和所述每个处理器对应的锁定寄存器；所述方法包括：
    每个统计寄存器统计所述每个统计寄存器对应的处理器在预设时间内所访问的Cache容量，得到所述每个处理器的Cache访问容量，发送所述每个处理器的Cache访问容量至所述Cache控制器；
    所述Cache控制器根据所述每个处理器的Cache访问容量，确定出所述每个处理器的Cache分配容量；
    所述Cache控制器将所述每个处理器的Cache分配容量写入所述每个处理器对应的锁定寄存器中。
  2. 根据权利要求1所述的方法，其中，所述Cache控制器根据所述每个处理器的Cache访问容量，确定出所述每个处理器的Cache分配容量，包括：
    所述Cache控制器根据所述每个处理器的Cache访问容量的大小，按照正相关关系确定出所述每个处理器的Cache分配容量。
  3. 根据权利要求2所述的方法，其中，所述Cache控制器根据所述每个处理器的Cache访问容量的大小，按照正相关确定出所述每个处理器的Cache分配容量，包括：
    所述Cache控制器根据所述每个处理器的Cache访问容量的大小，按照正比例关系确定出所述每个处理器的Cache分配容量。
  4. 根据权利要求1所述的方法，其中，所述Cache寄存器还包括：一个计数寄存器；
    相应地，所述每个统计寄存器统计所述每个统计寄存器对应的处理器 在预设时间内所访问的Cache容量，得到所述每个处理器的Cache访问容量，包括：
    所述Cache控制器控制所述每个统计寄存器开始统计所述每个统计寄存器对应的处理器所访问的Cache容量，且启动所述计数寄存器计数；
    所述Cache控制器在确定所述计数寄存器计数结束时，控制所述每个统计寄存器结束统计所述每个统计寄存器对应的处理器所访问的Cache容量，得到所述每个处理器的Cache访问容量。
  5. 根据权利要求1所述的方法，其中，所述每个统计寄存器的位宽与所述每个统计寄存器对应的处理器中运行的软件代码量成正相关。
  6. 一种高速缓冲存储器Cache，所述Cache包括：Cache控制器和Cache寄存器；所述Cache寄存器包括：每个处理器对应的统计寄存器和所述每个处理器对应的锁定寄存器；其中，
    每个统计寄存器，配置为统计所述每个统计寄存器对应的处理器在预设时间内所访问的Cache容量，得到所述每个处理器的Cache访问容量，发送所述每个处理器的Cache访问容量至所述Cache控制器；
    所述Cache控制器，配置为根据所述每个处理器的Cache访问容量，确定出所述每个处理器的Cache分配容量；将所述每个处理器的Cache分配容量写入所述每个处理器对应的锁定寄存器中。
  7. 根据权利要求6所述的Cache，其中，所述Cache控制器，还配置为根据所述每个处理器的Cache访问容量的大小，按照正相关关系确定出所述每个处理器的Cache分配容量。
  8. 根据权利要求7所述的Cache，其中，所述Cache控制器，还配置为根据所述每个处理器的Cache访问容量的大小，按照正比例关系确定出所述每个处理器的Cache分配容量。
  9. 根据权利要求6所述的Cache，其中，所述Cache寄存器还包括： 一个计数寄存器；
    相应地，所述Cache控制器，还配置为控制所述每个统计寄存器开始统计所述每个统计寄存器对应的处理器所访问的Cache容量，且启动所述计数寄存器计数；在确定所述计数寄存器计数结束时，控制所述每个统计寄存器结束统计所述每个统计寄存器对应的处理器所访问的Cache容量，得到所述每个处理器的Cache访问容量。
  10. 根据权利要求6所述的Cache，其中，所述每个统计寄存器的位宽与所述每个统计寄存器对应的处理器中运行的软件代码量成正相关。
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