WO2018075811A3 - Architecture réseau sur puce - Google Patents

Architecture réseau sur puce Download PDF

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Publication number
WO2018075811A3
WO2018075811A3 PCT/US2017/057464 US2017057464W WO2018075811A3 WO 2018075811 A3 WO2018075811 A3 WO 2018075811A3 US 2017057464 W US2017057464 W US 2017057464W WO 2018075811 A3 WO2018075811 A3 WO 2018075811A3
Authority
WO
WIPO (PCT)
Prior art keywords
methods
systems include
data packet
slot
routing policy
Prior art date
Application number
PCT/US2017/057464
Other languages
English (en)
Other versions
WO2018075811A2 (fr
Inventor
Paul Michael SEBEXEN
Thomas SOHMERS
Edmond A. COTE
Nariman MOEZZI MADANI
Piyush Shrinivas KASAT
Original Assignee
Rex Computing, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/298,183 external-priority patent/US10700968B2/en
Priority claimed from US15/298,180 external-priority patent/US10355975B2/en
Priority claimed from US15/298,187 external-priority patent/US10127043B2/en
Application filed by Rex Computing, Inc. filed Critical Rex Computing, Inc.
Publication of WO2018075811A2 publication Critical patent/WO2018075811A2/fr
Publication of WO2018075811A3 publication Critical patent/WO2018075811A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

La présente invention concerne des procédés et des systèmes comprenant une série de cœurs de processeur et une série de routeurs : chaque routeur pouvant fonctionner pour envoyer un paquet de données sur la base d'une adresse de destination physique et retenir un paquet de données en cas de condition de trafic, et chaque routeur met en œuvre une politique de routage déterministe. Les procédés et les systèmes comprennent un processeur informatique simulant l'exécution de différentes configurations de fonctions sur une puce de microprocesseur multicœur formant une puce de réseau sur puce mettant en œuvre une politique de routage de priorité statique déterministe, et sélectionnant une configuration optimale parmi les différentes configurations sur la base d'un classement. Les procédés et les systèmes comprennent la mise en œuvre de mots d'instruction très longs (VLIW) comprenant un ensemble d'instructions de créneau, comprenant un code d'opération, correspondant à un ensemble d'unités fonctionnelles, et l'ordre à chaque unité fonctionnelle d'effectuer une opération identifiée par une instruction de créneau correspondante à l'aide de bits dédiés correspondants et de bits quelconques pouvant être attribués déterminés comme étant attribués à l'instruction de créneau.
PCT/US2017/057464 2016-10-19 2017-10-19 Architecture réseau sur puce WO2018075811A2 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US15/298,183 2016-10-19
US15/298,183 US10700968B2 (en) 2016-10-19 2016-10-19 Optimized function assignment in a multi-core processor
US15/298,187 2016-10-19
US15/298,180 US10355975B2 (en) 2016-10-19 2016-10-19 Latency guaranteed network on chip
US15/298,187 US10127043B2 (en) 2016-10-19 2016-10-19 Implementing conflict-free instructions for concurrent operation on a processor
US15/298,180 2016-10-19

Publications (2)

Publication Number Publication Date
WO2018075811A2 WO2018075811A2 (fr) 2018-04-26
WO2018075811A3 true WO2018075811A3 (fr) 2018-05-31

Family

ID=62019573

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2017/057464 WO2018075811A2 (fr) 2016-10-19 2017-10-19 Architecture réseau sur puce

Country Status (1)

Country Link
WO (1) WO2018075811A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111104775B (zh) * 2019-11-22 2023-09-15 核芯互联科技(青岛)有限公司 一种片上网络拓扑结构及其实现方法
CN113138711B (zh) * 2020-01-20 2023-11-17 北京希姆计算科技有限公司 一种存储管理装置及芯片
CN113986813B (zh) * 2021-09-18 2023-08-04 苏州浪潮智能科技有限公司 片上网络结构构建及使用的方法、系统、设备和存储介质
CN113923157A (zh) * 2021-10-14 2022-01-11 芯盟科技有限公司 一种基于片上网络的多核系统和处理方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090259713A1 (en) * 2001-02-24 2009-10-15 International Business Machines Corporation Novel massively parallel supercomputer
US8151088B1 (en) * 2008-07-08 2012-04-03 Tilera Corporation Configuring routing in mesh networks
US20150188847A1 (en) * 2013-12-30 2015-07-02 Netspeed Systems STREAMING BRIDGE DESIGN WITH HOST INTERFACES AND NETWORK ON CHIP (NoC) LAYERS

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090259713A1 (en) * 2001-02-24 2009-10-15 International Business Machines Corporation Novel massively parallel supercomputer
US8151088B1 (en) * 2008-07-08 2012-04-03 Tilera Corporation Configuring routing in mesh networks
US20150188847A1 (en) * 2013-12-30 2015-07-02 Netspeed Systems STREAMING BRIDGE DESIGN WITH HOST INTERFACES AND NETWORK ON CHIP (NoC) LAYERS

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
VAN DER LAAN, D., THE STRUCTURE AND PERFORMANCE OF OPTIMAL ROUTING SEQUENCES, 8 September 1976 (1976-09-08), XP055488718, Retrieved from the Internet <URL:http.//elleseerx.lst.psu.edu/viewdoc/docWnload?doi=10.1.1.732.5643&rep=1&type=pdf> [retrieved on 20180328] *

Also Published As

Publication number Publication date
WO2018075811A2 (fr) 2018-04-26

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