WO2018075225A1

WO2018075225A1 - Integrated direct dielectric and metal deposition

Info

Publication number: WO2018075225A1
Application number: PCT/US2017/054485
Authority: WO
Inventors: William T. Lee; Bart J. Van Schravendijk; David Charles Smith; Michael Danek; Patrick A. Van Cleemput; Ramesh Chandrasekharan
Original assignee: Lam Research Corp
Current assignee: Lam Research Corp
Priority date: 2016-10-17
Filing date: 2017-09-29
Publication date: 2018-04-26
Anticipated expiration: 2019-04-17
Also published as: CN109906498B; TW201828458A; KR20190057415A; JP2019537837A; US10128116B2; KR102549735B1; US20180108529A1; CN109906498A

Abstract

Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO₂/TiN, in a single tool, and even in a single process chamber enhances throughput without compromising quality when directly depositing a OMOM stack with many layers. Conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions, can be achieved.

Description

INTEGRATED DIRECT DIELECTRIC AND METAL DEPOSITION

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. Patent Application No. 15/593, 187, filed May 11, 2017, and entitled "INTEGRATED DIRECT DIELECTRIC AND METAL DEPOSITION," which claims priority to U.S. Provisional Patent Application No. 62/409,269, filed October 17, 2016, and titled "INTEGRATED DIELECTRIC AND METAL DEPOSITION," each of which is incorporated by reference herein in its entirety and for all purposes.

BACKGROUND

[0002] As memory density continues to increase, the industry has turned to 3D structures. Vertically-arranged storage devices are constructed within stacks of alternating layers of dielectric and metal in 3D NAND devices. And there are new types of memory such as PCRAM, ReRAM, FeRAM, etc. that will also utilize similar 3D configurations.

[0003] Currently, the stacks of alternating layers of dielectric and metal in 3D NAND devices are constructed by first depositing alternating layers of permanent dielectric (e.g., Si0₂) and temporary/sacrificial dielectric (e.g., Si₃N₄). Then, after channel hole etch and NAND device formation in the channel hole, the Si₃N₄ layers are removed, typically by wet etch, and replaced by metal layers (e.g., TiN barrier plus W fill for the lateral wordlines in 3D NAND). As the stacks get taller (e.g., from first generation 24/36-pair to future 96/>100- pair), the vertical features (such as channel holes, slits/trenches, staircases, etc.) will become more difficult to etch, and the lateral metal (wordline for 3D NAND) layers more difficult to fill post-Si₃N₄ removal. SUMMARY

[0004] This disclosure relates to apparatus and methods to efficiently and effectively directly deposit a dielectric/conductor stack, also referred to herein as an OMOM (oxide/metal) stack. Currently, oxide deposition and metal/metal nitride deposition are generally performed in separate tools, with oxide and metal/metal nitride dedicated process chambers. Efficient sequential deposition of alternating layers of oxide and metals in a single tool, and even in a single process chamber, reduces or minimizes the non-value added time of moving wafers between tools or between chambers when directly depositing an OMOM stack with many layers. Such apparatus and methods are provided herein.

[0005] For the purposes of this disclosure, "metal" used in this OMOM context should more generally understood in various embodiments to mean a conductor with a maximum resistivity of 500 micro Ohm cm. And "oxide" used in this OMOM context should more generally understood in various embodiments to mean a dielectric. Thus, in various embodiments, the conductor in the OMOM stack may be a metal, such as Ti, or a conductive metal salt, in particular a conductive metal nitride, for example, TiN; and the dielectric may be an oxide, such as silicon dioxide (Si0₂).

[0006] In various embodiments, the disclosed apparatus and methods can be generalized to other multi-film sequential direct dielectric/conductor deposition, particularly using multi- pedestal process modules, on a multi-module platform, running pedestals or modules in sequential or batch modes. The disclosure relates to hardware features to implement direct dielectric/metal deposition in the same process module, as well as to methods to reduce wafer handling overhead moving wafers between pedestals and process modules, and within a single vacuum process environment.

[0007] Various embodiments of a method of forming a film stack on a patterned semiconductor substrate are provided. Disclosed methods involve depositing a conductive film and depositing a dielectric film, such that the conductive and dielectric film depositions result in the formation of a conductor/di electric film pair on a patterned semiconductor substrate. Then, the depositing of the conductive and dielectric films are repeated to form a film stack comprising at least 20 pairs of alternating layers of conductor film and dielectric film. The conductive and dielectric film depositions are conducted in the same processing tool or chamber, without breaking vacuum between the film depositions, and there is no substantial cross-contamination between the conductive and dielectric film depositions.

[0008] In some implementations, the conductor (e.g., metal and/or conductive metal nitride) and dielectric (e.g., oxide), e.g., TiN and Si0₂, film pair depositions are conducted in different modules of the same tool without breaking vacuum between the depositions. In some implementations, the conductor/di electric film pair depositions are conducted on different stations in the same module of the same tool without breaking vacuum between the depositions. In some other implementations, the conductor/di electric film pair depositions are conducted on the same station in the same module of the same tool without breaking vacuum between the depositions.

[0009] In some implementations, at least 20 pairs of the conductor/di electric film pairs are deposited at a rate of at least 5 wafers per hour.

[0010] In another aspect, the disclosure relates to apparatus for integrated formation a film stack comprising layers of conductor and dielectric film on a patterned semiconductor substrate. The conductor and dielectric film depositions are conducted in the same processing tool or chamber, without breaking vacuum between the film depositions; and wherein there is no substantial cross-contamination between the conductor and dielectric film depositions. Apparatus architecture permits deposition of a stack of at least 20 conductor/di electric film pairs at a rate of at least 5 wafers per hour.

[0011] In some implementations of the apparatus, the conductor and dielectric (e.g., metal nitride and oxide, e.g., TiN and Si0₂) pair depositions are conducted in different modules of the same tool without breaking vacuum between the depositions. In some implementations of the apparatus, the conductor/di electric film pair depositions are conducted on different stations in the same module of the same tool without breaking vacuum between the depositions. In some other implementations of the apparatus, the conductor/di electric film pair depositions are conducted on the same station in the same module of the same tool without breaking vacuum between the depositions.

[0012] These and other aspects the disclosure are further described below with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Fig. 1 depicts a representative 3D NAND device including an OMOM film stack. [0014] Fig. 2 depicts a flow chart illustrating a method for depositing an OMOM

(oxide/metal) film stack in-situ using a plurality of plasma-activated film deposition phases, in accordance with one embodiment.

[0015] Fig. 3 depicts integrated dielectric and metal deposition implemented in different modules of the same tool, in accordance with a first embodiment. [0016] Fig. 4 depicts an integrated dielectric and metal deposition implemented on different pedestals in the same module(s) of the same tool, in accordance with a second embodiment.

[0017] Fig. 5 depicts an integrated dielectric and metal deposition sequentially

implemented on the same pedestal(s) in the same module(s) of the same tool, in accordance with a third embodiment.

[0018] Figs. 6 and 7 depict schematic diagrams showing a chemical deposition apparatus in accordance with embodiments disclosed herein.

[0019] Fig. 8 depicts a cross-sectional view of a chemical deposition apparatus having a gas based sealing system in accordance with an exemplary embodiment.

[0020] Fig. 9 depicts a cross-sectional view of a portion of a deposition chamber of a chemical deposition apparatus having a gas based sealing system in accordance with an exemplary embodiment.

[0021] Fig. 10 depicts a cross-sectional view of a portion of the deposition chamber of a chemical deposition apparatus with a gas based sealing system.

[0022] Fig. 11 depicts a cross-sectional view of a portion of the deposition chamber of a chemical deposition apparatus with a gas based sealing system in accordance with an exemplary embodiment.

[0023] Fig. 12 depicts a cross-sectional view of a portion of the deposition chamber of a chemical deposition apparatus with a gas based sealing system in accordance with an exemplary embodiment.

[0024] Fig. 13 depicts a schematic of a gas based sealing system in accordance with an exemplary embodiment.

[0025] Fig. 14 depicts a cut-away view of a showerhead module.

[0026] Fig. 15 depicts another cut-away view of the showerhead module of Fig. 14.

[0027] Fig. 16 depicts a cross-sectional schematic of a single-station substrate processing apparatus.

[0028] Fig. 17 depicts a schematic illustration of a pair of process stations. [0029] Fig. 18 depicts an example processing chamber that includes a showerhead configured to release curtain gas into the process chamber.

[0030] Fig. 19 depicts a second example processing chamber that is configured to release curtain gas into the process chamber.

[0031] Fig. 20 depicts a third example processing chamber that includes a pedestal configured to release curtain gas into the process chamber.

[0032] Fig. 21 depicts an example of a substrate processing system.

[0033] Fig. 22 depicts an example of collar of Fig. 21.

[0034] Fig. 23 depicts an example of the fluid connector for the collar of Fig. 21.

[0035] Figs. 24 A and 24B depict examples of the plate of Fig. 21.

DETAILED DESCRIPTION

[0036] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.

Introduction

[0037] Efficient sequential deposition of alternating layers of dielectric and metals in a single tool, and even in a single process chamber, enhances throughput without compromising quality when directly depositing a dielectric/metal stack with many layers. For the purposes of this disclosure, "metal" used in this context should be understood to mean conductor with a maximum resistivity of 500 micro Ohm cm, including metals and conductive metal salts, in particular conductive metal nitrides, e.g., TiN. Such apparatus and methods are provided herein. [0038] In typical current 3D NA D manufacturing, the "mold stack" comprising a stack of 24 to 64 pairs of Si0₂/Si₃N₄ layers is typically deposited in a PECVD dielectric deposition tool. The Si0₂ layer and Si₃N₄ layer are deposited sequentially on each station (also referred to as a pedestal) without moving the wafer until the entire stack, or a substantial fraction of the stack, is deposited. Vertical channels are then etched down through the oxide and nitride layers in the mold stack by high aspect ratio etching, and filled with metal to form contacts. Then, a thick photoresist layer is applied and patterned, one set of oxide/nitride pairs is etched and then the photoresist pattern is shrunk and the next pair of oxide/nitride layers is etched. This sequence is repeated to create a stair step structure at the edge of the array. After a thick oxide layer is deposited and planarized, a word line slot mask is applied and a slot is etched down through all of the oxide/nitride layer pairs. The nitride layers are then etched out through the word line slot. A gate stack of silicon dioxide, silicon nitride, aluminum oxide, tungsten and tantalum nitride is then deposited and etched back and finally the slot is filled with oxide and tungsten. Metal deposition occurs in a separate metal fill tool such as Lam's ALTUS Max. A typical 3D NAND device 1 formed in this way is depicted in Fig. 1, showing the stack 2, channel 3 and contact metal fill 4, staircase formed by staircase etch 5, slit 6 and wordline metal fill 7, and bitline 8, above. A single memory cell 9 is shown enlarged.

[0039] This approach works for layers at the current stack layer thickness of approximately 25nm to 30nm each, but becomes difficult for lower thicknesses, for example approximately lOnm to 15nm each. The need for thinner layers is driven by the need to control the total stack thickness (e.g., to maintain total planarity for lithography, to minimize total wafer bow from accumulated stress, to ease etch requirements, etc.). Therefore this "ONON" (oxide/nitride) deposition followed by replacement of 'N' by metal, or other metal-containing conductive material, may eventually become impractical.

[0040] According to currently available methodologies to directly deposit a dielectric/metal stack, the wafer has to move between dielectric-specific deposition tool and metal-specific deposition tool, which would typically be in different parts of a semiconductor fabrication plant. Therefore, for an n-pair stack, the wafer would have to travel 2n times between tools. This is extremely time-consuming, creates a tremendous amount of WIP (work-in-progress) wafer inventory, and adds an unacceptable amount of cost. [0041] A PVD (either evaporation type, or sputter type) with multiple targets (one for dielectric and the other for metal) could be used to directly deposit alternating dielectric/metal layers in a stack without breaking vacuum. However, these tools tend to deposit films that are not uniform enough for use in high-layer count 3D memory devices, and the dielectric quality using PVD methods tend to be of poor quality due to intrinsic damage, defects and/or traps.

[0042] The present disclosure describes apparatus and processes for efficiently depositing both very smooth, high-quality dielectric and metal/conductive metal -containing layers with excellent thickness uniformity on the same tool, and even in the same process module: Integrated direct dielectric and metal deposition.

Integrated OMOM Film Stack Deposition Processes

[0043] Various embodiments of a method of forming a film stack on a patterned semiconductor substrate are provided. Fig. 2 provides a process flow for disclosed methods including depositing a conductive film (20) and depositing a dielectric film, such that the conductive and dielectric film depositions result in the formation of a conductor/di electric film pair on a patterned semiconductor substrate (21). Then, the depositing of the conductive and dielectric films are repeated to form a film stack comprising at least 20 pairs of alternating layers of conductor film and dielectric film (22). The conductive and dielectric film depositions are integrated by being conducted in the same processing tool or chamber, without breaking vacuum between the film depositions (23), and there is no substantial cross- contamination between the conductive and dielectric film depositions (24).

[0044] The integrated deposition enhances throughput. In various embodiments, particularly in which conductor and dielectric deposition are conducted in the same module, the conductive and dielectric film pairs are deposited in the stack at a rate of at least 5 wafers per hour (25, shown in broken lines as a feature of some but not necessarily all embodiments).

[0045] In one aspect, the disclosure relates to a method of forming a film stack comprising pairs of alternating layers of titanium nitride (TiN; metal) film and silicon oxide (Si0₂; oxide) film on a patterned semiconductor substrate. The method involves depositing a TiN film, the TiN film formed from the reaction of a TiN precursor, and depositing a silicon oxide film, the silicon oxide film formed from the reaction of one or more precursor comprising silicon and an oxidant, and repeating the depositing of the TiN and the Si0₂ film to form a film stack comprising at least 20 pairs of alternating layers of TiN and Si0₂ films. The TiN and Si0₂ film film pair depositions are conducted in the same processing tool or chamber, without breaking vacuum between the film depositions, and there is no substantial cross- contamination between the TiN and Si0₂ film depositions.

[0046] In some implementations, the conductor (e.g., metal and/or conductive metal nitride) and dielectric (e.g., silicon oxide) film pair depositions are conducted in different modules of the same tool without breaking vacuum between the depositions. In some implementations, the metal and/or conductive metal nitride and silicon oxide film pair depositions are conducted on different stations in the same module of the same tool without breaking vacuum between the depositions. In some other implementations, the metal and/or conductive metal nitride and silicon oxide film pair depositions are conducted on the same station in the same module of the same tool without breaking vacuum between the depositions. [0047] In some implementations, at least 20 pairs of the metal and/or conductive metal nitride and silicon oxide film pairs are deposited at a rate of at least 5 wafers per hour. In other implementations, least at least 40 pairs, or at least 50, 60, 70, 80, 90 or 100 pairs of the metal and/or conductive metal nitride and silicon oxide film pairs are deposited.

[0048] In various implementations, the silicon oxide precursor can be silane or TEOS, or other Si-based precursors typically used for Si0₂ deposition processes. Examples of suitable Si0₂ precursors include Si-based precursors that contain H, halides, alkoxides, alkyl and amide ligands, such as SiH₄, SiH₂Cl₂, Si(OET)₄, Si(NMe₂)4, SiX_nH_y (where X is a halide, n = 0-4 and y = 4 - n) , Si(OR)₄ (where R is an alkyl group such at methyl, ethyl, etc.), and SiH_x(NR₂)y, (where R is an alkyl, x =1-3, y = 4 - x). Examples of suitable oxidizers include 0₂, N₂0, C0₂, 0₃ and CO.

[0049] In various implementations, the one or more metal and/or metal nitride precursor can be metal and or metal nitride precursors used for thermal CVD, PECVD or ALD of such thin films, such as metal halides, metal amides and organometallics for metal s/conductors such as titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, cobalt, and cobalt nitride. Specific examples include PECVD with TiCl₄ or ALD with TiCl_4, and NH₃ or H₂/N₂. [0050] In some implementations, an inert gas species is introduced to the processing chamber between the metal and/or metal nitride and oxide depositions.

Integrated— Same Tool / Different Modules

[0051] Referring to Fig. 3, in a first embodiment, integrated dielectric and metal deposition may be implemented in different modules 31, 32, 33, 34 of the same tool 30. For example, Lam Research Strata PECVD and/or Striker ALD dielectric deposition modules may be integrated in the same tool platform as Lam Research ALTUS metal deposition modules. In this way, there is no air break between layers, and each module optimized for each film type (reactor type, pressure, temp, etc.). As a result, technical performance is not compromised by having metal and dielectric process gases, films and by-products in the same process module and there is no cross-contamination (gate valves between modules), resulting in excellent film properties.

[0052] Referring to Fig. 3, a suitable tool 30 may be configured with at least one pair of dielectric and metal deposition modules, in this implementation two dielectric deposition modules 31, 33, such as the VECTOR Strata PECVD or Striker ALD dielectric deposition modules, available from Lam Research Corporation, Fremont, CA, and two metal deposition modules 32, 34, such as Lam Research ALTUS metal deposition module. A suitable tool 30 configuration includes four QSMs (quad-station modules) 31, 32, 33, 34 on a Lam Mach IQ platform 35. [0053] The platform 35 includes a load lock 36 and robot 37 is configured to move wafers from a cassette loaded through one or more pods 38 into the load lock 36 via an atmospheric port. A wafer may be heated or exposed to plasma when inbound in the load lock 36, for example, to remove moisture and adsorbed gases, or for other pretreatment reasons. Then another robot (e.g., 39) can place the wafer into a deposition module for processing. [0054] As depicted by the arrows 40 and 41 in Fig. 3, wafers can be transferred back and forth between dielectric and metal deposition modules without breaking vacuum to conduct the alternating dielectric and metal depositions to form the stack. In addition, unequal dielectric and metal process times can be addressed by different module ratios (e.g., if dielectric deposition time is twice the metal deposition time, then the tool can be configured with twice the dielectric modules than metal modules). [0055] Potential large wafer transfer time overhead may be offset through the use of a many-bladed transfer robot 39 to permit some batch load and unload, and the use buffer station(s) 42, for example, heat-up/cool-down stations between dielectric and metal depositions at different temperatures. Integrated In-Situ Sequential - Same Tool / Same Module / Different Pedestals

[0056] Referring to Fig. 4, in a second embodiment, integrated dielectric and metal deposition may be implemented on different pedestals 62 in the same module(s) 51 of the same tool 50. A suitable tool 50 may be configured for integrated in-situ sequential processing in accordance with this embodiment with at least one dielectric and metal deposition module, in this implementation four QSMs (quad-station modules) 51, 52, 53, 54 on a Lam Mach IQ platform 55. The platform 55 includes a load lock 56 and robot 57 is configured to move wafers from a cassette loaded through one or more pods 58 into the load lock 56 via an atmospheric port. A wafer may be heated or exposed to plasma when inbound in the load lock 56, for example, to remove moisture and adsorbed gases, or for other pretreatment reasons. Then another robot (e.g., 59) can place the wafer into a deposition module for processing.

[0057] For example, Lam Research Strata PECVD and/or Striker ALD dielectric deposition modules station designs may be integrated in the same module as Lam Research ALTUS metal deposition module station designs. Or, Lam Research Strata PECVD and/or Striker ALD dielectric deposition modules station designs may be adapted such that dielectric and metal deposition may be effectively conducted at different stations within the same module. For example, station/pedestal 62a may be a dielectric deposition station and station 62b may be a metal deposition station, with the wafers rotated between stations within the module 51, as indicated by arrow 60. In this way, there also is no air break between layers, and indexing a wafer from pedestal to pedestal is faster than transferring wafers between process modules via a central handling robot 59. As a result, efficiency (throughput) is enhanced without substantially sacrificing technical performance, and cross-contamination is controlled or minimized, resulting in excellent film properties.

[0058] In addition, each station/pedestal can be configured or optimized for each deposition type, and pedestals can be isolated from each other to reduce or minimize cross- contamination/cross-talk between dielectric and metal deposition processes, for example by gas curtains or other station-specific barriers like gas seals, such as are described, for example, in U.S. Patent Application Publication No. 2015/0004798 and U.S. Patent Application Publication No. 2017/0101710, the disclosures of which in this regard are hereby incorporated by reference herein. Within ranges, each pedestal process can be at a different temperature and pressure. And each station's pedestal, showerhead, wall, etc. temperature can be independently set optimally for each process, without needing to cycle. Gas distribution to each station can be kept separate. By adding multiple throttle valves, one for the dielectric (e.g., oxide) stations and one for the metal (e.g., TiN) stations, pressures can be independently maintained. Exhaust for each station can be local and not shared, so that the exhaust can stay independent without cross mixing/contamination of gases.

Example gas seal barriers

[0059] There are generally two main types of deposition showerheads, the chandelier type and the flush mount. The chandelier showerheads have a stem attached to the top of the chamber on one end and the faceplate on the other end, resembling a chandelier. A part of the stem may protrude the chamber top to enable connection of gas lines and RF power. The flush mount showerheads are integrated into the top of a chamber and do not have a stem. Present embodiments pertain to a flush mount type showerhead wherein the flush mount showerhead reduces chamber volume, which must be evacuated by a vacuum source during processing.

[0060] Figs. 6 and 7 are schematic diagrams showing a chemical deposition apparatus 100 in accordance with embodiments disclosed herein. As shown in Figs. 6 and 7, the chemical apparatus includes a chemical isolation chamber or housing 110, a deposition chamber 120, a showerhead module 130, and a moving pedestal module 140 that can be vertically raised or lowered relative to the showerhead module 130 to raise and lower a substrate (or wafer) 190 position on an upper surface of the pedestal module 140. The showerhead module 130 can also be vertically raised and lowered. Reactant material gases (or process gases) 192 are introduced into the sub- chamber (or wafer cavity) 150 via gas lines 112 through a central plenum 202 of the showerhead module 130. Each of the gas lines 112 may have a corresponding accumulator (not shown), which can be isolated from the apparatus 100 using isolation valves (not shown). In accordance with an exemplary embodiment, the apparatus 100 can be modified to have one or more gas lines 112 with isolation valves and accumulators, depending on the number of reactant gases used. Also, reactant gas delivery lines 112 can be shared between a plurality of chemical deposition apparatuses or multistation system.

[0061] In accordance with an exemplary embodiment, the chamber 120 can be evacuated through one or more vacuum lines 160 that are connected to a vacuum source (not shown). For example, the vacuum source can be a vacuum pump (not shown). In multi-station reactors, for example, those having multiple stations or apparatuses 100 that perform the same deposition process, a vacuum line 160 from another station may share a common foreline with the vacuum line 160. In addition, the apparatus 100 can be modified to have one or more vacuum lines 160 per station or apparatus 100. [0062] In accordance with an exemplary embodiment, a plurality of evacuation conduits 170 can be configured to be in fluid communication with one or more exhaust outlets 174 within the faceplate 136 of the showerhead module 130. The exhaust outlets 174 can be configured to remove process gases or reactor chemistries 192 from the wafer cavity 150 between deposition processes. The plurality of evacuation conduits 170 are also in fluid communication with the one or more vacuum lines 160. The evacuation conduits 170 can be spaced circumferentially around the substrate 190 and may be evenly spaced. In some instances, the spacing of plurality of conduits 170 may be designed to compensate for the locations of the vacuum lines 160. Because there are generally fewer vacuum lines 160 than there are plurality of conduits 170, the flow through the conduit 170 nearest to a vacuum line 160 may be higher than one further away. To ensure a smooth flow pattern, the conduits 170 may be spaced closer together if they are further away from the vacuum lines 160.

[0063] Embodiments disclosed herein are preferably implemented in a plasma enhanced chemical deposition apparatus (e.g., PECVD apparatus, PEALD apparatus, or PEPDL apparatus). Such an apparatus may take different forms wherein the apparatus can include one or more chambers or "reactors" 110, which can include multiple stations or deposition chambers 120 as described above, that house one or more substrates 190 and are suitable for substrate processing. Each chamber 120 may house one or more substrates for processing. The one or more chambers 120 maintain the substrate 190 in a defined position or positions (with or without motion within that position, e.g. rotation, vibration, or other agitation). In one embodiment, a substrate 190 undergoing deposition and treatment can be transferred from one station (e.g. deposition chamber 120) to another within the apparatus 100 during the process. While in process, each substrate 190 is held in place by a pedestal, wafer chuck and/or other wafer holding apparatus of the pedestal module 140. For certain operations in which the substrate 190 is to be heated, the pedestal module 140 may include a heater such as a heating plate.

[0064] Fig. 8 is a cross-sectional view of a chemical deposition apparatus 100 having a gas based sealing system 200 in accordance with an exemplary embodiment. As shown in Fig. 8, the chemical deposition apparatus 100 includes a substrate pedestal module 140, which is configured to receive and/or discharge a semiconductor substrate (or wafer) 190 from an upper surface 142 of the pedestal module 140. In a lower position, a substrate 190 is placed on the upper surface 142 of the pedestal module 140, which is then raised vertically upward towards the showerhead module 130. In accordance with an exemplary embodiment, the distance between the upper surface 142 of the pedestal module 140 and a lower surface 132 of the showerhead module 130, which forms a wafer cavity 150 can be about 0.2 inches (5 millimeters) to about 0.6 inches (15 millimeters). The upward vertical movement of the pedestal module 140 to close the wafer cavity 150 creates a narrow gap 240 between the pedestal module 140 and a step 135 around an outer portion 131 of the faceplate 136 of the showerhead module 130.

[0065] In accordance with an exemplary embodiment, the gas based sealing system 200 can be configured to help control and regulate flow out from the wafer cavity 150 during flow of process material or purge gas. In accordance with an exemplary embodiment, the evacuation or purging of the wafer cavity 150 uses an inert or purge gas (not shown), which is fed into the wafer cavity 150 through the showerhead module 130. In accordance with an exemplary embodiment, one or more conduits 170 can be connected to the vacuum lines 160 via an annular evacuation passage 176, which is configured to remove inert seal gas 182 from a zone below the pedestal module 140. [0066] In accordance with an exemplary embodiment, the showerhead module 130 is configured to deliver reactor chemistries to the wafer cavity (or reaction chamber) 150. The showerhead module 130 can include a faceplate 136 having a plurality of inlets or through holes 138 and a backing plate 139. In accordance with an exemplary embodiment, the faceplate 136 can be a single plate having a plurality of inlets or through holes 138 and the step 135, which extends around the outer periphery 137 of the faceplate 136. Alternatively, the step 135 can be a separate ring 133, which is secured to a lower surface of the outer portion 131 of the faceplatel36. For example, the step 135 can be secured to the outer portion 131 of the faceplate 136 with screws 143.

[0067] In accordance with an exemplary embodiment, the wafer cavity 150 is formed beneath the lower surface 132 of the faceplate 136 of the showerhead module 130 and the upper surface 142 of the substrate pedestal module 140. The plurality of concentric evacuation conduits or exhaust outlets 174 within the faceplate 136 of the showerhead module 130 can be fluidly connected to the one or more of the plurality of conduits 170 to remove process gases or reactor chemistries 192 from the wafer cavity 150 between deposition processes. [0068] As shown in Fig. 8, the apparatus 100 also includes a source 180 of inert gas or seal gas 182, which is fed through the one or more conduits 184 to an outer plenum 204 of the gas based sealing system 200. In accordance with an exemplary embodiment, the inert or seal gas 182 can be a nitrogen gas or argon gas. In accordance with an exemplary embodiment, the inert gas source 180 is configured to feed an inert seal gas 182 via one or more conduits 184 so as to flow radially inward through the narrow gap 240, which extends outward from the wafer cavity 150 and is formed between a lower surface 134 of a step 135 around the outer periphery 137 of the faceplate 136 and the upper surface 142 of the pedestal module 140. In accordance with an exemplary embodiment, the inert seal gas 182 communicates with process gases or reactor chemistries 192 from the wafer cavity 150 within the narrow gap 240 to form a gas seal during processing. As shown in Figs. 9 and 10, the inert seal gas 182 only partly enters the narrow gap 240, which forms a gas seal between the reactor chemistries 192 and the inert gas 182 within the narrow gap. Alternatively, as shown in Figs. 11 and 12, the flow of the inert gas 182 can be to an outer edge of the wafer cavity 150 and removed from the wafer cavity 150 through the one or more exhaust outlets 174 within the showerhead module 130.

[0069] In accordance with an exemplary embodiment, the annular evacuation passage 176 is fluidly connected to one or more of the plurality of evacuation conduits 170. In accordance with an exemplary embodiment, the annular evacuation passage 176 has one or more outlets (not shown) and is configured to remove the inert gases 182 from the zone surrounding the periphery of the substrate 190 and the inert gases 182 traveling or flowing radially inward through the narrow gap 240. The evacuation passage 176 is formed within an outer portion 144 of the substrate pedestal 140. The annular evacuation passage 176 can also be configured to remove the inert gases 182 from underneath the substrate pedestal 140. Further embodiments with multiple conduits similar to 176 can aid in withdrawing more inert gas 182 and enabling higher flow of inert gas into exhaust passages 178 and portion below the pedestal module 140. The exhaust passages 178 can also aid in creating a higher pressure drop on the seal gas and lower diffusion of the seal gas into the wafer cavity 150.

[0070] Fig. 9 is a cross-sectional view of a portion of a deposition chamber 120 of a chemical deposition apparatus 100 having a gas based sealing system 200 in accordance with an exemplary embodiment. As shown in Fig. 9, the outer plenum 204 can be formed in the outer portion 131 of the faceplate 136. The outer plenum 204 can include one or more conduits 220, which are configured to receive the inert gas 182 from the inert gas source 180. The inert gas 182 flows through the outer plenum 204 via the one or more conduits 220 to a lower outlet 228. The lower outlet 228 is in fluid communication with the narrow gap 240. In accordance with an exemplary embodiment, distance from an outer edge 152 of the wafer cavity 150 to the outer periphery 141 of the faceplate 136 in communication with the outer plenum 204 is at a finitely controlled distance. For example, the distance (or width) from the outer edge 152 of the cavity 150 to the outer edge 141 of the faceplate 136 in communication with the outer plenum 204 can be from about 5.0 mm to 25.0 mm.

[0071] In accordance with an exemplary embodiment, the outer plenum 204 can be an outer annular recess 222. The outer annular recess 222 is configured to be in fluid communication with the narrow gap 240 on an outer edge of the wafer cavity 150 via the one or more conduits 220. The outer annular recess 222 can be configured to have an upper annular recess 224 and a lower annular recess 226, wherein the upper annular recess 224 has a greater width than the lower annular recess 226. In accordance with an exemplary embodiment, the lower outlet 228 is an annular outlet on a lower portion of the lower annular recess 226, which is in fluid communication with the narrow gap 240.

[0072] In accordance with an exemplary embodiment, as shown in Fig. 9, the inert gas 182 is fed through the outer plenum 204 at the outer edge of the wafer cavity 150 spaced at finitely controlled distances. The flow rate of the inert gas 182 flowing through the outer plenum 204 can be such that the Peclet number is greater than about 1.0, thus containing the reactor gas chemistries 192 within the wafer cavity 150, as shown in Fig. 9. For example, if the Peclet number is greater than 1.0, the inert gas 182 and the reactor gas chemistries 192 can establish an equilibrium within an inner portion 242 of the narrow gap 240. As a result, reactor gas chemistries 192 can be prevented from flowing beneath the substrate pedestal module 140 and contaminating portions of the deposition chamber 120 outside of the wafer cavity 150.

[0073] In accordance with an exemplary embodiment, if the process is a constant pressure process, then a single (or constant) flow of the inert gas 182 in combination with the pressure from below the pedestal module 140 can be sufficient to ensure an inert gas seal between the reactor gas chemistries 192 within the wafer cavity 150 and the inert gas 180 flowing radially inward through the narrow gap 240. For example, in accordance with an exemplary embodiment, the gas based sealing system 200, can be used with ALD oxides of Si, which can be generally run in a relatively constant pressure mode. In addition, the gas based sealing system 200 can act as a means to control gas sealing across different processes and pressure regimes within the deposition chamber 120 and the wafer cavity 150, for example, during an ALD nitride process by varying the flow rate of the inert gas 182 or pressure below the pedestal module 140 and/or a combination of both. [0074] In accordance with an exemplary embodiment, the sealing gas system 200 as disclosed individually, or in combination with the pressures associated with the exhaust conduits 174, 176 can help prevent flow and/or diffusion of reactor chemistries 192 out of wafer cavity 150 during processing. In addition, the system 200 individually, or in combination with the exhaust conduits 174, 176 and pressure associated with the exhaust conduits 174, 176 can also prevent the bulk flow of the inert gas 182 into the wafer cavity 150 and over onto the substrate 190. The flow rate of the inert gas 182 into the narrow gap 240 to isolate the wafer cavity 150 can be adjusted based on the pressure produced by the exhaust outlets 174. In accordance with an exemplary embodiment, for example, the inert gas or seal gas 182 can be fed through the outer plenum 204 at a rate of about 100 cc/minute to about 5.0 standard liters per minute (slm), which can be used to isolate the wafer cavity 150.

[0075] In accordance with an exemplary embodiment, one or more evacuation cavities 250 can be located in an outer portion of the pedestal module 140, which surrounds the wafer cavity 150. The one or more evacuation cavities 250 can be in fluid communication with the narrow gap 240 and the lower outlet 228, which can add to the pressure drop from the wafer cavity 150 to the inert or gas feed 180. The one or more evacuation cavities 250 (or annular channel) can also provide an added control mechanism to enable gas sealing across various process and pressure regimes, for example, during ALD nitride processing. In accordance with an exemplary embodiment, the one or more evacuation cavities 250 can be equally spaced around the deposition chamber 120. In an exemplary embodiment, the one or more evacuation cavities 250 can be an annular channel, which is concentric and of larger wi dth than the 1 ower outl et 228.

[0076] Fig. 10 is a cross-sectional view of a portion of the deposition chamber 120 of a chemical deposition apparatus 100 with a gas based sealing system 200. As shown in Fig. 10, if the flow rate of the reactor chemistries 192 is greater than or about equal to the flow rate of the inert gas 182, the flow of the reactor chemistries 192 may extend outside of the wafer cavity 150, which may not be desirable.

[0077] As shown in Fig. 10, an annular evacuation passage 176 provides a secondary evacuation path in addition to the main evacuation path 174 in the faceplate 136. The annular evacuation passage 176 is configured to remove the inert gases 182 from underneath the substrate pedestal 140 and from a zone surrounding a periphery of the substrate 190. In accordance with an exemplary embodiment, the annular evacuation passage 176 has one or more outlets (not shown) and is configured to remove the inert gases 182 from the zone surrounding the periphery of the substrate 190 and the inert gases 182 flowing or diffusing radially inward through the narrow gap 240.

[0078] Fig. 11 is a cross-sectional view of a portion of the deposition chamber 120 of a chemical deposition apparatus 100 with a gas based sealing system 200 in accordance with an exemplary embodiment. The flow of inert gas 182 from outside the cavity 150 can be produced by reducing the flow rate of the reactor chemistries 192 and/or increasing the flow rate of the inert gas 182. In accordance with an exemplary embodiment, the inert gas 182 from the outer plenum 204 will flow into the wafer cavity 150 and can be removed through the one or more exhaust outlets 174 within the showerhead module 130.

[0079] Fig. 12 is a cross-sectional view of a portion of the deposition chamber 120 of a chemical deposition apparatus 100 with a gas based sealing system 300 in accordance with an exemplary embodiment. In accordance with an exemplary embodiment, a central plenum 202 of the showerhead module 130 includes the plurality of inlets or through -holes 138, which delivers the reactor chemistries 192 to the wafer cavity 150. The wafer cavity 150 also includes concentric conduits or exhaust outlets 174 which remove reactor chemistries 192 and inert gases 182 from the wafer cavity 150. The concentric conduits or exhaust outlets 174 can be in fluid communication with an intermediate plenum 208 between the backing plate 139 and an upper plate 310. The intermediate plenum 208 is in fluid communication with one or more of the plurality of evacuation conduits 170. [0080] The showerhead module 130 can also include vertical gas passage 370, which is configured to deliver an inert gas 182 around the outer periphery 137 of the faceplate 136. In accordance with an exemplary embodiment, an outer plenum 206 can be formed between the outer periphery 137 of the faceplate 136 and an inner periphery or edge 212 of an isolation ring 214. [0081] As shown in Fig. 12, the system 300 includes the vertical gas passage 370 formed within an inner channel 360 within the upper plate 310 and an outer portion 320 of the backing plate 139. The vertical gas passage 370 includes one or more conduits 312, 322, which are configured to receive the inert gas 182 from the inert gas source or feed 180. In accordance with an exemplary embodiment, the inert gas 182 flows through the upper plate 310 and the outer portion 320 of the backing plate 139 via the one or more conduits 312, 322 to one or more recesses and/or channels 330, 340, 350 to an outer edge of the wafer cavity 150.

[0082] In accordance with an exemplary embodiment, the one or more conduits 312 can include an upper annular recess 314 and a lower outer annular recess 316. In accordance with an exemplary embodiment, the upper recess 314 has a greater width than the lower recess 316. In addition, the one or more conduits 322 can be within the upper plate 310 and the outer portion 320 of the backing plate 139. The one or more conduits 322 can form an annular recess having an inlet 326 in fluid communication with an outlet 318 on the upper plate 310 and an outlet 328 in fluid communication with the narrow gap 240. In accordance with an exemplary embodiment, the outlet 328 within the outer portion 320 can be in fluid communication with one or more recesses and/or channels 330, 340, 350, which guides the flow of the inert gas 182 around an outer periphery of the faceplate 136 of the showerhead module 130 to an outer edge 243 of the narrow gap 240.

[0083] In accordance with an exemplary embodiment, the inert gas 182 is fed through the vertical gas passage 370 to the outer plenum 206, and radially inwardly at least partly through the narrow gap 240 towards the wafer cavity 150. The flow rate of the inert gas 182 flowing through the one or recesses and/or channels 330, 340, 350 can be such that the Peclet number is greater than 1.0, thus containing the reaction gas chemistries 192 within the wafer cavity 150. In accordance with an exemplary embodiment, if the Peclet number is greater than 1.0, the inert gas 182 and the reaction gas chemistries 192 establishes an equilibrium within the inner portion 242 of the narrow gap 240, which prevents the reaction gas chemistries 192 from flowing beneath the pedestal module 140 and contaminating portions of the deposition chamber 120 outside of the wafer cavity 150. In accordance with an exemplary embodiment, by containing the flow of the reaction gas chemistries 192 to the wafer cavity 150, the system 200 can reduce the usage of process gas 192. In addition, the system 200 can also reduce the fill time of the wafer cavity 150 with the process gas 192 during processing.

[0084] Fig. 13 is a schematic of a gas based sealing system 400 in accordance with an exemplary embodiment. As shown in Fig. 13, the system 400 includes a source of an inert or seal gas 180 and source of a process gas 19, which are configured to deliver an inert or seal gas 182 and a process gas 192, respectively, to the wafer cavity 150. The system 400 can also include a wafer-cavity or cavity pressure valve 410 and a lower chamber pressure valve 412, which control a wafer-cavity or cavity pressure 414, and a lower chamber pressure 416, respectively.

[0085] According to an embodiment, the Peclet number can be greater than 100 along an outer periphery of the semiconductor substrate. Preferably, precursor gases are injected centrally into the reactor cavity with minimum inlet volume and axisymmetric flow while seal gas is injected circumferentially around an outer periphery of the reactor cavity. The precursor gases are reacted to deposit a film on the semiconductor and byproduct gases flow radially outward towards exhaust outlets distributed circumferentially around an outer periphery of the reactor cavity. At the same time, the seal gas flows radially inward through inlets distributed circumferentially around the outer periphery of the reactor cavity. In order to obtain a high Peclet number, gas pressures are controlled according to the following equation:

[0086] C₂(P_V,-P_WC) m_wc»0-> P_V,»P_WC

[0087] One embodiment includes a showerhead module includes a faceplate having gas outlets, a backing plate having a central gas passage, and an isolation ring having seal gas passages distributed circumferentially around the reaction cavity so as to provide an inert gas seal with gas supplied through gas passages distributed circumferentially around an outer portion of the faceplate. In Figure 9 of U.S. Patent Publication No. 2017/0101710 the following equation, m₂ and m_vs represent mass flow rate in kg/s, C₂ , C₃ and C₄ represent gas conductance in liters/second and _e/f represents the effective pumping speed in liters/second. In order to obtain a high Peclet number it is desirable that m_wc should not be so large that it overwhelms the effective pumping speed, mvs should be large, C₂ should be larger than C₃, S_eff should be large and P_c^ can be large (but creates issues with dilution) as shown below:

[0088] C2 C3(CsP_ch+m_vsj-m_wc/S_eff»0 where ._/(· .ST / .V (^"/. [0089] During wafer processing, pressures in the reactor cavity and main chamber are modulated whereas the seal gas flow rate is kept constant. If the reactor cavity pressure is maintained ±1 Torr in relation to main chamber pressure, it is possible to contain the precursor gases within the reactor cavity. With the virtual gas seal arrangement, it is possible to maintain desired pressure in the reactor cavity with the inert gas seal. [0090] Fig. 14 illustrates a cut-away view of a showerhead module 600 which includes a faceplate 602 having gas inlets 604, a backing plate 606 having a central gas passage 608, an isolation ring 610 having an inner ring 612 and outer ring 614. The inner ring 612 and outer ring 614 fit together such that a seal 613 around a lower portion of the inner ring 612 provides an annular plenum between opposed surfaces of the inner and outer rings. The inner ring 612 includes seal gas inlets 616 distributed circumferentially around an upper part of an inner surface 618, horizontal passages 620 extending radially outward from the inlets 616, vertical passages 622 extending downwardly from the horizontal passages 620 and seal gas outlets 624 distributed circumferentially around a lower surface 626 of the inner ring 612.

[0091] The inner ring 612 includes primary exhaust outlets 627 comprising radially extending slots distributed circumferentially around a lower portion of the inner surface 618 and secondary exhaust outlets 628 distributed circumferentially around the lower surface 626. The primary exhaust gas outlets 627 are connected to vertical passages 630 extending upward from the primary exhaust gas outlets 627 and inwardly extending horizontal passages having primary exhaust gas outlets 632 distributed circumferentially around the inner surface 618 at a location below the seal gas inlets 616. The secondary exhaust gas outlets 628 are connected to vertical passages (not shown) and horizontal passages having secondary exhaust gas outlets 629 distributed circumferentially around an outer surface 619 of the inner ring 612. The seal gas outlets 624 deliver seal gas to create a gas seal below the isolation ring 610 and some of the seal gas is withdrawn through the secondary exhaust gas outlets 628 during semiconductor substrate processing in the wafer cavity 150. [0092] Fig. 15 depicts another cut-away view of the showerhead module of Figure 14 and illustrates how inner ring 612 fits around an outer periphery of the faceplate 602 and backing plate (gas distribution plate or GDP) 606 such that seal gas can be supplied from seal gas supply plenum 650 in an outer portion of the GDP 606 to radially extending seal gas passages 652. The seal gas passages 652 open into an annular plenum 658 located between upper and lower gas seals 654, 656. The annular plenum 658 is in fluid communication with the seal gas inlets 616 in the inner surface 618 of the inner ring 612 to deliver seal gas through the seal gas outlets 624 in the lower surface 626 of the inner ring 612.

[0093] The GDP 606 includes a primary exhaust gas plenum 680 connected to radially extending primary exhaust outlets 682 in an outer periphery of the GDP 606. The outlets 682 open into an annular exhaust plenum 684 between the lower seal 656 and an annular seal 686. The annular exhaust plenum 684 communicates with the primary exhaust gas outlets 632 on the inner surface 618 of the inner ring 612. The primary exhaust gas outlets 632 connect with the vertical passages 630 and the slots 627 to allow primary gas to be exhausted from the wafer cavity 150. [0094] The outer ring 614 surrounds the inner ring 612 with a plenum between the outer surface 619 of the inner ring 612 and an inner surface 615 of the outer ring 614. The secondary exhaust outlets 628 provide for secondary exhaust gas to be withdrawn through the secondary exhaust gas outlets 629 into the plenum between the inner ring 612 and the outer ring 614. The GDP includes at least one opening 670 in an upper surface to allow the secondary exhaust gas to be withdrawn while bypassing the throttle vale pumping arrangement connected to the primary exhaust gas plenum 680. Preferably, two opposed openings 670 are provided in the GDP for azimuthal uniformity of gas flow.

[0095] In some implementations, the different stations are each micro-volume stations, and may be particularly configured or operated to prevent cross-contamination between stations in the module. Such configuration or operational features include gas seals, as described above, or virtual sealing with curtain gas such as described in U.S. Patent No. 9,738,977 and U.S. Patent Application Publication Nos. 2013/0344245 that use inert gases that allow for each micro-volume to run isolated from the larger chamber volume. The modules can also be equipped with dedicated gas flow valving at each station to enable separate flow to each station, and local pumping out of the micro-volume through the side or top can be conducted to avoid mixing of exhaust. Fully ceramic station hardware can be used for metal halide (e.g., T1CI₄) stations to avoid corrosion or contamination from Al or other metals.

Example Virtual Sealing with Curtain Gas

[0096] One way to "simulate" smaller chamber volumes within a large multi-process chamber is by flowing curtains of gas between the various process stations and thereby volumetncally isolating the different process stations during film deposition operations. For instance, during a sequence of ALD cycles, such a "curtain gas" may be flowed between the process stations to prevent intermixing of reactants, plasma feed gases, etc. while not adversely affecting the reactive film-deposition processes occurring at each process station. While this may "simulate" a smaller volume for the purposes of reactant flow and by-product purge, the advantages of a larger chamber volume remain intact with respect to high-plasma power and scaling of certain component costs. Moreover, in addition to the foregoing benefits, volumetric isolation of process stations via curtain gas flow may allow the sequence of operations making up an ALD cycle to be staggered between process stations.

[0097] It is noted, however, that in order for the foregoing benefits to be achieved, it is not necessarily the case that the various process stations are perfectly volumetrically isolated from one another by the curtain gas flow. In general, one would expect this not to be the case. Thus, in the context of this disclosure, "volumetrically isolating" one process station from another via curtain gas flow is to be interpreted to mean that the curtain gas flow between process stations works to significantly reduce the mixing of gases between process stations that what would occur if no such curtain gas were employed. This is to be contrasted with the "complete" or "perfect" volumetric isolation that would exist if each process station resided in its own separate process chamber; volumetrically isolating with a curtain gas does not imply or require such perfect/complete separation/isolation.

[0098] Note also that, depending on the embodiment, the flow rate of curtain gas into the process chamber may be different than the flow rate of plasma feed gas into the process chamber. In some embodiments, the plasma feed gas may be flowed into the process chamber at each station at a rate of about 5 to 50 standard liters/minute (SLM) per station, or more particularly about 10 to 35 SLM per station, or yet more particularly about 15 to 20 SLM per station. In some embodiments, the curtain gas may be flowed into the process chamber at a rate of about 3 to 60 SLM per station, or more particularly about 10 to 50 SLM per station, or yet more particularly about 15 to 40 SLM per station, or still more particularly about 20 to 30 SLM per station. Such curtain gas flow rates reduce (and/or prevent) back- diffusion of reactant and plasma feed gases from the vicinity of the process stations to remote areas of the processing chamber (such as the showerhead backsides).

[0099] In some embodiments, multi-station film deposition apparatuses may employ chandelier-type showerheads, one associated with each process station. Such chandelier showerheads may generally include a head portion and stem portion, the bottom surface of the head portion providing apertures for flowing film precursor (e.g., for substrate surface adsorption in ALD operation), plasma feed gas (e.g., for plasma activation in ALD operation), and possibly a distinct purge gas into the processing chamber in the vicinity of each process station. The stem portion of the showerhead is present to support/hang the head portion above each process station within the processing chamber, and also to provide a fluidic path/connection for flowing film precursor (and/or other reactants), plasma feed gas, etc. to the apertures in the head portion. Generally, it is seen that chandelier-type showerhead designs allow for a good spatially uniform distribution of film precursor flow relative to the substrate surface, and improved in comparison to what would otherwise be achieved with just a few nozzles serving as point sources of flow.

[0100] Because they are used for different purposes, the plasma feed gas and the curtain gas generally have different entry points into the processing chamber. While the plasma feed gas enters the chamber through apertures in the bottom surface of the head portions of the showerheads (as just described), the curtain gas may be introduced into the processing chamber from entry points suitable for its role in providing volumetric isolation for the various process stations (as well as potentially providing other benefits). For instance, for embodiments employing process-station-specific chandelier showerheads, the curtain gas may be released into the process chamber from behind the head portions of each of the chandelier showerheads, and in particular, in some embodiments, through apertures in the showerhead collars which surround the stem portions of the showerheads. Moreover, in certain such embodiments, the curtain gas may be flowed from these apertures in directions substantially parallel to the plane of the substrate and/or the bottom surfaces of the head portions, and thus, generally initially in directions perpendicular to the flow emanating from the bottom surface of the head of the showerhead. This flow of curtain gas may continue laterally until the curtain gas reaches the end of the backside of the showerhead (top surface of the head portion of the showerhead) at which point the curtain gas flow may turn downward, now substantially parallel to the flow of plasma feed and/or purge gas from the head of the showerhead.

[0101] As described, in a multi-station processing chamber, this flow pattern of curtain gas may be used to provide volumetric separation between process stations; however, even in the context of a single process station embodiment, there may be attendant advantages in establishing curtain gas flow from behind the head portion of the showerhead. To illustrate such a flow pattern— first in the simpler context of a single process station embodiment— Fig. 16 depicts a cross-sectional schematic of a single-station substrate processing apparatus 1700 having a processing chamber 1702, a showerhead 1706 and showerhead collar 1730, and featuring curtain gas flowpaths 1720, and plasma feed gas (and reactant precursor) flowpaths 1710. In the configuration shown in Fig. 16, consistent with the foregoing description, plasma feed gas from plasma feed gas source 1713 is flowed into chamber 1702 through the bottom surface of the head portion of showerhead 1706, while curtain gas from curtain gas source 1722 is flowed into chamber 1702 through apertures in the showerhead collar 1730 which surrounds the stem portion of showerhead 1706. Thus, the curtain gas here (note the descriptive phrase "curtain gas" is retained, even in the single station context) is introduced into the processing chamber 1702 near to the center axis of the backside of the showerhead 1706 and introduced with a flow substantially parallel to the plane of the substrate 1712 held on pedestal 1708 (and substantially parallel to the bottom surface of the head portion of the showerhead 1706). The curtain gas so introduced then proceeds to flow around the showerhead, around the periphery of the showerhead and station, and down the chamber sidewalls before exiting the chamber in the vicinity of cross-plates 1703 (as schematically illustrated by the arrows in Fig. 16).

[0102] As discussed though, in a multi-station substrate processing chamber, the curtain gas may additionally provide volumetric isolation between process stations. Fig. 17 depicts a schematic illustration of a pair of process stations 1811 and 1812 (see dashed lines in Fig. 17) within a multi-station processing chamber 1802 of a processing tool 1800. As illustrated in the figure by arrows indicative of the direction of gas flow, in addition to the curtain gas flow pattern shown in Fig. 16 (in the context of a single station), here the curtain gas 1820 additionally flows between the process stations 1811 and 1812 volumetrically isolating them from one another. Note that this view shows a pair of process stations in cross section, so the view could represent a 2-station processing chamber embodiment, or it could represent a cross-sectional view of a 4-station processing chamber embodiment. In any event, each process station of the pair shown are analogous to the single process station shown in Fig. 16, and thus the description accompanying Fig. 16 (as well as reference numbering), applies to Fig. 17 as well where appropriate, one difference being that in Fig. 17 there are a pair of process stations 1811 and 1812, and the pair are volumetrically isolated/separated from each other by the flow of curtain gas 1820.

[0103] In some other embodiments, the curtain gas may be released into the process chamber from other entry points within the processing chamber, such as from the pedestal, from the showerhead, or the processing chamber itself. For example, the pedestal in a station may include apertures and/or slots along the circumferential edge and/or sidewall that are configured (e.g., fluidically connected to the curtain gas source) to release curtain gas into the process chamber. In another example, the showerhead may also include apertures and/or slots along the circumferential edge and/or a surface of the showerhead (e.g., the circumferential side or the top) that are configured to release curtain gas into the process chamber. In yet another example, the processing chamber may be configured to release curtain gas around each station. In some such embodiments, the processing chamber may include nozzles, apertures, slots, or other openings that are fluidically connected to the curtain gas source in order to flow such curtain gas and such openings may be arranged and placed within the processing chamber in order to suitably provide the volumetric isolation for the various process stations. For instance, the chamber may include a series of apertures or nozzles arranged in a circular pattern above each process station such that curtain gas may flow into the process chamber and around each process station.

[0104] Fig. 18 depicts an example processing chamber that includes a showerhead configured to release curtain gas into the process chamber. As can be seen, Fig. 18 includes an apparatus 1900 with a processing chamber 1702 and a showerhead 1906, as well as some of the features described and included in Fig. 16. The showerhead 1906 is fluidically connected to curtain gas source 1722 and is configured to flow curtain gas 1920, identified with dashed lines, into the processing chamber. Fig. 18 is intended to show the general concept of curtain gas flowing from showerhead 1906 and therefore, some of the features depicted in Fig. 18 are similar and/or identical to those in Fig. 16 and some have been omitted for illustrative purposes, such as the showerhead collar. The curtain gas flow may emanate from any portion or portions of the showerhead, such as the circumferential side wall, the top, or the bottom.

[0105] Similarly, Fig. 19 depicts a second example processing chamber that is configured to release curtain gas into the process chamber. Fig. 19 includes an apparatus 2000 with a processing chamber body 2002 as well as some of the features described and included in Fig. 16. The processing chamber 2002 is fluidically connected to curtain gas source 1722 and is configured to flow curtain gas 2020, identified with dashed lines, into the processing chamber. Fig. 19 is intended to show the general concept of curtain gas flowing from the processing chamber body, e.g. the top of the processing chamber, and therefore, some of the features depicted are similar and/or identical to those in Fig. 16 and some have been omitted for illustrative purposes, such as the showerhead collar.

[0106] Fig. 20 depicts a third example processing chamber that includes a pedestal configured to release curtain gas into the process chamber. As can be seen, Fig. 20 includes an apparatus 2100 with a pedestal 2108 as well as some of the features described and included in Fig. 16. The pedestal 2108 is fluidically connected to curtain gas source 1722 and is configured to flow curtain gas 2120, identified with dashed lines, into the processing chamber. Fig. 20 is intended to show the general concept of curtain gas flowing from the pedestal 2108, e.g. the top of the processing chamber, and therefore, some of the features depicted are similar and/or identical to those in Fig. 16 and some have been omitted for illustrative purposes, such as the showerhead collar. [0107] The present disclosure introduces an axisymmetric inert gas flow from a backside of the showerhead. In some examples, the flow of purge gas in the cavity satisfies a Peclet condition (typically a Peclet number greater than one) to prevent back diffusion (or flow) of precursor into the cavity. As a result, chamber volume can be reduced while minimizing unwanted deposition in the cavity, which can be hard to clean. Further improvement may be accomplished by combining the backside flow with RF isolation/suppression devices. The RF isolation/suppression devices may reduce electric fields in the cavity, which reduces the chance of parasitic plasma. [0108] Referring now to Fig. 21, which depicts an example of a substrate processing system 2250 including a processing chamber 860 having a showerhead 870 is shown. The showerhead 870 includes a stem portion 872 and a head portion 874. The head portion 874 defines an inner cavity 875. Fluids such as precursor or purge gas flow through the stem portion 872, onto a dispersion plate 876 and into the inner cavity 875. The fluids then pass through spaced holes 878 in a bottom surface of the head portion 874 and into the processing chamber.

[0109] The stem portion 872 of the showerhead 870 is connected to a top wall of the processing chamber 860 by a collar 880. The collar 880 has a generally "T"-shaped cross section and includes a head portion 881 and a stem portion 883. The collar 880 defines an inner cavity 884 that is cylinder-shaped and that receives the stem portion 872 of the showerhead 870. A plurality of slots 886 are formed in the stem portion 883 to allow fluid such as purge gas to flow from the inner cavity 884 to an outer surface of the stem portion 883. [0110] A fluid connector 890 may be connected to an edge of the head portion 81 of the collar 880 and is used to supply fluid such as purge gas. The fluid connector 890 includes one or more conduits and/or connectors that are generally identified at 892. The head portion 881 of the collar 880 likewise includes conduits and/or connectors that are generally identified at 893 to direct the flow of fluid to the inner cavity 884 of the collar 880. [0111] A plate 900 is arranged between the head portion 874 of the showerhead 870 and the collar 880. The plate 900 includes an upper surface 904, a centering opening or bore 910, and a bottom surface 914. In some examples, the plate 900 is made of ceramic. A thickness of the plate 900 may be selected to minimize material and capacitive coupling to ground or parasitic plasma. The upper surface 904 of the plate 900 is spaced from a bottom edge of the collar 880 to allow fluid to pass there between. The centering bore 910 is also spaced from the stem portion 872 to allow fluid to pass there between. The bottom surface 914 of the plate is spaced from the upper surface of the showerhead 870 to allow fluid to flow there between. In some examples, the plate 900 may be omitted and the processing chamber may be operated without the plate 900. [0112] Flowing the purge gas through the collar inhibits process deposition chemistry from entering areas in the cavity to prevent unwanted film deposition there. Dimensions of the slots and other gaps may be selected to prevent plasma light-up therein and to allow for a Peclet condition to be satisfied to prevent back diffusion for the desired gas flow rates.

[0113] Referring now to Fig. 22, which depicts an example of collar 880 of Fig. 21 that includes the head portion 881 and the stem portion 883. The slots 886 may have an arcuate shape and may be arranged around the stem portion 883. The slots 886 allow fluid to flow from the inner cavity 884 through the slots 886. The head portion 881 may include a mating portion 918 that mates with a corresponding mating portion on the fluid connector 890. When connected, the conduit 893 of the collar 880 is aligned with the conduit 892 of the fluid connector 890. [0114] Referring now to Fig. 23, which depicts an example of the fluid connector 890 for the collar 880, the fluid connector 890 is shown to include a second mating portion 920, a conduit 930, a connector 932, a conduit 934, and a connector 936; nevertheless, other configurations of the fluid connector are contemplated.

[0115] Figs. 24A and 24B depict examples of the plate 900 of Fig. 21. In Fig. 24A, the upper surface 904 of the plate 900 is shown to have a generally circular cross-section and a centering bore 910 arranged at a center of the plate 900. The centering bore 910 includes one or more projections 940 that extend radially inwardly from the centering bore 910. The projections 940 provide uniform spacing between the plate 900 and the stem portion 872. In Fig. 24B, the bottom surface 914 of the plate 900 is shown to include projections 944 that extend downwardly relative to a top of the processing chamber. The projections 944 provide uniform spacing between the bottom surface 914 of the plate 900 and the upper surface of the head portion 874 of the showerhead 870. The projections 940 and 944 may provide spacing that is sufficiently close to prevent parasitic plasma. For example only, spacing of approximately 3 mm or less may be suitable to prevent parasitic plasma for typical process conditions. Using this spacing for typical process conditions, there is insufficient space for plasma to form along with plasma sheaths (less than two plasma sheath lengths). Formation of plasma may be affected by plasma density, plasma electron temperature, and voltage across the sheath.

[0116] Further, referring back to Fig. 4, the number of pedestals in a multi-station process module can be varied, for example two or more, not necessarily four. The ratio of dielectric to metal pedestals can be varied, for example in a QSM 2:2 or a different ratio such as 1 :3, for example to account for variability in step times. If the metal is not a single layer but has barrier/liners on either side (e.g., WN/W/WN), then pedestals (stations) within a multi-station module may be configured accordingly, for example pedestal 1 = dielectric, pedestal 2 = liner 1, pedestal 3 = metal, pedestal 4 = liner 2. A pedestal can also serve a different function such as pre-heat, chemical pre-treat, cool-down, post-treat, nucleation, etc. or other operation.

[0117] Potential large wafer transfer time overhead may be offset through the use of a many-bladed transfer robot 59 to permit some batch load and unload, including prior to and after stack deposition completion, or wafers may be transferred between modules during stack deposition, for example to enhance wafer-to-wafer uniformity. Efficiency may also be enhanced the use buffer station(s) 61, for example, heat-up/cool-down stations between dielectric and metal depositions at different temperatures.

[0118] This in-situ sequential MSM (multi- station module) implementation, in particular, offers the prospect of enhanced performance in a commercial scale, quality and throughput context. Efficiency (throughput) is enhanced without substantially sacrificing technical performance, so that a maximum acceptable threshold of cross-contamination is not crossed, and/or process variability due to off-target deposition effects changing the deposition characteristics of the pedestal over time and across wafers is controlled in a well-engineered and controlled MSM tool.

Integrated In-Situ Temporal Batch - Same Tool / Same Module / Same Pedestal

[0119] Referring to Fig. 5, in a third embodiment, integrated dielectric and metal deposition may be sequentially implemented on the same pedestal(s) 82 (82a/82b) in the same module(s) 71 of the same tool 70. A suitable tool 70 may be configured for in-situ temporal batch processing in accordance with this embodiment with at least one dielectric and metal deposition module, in this implementation four QSMs (quad-station modules) 71, 72, 73, 74 on a Lam Mach IQ platform 75. The platform 75 includes a load lock 76 and robot 77 is configured to move wafers from a cassette loaded through one or more pods 78 into the load lock 76 via an atmospheric port. A wafer may be heated or exposed to plasma when inbound in the load lock 76, for example, to remove moisture and adsorbed gases, or for other pretreatment reasons. Efficiency may also be enhanced the use buffer station(s) 81, for example, heat-up/cool-down stations between dielectric and metal depositions at different temperatures. Then another robot (e.g., 79) can place the wafer into a deposition module for processing.

[0120] For example, aspects of Lam Research Strata PECVD and/or Striker ALD dielectric deposition modules station designs may be integrated on the same pedestal (station) in the same module as aspects of Lam Research ALTUS metal deposition modules station designs. Or, Lam Research Strata PECVD and/or Striker ALD dielectric deposition module station designs may be adapted such that dielectric and metal deposition may be effectively conducted at the same stations within the same module. In this way, there again is no air break between layers. In some implementations, the different stations are each micro-volume stations, and may be particularly configured or operated to prevent cross-contamination between deposition operations conducted on the same stations in the module. Such configuration or operational features include gas seals such as described above with reference to Application Publication Nos. 2015/0004798 and 2017/0101710. The modules can be equipped with dedicated gas flow valving at each station to enable separate flow to each station, and local pumping out of the micro-volume through separate side or top outlets can be conducted to avoid mixing of exhaust. Fully ceramic station hardware can be used for metal halide (e.g., TiCl₄) stations to avoid corrosion or contamination from Al or other metals. Since each wafer does not move between dielectric and metal deposition operations, this should have high throughput and low cost-per-wafer implementation. Controller

[0121] In some implementations, apparatus in accordance with this disclosure may incorporate one or more system controllers, in or associated with the individual modules and/or in or associated with the tool, such as a part of the tool platform 35, 55, 75. A suitable controller includes machine-readable instructions for movement of the wafers, into, through and out of modules and the tool, flowing reagent gas species to the module processing chamber(s)/station(s), and otherwise implementing the integrated conductor and dielectric deposition processes.

[0122] The program instructions may control a variety of process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control the parameters to operate in-situ deposition of film stacks according to various embodiments described herein. [0123] The system controller will typically include one or more memory devices and one or more processors configured to execute the instructions so that the apparatus will perform a method in accordance with disclosed embodiments. Machine-readable media containing instructions for controlling process operations in accordance with disclosed embodiments may be coupled to the system controller.

[0124] In some implementations, the system controller is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the "controller," which may control various components or subparts of the system or systems. The system controller, depending on the processing conditions and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system. [0125] Broadly speaking, the system controller may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the system controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer. [0126] The system controller, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the system controller may be in the "cloud" or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the system controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the system controller is configured to interface with or control. Thus as described above, the system controller may be distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0127] Depending on the process step or steps to be performed by the tool, the system controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.

Implementation of Specific Embodiment [0128] Parameter ranges for example silane-based silicon dioxide and titanium nitride processes using an example four-station PEALD/PECVD process tool (e.g., Lam Striker) are provided in Tables 1A and IB. It will be appreciated that other suitable parameter ranges may be employed in other embodiments of film-forming process chemistries. For example, other parameter ranges may apply for silicon dioxide films formed from silane using CO and/or C0₂ as an oxygen source and for titanium nitride films formed from Titanium halides using nitrogen atoms obtained from N₂, H₃ and/or N₂/H₂ plasmas.

[0129] TiN deposition: Table 1A

[0130] Si0₂ deposition: Table IB

[0131] An example titanium nitride process using Titanium halides and ammonia and an example four-station process tool is provided in Table 2A and an example silicon dioxide process using silane and nitrous oxide and an example four-station process tool is provided in Table 2B.

[0132] TiN deposition:

Ar (seem) 0

Pressure (torr) 2.8

Temp (°C) 550

HF Power (W) 1000

LF Power (W) 100

Si0₂ deposition:

CONCLUSION

Although the foregoing embodiments have been described in some detail for of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

CLAIMS:

1. A method of forming a film stack on a patterned semiconductor substrate, the method comprising: depositing a conductive film; and depositing a dielectric film; such that the conductive and dielectric film depositions result in the formation of a conductor/di electric film pair on a patterned semiconductor substrate; and repeating the depositing of the conductive and dielectric films to form a film stack comprising at least 20 pairs of alternating layers of conductor film and dielectric film; wherein the conductive and dielectric film depositions are conducted in the same processing tool or chamber, without breaking vacuum between the film depositions; and wherein there is no substantial cross-contamination between the conductive and dielectric film depositions.

2. The method of claim 1, wherein the conductive and dielectric film pairs are deposited in the stack at a rate of at least 5 wafers per hour.

3. The method of claim 1, wherein the conductive and dielectric film pair depositions are conducted in different modules of the same tool without breaking vacuum between the depositions.

4. The method of claim 1, wherein the conductive and dielectric film pair depositions are conducted on different stations in the same module of the same tool without breaking vacuum between the depositions.

5. The method of claim 1, wherein the conductive and dielectric film pair depositions are conducted on the same station in the same module of the same tool without breaking vacuum between the depositions.

6. The method of claim 1, wherein at least 50 of the metal and/or conductive metal nitride and silicon oxide film pairs are deposited.

7. The method of claim 1, wherein the conductive film has a maximum resistivity of 500 micro Ohm cm.

8 The method of claim 7, wherein the conductive film is a metal or metal nitride.

9. The method of claim 8, wherein the conductive film is TiN.

10. The method of claim 1, wherein the dielectric is an oxide.

11. The method of claim 10, wherein the oxide is Si0₂.

12. The method of claim 1, wherein the depositions are conducted by thermal chemical vapor deposition (CVD).

13. The method of claim 1, wherein the depositions are conducted by plasma-enhanced chemical vapor deposition (PECVD).

14. The method of claim 1, wherein the depositions are conducted by atomic layer deposition (ALD).

15. The method of claim 4, wherein the different stations are each micro-volume stations.

16. The method of claim 15, wherein the micro-volume stations comprise multiple throttle valves, one for the dielectric station(s) and one for the conductor station(s) such that pressures can be independently maintained.

17. The method of claim 15, wherein exhaust for each station is local and not shared, such that exhaust from each station can stay independent without cross mixing/contamination of gases.

18. The method of claim 15, wherein cross-contamination between stations in the module is prevented by virtual sealing with curtain gas.

19. The method of claim 15, wherein the station hardware comprises ceramic to avoid corrosion or contamination.

20. The method of claim 4, wherein the conductive and dielectric film pairs are deposited in the stack at a rate of at least 5 wafers per hour.

21. Apparatus for integrated formation a film stack comprising layers of conductor and dielectric film on a patterned semiconductor substrate, the apparatus comprising one or modules comprising processing chambers in a processing tool configured to conduct conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions.

22. The apparatus of claim 21, wherein the apparatus further comprises a controller comprising program instructions for conducting the conductor/di electric film pair depositions in different modules of the same tool without breaking vacuum between the depositions.

23. The apparatus of claim 21, wherein the apparatus further comprises a controller comprising program instructions for conducting the conductor/di electric film pair depositions on different stations in the same module of the same tool without breaking vacuum between the depositions.

24. The apparatus of claim 21, wherein the apparatus further comprises a controller comprising program instructions for conducting the conductor/di electric film pair depositions on the same station in the same module of the same tool without breaking vacuum between the depositions.