WO2018072070A1

WO2018072070A1 - Neuron circuit

Info

Publication number: WO2018072070A1
Application number: PCT/CN2016/102330
Authority: WO
Inventors: 张金勇; 孙宏伟; 林福江; 王磊
Original assignee: 中国科学院深圳先进技术研究院
Priority date: 2016-10-18
Filing date: 2016-10-18
Publication date: 2018-04-26

Abstract

Provided is a neuron circuit, comprising: an impulse generation circuit configured to simulate neural impulse oscillation by means of a first Tau-cell circuit structure and a second Tau-cell circuit structure, the first Tau-cell circuit structure comprising a first capacitor C_v used to simulate a neuron membrane potential v, and the second Tau-cell circuit structure comprising a second capacitor C_u used to simulate a neuron membrane potential adjustment variable u; an adjustment circuit connected to the impulse generation circuit and used to reassign the neuron membrane potential v; and a comparison circuit connected to the impulse generation circuit and used to reassign the neuron membrane potential adjustment variable u. The neuron circuit can reduce power consumption and an area occupied thereby.

Description

Neuron circuit

Technical field

The present invention relates to the field of artificial neural network technology, and more particularly to a neuron circuit.

Background technique

With the deep research of artificial neural networks, the traditional shortcomings of using digital circuits to realize neural networks are becoming more and more obvious. The neuron synaptic circuits required to achieve the required multiplication and addition operations and nonlinear transformations are large in scale. It is so expensive and bulky that it is difficult to adapt to the needs of development. The analog circuit has a simple structure, low power consumption, and fast calculation speed, which can significantly improve the computational efficiency of the neural network. The analog neuron circuit is one of the basic units of the simulated neural network.

The Izhikevich model is a mathematical model of neurons, proposed by Izhikevich, related reference: Izhikevich E M. Simple model of spiking neurons. [J]. IEEE Transactions on Neural Networks, 2010, 14(6): 1569-1572. This mathematical model can describe multiple forms of discharge of neurons.

The basic formula is as follows:

When ν ≥ 30mV, there is

Where ν represents the membrane potential of the neuron, u represents the membrane potential adjustment variable of the neuron, a, b, c, d are dimensionless parameters, t represents time, and I represents the stimulation current received by the neuron. The physiological process simulated by the model is as follows: after the neurons are stimulated by the synaptic current, a pulse is generated, and the membrane potential ν starts to rise, and rises to a certain extent (about 30 mV), due to the effect of the adjustment variable u, ν It returns to the potential indicated by the set value c, and u returns to u+d. Since the parameters a, b, c, and d can be flexibly set, the discharge patterns of a variety of neurons can be simulated.

Since the model contains product and square terms, the traditional analog CMOS (Complementary Metal Oxide Semiconductor) circuit is more complicated to implement. The model implemented in the neural network is generally implemented by digital or software algorithm. However, using digital or software algorithms to implement the neurons of the model, the power consumption is large, especially in the case of large-scale integration, it is difficult to adapt to the needs of future development; In the analog neural network, the neuron signal needs to be continuously converted between digital and analog, which requires a large number of D/A and A/D converters, which greatly increases the power consumption and area of the circuit.

Summary of the invention

Embodiments of the present invention provide a neuron circuit for reducing power consumption of a neuron circuit and reducing a footprint of a neuron circuit, the neuron circuit including:

The pulse generating circuit is configured to simulate a neural pulse oscillation through the first Tau-cell circuit structure and the second Tau-cell circuit structure; the first Tau-cell circuit structure includes a portion for simulating a neuron membrane potential ν a capacitor C _v ; the second Tau-cell circuit structure includes a second capacitor C _u for simulating the neuron membrane potential adjustment variable _u ;

An adjustment circuit connected to the pulse generating circuit for assigning a value to the neuron membrane potential ν;

A comparison circuit connected to the pulse generating circuit for reassigning the neuron membrane potential adjustment variable u.

The neuron circuit of the embodiment of the present invention can implement a neuron based on the Izhikevich model by a pulse generating circuit including a first Tau-cell circuit structure and a second Tau-cell circuit structure, an adjusting circuit and a comparison circuit connected to the pulse generating circuit. A variety of discharge modes, compared to traditional analog CMOS circuits, the structure of the neuron circuit is simple; compared to the use of digital or software algorithms to achieve lower power consumption, without the need for a large number of D / A and A / D converters, to the greatest extent Reduced circuit power and area.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Other drawings may also be obtained from those of ordinary skill in the art in light of the inventive work. In the drawing:

1 is a schematic structural diagram of a Tau-cell circuit according to an embodiment of the present invention;

2 is a diagram showing a specific example of a neuron circuit in an embodiment of the present invention.

detailed description

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The illustrative embodiments of the present invention and the description thereof are intended to explain the present invention, but are not intended to limit the invention.

The embodiment of the invention provides a neuron circuit for implementing the Izhikevich model. The neuron circuit is based on a Tau-cell circuit structure, and utilizes the operational characteristics of the Tau-cell circuit structure to implement a plurality of neuron discharge modes based on the Izhikevich model. The neuron circuit has low power consumption and a small footprint.

The Tau-cell circuit structure will be described below. The neuron circuit in the embodiment of the present invention adopts a Tau-cell circuit structure. 1 is a schematic structural diagram of a Tau-cell circuit according to an embodiment of the present invention. As shown in FIG. 1, in the Tau-cell circuit structure, M1, M2, M3, and M4 are NMOS devices, VDD is a power supply, and GND is a ground, V. _Ref represents a certain voltage. I _c is the current on the capacitor and V _c is the node voltage. In the Tau-cell circuit structure, M1, M2, M3, and M4 all operate in a subthreshold region. At this time, the Tau-cell circuit structure satisfies the principle of translinearity, and the following relationship can be obtained:

I _in ·I _τ =I ₁ ·I _out

The above introduction to the Tau-cell circuit structure is from the reference: Chicca E, Stefanini F, Bartolozzi C, et al. Neuromorphic electronic circuits for building autonomous cognitive systems [J]. Proceedings of the IEEE, 2014, 102 (9): 1367 -1388.

The neuron circuit in the embodiment of the present invention includes: a pulse generating circuit configured to simulate a neural pulse oscillation through a first Tau-cell circuit structure and a second Tau-cell circuit structure; in the first Tau-cell circuit structure A first capacitor C _v for simulating a neuron membrane potential ν is included; a second capacitor C _u for simulating a neuron membrane potential adjustment variable u is included in the second Tau-cell circuit structure; an adjustment circuit connected to the pulse generation circuit For re-evaluating the neuron membrane potential ν; a comparison circuit connected to the pulse generating circuit for re-assigning the neuron membrane potential adjustment variable u.

The specific implementation of the neuron circuit of the embodiment of the present invention will be described below with reference to the example of FIG. Of course, those skilled in the art can easily understand that the specific circuit structure shown in FIG. 2 is only one specific example of the implementation of the embodiment of the present invention. In the specific implementation, some or all of the structural units in the circuit can be completely modified. For example, the same function can be realized by adding or adding transistors, and further, for example, structurally reconfiguring a transistor, a capacitor, an adjustment circuit or a comparison circuit in a first Tau-cell circuit structure or a second Tau-cell circuit structure. Design, while maintaining the same principle of implementation of each part of the circuit.

As shown in Figure 2, in the neuron circuit of this example, the second Tau-cell circuit structure further includes a first NMOS device M1, a second NMOS device M2, a third NMOS device M3, a fourth NMOS device M4;

The drain of the first NMOS device M1 is short-circuited with the gate; the gate of the first NMOS device M1 is connected to the gate of the second NMOS device M2; the source of the first NMOS device M1 is grounded; the drain of the second NMOS device M2 is connected to the power supply VDD; The second NMOS device M2 is connected to the second capacitor C _u positive and the third NMOS device M3 source; the second capacitor C _{u is} negatively grounded; the third NMOS device M3 is short-circuited to the gate and connected to the first constant current source I _1u output terminal; the first constant current source I _1u input terminal is connected to the power supply VDD; the third NMOS device M3 gate is connected to the fourth NMOS device M4 gate; the third NMOS device M3 source is connected to the second constant current source I _2u input The second constant current source I _2u output terminal is grounded; the fourth NMOS device M4 source is grounded; the fourth NMOS device M4 drain is connected to the third constant current source I _in output terminal and the fourth constant current source I _dc output terminal; The third constant current source I _in output is connected to the fourth constant current source I _dc output terminal; the third constant current source I _in input terminal and the fourth constant current source I _dc input terminal are connected to the power supply VDD;

The first Tau-cell circuit structure further includes: a seventh NMOS device M7, an eighth NMOS device M8, a ninth NMOS device M9, and a tenth NMOS device M10;

The seventh NMOS device M7 is short-circuited to the gate and connected to the third constant current source I _in output terminal and the fourth constant current source I _dc output terminal; the seventh NMOS device M7 gate is connected to the eighth NMOS device M8 gate The seventh NMOS device M7 source is grounded; the eighth NMOS device M8 is connected to the power supply VDD; the eighth NMOS device M8 is connected to the fifth constant current source I _2v input terminal and the ninth NMOS device M9 source; I _2v output current source connected to ground; the ninth NMOS devices M3 and the gate-drain shorted, and connected to the sixth output terminal of the constant current source I _1v; a sixth constant current source I _1v the VDD power supply input terminal; ninth NMOS device The M9 gate is connected to the gate of the tenth NMOS device M10; the ninth NMOS device M9 source is connected to the first capacitor C _v positive electrode; the first capacitor C _{v is} negatively grounded; the tenth NMOS device M10 source is grounded;

The pulse generating circuit further includes: a fifth PMOS device M5, a sixth PMOS device M6, an eleventh PMOS device M11, a twelfth PMOS device M12, a thirteenth PMOS device M13, and a seventh constant current source _Id ;

The fifth PMOS device M5 is connected to the power supply VDD; the fifth PMOS device M5 is connected to the drain of the first NMOS device M1; the fifth PMOS device M5 is connected to the comparator input terminal; and the sixth PMOS device M6 is connected to the seventh port. Constant current source I _d output terminal; seventh constant current source I _d input terminal is connected to power supply VDD; sixth PMOS device M6 source is connected to second capacitor C _u positive electrode; sixth PMOS device M6 gate is connected to comparison circuit output terminal; The eleventh PMOS device M11 source is connected to the power supply VDD; the eleventh PMOS device M11 is connected to the twelfth PMOS device M12 gate and the comparison circuit input end; the eleventh PMOS device M11 is connected to the first capacitor C _v positive electrode; The twelfth PMOS device M12 is short-circuited to the gate and connected to the drain of the tenth NMOS device M10; the twelfth PMOS device M12 is connected to the power supply VDD; the thirteenth PMOS device M13 is connected to the comparator output terminal; The thirteenth PMOS device M13 is connected to the first capacitor C _v positive electrode; the thirteenth PMOS device M13 is connected to the drain adjusting circuit output terminal.

In a specific implementation, the neuron circuit of the embodiment of the invention operates in a subthreshold region. The transistor in the neuron circuit operates in the sub-threshold region. The transistor operating in this region has a small operating current and a small operating voltage. In the experiment, the operating voltage of the neuron circuit can be as low as 1 V or less, which can greatly reduce power consumption.

The following is an example of how the neuron circuit of the embodiment of the present invention implements multiple discharge modes of neurons based on the Izhikevich model.

In order to simplify the mathematical formula of the Izhikevich model, we express u and ν as currents, so that:

v=I _v -100 (4)

u=I _u -100b (5)

Bringing equations (4) and (5) into equation (1), we can simplify equation (1) to:

As shown in FIG. 2, in the first Tau-cell circuit structure including the seventh NMOS device M7, the eighth NMOS device M8, the ninth NMOS device M9, and the tenth NMOS device M10, the characteristics of the Tau-cell circuit structure can be Get the following relationship:

(I _in +I _dc -I _u )·I _1v =(I _2v +I _Cv -I _1v -I _v )·I _v (7)

Where I _Cv is the first capacitor C _v current. (7) Both sides of the formula can be divided by I _1v to get:

Moreover, since the MOS transistor in the neuron circuit of the embodiment of the present invention operates in the sub-threshold region, the relationship between the gate-source voltage V _GS and the drain-source current I _D of the MOS transistor operating in the state is:

Where I _S , n, V _t are inherent parameters of the MOS tube itself.

As can be seen from the symmetry of the circuit, the gate-source voltage of M8 is equal to the voltage across the first capacitor _Cv , which can be obtained by (9):

V _GS10 represents the gate-to-source voltage of M10, and (10) is brought into equation (8).

It can be seen that the form of the formula (11) is the same as the formulas (1) and (6).

Similarly, in the second Tau-cell circuit structure including the first NMOS device M1, the second NMOS device M2, the third NMOS device M3, and the fourth NMOS device M4, the following characteristics can be obtained by the characteristics of the Tau-cell circuit structure. Relationship:

(I _Cu +I _2u -I _1u )·I _u =I _1u ·I _v (12)

Where I _Cu is the second capacitor C _u current. (12) type shift can be obtained:

I _Cu ·I _u =I _1u ·I _v -(I _2u -I _1u )·I _u (13)

Similarly, it can be seen from the symmetry of the circuit that the voltage across the second capacitor C _u is the same as the gate-source voltage of M1, so

After finishing, you can get

It can be seen that the form of the formula (15) is the same as the formula (2).

The above describes how the neuron circuit structure of the embodiment of the present invention utilizes the Tau-cell circuit structure to implement the basic expressions of the Izhikevich model, namely, equations (1) and (2). The following describes how the neuron circuit structure of the embodiment of the present invention implements other functions in the model, that is, the implementation is (3).

As can be seen from FIG. 2, the neuron circuit structure of the embodiment of the present invention further includes a comparison circuit and an adjustment circuit. In a specific embodiment, the comparison circuit may be specifically configured to detect a change in the gate voltage of the fifth PMOS device M5 and the twelfth PMOS device M12, and output a re-valued voltage V _reset when the changed amplitude exceeds the set value. The sixth PMOS device M6 and the thirteenth PMOS device M13 are turned on, resetting the second capacitor C _u current, and resetting the first capacitor C _v current through the adjustment circuit. The change of the current I _v causes the gate voltages of M5 and M12 to change, and the comparison circuit detects the change of the gate voltage to generate a corresponding output. Once the magnitude of the comparison change exceeds a certain set value, the comparison circuit outputs V _reset . The transistors M6 and M13 are turned on, and the current I _{d is} injected onto the second capacitor C _u to reset the current on the second capacitor C _u , thereby changing I _Cu . Output current adjustment circuit is injected onto a first capacitor C _v, the current change on the first capacitor C _v, thereby changing the I _Cv.

In a specific embodiment, the adjustment circuit includes an eighth constant current source I _1v and a ninth constant current source I _c ; the eighth constant current source I _1v and the sixth constant current source I _{1v have the same} output current; For output comparison of the output current of the eighth constant current source I _1v and the ninth constant current source I _{c , an} output current for resetting the current of the first capacitor C _v is provided. The adjustment circuit can make the magnitude of the current injected into the first capacitor _Cv suitable by comparing the operations between the two currents.

Finally, by changing the changes of the parameters I _c and I _d , I _Cv representing the action of the neurons can generate various different discharge modes similar to the action potentials of the neurons, so that the neuron circuit of the embodiment of the present invention can simulate the Izhikevich model.

In summary, the neuron circuit of the embodiment of the present invention can be implemented based on a pulse generation circuit including a first Tau-cell circuit structure and a second Tau-cell circuit structure, and an adjustment circuit and a comparison circuit connected to the pulse generation circuit. The Izhikevich model has a variety of neuron discharge modes. Compared to traditional analog CMOS circuits, the neuron has a simple circuit structure. Compared to digital or software algorithms, it consumes less power and does not require a large amount of D/A and A/D conversion. Minimizes circuit power and area.

Further, in terms of power consumption, the transistor in the neuron circuit of the embodiment of the invention operates in a sub-threshold region, and the working current of the transistor operating in the region is small, the working voltage is also small, and the operating voltage of the neuron circuit can be as low as 1 V or less. Can greatly reduce power consumption. In terms of integration, the number of transistors used in the neuron circuit of the embodiment of the present invention is small, and the integration degree can be improved, and is applied to ultra-large-scale integration.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above described specific embodiments of the present invention are further described in detail, and are intended to be illustrative of the embodiments of the present invention. All modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

A neuron circuit, comprising:

The pulse generating circuit is configured to simulate a neural pulse oscillation through the first Tau-cell circuit structure and the second Tau-cell circuit structure; the first Tau-cell circuit structure includes a portion for simulating a neuron membrane potential ν a capacitor C v ; the second Tau-cell circuit structure includes a second capacitor C u for simulating the neuron membrane potential adjustment variable u ;

An adjustment circuit connected to the pulse generating circuit for assigning a value to the neuron membrane potential ν;

A comparison circuit connected to the pulse generating circuit for reassigning the neuron membrane potential adjustment variable u.
The neuron circuit according to claim 1, wherein the second Tau-cell circuit structure further comprises a first NMOS device M1, a second NMOS device M2, a third NMOS device M3, and a fourth NMOS device M4;

The drain of the first NMOS device M1 is short-circuited with the gate; the gate of the first NMOS device M1 is connected to the gate of the second NMOS device M2; the source of the first NMOS device M1 is grounded; the drain of the second NMOS device M2 is connected to the power supply VDD; The second NMOS device M2 source is connected to the second capacitor C u positive and the third NMOS device M3 source; the second capacitor Cu is negatively grounded; the third NMOS device M3 is short-circuited to the gate and connected to the first constant current source I 1u output terminal; the first constant current source I 1u input terminal is connected to the power supply VDD; the third NMOS device M3 gate is connected to the fourth NMOS device M4 gate; the third NMOS device M3 source is connected to the second constant current source I 2u input The second constant current source I 2u output terminal is grounded; the fourth NMOS device M4 source is grounded; the fourth NMOS device M4 drain is connected to the third constant current source I in output terminal and the fourth constant current source I dc output terminal; The third constant current source I in output is connected to the fourth constant current source I dc output terminal; the third constant current source I in input terminal and the fourth constant current source I dc input terminal are connected to the power supply VDD;

The first Tau-cell circuit structure further includes: a seventh NMOS device M7, an eighth NMOS device M8, a ninth NMOS device M9, and a tenth NMOS device M10;

The seventh NMOS device M7 is short-circuited to the gate and connected to the third constant current source I in output terminal and the fourth constant current source I dc output terminal; the seventh NMOS device M7 gate is connected to the eighth NMOS device M8 gate The seventh NMOS device M7 source is grounded; the eighth NMOS device M8 is connected to the power supply VDD; the eighth NMOS device M8 is connected to the fifth constant current source I 2v input terminal and the ninth NMOS device M9 source; I 2v output current source connected to ground; the ninth NMOS devices M3 and the gate-drain shorted, and connected to the sixth output terminal of the constant current source I 1v; a sixth constant current source I 1v the VDD power supply input terminal; ninth NMOS device The M9 gate is connected to the gate of the tenth NMOS device M10; the ninth NMOS device M9 source is connected to the first capacitor C v positive electrode; the first capacitor C v is negatively grounded; the tenth NMOS device M10 source is grounded;

The pulse generating circuit further includes: a fifth PMOS device M5, a sixth PMOS device M6, an eleventh PMOS device M11, a twelfth PMOS device M12, a thirteenth PMOS device M13, and a seventh constant current source Id ;

The fifth PMOS device M5 is connected to the power supply VDD; the fifth PMOS device M5 is connected to the drain of the first NMOS device M1; the fifth PMOS device M5 is connected to the comparator input terminal; and the sixth PMOS device M6 is connected to the seventh port. Constant current source I d output terminal; seventh constant current source I d input terminal is connected to power supply VDD; sixth PMOS device M6 source is connected to second capacitor C u positive electrode; sixth PMOS device M6 gate is connected to comparison circuit output terminal; The eleventh PMOS device M11 source is connected to the power supply VDD; the eleventh PMOS device M11 is connected to the twelfth PMOS device M12 gate and the comparison circuit input end; the eleventh PMOS device M11 is connected to the first capacitor C v positive electrode; The twelfth PMOS device M12 is short-circuited to the gate and connected to the drain of the tenth NMOS device M10; the twelfth PMOS device M12 is connected to the power supply VDD; the thirteenth PMOS device M13 is connected to the comparator output terminal; The thirteenth PMOS device M13 is connected to the first capacitor C v positive electrode; the thirteenth PMOS device M13 is connected to the drain adjusting circuit output terminal.
The neuron circuit according to claim 2, wherein the comparing circuit is specifically configured to detect a change in a gate voltage of the fifth PMOS device M5 and the twelfth PMOS device M12, and output when the changed amplitude exceeds a set value The reset voltage V reset causes the sixth PMOS device M6 and the thirteenth PMOS device M13 to be turned on, resets the second capacitor C u current, and resets the first capacitor C v current through the adjustment circuit.
The neuron circuit according to claim 2, wherein the adjustment circuit comprises an eighth constant current source I 1v and a ninth constant current source I c ; and an eighth constant current source I 1v and a sixth constant current source I 1v are output The currents are equal in magnitude;

The adjusting circuit is specifically configured to provide an output current for resetting the current of the first capacitor C v by performing an operational comparison of the output currents of the eighth constant current source I 1v and the ninth constant current source I c .
A neuron circuit according to any of claims 1 to 4, wherein the neuron circuit operates in a subthreshold region.