WO2018068001A1 - Adaptation de débit de tampon circulaire pour code polaire - Google Patents

Adaptation de débit de tampon circulaire pour code polaire Download PDF

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Publication number
WO2018068001A1
WO2018068001A1 PCT/US2017/055636 US2017055636W WO2018068001A1 WO 2018068001 A1 WO2018068001 A1 WO 2018068001A1 US 2017055636 W US2017055636 W US 2017055636W WO 2018068001 A1 WO2018068001 A1 WO 2018068001A1
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WIPO (PCT)
Prior art keywords
length
permutation
permutation pattern
bits
processors
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PCT/US2017/055636
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English (en)
Inventor
Wook Bong Lee
Eren SASOGLU
Ajit Nimbalker
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Intel Corporation
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Publication of WO2018068001A1 publication Critical patent/WO2018068001A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing

Definitions

  • Wireless systems typically include multiple User Equipment (UE) devices communicatively coupled to one or more Base Stations (BS).
  • the one or more BSs may be Long Term Evolved (LTE) evolved NodeBs (eNB) or New Radio (NR) next generation NodeBs (gNB) that can be communicatively coupled to one or more UEs by a Third- Generation Partnership Project (3 GPP) network.
  • LTE Long Term Evolved
  • eNB evolved NodeBs
  • gNB New Radio
  • 3 GPP Third- Generation Partnership Project
  • New Radio Access Technology is expected to support a broad range of use cases including Enhanced Mobile Broadband (eMBB), Massive Machine Type Communication (mMTC), Mission Critical Machine Type Communication (uMTC), and similar service types operating in frequency ranges up to 100 GHz.
  • eMBB Enhanced Mobile Broadband
  • mMTC Massive Machine Type Communication
  • uMTC Mission Critical Machine Type Communication
  • FEC forward error correction
  • ECC error-correcting code
  • One type of error correcting code is a Polar code, which has simple encoding and decoding complexity.
  • FIG. 1 illustrates an 8-bit Polar encoder circuit in accordance with an example
  • FIG. 2 illustrates performance characteristics of various coding methods for different coding rates in accordance with an example
  • FIG. 3 depicts functionality of a UE operable to communicate using polar coding and rate matching in accordance with an example
  • FIG. 4 depicts functionality of a gNB operable to communicate using polar coding and rate matching in accordance with an example
  • FIG. 5 depicts a flowchart of a machine readable storage medium having instructions embodied thereon for performing polar coding and rate matching in accordance with an example
  • FIG. 6 illustrates an architecture of a wireless network in accordance with an example
  • FIG. 7 illustrates a diagram of a wireless device (e.g., UE) in accordance with an example
  • FIG. 8 illustrates interfaces of baseband circuitry in accordance with an example
  • FIG. 9 illustrates a diagram of a wireless device (e.g., UE) in accordance with an example.
  • Channel coding or forward error correction is a method for minimizing errors when transmitting data over an unreliable communication channel.
  • This method can be implemented by sending an encoded message in a redundant manner using error- correcting code (ECC).
  • ECC error-correcting code
  • the redundancy in the encoded message allows the receiver to correct any errors in the encoded message without the retransmission of data. However, inserting redundancy into the encoded message results in a higher bandwidth.
  • Block codes operate on fixed blocks of bits of a predetermined size.
  • Convolutional codes operate on bits of arbitrary length and are often decoded by means of the Viterbi algorithm.
  • Turbo coding combines two or more convolutional codes and uses an interleaver to produce a block code.
  • a tail-biting convolutional code is a type of convolutional code that overcomes the rate loss that occurs from the transmission of extra bits resulting from starting and ending in the same state. Tail-biting convolutional coding avoids this by setting the starting and ending states of the encoder to be identical.
  • Polar code is a linear block error correcting code.
  • the method is based on the transformation of the physical channel into virtual outer channels.
  • the virtual outer channels will have either high or low reliability; in other words, the virtual outer channels polarize, with the data bits being transmitted on the most reliable channels.
  • Polar codes have simple encoding and decoding complexity on the order of 0(n log n), where n is a positive integer.
  • Rate- matching repeats or punctures the bits of a codeword to generate a selected number of bits based on a selected coding rate that may differ from the coding rate of a codeword. Puncturing is the process of removing some of the bits of the codeword, and has the effect of encoding at a higher rate. Rate-matching is important in using Polar coding because the length of a Polar codeword is a power of 2. However, the length of the desired coded block may not always be a power of 2. Therefore, the bits of a Polar codeword can either be repeated or punctured to provide a desired length.
  • a circular buffer bit selection based puncturing pattern can be used to allow the transmitter to select bits for transmission from the output of the Polar encoder.
  • One important purpose of the puncturing pattems is to randomize the impact of puncturing on the polarization property of the Polar encoder.
  • the circular buffer can also be formed by using a subblock permutation instead of the puncturing permutation.
  • FIG. 1 a standard encoder graph for a polar code of length 8 is illustrated.
  • the inputs to the encoder can be comprised of data bits or frozen bits.
  • the 4 data bits can be positioned into any of the input variables, ao - ai, and the 4 frozen bits can be positioned into any of the remaining input variables by setting those frozen bits to 0.
  • the encoder graph can also have internal values including bo - hi and co - C7. These internal values can be computed in the course of encoding but are not transmitted.
  • the encoder graph can also have codeword bits, do - d7, on the right-hand side of the encoder graph, which are the outputs. The codeword bits, do - d7, can be transmitted.
  • the small dots represent COPY nodes, the edges of which have the same value.
  • the input value, a7, and the internal value, b7 are joined by a COPY node, which means that a7 and b7 have the same value.
  • the two internal values, b7 and C7 are also joined by a COPY node, which means that they have the same value.
  • the internal value, C7, and the output, d7, are joined by a COPY node, which means that they have the same value.
  • a7, b7, C7, and d7 all have the same value.
  • the internal values, b2 and c 2 are also joined by a COPY node and have the same value.
  • the circled pluses represent exclusive OR (XOR) nodes, the edges of which sum to zero.
  • the data bit ao and the internal value bo are joined by an XOR node along with the data bit ai and the internal bit bi. If ao and ai/bi are set to 0, then bo is also be set to 0. If ao is set to 0 but ai/bi are set to 1, then bo is set to 1. If ao and ai/bi are set to 1, then bo is set to 0. If ao is set to 1, but ai/bi are set to 0, then bo is set to 1. In other words, the three edges surrounding the XOR node sum to 0.
  • the two internal values, bo and co, are also joined by an XOR node; therefore, the edges of bo and co, along with b2/c2 sum to zero. If bo and b2/c2 are set to 0, then co is also be set to 0. If bo is set to 0 but b2/c2 are set to 1, then co is set to 1. If bo and b2/c2 are set to 1, then co is set to 0. If bo is set to 1, but b2/c2 are set to 0, then co is set to 1.
  • the internal value, co, and the codeword bit, do, are also joined by an XOR node, along with C4 4; therefore the edges of co and do, along with C4/d4 sum to zero. If co and C4/d4 are set to 0, then do is also set to 0.
  • the input to the 8-bit polar encoder circuit can be [0, 0, 0, 1, 0, 1, 0, 1], in which ao, ai, a 2 , and a4 are frozen bits and ai, as, ae, and ai are data bits.
  • the input to encoder circuit can become [0, 0, 1, 1, 1, 1, 1, 1].
  • the first set of internal bits can become [1, 1, 1, 1, 0, 0, 1, 1].
  • the second set of internal bits can become [1, 1, 0, 0, 0, 0, 1, 1].
  • the input to the encoder circuit [0, 0, 0, 1, 0, 1, 0, 1] is transformed to the output or codeword [1, 1, 0, 0, 0, 0, 1, 1].
  • a transmitter can select bits from the output of the standard encoder graph using a circular buffer bit selection in conjunction with a permutation pattern.
  • the bits for transmission can be read out of this array so that the transmission bits are placed in an array for transmission, X, in an order determined by the permutation pattern.
  • puncP8 X would be equal to the array [d7, d4, dl, d2, d5, d3, dO, d6].
  • the codeword, do - d7 can be re-ordered according to the ordering scheme in the array X.
  • the codeword can be [0, 1, 0, 1, 1, 1, 0, 1].
  • the bits for transmission can be read out of the circular buffer in a circular manner starting from a starting position and wrapping around if the end of the circular buffer is reached. For example, the starting position for a codeword of length 8 for the
  • puncP8 could be d2.
  • the bits for transmission can be read out of the circular buffer starting from d2, and continuing until the end, d6 is reached, and then continuing on to d7 until ending on dl .
  • the order of bits for transmission would be: [d2, d5, d3, dO, d6, d7, d4, dl].
  • This partem can be derived from the partem stated above, [d7, d4, dl, d2, d5, d3, dO, d6], by taking the 4 th , 5 th , 6 th , 7 th , and 8 th values of the array and looping back around to the 1 st , 2 nd , and 3 rd values of the array.
  • the codeword being [0, 1, 0, 1, 1, 1, 0, 1]
  • the bits for transmission would be: [0, 1, 1, 0, 0, 1, 1, 1] .
  • the circular buffer can be formed by using a subblock permutation instead of the puncturing permutation.
  • subBLKP8 puncP(N - i), where N is the length of the codeword and i ranges from 0 to N-l .
  • the array subBLKP8 [puncP8(6), puncP8(5), puncP8(4), puncP8(3), puncP8(2), puncP8(l)].
  • the bits for transmission can be read out of this array so that the transmission bits are placed in an array for transmission, X, in an order determined by the permutation pattern.
  • puncP8, X can be equal to the array [dO d63 d2 dlO d21 d5 d58 d27 d29 d24 dl2 d44 d48 d28 d56 d61 d36 d62 dl l dl3 d38 d22 d43 d59 d32 d7 d33 d40 d51 d50 d37 d3 d34 d54 d39 d41 d46 d60 dl7 d25 dl8 d49 d52 d35 d53 dl4 d55 d8 dl6 d4 d9 d23 d26 dl9 d57 d30 d45 d31 dl d6 dl5 d20 d42 d47].
  • the codeword, do - d63 can be re-ordered
  • the permutation patterns can vary in length including the lengths of 8, 64, 128, 256, 512, 1024, 2048, and 4096. With these lengths, a codeword can be punctured by using the permutation patterns provided below.
  • the permutation pattem for a length of 64 is provided by: [47 42 20 15 6 1 31 45 30 57 19 26 23 9 4 16 8 55 14 53 35 52 49 18 25 17 60 46 41 39 54 34 3 37 50 51 40 33 7 32 59 43 22 38 13 11 62 36 61 56 28 48 44 12 24 29 27 58 5 21 10 2 63 0].
  • the permutation pattem for a length of 128 is provided by: [72 75 35 114 124 20 103 44 123 91 92 17 50 33 12 110 18 29 107 59 77 93 88 69 68 6 48 14 78 67 101 25 81 37 13 82 99 43 86 41 55 52 73 42 36 95 64 8 102 89 49 30 46 71 106 76 115 26 70 79 4 16 112 21 62 3 83 120 100 105 47 39 31 38 109 87 28 104 24 98 40 15 113 51 10 53 126 66 60 61 34 1 23 9 74 111 121 96 80 7 57 90 19 84 118 116 56 94 32 117 2 85 125 119 65 108 97 27 54 63 58 122 11 45 22 5 127 0].
  • the permutation pattem for a length of 256 is provided by:
  • the permutation partem for a length of 512 is provided by:
  • the permutation partem for a length of 1024 is provided by:
  • the permutation pattem for a length of 2048 is provided by: [6 1295 1741 1302 310 1561 1339 1113 1525 235 464 346 2019 314 44 1699 1563 1610 1745 1449 1446 933 850 289 1014 402 1090 783 1494 1120 679 1965 1927 496 303 1481 1299 446 737 504 1239 713 141 1942 579 1124 1051 1782 1503 2027 174 1354 1548 1008 281 1204 751 1666 966 1885 473 1079 1964 1517 817 1318 1348 1331 1508 1236 1599 1976 447 1609 202 436 33 327 74 639 1763 1202 1309 1685 1798 936 719 304 1420 734 841 1755 1119 1170 1667 1781 1480 178 725 71 493 1860 1000 1811 607 1233 788 1262 372 1774 1893 1938 1577 800 1493 1307 263 1290 4 1088
  • the permutation partem for a length of 4096 is provided by:
  • the permutation patterns provided above when used in conjunction with a cyclic redundancy check (CRC)-less Polar encoder, can provide performance as illustrated in FIG. 2.
  • the vertical axis shows the signal to noise ratio (SNR) to achieve a block error rate (BLER) of 1%, and is measured in decibels (dB).
  • SNR signal to noise ratio
  • BLER block error rate
  • dB decibels
  • the five distinct code types are: an LTE turbo code with a coding rate of 1/3, as shown by 201; a tail-biting convolutional code (TBCC) with a list size of 1 in the Viterbi algorithm and without a cyclic redundancy check (CRC), as shown by 202; a TBCC with a list size of 4 in the Viterbi algorithm and a CRC of 8 bits, as shown by 203; a polar code using a shortening-based rate matching with a list size of 4 in the Viterbi algorithm and without a CRC, as shown by 204; and a CRC-less polar encoder in conjunction with the permutation patterns provided above, as shown by 205.
  • the graph shows that the performance of the CRC-less polar encoder in conjunction with the permutation patterns can provide superior performance relative to the other 4 code types.
  • a CRC may also be attached prior to encoding to assist in list decoding.
  • an LTE turbo code with a coding rate of 1/3 shows inferior performance relative to the other four displayed code types in the range for K from 20 to 120 when the other four displayed code types use a coding rate of 2/3.
  • the LTE turbo code with a coding rate of 1/3 shows inferior performance relative to the other four displayed code types in the range for K from 20 to 80 when the other four displayed code types use a coding rate of 1/2.
  • the LTE turbo code with a coding rate of 1/3 shows inferior performance relative to the other four displayed code types in the range for K from 20 to 48 when the other four displayed code types use a coding rate of 1/3.
  • the LTE turbo code with a coding rate of 1/3 is not displayed when the other four displayed code types use a coding rate of 1/6.
  • a tail-biting convolutional code with a list size of 1 in the Viterbi algorithm and no CRC (TBCC LI, CO) shows superior performance relative to the other four displayed code types in the range for K from 20 to 120 for a coding rate of 2/3.
  • the TBCC LI, CO code shows superior performance relative to the other four displayed code types in the range for K from 20 to 80 for a coding rate of 1/2.
  • the TBCC LI, CO code shows superior performance relative to three of the other four displayed code types in the range for K from 20 to 64 for a coding rate of 1/3.
  • the TBCC LI, CO code shows superior performance relative to the other four displayed code types in the range for K from 20 to 48 for a coding rate of 1/6.
  • a tail-biting convolutional code with a list size of 4 in the Viterbi algorithm and a CRC of 8 bits (TBCC L4, C8) shows performance that lags the performance of the TBCC LI, CO for smaller block sizes and shows performance that is superior to the performance of TBCC LI, CO for larger block sizes.
  • the TBCC L4, C8 lag the performance of TBCC LI, CO for block sizes K ranging between 24 and 120 bits.
  • K ranging between 120 and 200 bits and a coding rate of 2/3
  • TBCC LI CO lags behind the performance of TBCC L4, C8.
  • a polar code can use shortening-based rate matching with a list size of 4 in the Viterbi algorithm and no CRC (PC-S L4, CO), which complicates the use of flexible puncturing based on one mother code.
  • PC-S L4, CO shows superior performance relative to the other 4 code types for larger block sizes and shows inferior performance for smaller block sizes.
  • a CRC-less polar encoder with a list size of 4 in the Viterbi algorithm (PC-P L4, CO), in conjunction with the permutation patterns can provide very good performance relative to the other four code types.
  • PC-P L4, CO is better than 3 of the 4 code types, lagging behind the 1/3 Turbo Code for smaller block sizes.
  • the performance of PC-P is better than 3 of the 4 code types, lagging behind the 1/3 Turbo Code for smaller block sizes.
  • the performance of PC-P L4, CO is comparable to the other 4 code types, lagging behind the 1/3 Turbo Code for smaller block sizes.
  • the performance of PC-P L4, CO is comparable to the other 4 code types, lagging behind the 1/3 Turbo Code for smaller block sizes ranging between 24 and 48.
  • the performance of PC-P L4, CO which does not rely on a CRC, is relatively superior to 3 of the 4 coding types for most block sizes in the tested range, lagging behind the rate 1/3 Turbo Code at smaller block sizes.
  • the UE can comprise one or more processors.
  • the one or more processors can be configured to select, at the UE, K date bits, wherein K is a positive integer, as in block 310.
  • the one or more processors can be configured to determine, at the UE, a coding rate r, wherein r is a positive real number as in block 320.
  • the one or more processors can be configured to determine, at the UE, a number of parity bits, ⁇ , for transmission, wherein the number of ⁇ parity bits is based on the K data bits and the coding rate r, and wherein NTX is a positive integer, as in block 330.
  • the one or more processors can be configured to encode, at the UE, the K data bits into N coded bits, wherein the K data bits are based on a polar code of a length N, wherein N is equal to 2 n where n is a positive integer, as in block 340.
  • the one or more processors can be configured to select, at the UE for transmission to the gNB, the NTX parity bits from the N coded bits using a circular buffer bit selection, wherein the NTX parity bits are based on a permutation of the length N, wherein the circular buffer bit selection uses a permutation partem of length N, wherein the permutation partem is used, as shown in block 350: to puncture the polar code of length N, as shown in block 360, or in a subblock permutation of length N - i, wherein i is an integer greater than or equal to 0 but less than N, as shown in block 370.
  • the UE can comprise a memory interface configured to receive from a memory the NTX parity bits.
  • the gNB can comprise one or more processors.
  • the one or more processors can be configured to select, at the gNB, K date bits, wherein K is a positive integer, as in block 410.
  • the one or more processors can be configured to determine, at the gNB, a coding rate r, wherein r is a positive real number as in block 420.
  • the one or more processors can be configured to determine, at the gNB, a number of parity bits, NTX, for transmission, wherein the number of NTX parity bits is based on the K data bits and the coding rate r, and wherein NTX is a positive integer, as in block 430.
  • the one or more processors can be configured to encode, at the gNB, the K data bits into N coded bits, wherein the K data bits are based on a polar code of a length N, wherein N is equal to 2 n where n is a positive integer, as in block 440.
  • the one or more processors can be configured to select, at the gNB for transmission to the UE, the NTX parity bits from the N coded bits using a circular buffer bit selection, wherein the NTX parity bits are based on a permutation of the length N, wherein the circular buffer bit selection uses a permutation pattern of length N, wherein the permutation pattern is used, as shown in block 450: to puncture the polar code of length N, as shown in block 460, or in a subblock permutation of length N - i, wherein i is an integer greater than or equal to 0 but less than N, as shown in block 470.
  • the gNB can comprise a memory interface configured to receive from a memory the NTX parity bits.
  • Another example provides at least one machine readable storage medium having instructions 500 embodied thereon for performing communication using polar coding and rate matching, as shown in FIG. 5.
  • the instructions can be executed on a machine, where the instructions are included on at least one computer readable medium or one non- transitory machine readable storage medium.
  • the instructions when executed perform: select, at the UE, K date bits, wherein K is a positive integer, as in block 510.
  • the instructions when executed perform: determine, at the UE, a coding rate r, wherein r is a positive real number as in block 520.
  • the instructions when executed perform:
  • NTX parity bits
  • the instructions when executed perform: encode, at the UE, the K data bits into N coded bits, wherein the K data bits are based on a polar code of a length N, wherein N is equal to 2 n where n is a positive integer, as in block 540.
  • the instructions when executed perform: select, at the UE for transmission to the gNB, the
  • NTX parity bits from the N coded bits using a circular buffer bit selection, wherein the NTX parity bits are based on a permutation of the length N, wherein the circular buffer bit selection uses a permutation partem of length N, wherein the permutation pattern is used, as shown in block 550: to puncture the polar code of length N, as shown in block 560, or in a subblock permutation of length N - i, wherein i is an integer greater than or equal to 0 but less than N, as shown in block 570.
  • a fifth generation (5G) next generation node B can be used in place of the eNodeB. Accordingly, unless otherwise stated, any example herein in which an eNodeB has been disclosed, can similarly be disclosed with the use of a gNB.
  • FIG. 6 illustrates an architecture of a system 600 of a network in accordance with some embodiments.
  • the system 600 is shown to include a user equipment (UE) 601 and a UE 602.
  • the UEs 601 and 602 are illustrated as smartphones (e.g., handheld touchscreen mobile computing devices connectable to one or more cellular networks), but may also comprise any mobile or non-mobile computing device, such as Personal Data Assistants (PDAs), pagers, laptop computers, desktop computers, wireless handsets, or any computing device including a wireless communications interface.
  • PDAs Personal Data Assistants
  • any of the UEs 601 and 602 can comprise an Internet of Things (IoT) UE, which can comprise a network access layer designed for low-power IoT applications utilizing short-lived UE connections.
  • An IoT UE can utilize technologies such as machine-to-machine (M2M) or machine-type communications (MTC) for exchanging data with an MTC server or device via a public land mobile network
  • M2M machine-to-machine
  • MTC machine-type communications
  • PLMN Proximity-Based Service
  • D2D device-to-device
  • An IoT network describes interconnecting IoT UEs, which may include uniquely identifiable embedded computing devices (within the Internet infrastructure), with short-lived connections.
  • the IoT UEs may execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate the connections of the IoT network.
  • the UEs 601 and 602 may be configured to connect, e.g., communicatively couple, with a radio access network (RAN) 610—
  • the RAN 610 may be, for example, an Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN), a NextGen RAN (NG RAN), or some other type of RAN.
  • UMTS Evolved Universal Mobile Telecommunications System
  • E-UTRAN Evolved Universal Mobile Telecommunications System
  • NG RAN NextGen RAN
  • the UEs 601 and 602 utilize connections 603 and 604, respectively, each of which comprises a physical communications interface or layer (discussed in further detail below); in this example, the connections 603 and 604 are illustrated as an air interface to enable communicative coupling, and can be consistent with cellular communications protocols, such as a Global System for Mobile Communications (GSM) protocol, a code-division multiple access (CDMA) network protocol, a Push-to-Talk (PTT) protocol, a PTT over Cellular (POC) protocol, a Universal Mobile Telecommunications System (UMTS) protocol, a 3GPP Long Term Evolution (LTE) protocol, a fifth generation (5G) protocol, a New Radio (NR) protocol, and the like.
  • GSM Global System for Mobile Communications
  • CDMA code-division multiple access
  • PTT Push-to-Talk
  • POC PTT over Cellular
  • UMTS Universal Mobile Telecommunications System
  • LTE Long Term Evolution
  • 5G fifth generation
  • NR New Radio
  • the UEs 601 and 602 may further directly exchange communication data via a ProSe interface 605.
  • the ProSe interface 605 may alternatively be referred to as a sidelink interface comprising one or more logical channels, including but not limited to a Physical Sidelink Control Channel (PSCCH), a Physical Sidelink Shared Channel (PSSCH), a Physical Sidelink Discovery Channel (PSDCH), and a Physical Sidelink Broadcast Channel (PSBCH).
  • PSCCH Physical Sidelink Control Channel
  • PSSCH Physical Sidelink Shared Channel
  • PSDCH Physical Sidelink Discovery Channel
  • PSBCH Physical Sidelink Broadcast Channel
  • the UE 602 is shown to be configured to access an access point (AP) 606 via connection 607.
  • the connection 607 can comprise a local wireless connection, such as a connection consistent with any IEEE 802.15 protocol, wherein the AP 606 would comprise a wireless fidelity (WiFi®) router.
  • WiFi® wireless fidelity
  • the AP 606 is shown to be connected to the Internet without connecting to the core network of the wireless system (described in further detail below).
  • the RAN 610 can include one or more access nodes that enable the connections 603 and 604. These access nodes (ANs) can be referred to as base stations (BSs), NodeBs, evolved NodeBs (eNBs), next Generation NodeBs (gNB), RAN nodes, and so forth, and can comprise ground stations (e.g., terrestrial access points) or satellite stations providing coverage within a geographic area (e.g., a cell).
  • BSs base stations
  • eNBs evolved NodeBs
  • gNB next Generation NodeBs
  • RAN nodes and so forth, and can comprise ground stations (e.g., terrestrial access points) or satellite stations providing coverage within a geographic area (e.g., a cell).
  • the RAN 610 may include one or more RAN nodes for providing macrocells, e.g., macro RAN node 611, and one or more RAN nodes for providing femtocells or picocells (e.g., cells having smaller coverage areas, smaller user capacity, or higher bandwidth compared to macrocells), e.g., low power (LP) RAN node 612.
  • macro RAN node 611 e.g., macro RAN node 611
  • femtocells or picocells e.g., cells having smaller coverage areas, smaller user capacity, or higher bandwidth compared to macrocells
  • LP low power
  • any of the RAN nodes 611 and 612 can terminate the air interface protocol and can be the first point of contact for the UEs 601 and 602.
  • any of the RAN nodes 611 and 612 can fulfill various logical functions for the RAN 610 including, but not limited to, radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.
  • RNC radio network controller
  • the UEs 601 and 602 can be configured to communicate using Orthogonal Frequency -Division Multiplexing (OFDM)
  • OFDM Orthogonal Frequency -Division Multiplexing
  • OFDMMA Orthogonal Frequency -Division Multiple Access
  • SC-FDMA Single Carrier Frequency Division Multiple Access
  • the OFDM signals can comprise a plurality of orthogonal subcarriers.
  • a downlink resource grid can be used for downlink transmissions from any of the RAN nodes 611 and 612 to the UEs 601 and 602, while uplink transmissions can utilize similar techniques.
  • the grid can be a time-frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot.
  • a time-frequency plane representation is a common practice for OFDM systems, which makes it intuitive for radio resource allocation.
  • Each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively.
  • the duration of the resource grid in the time domain corresponds to one slot in a radio frame.
  • the smallest time-frequency unit in a resource grid is denoted as a resource element.
  • Each resource grid comprises a number of resource blocks, which describe the mapping of certain physical channels to resource elements.
  • Each resource block comprises a collection of resource elements; in the frequency domain, this may represent the smallest quantity of resources that currently can be allocated.
  • the physical downlink shared channel may carry user data and higher- layer signaling to the UEs 601 and 602.
  • the physical downlink control channel may carry user data and higher- layer signaling to the UEs 601 and 602.
  • PDCCH Physical Downlink Control Channel
  • H-ARQ Hybrid Automatic Repeat Request
  • downlink scheduling assigning control and shared channel resource blocks to the UE 602 within a cell
  • the downlink resource assignment information may be sent on the PDCCH used for (e.g., assigned to) each of the UEs 601 and 602.
  • the PDCCH may use control channel elements (CCEs) to convey the control information.
  • CCEs control channel elements
  • the PDCCH complex-valued symbols may first be organized into quadruplets, which may then be permuted using a sub-block interleaver for rate matching.
  • Each PDCCH may be transmitted using one or more of these CCEs, where each CCE may correspond to nine sets of four physical resource elements known as resource element groups (REGs).
  • RAGs resource element groups
  • QPSK Quadrature Phase Shift Keying
  • the PDCCH can be transmitted using one or more CCEs, depending on the size of the downlink control information (DCI) and the channel condition. There can be four or more different
  • Some embodiments may use concepts for resource allocation for control channel information that are an extension of the above-described concepts.
  • some embodiments may utilize an enhanced physical downlink control channel (EPDCCH) that uses PDSCH resources for control information transmission.
  • the EPDCCH may be transmitted using one or more enhanced the control channel elements (ECCEs). Similar to above, each ECCE may correspond to nine sets of four physical resource elements known as an enhanced resource element groups (EREGs). An ECCE may have other numbers of EREGs in some situations.
  • EPCCH enhanced physical downlink control channel
  • ECCEs enhanced the control channel elements
  • each ECCE may correspond to nine sets of four physical resource elements known as an enhanced resource element groups (EREGs).
  • EREGs enhanced resource element groups
  • An ECCE may have other numbers of EREGs in some situations.
  • the RAN 610 is shown to be communicatively coupled to a core network (CN) 620— via an SI interface 613.
  • the CN 620 may be an evolved packet core (EPC) network, a NextGen Packet Core (NPC) network, or some other type of CN.
  • EPC evolved packet core
  • NPC NextGen Packet Core
  • the SI interface 613 is split into two parts: the Sl-U interface 614, which carries traffic data between the RAN nodes 611 and 612 and the serving gateway (S-GW) 622, and the S l-mobility management entity (MME) interface 615, which is a signaling interface between the RAN nodes 611 and 612 and MMEs 621.
  • S-GW serving gateway
  • MME S l-mobility management entity
  • the CN 620 comprises the MMEs 621, the S-GW 622, the Packet Data Network (PDN) Gateway (P-GW) 623, and a home subscriber server (HSS) 624.
  • the MMEs 621 may be similar in function to the control plane of legacy Serving General Packet Radio Service (GPRS) Support Nodes (SGSN).
  • GPRS General Packet Radio Service
  • the MMEs 621 may manage mobility aspects in access such as gateway selection and tracking area list management.
  • the HSS 624 may comprise a database for network users, including subscription-related information to support the network entities' handling of
  • the CN 620 may comprise one or several HSSs 624, depending on the number of mobile subscribers, on the capacity of the equipment, on the organization of the network, etc.
  • the HSS 624 can provide support for routing/roaming, authentication, authorization, naming/addressing resolution, location dependencies, etc.
  • the S-GW 622 may terminate the SI interface 613 towards the RAN 610, and routes data packets between the RAN 610 and the CN 620.
  • the S-GW 622 may be a local mobility anchor point for inter-RAN node handovers and also may provide an anchor for inter-3GPP mobility. Other responsibilities may include lawful intercept, charging, and some policy enforcement.
  • the P-GW 623 may terminate an SGi interface toward a PDN.
  • the P-GW 623 may route data packets between the EPC network 623 and external networks such as a network including the application server 630 (alternatively referred to as application function (AF)) via an Internet Protocol (IP) interface 625.
  • the application server 630 may be an element offering applications that use IP bearer resources with the core network (e.g., UMTS Packet Services (PS) domain, LTE PS data services, etc.).
  • PS UMTS Packet Services
  • LTE PS data services etc.
  • the P-GW 623 is shown to be communicatively coupled to an application server 630 via an IP communications interface 625.
  • the application server 630 can also be configured to support one or more communication services (e.g., Voice- over-Internet Protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) for the UEs 601 and 602 via the CN 620.
  • VoIP Voice- over-Internet Protocol
  • PTT sessions PTT sessions
  • group communication sessions social networking services, etc.
  • the P-GW 623 may further be a node for policy enforcement and charging data collection.
  • Policy and Charging Enforcement Function (PCRF) 626 is the policy and charging control element of the CN 620.
  • PCRF Policy and Charging Enforcement Function
  • HPLMN Home Public Land Mobile Network
  • IP-CAN Internet Protocol Connectivity Access Network
  • HPLMN Home Public Land Mobile Network
  • V-PCRF Visited PCRF
  • VPLMN Visited Public Land Mobile Network
  • the PCRF 626 may be communicatively coupled to the application server 630 via the P-GW 623.
  • the application server 630 may signal the PCRF 626 to indicate a new service flow and select the appropriate Quality of Service (QoS) and charging parameters.
  • the PCRF 626 may provision this rule into a Policy and Charging Enforcement Function (PCEF) (not shown) with the appropriate traffic flow template (TFT) and QoS class of identifier (QCI), which commences the QoS and charging as specified by the application server 630.
  • PCEF Policy and Charging Enforcement Function
  • TFT traffic flow template
  • QCI QoS class of identifier
  • FIG. 7 illustrates example components of a device 700 in accordance with some embodiments.
  • the device 700 may include application circuitry 702, baseband circuitry 704, Radio Frequency (RF) circuitry 706, front-end module
  • RF Radio Frequency
  • FEM power management circuitry
  • PMC power management circuitry
  • the components of the illustrated device 700 may be included in a UE or a RAN node.
  • the device 700 may include less elements (e.g., a RAN node may not utilize application circuitry 702, and instead include a processor/controller to process IP data received from an EPC).
  • the device 700 may include additional elements such as, for example, memory /storage, display, camera, sensor, or input/output (I/O) interface.
  • the components described below may be included in more than one device (e.g., said circuitries may be separately included in more than one device for Cloud-RAN (C-RAN) implementations).
  • C-RAN Cloud-RAN
  • the application circuitry 702 may include one or more application processors.
  • the application circuitry 702 may include circuitry such as, but not limited to, one or more single-core or multi-core processors.
  • the processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.).
  • the processors may be coupled with or may include memory /storage and may be configured to execute instructions stored in the memory /storage to enable various applications or operating systems to run on the device 700.
  • processors of application circuitry 702 may process IP data packets received from an EPC.
  • the baseband circuitry 704 may include circuitry such as, but not limited to, one or more single-core or multi-core processors.
  • the baseband circuitry 704 may include one or more baseband processors or control logic to process baseband signals received from a receive signal path of the RF circuitry 706 and to generate baseband signals for a transmit signal path of the RF circuitry 706.
  • Baseband processing circuity 704 may interface with the application circuitry 702 for generation and processing of the baseband signals and for controlling operations of the RF circuitry 706.
  • the baseband circuitry 704 may include a third generation (3G) baseband processor 704a, a fourth generation (4G) baseband processor 704b, a fifth generation (5G) baseband processor 704c, or other baseband processor(s) 704d for other existing generations, generations in development or to be developed in the future (e.g., second generation (2G), sixth generation (6G), etc.).
  • the baseband circuitry 704 e.g., one or more of baseband processors 704a-d
  • baseband processors 704a-d may be included in modules stored in the memory 704g and executed via a Central Processing Unit (CPU) 704e.
  • the radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency shifting, etc.
  • modulation/demodulation circuitry of the baseband circuitry 704 may include Fast-Fourier Transform (FFT), precoding, or constellation mapping/demapping functionality.
  • encoding/decoding circuitry of the baseband circuitry 704 may include convolution, tail-biting convolution, turbo, Viterbi, or Low Density Parity Check (LDPC) encoder/decoder functionality.
  • LDPC Low Density Parity Check
  • the baseband circuitry 704 may include one or more audio digital signal processor(s) (DSP) 704f.
  • the audio DSP(s) 704f may be include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments.
  • Components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments.
  • some or all of the constituent components of the baseband circuitry 704 and the application circuitry 702 may be implemented together such as, for example, on a system on a chip (SOC).
  • SOC system on a chip
  • the baseband circuitry 704 may provide for
  • the baseband circuitry 704 may support communication with an evolved universal terrestrial radio access network (EUTRAN) or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), a wireless personal area network (WPAN).
  • EUTRAN evolved universal terrestrial radio access network
  • WMAN wireless metropolitan area networks
  • WLAN wireless local area network
  • WPAN wireless personal area network
  • multi-mode baseband circuitry Embodiments in which the baseband circuitry 704 is configured to support radio communications of more than one wireless protocol.
  • RF circuitry 706 may enable communication with wireless networks
  • the RF circuitry 706 may include switches, filters, amplifiers, etc. to facilitate the communication with the wireless network.
  • RF circuitry 706 may include a receive signal path which may include circuitry to down-convert RF signals received from the FEM circuitry 708 and provide baseband signals to the baseband circuitry 704.
  • RF circuitry 706 may also include a transmit signal path which may include circuitry to up-convert baseband signals provided by the baseband circuitry 704 and provide RF output signals to the FEM circuitry 708 for transmission.
  • the receive signal path of the RF circuitry 706 may include mixer circuitry 706a, amplifier circuitry 706b and filter circuitry 706c.
  • the transmit signal path of the RF circuitry 706 may include filter circuitry 706c and mixer circuitry 706a.
  • RF circuitry 706 may also include synthesizer circuitry 706d for synthesizing a frequency for use by the mixer circuitry 706a of the receive signal path and the transmit signal path.
  • the mixer circuitry 706a of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 708 based on the synthesized frequency provided by synthesizer circuitry 706d.
  • the amplifier circuitry 706b may be configured to amplify the down-converted signals and the filter circuitry 706c may be a low-pass filter (LPF) or band-pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals.
  • Output baseband signals may be provided to the baseband circuitry 704 for further processing.
  • the output baseband signals may be zero-frequency baseband signals, although this is not a necessity.
  • mixer circuitry 706a of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.
  • the mixer circuitry 706a of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 706d to generate RF output signals for the FEM circuitry 708.
  • the baseband signals may be provided by the baseband circuitry 704 and may be filtered by filter circuitry 706c.
  • the mixer circuitry 706a of the receive signal path and the mixer circuitry 706a of the transmit signal path may include two or more mixers and may be arranged for quadrature downconversion and upconversion, respectively.
  • the mixer circuitry 706a of the receive signal path and the mixer circuitry 706a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rej ection).
  • the mixer circuitry 706a of the receive signal path and the mixer circuitry 706a may be arranged for direct downconversion and direct upconversion, respectively.
  • the mixer circuitry 706a of the receive signal path and the mixer circuitry 706a of the transmit signal path may be configured for super-heterodyne operation.
  • the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect.
  • the output baseband signals and the input baseband signals may be digital baseband signals.
  • the RF circuitry 706 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry and the baseband circuitry 704 may include a digital baseband interface to communicate with the RF circuitry 706.
  • ADC analog-to-digital converter
  • DAC digital-to-analog converter
  • a separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.
  • the synthesizer circuitry 706d may be a fractional-N synthesizer or a fractional N/N+l synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable.
  • synthesizer circuitry 706d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider.
  • the synthesizer circuitry 706d may be configured to synthesize an output frequency for use by the mixer circuitry 706a of the RF circuitry 706 based on a frequency input and a divider control input.
  • the synthesizer circuitry 706d may be a fractional N/N+l synthesizer.
  • frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a necessity.
  • VCO voltage controlled oscillator
  • Divider control input may be provided by either the baseband circuitry 704 or the applications processor 702 depending on the desired output frequency.
  • a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the applications processor 702.
  • Synthesizer circuitry 706d of the RF circuitry 706 may include a divider, a delay- locked loop (DLL), a multiplexer and a phase accumulator.
  • DLL delay- locked loop
  • the divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DPA).
  • the DMD may be configured to divide the input signal by either N or N+l (e.g., based on a carry out) to provide a fractional division ratio.
  • the DLL may include a set of cascaded, tunable, delay elements, a phase detector, a charge pump and a D-type flip-flop.
  • the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.
  • synthesizer circuitry 706d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other.
  • the output frequency may be a LO frequency (fLO).
  • the RF circuitry 706 may include an IQ/polar converter.
  • FEM circuitry 708 may include a receive signal path which may include circuitry configured to operate on RF signals received from one or more antennas 710, amplify the received signals and provide the amplified versions of the received signals to the RF circuitry 706 for further processing.
  • FEM circuitry 708 may also include a transmit signal path which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 706 for transmission by one or more of the one or more antennas 710.
  • the amplification through the transmit or receive signal paths may be done solely in the RF circuitry 706, solely in the FEM 708, or in both the RF circuitry 706 and the FEM 708.
  • the FEM circuitry 708 may include a TX/RX switch to switch between transmit mode and receive mode operation.
  • the FEM circuitry may include a receive signal path and a transmit signal path.
  • the receive signal path of the FEM circuitry may include an LNA to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 706).
  • the transmit signal path of the FEM circuitry 708 may include a power amplifier (PA) to amplify input RF signals (e.g., provided by RF circuitry 706), and one or more filters to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas 710).
  • PA power amplifier
  • the PMC 712 may manage power provided to the baseband circuitry 704.
  • the PMC 712 may control power-source selection, voltage scaling, battery charging, or DC-to-DC conversion.
  • the PMC 712 may often be included when the device 700 is capable of being powered by a battery, for example, when the device is included in a UE.
  • the PMC 712 may increase the power conversion efficiency while providing desirable implementation size and heat dissipation characteristics.
  • FIG. 7 shows the PMC 712 coupled only with the baseband circuitry 704.
  • the PMC 7 12 may be additionally or alternatively coupled with, and perform similar power management operations for, other components such as, but not limited to, application circuitry 702, RF circuitry 706, or FEM 708.
  • the PMC 712 may control, or otherwise be part of, various power saving mechanisms of the device 700. For example, if the device 700 is in an RRC_Connected state, where it is still connected to the RAN node as it expects to receive traffic shortly, then it may enter a state known as Discontinuous Reception Mode (DRX) after a period of inactivity. During this state, the device 700 may power down for brief intervals of time and thus save power.
  • DRX Discontinuous Reception Mode
  • the device 700 may transition off to an RRC Idle state, where it disconnects from the network and does not perform operations such as channel quality feedback, handover, etc.
  • the device 700 goes into a very low power state and it performs paging where again it periodically wakes up to listen to the network and then powers down again.
  • the device 700 may not receive data in this state, in order to receive data, it can transition back to
  • An additional power saving mode may allow a device to be unavailable to the network for periods longer than a paging interval (ranging from seconds to a few hours). During this time, the device is totally unreachable to the network and may power down completely. Any data sent during this time incurs a large delay and it is assumed the delay is acceptable.
  • Processors of the application circuitry 702 and processors of the baseband circuitry 704 may be used to execute elements of one or more instances of a protocol stack.
  • processors of the baseband circuitry 704 alone or in combination, may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of the application circuitry 704 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers).
  • Layer 3 may comprise a radio resource control (RRC) layer, described in further detail below.
  • RRC radio resource control
  • Layer 2 may comprise a medium access control (MAC) layer, a radio link control (RLC) layer, and a packet data convergence protocol (PDCP) layer, described in further detail below.
  • Layer 1 may comprise a physical (PHY) layer of a UE/RAN node, described in further detail below.
  • FIG. 8 illustrates example interfaces of baseband circuitry in accordance with some embodiments.
  • the baseband circuitry 704 of FIG. 7 may comprise processors 704a-704e and a memory 704g utilized by said processors.
  • Each of the processors 704a-704e may include a memory interface, 804a-804e, respectively, to send/receive data to/from the memory 704g.
  • the baseband circuitry 704 may further include one or more interfaces to communicatively couple to other circuitries/devices, such as a memory interface 812 (e.g., an interface to send/receive data to/from memory external to the baseband circuitry 704), an application circuitry interface 814 (e.g., an interface to send/receive data to/from the application circuitry 702 of FIG. 7), an RF circuitry interface 816 (e.g., an interface to send/receive data to/from RF circuitry 706 of FIG.
  • a memory interface 812 e.g., an interface to send/receive data to/from memory external to the baseband circuitry 704
  • an application circuitry interface 814 e.g., an interface to send/receive data to/from the application circuitry 702 of FIG. 7
  • an RF circuitry interface 816 e.g., an interface to send/receive data to/from RF circuitry 706 of FIG.
  • a wireless hardware connectivity interface 818 e.g., an interface to send/receive data to/from Near Field Communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components
  • a power management interface 820 e.g., an interface to send/receive power or control signals to/from the PMC 712.
  • FIG. 9 provides an example illustration of the wireless device, such as a user equipment (UE), a mobile station (MS), a mobile wireless device, a mobile
  • the wireless device can include one or more antennas configured to communicate with a node, macro node, low power node (LPN), or, transmission station, such as a base station (BS), an evolved Node B (eNB), a baseband processing unit (BBU), a remote radio head (RRH), a remote radio equipment (RRE), a relay station (RS), a radio equipment (RE), or other type of wireless wide area network (WWAN) access point.
  • the wireless device can be configured to communicate using at least one wireless communication standard such as, but not limited to, 3 GPP LTE, WiMAX, High Speed Packet Access (HSPA), Bluetooth, and WiFi.
  • the wireless device can communicate using separate antennas for each wireless communication standard or shared antennas for multiple wireless communication standards.
  • the wireless device can communicate in a wireless local area network
  • the wireless device can also comprise a wireless modem.
  • the wireless modem can comprise, for example, a wireless radio transceiver and baseband circuitry (e.g., a baseband processor).
  • the wireless modem can, in one example, modulate signals that the wireless device transmits via the one or more antennas and demodulate signals that the wireless device receives via the one or more antennas.
  • FIG. 9 also provides an illustration of a microphone and one or more speakers that can be used for audio input and output from the wireless device.
  • the display screen can be a liquid crystal display (LCD) screen, or other type of display screen such as an organic light emitting diode (OLED) display.
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • the display screen can be configured as a touch screen.
  • the touch screen can use capacitive, resistive, or another type of touch screen technology.
  • An application processor and a graphics processor can be coupled to internal memory to provide processing and display capabilities.
  • a non-volatile memory port can also be used to provide data input/output options to a user.
  • the non-volatile memory port can also be used to expand the memory capabilities of the wireless device.
  • a keyboard can be integrated with the wireless device or wirelessly connected to the wireless device to provide additional user input.
  • a virtual keyboard can also be provided using the touch screen.
  • Example 1 includes an apparatus of a user equipment (UE) configured to communicate using polar coding and rate matching, the apparatus comprising: one or more processors configured to: select, at the UE, K data bits, wherein K is a positive integer, determine, at the UE, a coding rate r, wherein r is a positive real number, determine, at the UE, a number of parity bits, NTX, for transmission, wherein the number of NTX parity bits is based on the K data bits and the coding rate r, and wherein ⁇ is a positive integer, encode, at the UE, the K data bits into N coded bits, wherein the K data bits are based on a polar code of a length N, wherein N is equal to 2 n where n is a positive integer, select, at the UE for transmission to a node, the Ntx parity bits from the N coded bits using a circular buffer bit selection process, wherein the NTX parity bits are based on a
  • Example 2 includes the apparatus of Example 1, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 64 and consists of: [47 42 20 15 6 1 31 45 30 57 19 26 23 9 4 16 8 55 14 53 35 52 49 18 25 17 60 46 41 39 54 34 3 37 50 51 40 33 7 32 59 43 22 38 13 11 62 36 61 56 28 48 44 12 24 29 27 58 5 21 10 2 63 0].
  • Example 3 includes the apparatus of Example 1, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 128 and consists of: [72 75 35 114 124 20 103 44 123 91 92 17 50 33 12 110 18 29 107 59 77 93 88 69 68 6 48 14 78 67 101 25 81 37 13 82 99 43 86 41 55 52 73 42 36 95 64 8 102 89 49 30 46 71 106 76 115 26 70 79 4 16 112 21 62 3 83 120 100 105 47 39 31 38 109 87 28 104 24 98 40 15 113 51 10 53 126 66 60 61 34 1 23 9 74 111 121 96 80 7 57 90 19 84 118 116 56 94 32 117 2 85 125 119 65 108 97 27 54 63 58 122 11 45 22 5 127 0].
  • Example 4 includes the apparatus of Example 1, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 256 and consists of: [161 25 28 196 243 114 251 160 135 182 62 95 36 240 128 101 189 7 237 110 42 100 239 153 27 32 24 177 66 235 181 6 89 245 53 137 72 92 52 78 173 63 165 214 77 202 40 56 87 20 216 81 122 229 170 35 234 34 98 16 152 145 212 242 176 102 88 220 223 97 180 211 84 73 11 8 79 13 158 190 47 197 194 90 183 50 208 30 48 193 5 192 155 118 156 129 205 169 131 150 38 231 230 195 171 252 141 18 139 9 136 226 117 80 187 209 201 248 46 113 37 109 191
  • Example 5 includes the apparatus of Example 1, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 512 and consists of: [452 215 244 481 66 227 153 73 167 189 509 335 274 325 304 411 447 10 409 111 316 26 331 17 18 105 55 288 364 70 461 388 42 478 284 100 318 436 328 222 420 349 192 255 374 200 138 71 249 35 296 438 413 310 31 82 94 123 43 96 426 203 32 161 507 75 217 176 118 165 98 214 219 134 483 342 28 500 391 463 427 345 208 290 424 45 338 235 267 182 83 489 223 399 505 104 353 231 486 435 40 90 191 404 158 460 95 131 484 471 209 256 422
  • Example 6 includes the apparatus of Example 1, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 1024 and consists of: [812 674 648 185 689 1021 437 376 252 383 488 564 737 480 833 955 511 419 463 996 166 630 83 565 444 620 440 945 828 106 369 928 719 448 591 184 29 580 455 294 974 168 389 622 862 753 324 868 333 89 925 219 132 412 731 483 239 194 101 986 826 403 198 418 768 363 550 327 336 56 508 764 924 225 516 432 560 251 894 377 762 747 300 723 700 556 199 41 4 407 858 434 734 918 385 569 936 790 532 539 1008 482 156 788 805 500 570
  • Example 7 includes the apparatus of Example 1, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 2048 and consists of: [6 1295 1741 1302 310 1561 1339 1113 1525 235 464 346 2019 314 44 1699 1563 1610 1745 1449 1446 933 850 289 1014 402 1090 783 1494 1120 679 1965 1927 496 303 1481 1299 446 737 504 1239 713 141 1942 579 1124 1051 1782 1503 2027 174 1354 1548 1008 281 1204 751 1666 966 1885 473 1079 1964 1517 817 1318 1348 1331 1508 1236 1599 1976 447 1609 202 436 33 327 74 639 1763 1202 1309 1685 1798 936 719 304 1420 734 841 1755 1119 1170 1667 1781 1480 178 725 71 493 1860 1000 1811 607 1233 788 12
  • Example 8 includes the apparatus of Example 1, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 4096 and consists of: [917 875 3590 580 3519 3825 1404 1869 352 3712 433 3630 2341 3619 175 2669 2298 3651 1194 624 3119 1690 2973 593 3739 2367 3862 1357 1930 2189 3587 3695 510 3093 3018 1004 2562 3818 1986 3468 1125 2852 2646 1754 1147 1841 1342 52 771 1598 3115 2056 3323 3633 4073 1330 549 3161 4081 3295 4077 2799 2223 530 3090 4027 3359 2157 79 1288 2317 2304 1064 366 4008 342 1771 4036 3925 2989 1938 389 127 717 3755 3385 2740 3615 2516 1614 2039 2257 1633 4042 2399 1669 1567 2143 505 430 2542 3297 791 3306 1349
  • Example 9 includes the apparatus of Examples 1-8, wherein the node is one or more of a base station (BS), a Node B (NB), an evolved Node B (eNB), a next generation Node B (gNG), a baseband unit (BBU), a remote radio head (RRH), a remote radio equipment (RRE), or a remote radio unit (RRU).
  • BS base station
  • NB Node B
  • eNB evolved Node B
  • gNG next generation Node B
  • BBU baseband unit
  • RRH remote radio head
  • RRE remote radio equipment
  • RRU remote radio unit
  • Example 10 includes An apparatus of a next generation node B (gNB) configured to communicate using polar coding and rate matching, the apparatus comprising: one or more processors configured to: select, at the gNB, K data bits, wherein K is a positive integer, determine, at the gNB, a coding rate r, wherein r is a positive real number, determine, at the gNB, a number of parity bits, ⁇ , for transmission, wherein the number of NTX parity bits is based on the K data bits and the coding rate r, and wherein ⁇ is a positive integer, encode, at the gNB, the K data bits into N coded bits , wherein the K data bits are based on a polar code of a length N, wherein N is equal to 2 N where n is a positive integer, select, at the gNB for transmission to the UE, the Ntx parity bits from the N coded bits using a circular buffer bit selection, wherein the NTX parity bits
  • Example 11 includes the apparatus of Example 10, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 64 and consists of: [47 42 20 15 6 1 31 45 30 57 19 26 23 9 4 16 8 55 14 53 35 52 49 18 25 17 60 46 41 39 54 34 3 37 50 51 40 33 7 32 59 43 22 38 13 11 62 36 61 56 28 48 44 12 24 29 27 58 5 21 10 2 63 0].
  • Example 12 includes the apparatus of Example 10, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 128 and consists of: [72 75 35 114 124 20 103 44 123 91 92 17 50 33 12 110 18 29 107 59 77 93 88 69 68 6 48 14 78 67 101 25 81 37 13 82 99 43 86 41 55 52 73 42 36 95 64 8 102 89 49 30 46 71 106 76 115 26 70 79 4 16 112 21 62 3 83 120 100 105 47 39 31 38 109 87 28 104 24 98 40 15 113 51 10 53 126 66 60 61 34 1 23 9 74 111 121 96 80 7 57 90 19 84 118 116 56 94 32 117 2 85 125 119 65 108 97 27 54 63 58 122 11 45 22 5 127 0] .
  • Example 13 includes the apparatus of Example 10, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 256 and consists of: [161 25 28 196 243 114 251 160 135 182 62 95 36 240 128 101 189 7 237 110 42 100 239 153 27 32 24 177 66 235 181 6 89 245 53 137 72 92 52 78 173 63 165 214 77 202 40 56 87 20 216 81 122 229 170 35 234 34 98 16 152 145 212 242 176 102 88 220 223 97 180 211 84 73 11 8 79 13 158 190 47 197 194 90 183 50 208 30 48 193 5 192 155 118 156 129 205 169 131 150 38 231 230 195 171 252 141 18 139 9 136 226 117 80 187 209 201 248 46 113 37 109 191
  • Example 14 includes the apparatus of Example 10, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 512 and consists of: [452 215 244 481 66 227 153 73 167 189 509 335 274 325 304 411 447 10 409 111 316 26 331 17 18 105 55 288 364 70 461 388 42 478 284 100 318 436 328 222 420 349 192 255 374 200 138 71 249 35 296 438 413 310 31 82 94 123 43 96 426 203 32 161 507 75 217 176 118 165 98 214 219 134 483 342 28 500 391 463 427 345 208 290 424 45 338 235 267 182 83 489 223 399 505 104 353 231 486 435 40 90 191 404 158 460 95 131 484 471 209 256 422
  • Example 15 includes the apparatus of Example 10, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 1024 and consists of: [812 674 648 185 689 1021 437 376 252 383 488 564 737 480 833 955 511 419 463 996 166 630 83 565 444 620 440 945 828 106 369 928 719 448 591 184 29 580 455 294 974 168 389 622 862 753 324 868 333 89 925 219 132 412 731 483 239 194 101 986 826 403 198 418 768 363 550 327 336 56 508 764 924 225 516 432 560 251 894 377 762 747 300 723 700 556 199 41 4 407 858 434 734 918 385 569 936 790 532 539 1008 482 156 788 805 500 570
  • Example 16 includes the apparatus of Example 10, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 2048 and consists of: [6 1295 1741 1302 310 1561 1339 1113 1525 235 464 346 2019 314 44 1699 1563 1610 1745 1449 1446 933 850 289 1014 402 1090 783 1494 1120 679 1965 1927 496 303 1481 1299 446 737 504 1239 713 141 1942 579 1124 1051 1782 1503 2027 174 1354 1548 1008 281 1204 751 1666 966 1885 473 1079 1964 1517 817 1318 1348 1331 1508 1236 1599 1976 447 1609 202 436 33 327 74 639 1763 1202 1309 1685 1798 936 719 304 1420 734 841 1755 1119 1170 1667 1781 1480 178 725 71 493 1860 1000 1811 607 1233 788 12
  • Example 17 includes the apparatus of Example 10, wherein the one or more processors are further configured to use the permutation pattern, wherein the permutation pattern is of length 4096 and consists of: [917 875 3590 580 3519 3825 1404 1869 352 3712 433 3630 2341 3619 175 2669 2298 3651 1194 624 3119 1690 2973 593 3739 2367 3862 1357 1930 2189 3587 3695 510 3093 3018 1004 2562 3818 1986 3468 1125 2852 2646 1754 1147 1841 1342 52 771 1598 3115 2056 3323 3633 4073 1330 549 3161 4081 3295 4077 2799 2223 530 3090 4027 3359 2157 79 1288 2317 2304 1064 366 4008 342 1771 4036 3925 2989 1938 389 127 717 3755 3385 2740 3615 2516 1614 2039 2257 1633 4042 2399 1669 1567 2143 505 430 2542 3297 791 3306 1349
  • Example 18 includes at least one machine readable storage medium having instructions embodied thereon for performing communication using polar coding and rate matching, the instructions when executed by one or more processors at a user equipment (UE) perform the following: select, at the UE, K data bits, wherein K is a positive integer, determine, at the UE, a coding rate r, wherein r is a positive real number, determine, at the UE, a number of parity bits, NTX, for transmission, wherein the number of ⁇ parity bits is based on the K data bits and the coding rate r, and wherein NTX is a positive integer, encode, at the UE, the K data bits into N coded bits , wherein the K data bits are based on a polar code of a length N, wherein N is equal to 2 n where n is a positive integer, select, at the UE for transmission to a node, the Ntx parity bits from the N coded bits using a circular buffer bit selection, where
  • Example 19 includes the at least one machine readable storage medium of Example 18, wherein the permutation pattern is of length 64 and consists of: [47 42 20 15 6 1 31 45 30 57 19 26 23 9 4 16 8 55 14 53 35 52 49 18 25 17 60 46 41 39 54 34 3 37 50 51 40 33 7 32 59 43 22 38 13 11 62 36 61 56 28 48 44 12 24 29 27 58 5 21 10 2 63 0].
  • Example 20 includes the at least one machine readable storage medium of
  • Example 18 wherein the permutation pattern is of length 128 and consists of: [72 75 35 114 124 20 103 44 123 91 92 17 50 33 12 110 18 29 107 59 77 93 88 69 68 6 48 14 78 67 101 25 81 37 13 82 99 43 86 41 55 52 73 42 36 95 64 8 102 89 49 30 46 71 106 76 115 26 70 79 4 16 112 21 62 3 83 120 100 105 47 39 31 38 109 87 28 104 24 98 40 15 113 51 10 53 126 66 60 61 34 1 23 9 74 111 121 96 80 7 57 90 19 84 118 116 56 94 32 117 2 85 125 119 65 108 97 27 54 63 58 122 11 45 22 5 127 0] .
  • Example 21 includes the at least one machine readable storage medium of Example 18, wherein the permutation pattern is of length 256 and consists of: [161 25 28 196 243 114 251 160 135 182 62 95 36 240 128 101 189 7 237 110 42 100 239 153 27 32 24 177 66 235 181 6 89 245 53 137 72 92 52 78 173 63 165 214 77 202 40 56 87 20 216 81 122 229 170 35 234 34 98 16 152 145 212 242 176 102 88 220 223 97 180 211 84 73 11 8 79 13 158 190 47 197 194 90 183 50 208 30 48 193 5 192 155 118 156 129 205 169 131 150 38 231 230 195 171 252 141 18 139 9 136 226 117 80 187 209 201 248 46 113 37 109 191 221 99 76 3 210 54 167
  • Example 22 includes the at least one machine readable storage medium of Example 18, wherein the permutation pattern is of length 512 and consists of: [452 215 244 481 66 227 153 73 167 189 509 335 274 325 304 411 447 10 409 111 316 26 331 17 18 105 55 288 364 70 461 388 42 478 284 100 318 436 328 222 420 349 192 255 374 200 138 71 249 35 296 438 413 310 31 82 94 123 43 96 426 203 32 161 507 75 217 176 118 165 98 214 219 134 483 342 28 500 391 463 427 345 208 290 424 45 338 235 267 182 83 489 223 399 505 104 353 231 486 435 40 90 191 404 158 460 95 131 484 471
  • Example 23 includes the at least one machine readable storage medium of Example 18, wherein the permutation pattern is of length 1024 and consists of: [812 674 648 185 689 1021 437 376 252 383 488 564 737 480 833 955 511 419 463 996 166 630 83 565 444 620 440 945 828 106 369 928 719 448 591 184 29 580 455 294 974 168 389 622 862 753 324 868 333 89 925 219 132 412 731 483 239 194 101 986 826 403 198 418 768 363 550 327 336 56 508 764 924 225 516 432 560 251 894 377 762 747 300 723 700 556 199 41 4 407 858 434 734 918 385 569 936 790 532 539 1008 482 156 788 805 500 570 990 278 517 125 208 749
  • Example 24 includes the at least one machine readable storage medium of Example 18, wherein the permutation pattern is of length 2048 and consists of: [6 1295 1741 1302 310 1561 1339 1113 1525 235 464 346 2019 314 44 1699 1563 1610 1745 1449 1446 933 850 289 1014 402 1090 783 1494 1120 679 1965 1927 496 303 1481 1299 446 737 504 1239 713 141 1942 579 1124 1051 1782 1503 2027 174 1354 1548 1008 281 1204 751 1666 966 1885 473 1079 1964 1517 817 1318 1348 1331 1508 1236 1599 1976 447 1609 202 436 33 327 74 639 1763 1202 1309 1685 1798 936 719 304 1420 734 841 1755 1119 1170 1667 1781 1480 178 725 71 493 1860 1000 1811 607 1233 788 1262 372 1774 1893 1938 1577 800 14
  • Example 25 includes the at least one machine readable storage medium of Example 18, wherein the permutation pattern is of length 4096 and consists of: [917 875 3590 580 3519 3825 1404 1869 352 3712 433 3630 2341 3619 175 2669 2298 3651 1194 624 3119 1690 2973 593 3739 2367 3862 1357 1930 2189 3587 3695 510 3093 3018 1004 2562 3818 1986 3468 1125 2852 2646 1754 1147 1841 1342 52 771 1598 3115 2056 3323 3633 4073 1330 549 3161 4081 3295 4077 2799 2223 530 3090 4027 3359 2157 79 1288 2317 2304 1064 366 4008 342 1771 4036 3925 2989 1938 389 127 717 3755 3385 2740 3615 2516 1614 2039 2257 1633 4042 2399 1669 1567 2143 505 430 2542 3297 791 3306 1349 2310 750 3104 1774 1923 2366
  • Example 26 includes the at least one machine readable storage medium of Examples 18-25, wherein the node is one or more of a base station (BS), a Node B (NB), an evolved Node B (eNB), a next generation Node B (gNG), a baseband unit (BBU), a remote radio head (RRH), a remote radio equipment (RRE), or a remote radio unit (RRU).
  • BS base station
  • NB Node B
  • eNB evolved Node B
  • gNG next generation Node B
  • BBU baseband unit
  • RRH remote radio head
  • RRE remote radio equipment
  • RRU remote radio unit
  • Example 27 includes a user equipment (UE) configured to communicate using polar coding and rate matching, the UE comprising: means for selecting, at the UE, K data bits, wherein K is a positive integer, means for determining, at the UE, a coding rate r, wherein r is a positive real number, means for determining, at the UE, a number of parity bits, ⁇ , for transmission, wherein the number of ⁇ parity bits is based on the K data bits and the coding rate r, and wherein ⁇ is a positive integer, means for encoding, at the UE, the K data bits into N coded bits , wherein the K data bits are based on a polar code of a length N, wherein N is equal to 2 N where n is a positive integer, means for selecting, at the UE for transmission to a node, the Ntx parity bits from the N coded bits using a circular buffer bit selection, wherein the NTX parity bits are based on
  • Example 28 includes the UE of Example 27, wherein the permutation pattern is of length 64 and consists of: [47 42 20 15 6 1 31 45 30 57 19 26 23 9 4 16 8 55 14 53 35 52 49 18 25 17 60 46 41 39 54 34 3 37 50 51 40 33 7 32 59 43 22 38 13 11 62 36 61 56 28 48 44 12 24 29 27 58 5 21 10 2 63 0].
  • Example 29 includes the UE of Example 27, wherein the permutation pattern is of length 128 and consists of: [72 75 35 114 124 20 103 44 123 91 92 17 50 33 12 110 18 29 107 59 77 93 88 69 68 6 48 14 78 67 101 25 81 37 13 82 99 43 86 41 55 52 73 42 36 95 64 8 102 89 49 30 46 71 106 76 115 26 70 79 4 16 112 21 62 3 83 120 100 105 47 39 31 38 109 87 28 104 24 98 40 15 113 51 10 53 126 66 60 61 34 1 23 9 74 111 121 96 80 7 57 90 19 84 118 116 56 94 32 117 2 85 125 119 65 108 97 27 54 63 58 122 11 45 22 5 127 0].
  • Example 30 includes the UE of Example 27, wherein the permutation pattern is of length 256 and consists of: [161 25 28 196 243 114 251 160 135 182 62 95 36 240 128 101 189 7 237 110 42 100 239 153 27 32 24 177 66 235 181 6 89 245 53 137 72 92 52 78 173 63 165 214 77 202 40 56 87 20 216 81 122 229 170 35 234 34 98 16 152 145 212 242 176 102 88 220 223 97 180 211 84 73 11 8 79 13 158 190 47 197 194 90 183 50 208 30 48 193 5 192 155 118 156 129 205 169 131 150 38 231 230 195 171 252 141 18 139 9 136 226 117 80 187 209 201 248 46 113 37 109 191 221 99 76 3 210 54 167 58 116 159 49
  • Example 31 includes the UE of Example 27, wherein the permutation pattern is of length 512 and consists of: [452 215 244 481 66 227 153 73 167 189 509 335 274 325 304 411 447 10 409 111 316 26 331 17 18 105 55 288 364 70 461 388 42 478 284 100 318 436 328 222 420 349 192 255 374 200 138 71 249 35 296 438 413 310 31 82 94 123 43 96 426 203 32 161 507 75 217 176 118 165 98 214 219 134 483 342 28 500 391 463 427 345 208 290 424 45 338 235 267 182 83 489 223 399 505 104 353 231 486 435 40 90 191 404 158 460 95 131 484 471 209 256 422 143 371 333 286 415 357 287 129 122
  • Example 32 includes the UE of Example 27, wherein the permutation pattern is of length 1024 and consists of: [812 674 648 185 689 1021 437 376 252 383 488 564 737 480 833 955 511 419 463 996 166 630 83 565 444 620 440 945 828 106 369 928 719 448 591 184 29 580 455 294 974 168 389 622 862 753 324 868 333 89 925 219 132 412 731 483 239 194 101 986 826 403 198 418 768 363 550 327 336 56 508 764 924 225 516 432 560 251 894 377 762 747 300 723 700 556 199 41 4 407 858 434 734 918 385 569 936 790 532 539 1008 482 156 788 805 500 570 990 278 517 125 208 749 170 679 221
  • Example 33 includes the UE of Example 27, wherein the permutation pattern is of length 2048 and consists of: [6 1295 1741 1302 310 1561 1339 1113 1525 235 464 346 2019 314 44 1699 1563 1610 1745 1449 1446 933 850 289 1014 402 1090 783 1494 1120 679 1965 1927 496 303 1481 1299 446 737 504 1239 713 141 1942 579 1124 1051 1782 1503 2027 174 1354 1548 1008 281 1204 751 1666 966 1885 473 1079 1964 1517 817 1318 1348 1331 1508 1236 1599 1976 447 1609 202 436 33 327 74 639 1763 1202 1309 1685 1798 936 719 304 1420 734 841 1755 1119 1170 1667 1781 1480 178 725 71 493 1860 1000 1811 607 1233 788 1262 372 1774 1893 1938 1577 800 1493 1307 263 12
  • Example 34 includes the UE of Example 27, wherein the permutation pattern is of length 4096 and consists of: [917 875 3590 580 3519 3825 1404 1869 352 3712 433 3630 2341 3619 175 2669 2298 3651 1194 624 3119 1690 2973 593 3739 2367 3862 1357 1930 2189 3587 3695 510 3093 3018 1004 2562 3818 1986 3468 1125 2852 2646 1754 1147 1841 1342 52 771 1598 3115 2056 3323 3633 4073 1330 549 3161 4081 3295 4077 2799 2223 530 3090 4027 3359 2157 79 1288 2317 2304 1064 366 4008 342 1771 4036 3925 2989 1938 389 127 717 3755 3385 2740 3615 2516 1614 2039 2257 1633 4042 2399 1669 1567 2143 505 430 2542 3297 791 3306 1349 2310 750 3104 1774 1923 2366 625 1153 1568
  • Various techniques, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, compact disc-read-only memory (CD-ROMs), hard drives, non-transitory computer readable storage medium, or any other machine-readable storage medium wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the various techniques.
  • the computing device may include a processor, a storage medium readable by the processor (including volatile and nonvolatile memory and/or storage elements), at least one input device, and at least one output device.
  • the volatile and non-volatile memory and/or storage elements may be a random-access memory (RAM), erasable programmable read only memory (EPROM), flash drive, optical drive, magnetic hard drive, solid state drive, or other medium for storing electronic data.
  • the node and wireless device may also include a transceiver module (i.e., transceiver), a counter module (i.e., counter), a processing module (i.e., processor), and/or a clock module (i.e., clock) or timer module (i.e., timer).
  • transceiver module i.e., transceiver
  • a counter module i.e., counter
  • a processing module i.e., processor
  • a clock module i.e., clock
  • timer module i.e., timer
  • selected components of the transceiver module can be located in a cloud radio access network (C-RAN).
  • C-RAN cloud radio access network
  • One or more programs that may implement or utilize the various techniques described herein may use an application programming interface (API), reusable controls, and the like.
  • API application programming interface
  • Such programs may be implemented in a high level procedural or object oriented programming language to communicate with a computer system.
  • the program(s) may be implemented in assembly or machine language, if desired.
  • the language may be a compiled or interpreted language, and combined with hardware implementations.
  • circuitry may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality.
  • ASIC Application Specific Integrated Circuit
  • the circuitry may be implemented in, or functions associated with the circuitry may be implemented by, one or more software or firmware modules.
  • circuitry may include logic, at least partially operable in hardware.
  • modules may be implemented as a hardware circuit comprising custom very-large-scale integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components.
  • VLSI very-large-scale integration
  • a module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.
  • Modules may also be implemented in software for execution by various types of processors.
  • An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions, which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module may not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module.
  • a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices.
  • operational data may be identified and illustrated herein within modules, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network.
  • the modules may be passive or active, including agents operable to perform desired functions.

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  • Engineering & Computer Science (AREA)
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Abstract

L'invention concerne une technologie pour un équipement utilisateur (UE) configuré pour communiquer en utilisant un codage polaire et une adaptation de débit. L'UE peut sélectionner K bits de données et peut déterminer un débit de codage r. L'UE peut déterminer un nombre de bits de parité, NTx, pour une transmission, le nombre de NTx bits de parité étant basé sur les K bits de données et le taux de codage r. L'UE peut coder les K bits de données en N bits codés, les K bits de données étant basés sur un code polaire d'une longueur N. L'UE peut sélectionner, pour une transmission au nœud B de prochaine génération (gNB), les Ntx bits de parité à partir des N bits codés à l'aide d'une sélection de bit de tampon circulaire. Les NTx bits de parité peuvent être basés sur une permutation de longueur N à l'aide d'un motif de permutation de longueur N qui est utilisé : pour percer le code polaire, ou dans une permutation de sous-bloc.
PCT/US2017/055636 2016-10-06 2017-10-06 Adaptation de débit de tampon circulaire pour code polaire WO2018068001A1 (fr)

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Citations (4)

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US20080320353A1 (en) * 2007-06-20 2008-12-25 Motorola, Inc. Apparatus comprising a circular buffer and method for assigning redundancy versions to a circular buffer
US20090100309A1 (en) * 2007-10-12 2009-04-16 Industrial Technology Research Institute Methods and devices for encoding data in communication systems
WO2015139248A1 (fr) * 2014-03-19 2015-09-24 华为技术有限公司 Procede d'adaptation de debit de code polaire et dispositif d'adaptation de debit
CA2972655A1 (fr) * 2014-03-24 2015-10-01 Huawei Technologies Co., Ltd. Procede de mise en correspondance de debits et appareil de mise en correspondance de debits pour des codes polaires

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US20090100309A1 (en) * 2007-10-12 2009-04-16 Industrial Technology Research Institute Methods and devices for encoding data in communication systems
WO2015139248A1 (fr) * 2014-03-19 2015-09-24 华为技术有限公司 Procede d'adaptation de debit de code polaire et dispositif d'adaptation de debit
EP3113398A1 (fr) * 2014-03-19 2017-01-04 Huawei Technologies Co., Ltd Procédé d'adaptation de débit de code polaire et dispositif d'adaptation de débit
CA2972655A1 (fr) * 2014-03-24 2015-10-01 Huawei Technologies Co., Ltd. Procede de mise en correspondance de debits et appareil de mise en correspondance de debits pour des codes polaires

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MEDIATEK INC: "Examination of NR Coding Candidates for Low-Rate Applications", vol. RAN WG1, no. Gothenburg, Sweden; 20160822 - 20160826, 21 August 2016 (2016-08-21), XP051140704, Retrieved from the Internet <URL:http://www.3gpp.org/ftp/Meetings_3GPP_SYNC/RAN1/Docs/> [retrieved on 20160821] *
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